KR20240048456A - Integrated circuit including backside wiring and method of designing the same - Google Patents

Abstract

The integrated circuit may include a cell region in which a plurality of cells are arranged, and a peripheral region in which a circuit for controlling the plurality of cells is arranged, and the cell region includes a plurality of first gate lines extending over the substrate, a plurality of A plurality of first patterns extending from the first wiring layer above the first gate lines, a plurality of second patterns extending in the first horizontal direction from the rear wiring layer below the substrate, and a plurality of second patterns each penetrating the substrate in a vertical direction. It may include one via, and each of the plurality of first vias may have an upper surface connected to one of the plurality of first patterns and a lower surface connected to one of the plurality of second patterns.

Description

Integrated circuit including backside wiring and method of designing the same

The technical idea of the present disclosure relates to integrated circuits, and more specifically, to an integrated circuit including rear wiring and a method of designing the same.

Due to demands for high integration and advancements in semiconductor processes, the width, spacing, and/or height of interconnections included in an integrated circuit may decrease, and the influence of parasitic elements of interconnections may increase. Additionally, the power supply voltage of the integrated circuit may be reduced for reduced power consumption, high operating speed, etc., and accordingly, the influence of parasitic components of wiring on the integrated circuit may be more significant. Despite such parasitic components, an integrated circuit including a cell array composed of cells of the same structure may be required to stably provide high integration and performance according to the requirements of various applications.

The technical idea of the present disclosure provides an integrated circuit including a cell array routed by rear wiring and a method of designing the same.

An integrated circuit according to one aspect of the technical idea of the present disclosure may include a cell region in which a plurality of cells are arranged, and a peripheral region in which a circuit for controlling the plurality of cells is arranged, and the cell region extends over the substrate. A plurality of first gate lines, a plurality of first patterns extending from the first wiring layer above the plurality of first gate lines, a plurality of second patterns extending in the first horizontal direction from the rear wiring layer below the substrate, and a substrate may include a plurality of first vias each penetrating in a vertical direction, wherein each of the plurality of first vias has an upper surface connected to one of the plurality of first patterns and a lower surface connected to one of the plurality of second patterns. You can have

An integrated circuit according to one aspect of the technical idea of the present disclosure may include a cell region in which a plurality of cells are arranged, and a peripheral region in which a circuit for controlling the plurality of cells is arranged, and the cell region extends over the substrate. It may include a plurality of first gate lines, a plurality of first patterns extending from the first wiring layer above the plurality of first gate lines, and a plurality of second patterns extending in the first horizontal direction from the rear wiring layer below the substrate. Each of the plurality of second patterns may receive a control signal commonly provided to cells arranged in a row extending in the first horizontal direction among the plurality of cells.

An integrated circuit according to one aspect of the technical idea of the present disclosure may include a cell region in which a plurality of cells are arranged, and a peripheral region adjacent to the cell region and in which a circuit for controlling the plurality of cells is disposed, and the cell region is a plurality of first gate lines extending above the substrate, a plurality of first patterns extending from a first wiring layer above the plurality of first gate lines, extending in a first horizontal direction in a rear wiring layer below the substrate, and a plurality of first patterns extending from a first wiring layer below the substrate. a plurality of second patterns that receive a first supply voltage provided to the cells, and each of a plurality of second patterns vertically penetrating the substrate and connected to one of the plurality of first patterns and one of the plurality of second patterns It may include first vias.

According to the integrated circuit and method according to example embodiments of the present disclosure, routing resources of the integrated circuit may be increased, and accordingly, the area of the integrated circuit may be reduced.

Additionally, according to the integrated circuit and method according to an exemplary embodiment of the present disclosure, parasitic components of wiring can be reduced, and thus the performance of the integrated circuit can be increased.

The effects that can be obtained from the exemplary embodiments of the present disclosure are not limited to the effects mentioned above, and other effects not mentioned are common knowledge in the technical field to which the exemplary embodiments of the present disclosure belong from the following description. It can be clearly derived and understood by those who have it. That is, unintended effects resulting from implementing the exemplary embodiments of the present disclosure may also be derived by those skilled in the art from the exemplary embodiments of the present disclosure.

1 is a diagram showing the layout of an integrated circuit according to an exemplary embodiment of the present disclosure.
2A to 2D are diagrams showing examples of devices according to example embodiments of the present disclosure.
Figure 3 is a block diagram showing an integrated circuit according to an exemplary embodiment of the present disclosure.
Figure 4 is a plan view showing the layout of an integrated circuit according to an exemplary embodiment of the present disclosure.
Figure 5 is a circuit diagram showing a memory cell according to an exemplary embodiment of the present disclosure.
6A and 6B are plan views showing the layout of an integrated circuit according to example embodiments of the present disclosure.
7A to 7E are plan views showing layouts of integrated circuits according to example embodiments of the present disclosure.
8A to 8E are plan views showing layouts of integrated circuits according to example embodiments of the present disclosure.
9A and 9B are plan views showing layouts of integrated circuits according to example embodiments of the present disclosure.
10 is a flowchart illustrating a method for manufacturing an integrated circuit according to an exemplary embodiment of the present disclosure.
Figure 11 is a flowchart showing a method of designing an integrated circuit according to an example embodiment of the present disclosure.
Figure 12 is a block diagram showing a system-on-chip according to an exemplary embodiment of the present disclosure.
Figure 13 is a block diagram showing a computing system including a memory for storing a program according to an exemplary embodiment of the present disclosure.

1 is a diagram showing the layout of an integrated circuit 10 according to an exemplary embodiment of the present disclosure. For example, the upper figure in FIG. 1 is a plan view showing the layout of the integrated circuit 10 as seen in the -Z-axis direction, and the lower figure in FIG. 1 shows the layout of the integrated circuit 10 along the line X1-X1'. It is a cross-sectional view showing a cross section cut along.

In this specification, the X-axis direction and the Y-axis direction may each be referred to as a horizontal direction, and the Z-axis direction may be referred to as a vertical direction. A plane consisting of the Orientationally placed components may be referred to as being below other components. Additionally, the area of a component may refer to the size occupied by the component in a plane parallel to the horizontal plane, and the width of the component may refer to the length in a direction perpendicular to the direction in which the component extends. The surface exposed in the +Z direction may be referred to as the top surface, the surface exposed in the -Z direction may be referred to as the bottom surface, and the surface exposed in the ±X or ±Y direction may be referred to as the top surface. It can be referred to as a side. For illustrative convenience, only some layers may be shown in the drawings, and a via connecting the upper pattern and lower pattern may be displayed in the upper pattern for understanding even though it is located below the upper pattern. Additionally, a pattern made of a conductive material, such as a pattern of a wiring layer, may be referred to as a conductive pattern, or may simply be referred to as a pattern.

Referring to FIG. 1, the integrated circuit 10 may include gate lines (or gate electrodes) extending in the X-axis direction and p-channel field effect transistor (PFET) regions extending in the Y-axis direction. and n-channel field effect transistor (NFET) regions. The pitch of the gate lines may be referred to as contact-poly-pitch (CPP). As will be described later with reference to FIGS. 2A to 2C, the portions that protrude in the +Z-axis direction and extend in the Y-axis direction in each of the PFET region and the NFET region may form a gate line and a transistor and will be referred to as an active pattern. You can. A source/drain may be formed on both sides of the gate line, a contact may be formed on the source/drain, and a channel may be formed between the sources/drains below the gate line. Examples of channels will be described below with reference to FIGS. 2A to 2D. A via of the first via layer (V0) may be disposed on the contact, and the via may be connected to the contact and the pattern of the first wiring layer (M1). For example, as shown in FIG. 1, via V1 may be connected to contact C1 and pattern M12. Source/drain (SD) may be connected to contact (C1). Although not shown in FIG. 1, at least one additional wiring layer may exist on the first wiring layer M1, and patterns may extend from the at least one wiring layer.

The integrated circuit 10 may include patterns extending in the Y-axis direction from the rear wiring layer below the substrate SUB. For example, as shown in FIG. 1, the first pattern BM11 in the backside metal layer BM may extend in the Y-axis direction under the PFET area. Additionally, the second pattern BM12 in the back metal layer BM may extend in the Y-axis direction under the NFET area. A backside interlayer dielectric (BILD) may be formed between the first pattern BM11 and the second pattern BM12.

The integrated circuit 10 may include a through silicon via that penetrates the substrate SUB in a vertical direction. The through silicon via may connect the pattern of the first wiring layer (M1) and the pattern of the back wiring layer. For example, as shown in FIG. 1, the through silicon via T1 may penetrate the substrate SUB, and the bottom surface connected to the first pattern BM11 of the rear wiring layer and the pattern of the first wiring layer M1 It may have an upper surface connected to (M11). Similarly, the integrated circuit 10 may include a through silicon via having a bottom surface connected to the second pattern BM12 of the rear wiring layer and an upper surface connected to the pattern M12 of the first wiring layer M1.

2A to 2D are diagrams showing examples of devices according to example embodiments of the present disclosure. For example, Figure 2A shows a FinFET (20a), Figure 2B shows a gate-all-around field effect transistor (GAAFET) 20b, and Figure 2C shows a multi-bridge channel field effect transistor (MBCFET) 20c. 2d shows a vertical field effect transistor (VFET) 20d. For ease of illustration, FIGS. 2A to 2C show one of the two source/drain regions removed, and FIG. 2D shows a view parallel to the plane consisting of the Y and Z axes and the channel of the VFET 20d ( Shows a cross section of the VFET (20d) cut through a plane passing through CH).

Referring to FIG. 2A, the FinFET 20a is formed by a fin-shaped active pattern extending in the X-axis direction between shallow trench isolations (STIs) and a gate (G) extending in the Y-axis direction. You can. Source/drain (S/D) may be formed on both sides of the gate (G), and accordingly, the source and drain may be spaced apart from each other in the X-axis direction. An insulating film may be formed between the channel (CH) and the gate (G). In some embodiments, FinFET 20a may be formed by a plurality of active patterns and a gate G that are spaced apart from each other in the Y-axis direction.

Referring to FIG. 2b, the GAAFET 20b is formed by active patterns, that is, nanowires, extending in the X-axis direction and spaced apart from each other in the Z-axis direction, and a gate (G) extending in the Y-axis direction. It can be. Source/drain (S/D) may be formed on both sides of the gate (G), and accordingly, the source and drain may be spaced apart from each other in the X-axis direction. An insulating film may be formed between the channel (CH) and the gate (G). Note that the number of nanowires included in GAAFET 20b is not limited to that shown in FIG. 2b.

Referring to FIG. 2C, the MBCFET 20c is formed by active patterns, that is, nanosheets, extending in the X-axis direction and spaced apart from each other in the Z-axis direction, and a gate (G) extending in the Y-axis direction. It can be. Source/drain (S/D) may be formed on both sides of the gate (G), and accordingly, the source and drain may be spaced apart from each other in the Y-axis direction. An insulating film may be formed between the channel (CH) and the gate (G). Note that the number of nanosheets included in the MBCFET 20c is not limited to that shown in FIG. 2c.

Referring to FIG. 2D, the VFET 20d has a top source/drain (T_S/D) and a bottom source/drain (B_S/) spaced apart from each other in the Z-axis direction with a channel (CH) in between. D) may be included. The VFET 20d may include a gate (G) surrounding the circumference of the channel (CH) between the upper source/drain (T_S/D) and the lower source/drain (B_S/D). An insulating film may be formed between the channel (CH) and the gate (G).

Hereinafter, the integrated circuit including the FinFET 20a or the MBCFET 20c will be mainly described, but it is noted that the elements included in the integrated circuit are not limited to the examples of FIGS. 2A to 2D. For example, the integrated circuit includes a ForkFET in which the nanosheets for the P-type transistor and the nanosheets for the N-type transistor have a structure in which the N-type transistor and the P-type transistor are closer together by being separated by a dielectric wall. can do. Additionally, the integrated circuit may include bipolar junction transistors as well as FETs, such as complementary field effect transistors (CFETs), negative capacitance field effect transistors (NCFETs), and carbon nanotube (CNT) FETs.

Figure 3 is a block diagram showing an integrated circuit according to an exemplary embodiment of the present disclosure. For example, the block diagram of FIG. 3 shows a memory device 30 included in an integrated circuit. In some embodiments, the memory device 30 may store data based on commands and addresses provided external to the integrated circuit, and the memory device 30 may be a standalone memory device. Additionally, in some embodiments, the integrated circuit may further include other components for writing data to or reading data from memory device 30, as described below with reference to FIG. 12. and the memory device 30 may be an embedded memory device. As shown in FIG. 3 , the memory device 30 may include a cell array 32, a row driver 34, a column driver 36, control logic 38, and a voltage generator 39. In the memory device 30, the components excluding the cell array 32, that is, the row driver 34, column driver 36, control logic 38, and voltage generator 39, are collectively considered peripheral circuits. can be referred to. Although not shown in FIG. 3, in some embodiments, the memory device 30 may further include an address buffer, a data buffer, and a data input/output circuit.

The memory device 30 can receive a command (CMD), an address, and data (DAT). For example, the memory device 30 may receive a command (CMD) instructing write, an address, and data (DAT), and store the received data (DAT) in the cell array 32 corresponding to the address. It can be saved in the area of . In addition, the memory device 30 can receive a command (CMD) instructing read and an address, and output data stored in an area of the cell array 32 corresponding to the address to the outside.

Cell array 32 may include a plurality of memory cells each accessed by a word line and a bit line. In some embodiments, the memory cells included in the cell array 32 may be volatile memory cells, such as static random access memory (SRAM), dynamic random access memory (DRAM), etc. In some embodiments, the memory cells included in the cell array 32 may be non-volatile memory cells, such as flash memory, resistive random access memory (RRAM), etc. Exemplary embodiments of the present disclosure will be described primarily with reference to an SRAM cell, as described below with reference to FIG. 5 and the like, but it is noted that the exemplary embodiments of the present disclosure are not limited thereto. In this specification, a memory cell may be simply referred to as a cell.

The row driver 34 may be connected to the cell array 32 through a plurality of word lines (WLs). The row driver 34 may activate one word line among the plurality of word lines WLs based on the row address A_ROW. Accordingly, among the memory cells included in the cell array 32, memory cells connected to the activated word line, that is, memory cells arranged in a row corresponding to the activated word line, may be selected. By the column driver 36, which will be described later, data DAT can be written into selected memory cells during a write operation, while data DAT can be read from the selected memory cells during a read operation.

The column driver 36 may be connected to the cell array 32 through a plurality of bit lines (BLs). The column driver 36 detects current and/or voltage received through a plurality of bit lines (BLs) during a read operation, thereby identifying values connected to the activated word line, that is, stored in selected memory cells. , data (DAT) can be output based on the identified values. Additionally, the column driver 36 may apply current and/or voltage to a plurality of bit lines BLs based on data DAT during a write operation, and may be connected to an activated word line, that is, selected memory cells. You can enter values in .

The control logic 38 may receive a command (CMD) and generate a first control signal (CTR1) and a second control signal (CTR2). For example, the control logic 38 may identify a read command by decoding the command CMD, and use the first control signal CTR1 and the second control signal to read data DAT from the cell array 32. A signal (CTR2) can be generated. In addition, the control logic 38 can identify the write command by decoding the command (CMD), and uses the first control signal (CTR1) and the second control signal (CTR1) to write data (DAT) to the cell array 32. CTR2) can be generated. In some embodiments, the row driver 34 may activate or deactivate the word line at a timing determined based on the first control signal CTR1. Additionally, in some embodiments, the column driver 36 detects the current and/or voltage in the plurality of bit lines BLs at a timing determined based on the second control signal CTR2, or detects the current and/or voltage in the plurality of bit lines BLs. Current and/or voltage may be applied to the BLs.

The voltage generator 39 may receive an external voltage (V_EXT) provided from outside the memory device 30, and other components of the memory device 30, such as the cell array 32 and the row driver 34. , the internal voltage (V_INT) can be provided to the column driver 36 and control logic 38. For example, the voltage generator 39 may receive the external cell voltage (VDDCE) as the external voltage (V_EXT) and generate the cell voltage (VDDC) from the external cell voltage (VDDCE). The cell voltage VDDC as the internal voltage V_INT may be provided to the cell array 32 and may provide power to a plurality of memory cells included in the cell array 32. Additionally, the voltage generator 39 may receive the external peripheral voltage (VDDPE) as the external voltage (V_EXT) and generate the peripheral voltage (VDDP) from the external peripheral voltage (VDDPE). The peripheral voltage (VDDP) as the internal voltage (V_INT) may be provided to peripheral circuits, such as the row driver 34, the column driver 36, and the control logic 38, and the row driver 34, the column driver 36 ) and can provide power to the control logic 38. The above-described external cell voltage (VDDCE), cell voltage (VDDC), external peripheral voltage (VDDPE), and peripheral voltage (VDDP) are voltages for power supply and may be referred to as positive supply voltages, and negative supply voltage (VSS) ) can be used for power supply.

In some embodiments, memory device 30 may include patterns extending from a rear wiring layer beneath the substrate. For example, as described above with reference to FIG. 1 , gate electrodes may extend over the substrate SUB, and patterns of the first wiring layer M1 may extend over the gate electrodes. Additionally, patterns may extend from the rear wiring layer under the gate electrodes or under the substrate (SUB). Patterns extending from the rear wiring layer can be used for routing of supply voltages or signals. Accordingly, routing resources in the memory device 30 may increase and the area of the memory device 30 may decrease. Additionally, parasitic components of wiring can be reduced, and performance of the memory device 30 can be increased.

Figure 4 is a plan view showing the layout of an integrated circuit according to an exemplary embodiment of the present disclosure. For example, the top view of Figure 4 shows the layout 40 corresponding to the memory device 30 of Figure 3. Hereinafter, FIG. 4 will be explained with reference to FIG. 3 .

The layout 40 may include at least one cell array in the cell area and may include peripheral circuitry in the peripheral area. For example, as shown in FIG. 4, the cell area may include a first cell array 41 and a second cell array 42, and the peripheral area may include a row driver 43 and a first column driver ( 44), a second column driver 45, control logic 46, and a voltage generator 47. In some embodiments, row driver 43, first column driver 44, second column driver 45, control logic 46, and voltage generator 47 are different from those shown in FIG. 4 in the peripheral area. It can be placed like this.

Patterns corresponding to the plurality of word lines (WLs) may extend parallel to each other in the X-axis direction in the first cell array 41 and the second cell array 42 and may be connected to the row driver 43. . Patterns corresponding to the plurality of bit lines BLs may extend parallel to each other in the Y-axis direction in the first cell array 41 and the second cell array 42, and may be connected to the first column driver 44 and the second cell array 42. It can be connected to a two-column driver (45). As described above with reference to FIG. 3, the patterns of the back wiring layer may extend under the substrate in the cell area and peripheral area.

Figure 5 is a circuit diagram showing a memory cell according to an exemplary embodiment of the present disclosure. For example, the circuit diagram of FIG. 5 shows an equivalent circuit 50 corresponding to four memory cells C11, C12, C21, and C22 arranged adjacent to each other in the cell array 32 of FIG. 3. As shown in FIG. 5, the memory cells C11, C12, C21, and C22 may have the same structure.

Referring to FIG. 5, the memory cell C11 and C12 arranged in the same row may be commonly connected to the word line WL[k], and the memory cell C21 and the memory arranged in the same row may be connected to the word line WL[k]. Cell C22 may be commonly connected to the word line WL[k+1] (k is an integer greater than 0). In addition, the memory cells C11 and C21 arranged in the same column may be connected to the first bit line BL1 and the first complementary bit line BLB1, and the memory cells arranged in the same column ( C12) and the memory cell C22 may be connected to the second bit line BL2 and the second complementary bit line BLB2.

Referring to FIG. 5, the memory cell C11 may include a first PFET (P11), a second PFET (P12), and first to fourth NFETs (N11 to N14), and may be a 6T (six transistors) SRAM cell. You can. The memory cell C11 may include a cross-coupled inverter pair between a node to which a cell voltage (VDDC) is applied and a node to which a negative supply voltage (or ground potential) (VSS) is applied. For example, of a cross-coupled inverter pair, the first inverter may include a first PFET (P11) and a first NFET (N11), and the second inverter may include a second PFET (P12) and a second NFET (N12). may include. In addition, the third NFET (N13) and the fourth NFET (N14) connect the first inverter and the second inverter to the first bit by the word line (WL[k]) that is activated (e.g., has a high level voltage). They may be referred to as pass transistors, configured to connect to line BL1 and first complementary bit line BLB1, respectively.

The memory cell C12 may include a first PFET (P21), a second PFET (P22), first to fourth NFETs (N21 to N24), and may be a 6T SRAM cell. The memory cell C21 may include a cross-coupled inverter pair between a node to which a cell voltage (VDDC) is applied and a node to which a negative supply voltage (or ground potential) (VSS) is applied. For example, of a cross-coupled inverter pair, the first inverter may include a first PFET (P21) and a first NFET (N21), and the second inverter may include a second PFET (P22) and a second NFET (N22). may include. In addition, the third NFET (N23) and the fourth NFET (N24) connect the first inverter and the second inverter to the second bit by the word line (WL[k]) that is activated (e.g., has a high level voltage). They may be referred to as pass transistors, configured to connect to line BL2 and second complementary bit line BLB2, respectively.

The memory cell C21 may include a first PFET (P31), a second PFET (P32), first to fourth NFETs (N31 to N34), and may be a 6T SRAM cell. The memory cell C21 may include a cross-coupled inverter pair between a node to which a cell voltage (VDDC) is applied and a node to which a negative supply voltage (or ground potential) (VSS) is applied. For example, of a cross-coupled inverter pair, the first inverter may include a first PFET (P31) and a first NFET (N31), and the second inverter may include a second PFET (P32) and a second NFET (N32). may include. In addition, the third NFET (N33) and the fourth NFET (N34) connect the first inverter and the second inverter to the first bit by the word line (WL[k]) that is activated (e.g., has a high level voltage). They may be referred to as pass transistors, configured to connect to line BL1 and first complementary bit line BLB1, respectively.

The memory cell C22 may include a first PFET (P41), a second PFET (P42), first to fourth NFETs (N41 to N44), and may be a 6T SRAM cell. The memory cell C41 may include a cross-coupled inverter pair between a node to which a cell voltage (VDDC) is applied and a node to which a negative supply voltage (or ground potential) (VSS) is applied. For example, of a cross-coupled inverter pair, the first inverter may include a first PFET (P41) and a first NFET (N41), and the second inverter may include a second PFET (P42) and a second NFET (N42). may include. In addition, the third NFET (N43) and the fourth NFET (N44) connect the first inverter and the second inverter to the second bit by the word line (WL[k]) that is activated (e.g., has a high level voltage). They may be referred to as pass transistors, configured to connect to line BL2 and second complementary bit line BLB2, respectively.

When a voltage drop occurs at the node to which the cell voltage (VDDC) is applied or the node to which the negative supply voltage (VSS) is applied, the memory cell (C11) provides a signal corresponding to the value latched in the cross-coupled inverter pair. 1 may not be properly output to the bit line (BL1) and the first complementary bit line (BLB1), and a value corresponding to the signal applied to the first bit line (BL1) and the first complementary bit line (BLB1) may not properly latch onto a cross-coupled inverter pair. Additionally, as the number of memory cells included in one row increases, the word line WL[k] may be extended, and the influence of parasitic resistance of the word line WL[k] may increase. Accordingly, a memory cell located far from the row driver 34 of FIG. 3 may identify activation of the word line at a delayed time, and the operation speed of the memory device 30 of FIG. 3 may be limited.

6A and 6B are plan views showing the layout 60 of an integrated circuit according to example embodiments of the present disclosure. For example, the plan views of FIGS. 6A and 6B show memory cells C11', C12', and C21 respectively corresponding to the four memory cells C11, C12, C21, and C22 included in the equivalent circuit 50 of FIG. 5. ', C22'). The top view of FIG. 6A shows some of the layers above the substrate in layout 60, and the top view of FIG. 6B shows the back wiring layer below the substrate in layout 60. In FIGS. 6A and 6B , the names written on the patterns indicate the voltage applied to the lines and/or patterns to which the corresponding patterns are electrically connected. For convenience of illustration, the illustration of source/drain is omitted in FIG. 5A. It is noted that the equivalent circuit 50 of Figure 5 is not limited to the layout 60 of Figures 6A and 6B.

Referring to FIG. 6A, four memory cells C11', C12', C21', and C22' may have the same footprint. Footprint can refer to the space occupied by a component in a plane. That is, the four memory cells (C11', C12', C21', and C22') may have the same area, the same horizontal length (or the same length in the X-axis direction) and the same vertical length (or the same length in the Y-axis direction). length). Memory cells C11' and C12' arranged in the same row may be commonly connected to the word line WL[k]. Memory cells C21' and C22' arranged in the same row may be commonly connected to the word line WL[k+1]. Memory cells C11' and C21' arranged in the same column may be commonly connected to the first bit line BL1 and the first complementary bit line BLB1. Memory cells C12' and C22' arranged in the same column may be commonly connected to the second bit line BL2 and the second complementary bit line BLB2.

The memory cell C11' may include an NFET area and a PFET area extending in the Y-axis direction. For example, as shown in FIG. 6A, NFET regions may extend in the Y-axis direction between PFET regions that extend in the Y-axis direction of the memory cell C11'. The memory cell C11' may include a gate electrode extending in the X-axis direction. The gate electrode may form NFETs in the NFET region, that is, the first to fourth NFETs (N11 to N14) of FIG. 5, and may form PFETs in the PFET region, that is, the first and second PFETs (P11, P12) can be formed. Sources/drains may be formed on both sides of the gate electrode, and the source/drain may be connected to the pattern of the M1 layer through contacts (which may be referred to as source/drain contacts) and vias. The gate electrode may be connected to the pattern of the M1 layer through contacts (may be referred to as gate contacts) and vias.

The memory cell C12' may include an NFET area and a PFET area extending in the Y-axis direction. For example, as shown in FIG. 6A, NFET regions may extend in the Y-axis direction between PFET regions that extend in the Y-axis direction of the memory cell C12'. The memory cell C12' may include a gate electrode extending in the X-axis direction. The gate electrode may form NFETs in the NFET region, that is, the first to fourth NFETs (N21 to N24) of FIG. 5, and may form PFETs in the PFET region, that is, the first and second PFETs (P21, P22) can be formed. Sources/drains may be formed on both sides of the gate electrode, and the source/drain may be connected to the pattern of the M1 layer through contacts and vias. The gate electrode may be connected to the pattern of the M1 layer through contacts and vias.

The memory cell C21' may include an NFET area and a PFET area extending in the Y-axis direction. For example, as shown in FIG. 6A, NFET regions may extend in the Y-axis direction between PFET regions that extend in the Y-axis direction of the memory cell C21'. The memory cell C21' may include a gate electrode extending in the X-axis direction. The gate electrode may form NFETs in the NFET region, that is, the first to fourth NFETs (N31 to N34) of FIG. 5, and may form PFETs in the PFET region, that is, the first and second PFETs (P31, P32) can be formed. Sources/drains may be formed on both sides of the gate electrode, and the source/drain may be connected to the pattern of the M1 layer through contacts and vias. The gate electrode may be connected to the pattern of the M1 layer through contacts and vias.

The memory cell C22' may include an NFET area and a PFET area extending in the Y-axis direction. For example, as shown in FIG. 6A, NFET regions may extend in the Y-axis direction between PFET regions that extend in the Y-axis direction of the memory cell C22'. The memory cell C22' may include a gate electrode extending in the X-axis direction. The gate electrode may form NFETs in the NFET region, that is, the first to fourth NFETs (N41 to N44) of FIG. 5, and may form PFETs in the PFET region, that is, the first and second PFETs (P41, P42) can be formed. Sources/drains may be formed on both sides of the gate electrode, and the source/drain may be connected to the pattern of the M1 layer through contacts and vias. The gate electrode may be connected to the pattern of the M1 layer through contacts and vias.

In some embodiments, memory cells included in layout 60 may have layouts that are flipped to each other. For example, the layout of the memory cell C11' may be symmetrical to the layout of the memory cell C12' around the boundary between the memory cells C11' and C12'. That is, the layout of the memory cell C11' may correspond to a layout in which the layout of the memory cell C12' is flipped around an axis parallel to the Y axis. Additionally, the layout of the memory cell C11' may be symmetrical to the layout of the memory cell C21' around the boundary between the memory cells C11' and C21'. That is, the layout of the memory cell C11' may correspond to a layout in which the layout of the memory cell C21' is flipped around an axis parallel to the X-axis. Additionally, the layout of the memory cell C12' may be symmetrical to the layout of the memory cell C22' around the boundary between the memory cells C12' and C22'. That is, the layout of the memory cell C12' may correspond to a layout in which the layout of the memory cell C22' is flipped around an axis parallel to the X-axis.

Referring to FIG. 6B, patterns to which a negative supply voltage (VSS) is applied may be extended in the rear wiring layer under the substrate of FIG. 5A. For example, as shown in FIG. 6B, the first to third patterns BM11, BM12, and BM13 may extend parallel to each other in the Y-axis direction, and the first to third patterns BM11, BM12, and BM13 may extend parallel to each other in the Y-axis direction. ) A negative supply voltage (VSS) may be applied. As described above with reference to FIG. 1 , through-silicon vias may be disposed on the first to third patterns BM11, BM12, and BM13, and memory cells may receive a negative supply voltage (VSS) through the through-silicon vias. can be supplied.

7A to 7E are plan views showing layouts of integrated circuits according to example embodiments of the present disclosure. For example, the plan views of FIGS. 7A to 7E show patterns of a rear wiring layer to which a supply voltage is applied in the cell region CR and the peripheral region PR. As described above with reference to FIG. 3, the cell voltage VDDC as the positive supply voltage may be generated from the external cell voltage VDDCE, and the peripheral voltage VDDP as the positive supply voltage may be generated from the external peripheral voltage VDDPE. can be created from

Referring to FIG. 7A, the layout 70a may include a cell region (CR) and a peripheral region (PR) adjacent to each other in the Y-axis direction. The layout 70a may include patterns of a rear wiring layer extending in the Y-axis direction in the cell region CR and/or the peripheral region PR. In some embodiments, patterns of the rear wiring layer to which the negative supply voltage VSS is applied may extend continuously in the cell region CR and the peripheral region PR. For example, as shown in FIG. 7A, the first pattern (BM01), the third pattern (BM03), the fourth pattern (BM04), and the sixth pattern (BM06) to which the negative supply voltage (VSS) is applied are It may extend in the Y-axis direction parallel to each other in the cell region (CR) and peripheral region (PR). As shown in FIG. 7A, the second pattern BM02 and the fifth pattern BM05 to which the negative supply voltage VSS is applied in the cell region CR are parallel to each other in the Y-axis direction in the cell region CR. can be extended to Additionally, patterns of the rear wiring layer to which the external cell voltage (VDDCE) or external peripheral voltage (VDDPE) is applied in the peripheral area (PR) may extend in the Y-axis direction.

Referring to FIG. 7B, the layout 70b may include a cell region (CR) and a peripheral region (PR) adjacent to each other in the Y-axis direction. The layout 70b may include patterns of a rear wiring layer extending in the Y-axis direction in the cell region CR and/or the peripheral region PR. In some embodiments, patterns of the rear wiring layer to which the cell voltage VDDC is applied may extend continuously in the cell region CR and the peripheral region PR. For example, as shown in FIG. 7B, the second pattern BM02 and the fifth pattern BM05 to which the cell voltage VDDC is applied are parallel to each other in the cell region CR and the peripheral region PR. It may extend axially. As shown in FIG. 7B, the first pattern (BM01), the third pattern (BM03), the fourth pattern (BM04), and the sixth pattern (BM06) to which the negative supply voltage (VSS) is applied are the cell region (CR). ) and the peripheral region (PR) may extend parallel to each other in the Y-axis direction. Additionally, patterns of the rear wiring layer to which the external cell voltage (VDDCE) or external peripheral voltage (VDDPE) is applied in the peripheral area (PR) may extend in the Y-axis direction.

Referring to FIG. 7C, the layout 70c may include a cell region (CR) and a peripheral region (PR) adjacent to each other in the Y-axis direction. The layout 70c may include patterns of a rear wiring layer extending in the Y-axis direction in the cell region CR and/or the peripheral region PR. In some embodiments, patterns of the rear wiring layer to which the negative supply voltage (VSS) is applied may extend in the cell region (CR). For example, as shown in FIG. 7C, the first to sixth patterns BM01 to BM06 to which the negative supply voltage VSS is applied may extend in the Y-axis direction parallel to each other only in the cell region CR. there is. As shown in FIG. 7C, the patterns of the rear wiring layer to which the external cell voltage (VDDCE), external peripheral voltage (VDDPE), or negative supply voltage (VSS) are applied in the peripheral region (PR) may extend in the Y-axis direction. there is.

Referring to FIG. 7D, the layout 70d may include a cell region (CR) and a peripheral region (PR) adjacent to each other in the Y-axis direction. The layout 70d may include patterns of a rear wiring layer extending in the Y-axis direction in the cell region CR and/or the peripheral region PR. In some embodiments, the patterns of the rear wiring layer to which the negative supply voltage (VSS) is applied may extend continuously in the Y-axis direction in the cell region (CR) and the peripheral region (PR) and in the cell region (CR) It may extend in the X-axis direction. For example, as shown in FIG. 7D, the pattern BM10 may include a portion continuously extending in the Y-axis direction in the cell region CR and the peripheral region PR. The pattern BM10 may include a portion extending in the Y-axis direction and a portion extending in the X-axis direction in the cell region CR. Accordingly, as shown in FIG. 7D, the pattern BM10 may have a mesh shape in the cell region CR. As shown in FIG. 7D, patterns of the rear wiring layer to which the external cell voltage (VDDCE) or external peripheral voltage (VDDPE) is applied in the peripheral area (PR) may extend in the Y-axis direction.

Referring to FIG. 7E, the layout 70e may include a cell region (CR) and a peripheral region (PR) adjacent to each other in the Y-axis direction. The layout 70e may include patterns of a rear wiring layer extending in the Y-axis direction in the cell region CR and/or the peripheral region PR. In some embodiments, patterns of the rear wiring layer to which the negative supply voltage VSS is applied may extend in the Y-axis direction and the X-axis direction in the cell region CR. For example, as shown in FIG. 7E, the pattern BM10 may include a portion extending in the Y-axis direction from the cell region CR and continuously extending in the X-axis direction from the cell region CR. Parts may be included. Accordingly, as shown in FIG. 7E, the pattern BM10 may have a mesh shape in the cell region CR. As shown in FIG. 7e, the patterns of the rear wiring layer to which the external cell voltage (VDDCE), external peripheral voltage (VDDPE), or negative supply voltage (VSS) are applied in the peripheral region (PR) may extend in the Y-axis direction. there is.

8A to 8E are plan views showing layouts of integrated circuits according to example embodiments of the present disclosure. For example, the top views of FIGS. 8A to 8E show patterns of the rear wiring layer and through silicon vias in the cell region (CR) and peripheral region (PR). In FIGS. 8A-8E the through silicon via is shown for illustration purposes despite the patterns of the backside interconnection layer.

The cell area CR may include a bit cell area and a dummy area. The bit cell area may include memory cells, as described above with reference to FIGS. 6A and 6B. The dummy area may be outside the bit cell area and may include dummy cells and/or tap cells. A tap cell may bias the substrate or well, and a dummy cell may be adjacent to the tap cell. In some embodiments, dummy cells and tap cells can have the same footprint as a memory cell. That is, the dummy cell and the tap cell may have the same area as the memory cell, and may have the same horizontal length and the same vertical length. In this specification, cells placed in the dummy area, that is, dummy cells and tap cells, may be collectively referred to as dummy cells.

The peripheral area PR may include a row driver, and as described above with reference to FIG. 3, the row driver may be connected to a plurality of word lines extending from the cell area CR. A control signal commonly provided to cells arranged in the same row in the cell region CR may be applied to the pattern of the rear wiring layer. For example, the patterns of the rear wiring layer may correspond to a plurality of word lines (WLs). As described above with reference to FIG. 1, the pattern of the rear wiring layer may be connected to the pattern of the first wiring layer (M1) through a through silicon via, and accordingly, the pattern of the rear wiring layer may be connected to the first wiring layer (M1) or the first wiring layer (M1). The pattern corresponding to the word line extending from the upper second wiring layer of the wiring layer M1 may be extended in parallel with each other, and thus the parasitic resistance of the word line may be reduced.

Referring to FIG. 8A, the layout 80a may include a cell region (CR) and a peripheral region (PR) adjacent to each other in the X-axis direction. Patterns of the rear wiring layer corresponding to the plurality of word lines may extend in the X-axis direction in the cell region CR. In some embodiments, a plurality of through silicon vias may be connected to patterns of the rear interconnection layer outside the dummy area. For example, as shown in FIG. 8A, the patterns of the rear wiring layer may extend in the X-axis direction through the bit cell area and the dummy area, and through silicon vias may be connected to the patterns of the rear wiring layer outside the dummy area. there is. The through silicon vias may be connected to the patterns of the first wiring layer (M1), and the row driver may be connected to the patterns of the first wiring layer (M1).

Referring to FIG. 8B, the layout 80b may include a cell region (CR) and a peripheral region (PR) adjacent to each other in the X-axis direction. Patterns of the rear wiring layer corresponding to the plurality of word lines may extend in the X-axis direction in the cell region CR. In some embodiments, a plurality of through silicon vias may be connected to patterns of the rear wiring layer in the dummy area. For example, as shown in FIG. 8B, the patterns of the rear wiring layer may extend in the X-axis direction through the bit cell area and the dummy area, and through silicon vias may be connected to the patterns of the rear wiring layer in the dummy area. there is. The through silicon vias may vertically penetrate the dummy cells and/or tab cells of the dummy area and may be connected to patterns of the first wiring layer M1. The row driver may be connected to the patterns of the first wiring layer (M1).

Referring to FIG. 8C, the layout 80c may include a cell region (CR) and a peripheral region (PR) adjacent to each other in the X-axis direction. Patterns of the rear wiring layer corresponding to the plurality of word lines may continuously extend in the X-axis direction in the peripheral area PR and cell area CR. In some embodiments, the plurality of through silicon vias may be connected to the patterns of the back wiring layer in the peripheral region PR and may be connected to the patterns of the back wiring layer outside the dummy region. For example, as shown in FIG. 8C, through-silicon vias may be connected to the patterns of the back wiring layer in the peripheral region PR, and the row driver may be connected to the patterns of the back wiring layer through the through-silicon vias. Additionally, through silicon vias may be connected to patterns of the back wiring layer outside the dummy area of the cell region CR.

Referring to FIG. 8D, the layout 80d may include a cell region (CR) and a peripheral region (PR) adjacent to each other in the X-axis direction. Patterns of the rear wiring layer corresponding to the plurality of word lines may continuously extend in the X-axis direction in the peripheral area PR and cell area CR. In some embodiments, the plurality of through silicon vias may be connected to the patterns of the rear wiring layer in the peripheral area PR and may be connected to the patterns of the rear wiring layer in the dummy region. For example, as shown in FIG. 8D, through-silicon vias may be connected to the patterns of the back wiring layer in the peripheral region PR, and the row driver may be connected to the patterns of the back wiring layer through the through-silicon vias. Additionally, through silicon vias may be connected to patterns of the back wiring layer in the dummy area of the cell region CR.

Referring to FIG. 8E, the layout 80e may include a cell region (CR) and a peripheral region (PR) adjacent to each other in the X-axis direction. The cell area CR may include a dummy area, and may include a first bit cell area BCR1 and a second bit cell area BCR2 spaced apart from each other in the X-axis direction. The patterns of the rear wiring layer corresponding to the plurality of word lines extend in the X-axis direction parallel to each other from the cell region CR through the dummy region, the first bit cell region BCR1, and the second bit cell region BCR2. It can be. In some embodiments, a plurality of through silicon vias may be connected to patterns of the rear wiring layer in the dummy area. For example, as shown in FIG. 8E, through-silicon vias may be connected to patterns of the rear wiring layer in a dummy area adjacent to the edge of the cell region CR, and in the first bit cell region BCR1 and the second bit cell region BCR1. The dummy area between the bit cell area (BCR2) may be connected to the patterns of the rear wiring layer. Accordingly, the parasitic resistance of the word line crossing the first bit cell area (BCR1) and the second bit cell area (BCR2) may be reduced.

9A and 9B are plan views showing layouts of integrated circuits according to example embodiments of the present disclosure. For example, the top views of FIGS. 9A and 9B show layouts 90a and 90b corresponding to memory device 30 of FIG. 3 . The plan views of FIGS. 9A and 9B show only the patterns of the rear wiring layer included in the cell area for illustration convenience. However, in some embodiments, as described above with reference to FIGS. 7A to 7E, etc., the rear wiring layer is formed in the peripheral area. It is noted that patterns can be extended.

Referring to FIG. 9A, the layout 90a may include a first cell array 91 and a second cell array 92 in the cell area, and a row driver 93 and a first column driver 94 in the peripheral area. ) and a second column driver 95. The layout 90a may include patterns of a rear wiring layer to which a supply voltage, for example, a negative supply voltage (VSS) is applied, below the cell array. For example, as in the example described above with reference to FIG. 7E , the layout 90a includes the patterns of the rear wiring layer extending below the first cell array 91 and the rear wiring layer extending below the second cell array 90a. It may include patterns of wiring layers. In some embodiments, the layout 90a includes a back wiring layer extending in the Y-axis direction under the first cell array 91 and the second cell array 90a, as described above with reference to FIGS. 9A to 9D. It may also include patterns.

Referring to FIG. 9B, the layout 90b may include a first cell array 91 and a second cell array 92 in the cell area, and a row driver 93 and a first column driver 94 in the peripheral area. ) and a second column driver 95. Layout 90a may include patterns of a rear wiring layer corresponding to word lines beneath the cell array. For example, as in the examples described above with reference to FIGS. 8A and 8B, the layout 90b includes patterns of the rear wiring layer and a pattern of the rear wiring layer extending in the X-axis direction below the first cell array 91. It may include through-silicon vias connected to the fields. Additionally, the layout 90b may include patterns of the back wiring layer extending in the X-axis direction under the second cell array 91 and through silicon vias connected to the patterns of the back wiring layer. In some embodiments, layout 90b may include patterns of a rear wiring layer extending into row driver 93, as described above with reference to FIGS. 8C and 8D, and disposed on row driver 93. May include through silicon vias. Additionally, in some embodiments, each of the first cell array 91 and the second cell array 92 may include two or more cell arrays spaced apart from each other, as described above with reference to FIG. 8E, Through silicon vias may be disposed between cell arrays spaced apart from each other.

10 is a flowchart illustrating a method for manufacturing an integrated circuit (IC) according to an example embodiment of the present disclosure. Specifically, the flowchart of FIG. 10 shows an example of a method for manufacturing an integrated circuit (IC) containing standard cells. A standard cell (standard ell) is a unit of layout included in an integrated circuit and may be designed to perform a predefined function. As shown in FIG. 10, a method for manufacturing an integrated circuit (IC) may include a plurality of steps S10, S30, S50, S70, and S90.

The cell library (or standard cell library) D12 may include information about standard cells, such as information about functions, characteristics, layout, etc. In some embodiments, the cell library D12 may define tap cells and dummy cells as well as functional cells that generate an output signal from an input signal. In some embodiments, the cell library D12 may define memory cells and dummy cells having the same footprint.

Design rules (D14) may include requirements that the layout of an integrated circuit (IC) must comply with. For example, the design rule D14 may include requirements for the distance (space) between patterns in the same layer, the minimum width of the pattern, the routing direction of the wiring layer, etc. In some embodiments, design rule D14 may define a minimum separation distance within the same track of the wiring layer.

In step S10, a logical synthesis operation may be performed to generate netlist data (D13) from RTL data (D11). For example, a semiconductor design tool (e.g., a logic synthesis tool) synthesizes logic by referencing a cell library (D12) from RTL data (D11) written in a Hardware Description Language (HDL) such as VHSIC Hardware Description Language (VHDL) and Verilog. can be performed, and netlist data D13 including a bitstream or netlist can be generated. Netlist data D13 may correspond to input of place and routing, which will be described later.

In step S30, standard cells may be deployed. For example, a semiconductor design tool (eg, P&R tool) may place standard cells used in the netlist data D13 with reference to the cell library D12. In some embodiments, a semiconductor design tool may place standard cells in a row extending in an X-axis direction or a Y-axis direction, and the placed standard cells may receive power from a power rail extending along row boundaries. there is.

In step S50, pins of standard cells may be routed. For example, a semiconductor design tool can generate interconnections that electrically connect the output pins and input pins of placed standard cells, and layout data (D15) defining the placed standard cells and the created interconnections. ) can be created. The interconnections may include patterns of vias and/or interconnection layers of via layers. The wiring layers may include a rear wiring layer located below the gate electrode as well as a wiring layer located above the gate electrode, such as the first wiring layer M1. The layout data D15 may have a format, for example GDSII, and may include geometric information of cells and interconnections. The semiconductor design tool can refer to the design rule (D14) while routing the pins of the cells. Layout data D15 may correspond to the output of placement and routing. An example of step S50 will be described later with reference to FIG. 11. Step S50 alone, or steps S30 and S50 collectively, may be referred to as a method for designing an integrated circuit.

In step S70, the operation of fabricating a mask can be performed. For example, in photolithography, optical proximity correction (OPC) to correct distortion such as refraction due to the characteristics of light may be applied to the layout data D15. Patterns on a mask may be defined to form patterns arranged in a plurality of layers based on OPC applied data, and at least one mask (or photomask) may be manufactured to form patterns in each of the plurality of layers. You can. In some embodiments, the layout of the integrated circuit (IC) may be limitedly modified in step S70, and the limited modification of the integrated circuit (IC) in step S70 may be performed after optimizing the structure of the integrated circuit (IC). As a treatment, it may be referred to as design polishing.

In step S90, an operation of manufacturing an integrated circuit (IC) may be performed. For example, an integrated circuit (IC) may be manufactured by patterning a plurality of layers using at least one mask fabricated in step S70. Front-end-of-line (FEOL) includes, for example, planarizing and cleaning the wafer, forming a trench, forming a well, forming a gate electrode, source And it may include forming a drain. By FEOL, individual elements such as transistors, capacitors, resistors, etc. can be formed on the substrate. Additionally, back-end-of-line (BEOL) may include, for example, siliciding the gate, source, and drain regions, adding a dielectric, planarizing, forming holes, and adding a metal layer. , forming a via, forming a passivation layer, etc. By BEOL, individual elements such as transistors, capacitors, resistors, etc. can be interconnected. In some embodiments, middle-of-line (MOL) may be performed between FEOL and BEOL and contacts may be formed on the individual devices. The integrated circuit (IC) can then be packaged in a semiconductor package and used as a component in a variety of applications.

Figure 11 is a flowchart showing a method of designing an integrated circuit according to an example embodiment of the present disclosure. For example, the flow chart in FIG. 11 shows an example of step S50 in FIG. 10. As described above with reference to FIG. 10, pins may be routed in step S50' of FIG. 11. As shown in FIG. 11, step S50' may include steps S51 and S52.

Referring to FIG. 11, a pattern may be created in the rear wiring layer in step S51. For example, a semiconductor design tool can use the backside wiring layer as a routing resource to route pins. Accordingly, the back wiring layer can be used for routing power pins for power supply as well as input pins and output pins of standard cells. Due to the increased routing resources, routing congestion can be eliminated, interconnections can be simplified, and signal paths can be shortened as a result.

In step S52, a through silicon via may be placed. For example, the semiconductor design tool may place a through silicon via to connect the pattern of the rear wiring layer created in step S51 to the pattern of the first wiring layer (M1). In some embodiments, as described above with reference to FIGS. 8A-8E, the through silicon via may be placed outside the bit cell array. In some embodiments, the through silicon via may penetrate the dummy cell in a vertical direction.

Figure 12 is a block diagram showing a system-on-chip 120 according to an exemplary embodiment of the present disclosure. System on Chip (SoC) 120 may refer to an integrated circuit that integrates components of a computing system or other electronic system. For example, an application processor (AP) as an example of system-on-chip 120 may include a processor and components for other functions. As shown in Figure 12, the system-on-chip 120 includes a core 121, a digital signal processor (DSP) 122, a graphics processing unit (GPU) 123, a built-in memory 124, and a communication interface. It may include 125 and a memory interface 126. Components of system-on-chip 120 may communicate with each other through bus 127.

The core 121 can process instructions and control the operation of components included in the system-on-chip 120. For example, the core 121 can drive an operating system and run applications on the operating system by processing a series of instructions. The DSP 122 may generate useful data by processing digital signals, for example, digital signals provided from the communication interface 125. The GPU 123 may generate data for an image output through a display device from image data provided from the built-in memory 124 or the memory interface 126, and may encode the image data. In some embodiments, the memory device described above with reference to the drawings may be included in the core 121, DSP 122, and/or GPU 123 as a cache memory and/or buffer. Accordingly, due to the high reliability and efficiency of the memory device, the core 121, DSP 122, and/or GPU 123 may also have high reliability and efficiency.

The built-in memory 124 can store data necessary for the core 121, DSP 122, and GPU 123 to operate. In some embodiments, embedded memory 124 may include a memory device described above with reference to the figures. Accordingly, the built-in memory 124 can have a reduced area and high efficiency, and as a result, the operational reliability and efficiency of the system-on-chip 120 can be improved.

The communication interface 125 may provide an interface for a communication network or one-to-one communication. The memory interface 126 may provide an interface to external memory of the system-on-chip 120, such as dynamic random access memory (DRAM) and flash memory.

FIG. 13 is a block diagram illustrating a computing system 130 including a memory for storing a program according to an exemplary embodiment of the present disclosure. A method of designing an integrated circuit, according to example embodiments of the present disclosure, such as at least some of the steps in the flowchart described above, may be performed on a computing system (or computer) 130.

Computing system 130 may be a stationary computing system, such as a desktop computer, workstation, server, etc., or a portable computing system, such as a laptop computer. As shown in FIG. 13, the computing system 130 includes a processor 131, input/output devices 132, a network interface 133, random access memory (RAM) 134, and read only memory (ROM) 135. ) and a storage device 136. The processor 131, input/output devices 132, network interface 133, RAM 134, ROM 135, and storage device 136 may be connected to the bus 137 and communicate with each other through the bus 137. Can communicate.

The processor 131 may be referred to as a processing unit, for example, a microprocessor (micro-processor), an application processor (AP), a digital signal processor (DSP), or a graphic processing unit (GPU), such as any instruction set (e.g., It may include at least one core capable of executing IA-32 (Intel Architecture-32), 64-bit extensions IA-32, x86-64, PowerPC, Sparc, MIPS, ARM, IA-64, etc.). For example, the processor 131 can access memory, that is, RAM 134 or ROM 135, through the bus 137 and execute instructions stored in RAM 134 or ROM 135.

The RAM 134 may store a program 134_1 or at least a portion thereof for a method of designing an integrated circuit according to an exemplary embodiment of the present disclosure, and the program 134_1 allows the processor 131 to use the integrated circuit. It is possible to perform at least some of the steps included in the method of designing, for example, the methods of FIG. 10. That is, the program 134_1 may include a plurality of instructions executable by the processor 131, and the plurality of instructions included in the program 134_1 allow the processor 131 to execute, for example, the instructions included in the above-described flowcharts. You can have at least some of the steps performed.

The storage device 136 may not lose stored data even if power supplied to the computing system 130 is cut off. For example, storage device 136 may include a non-volatile memory device or may include a storage medium such as magnetic tape, optical disk, or magnetic disk. Additionally, storage device 136 may be removable from computing system 130. The storage device 136 may store the program 134_1 according to an exemplary embodiment of the present disclosure, and the program 134_1 or At least part of it may be loaded into RAM 134. Alternatively, the storage device 136 may store a file written in a program language, and the program 134_1 or at least a portion thereof generated from the file by a compiler or the like may be loaded into the RAM 134. Additionally, as shown in FIG. 13, the storage device 136 may store a database 136_1, and the database 136_1 may store information necessary for designing an integrated circuit, such as information on designed blocks, the cell of FIG. 10 It may include a library (D12) and/or design rules (D14).

The storage device 136 may store data to be processed by the processor 131 or data processed by the processor 131. That is, the processor 131 may generate data by processing data stored in the storage device 136 according to the program 134_1, and may store the generated data in the storage device 136. For example, the storage device 136 may store RTL data D11, netlist data D13, and/or layout data D15 of FIG. 10 .

The input/output devices 132 may include an input device such as a keyboard, a pointing device, etc., and may include an output device such as a display device, a printer, etc. For example, a user may trigger execution of program 134_1 by processor 131 through input/output devices 132, RTL data D11 and/or netlist data D13 of FIG. 10. You can also input and check the layout data (D15) of FIG. 10.

Network interface 133 may provide access to a network external to computing system 130. For example, a network may include multiple computing systems and communication links, which may include wired links, optical links, wireless links, or any other type of links.

As above, exemplary embodiments have been disclosed in the drawings and specification. Although embodiments have been described in this specification using specific terminology, this is only used for the purpose of explaining the technical idea of the present disclosure and is not used to limit the meaning or scope of the present disclosure as set forth in the patent claims. . Therefore, those skilled in the art will understand that various modifications and other equivalent embodiments are possible therefrom.

Claims (20)

A cell area where a plurality of cells are arranged; and
It includes a peripheral area where a circuit for controlling the plurality of cells is placed,
The cell area is,
a plurality of first gate lines extending over the substrate;
a plurality of first patterns extending from a first wiring layer over the plurality of first gate lines;
a plurality of second patterns extending in a first horizontal direction on a rear wiring layer below the substrate; and
Includes a plurality of first vias each penetrating the substrate in a vertical direction,
Each of the plurality of first vias has an upper surface connected to one of the plurality of first patterns and a lower surface connected to one of the plurality of second patterns. In claim 1,
The plurality of second patterns include at least one second pattern configured to receive a first supply voltage provided to the plurality of cells. In claim 2,
The integrated circuit, wherein the at least one second pattern extends to the peripheral area in the first horizontal direction. In claim 2,
The cell region further includes a plurality of third patterns extending in a second horizontal direction orthogonal to the first horizontal direction in the rear wiring layer,
An integrated circuit, wherein the plurality of third patterns are connected to the plurality of second patterns. In claim 2,
The plurality of second patterns further include at least one second pattern configured to receive a second supply voltage provided to the plurality of cells and extending to the peripheral area. In claim 5,
wherein the peripheral area includes circuitry configured to generate the second supply voltage from an external supply voltage provided outside the peripheral area. In claim 1,
The surrounding area is,
a plurality of second gate lines extending over the substrate;
a plurality of fourth patterns extending from a first wiring layer over the plurality of second gate lines;
a plurality of fifth patterns extending from the rear wiring layer in the first horizontal direction; and
Includes a plurality of second vias penetrating the substrate in a vertical direction,
An integrated circuit, wherein each of the plurality of second vias is connected to one of the plurality of fourth patterns and one of the plurality of fifth patterns. In claim 7,
The plurality of fifth patterns include at least one fifth pattern configured to receive an external supply voltage provided from outside the peripheral area. In claim 1,
Each of the plurality of second patterns is configured to receive a control signal commonly provided to cells arranged in a row extending in the first horizontal direction among the plurality of cells. In claim 9,
The plurality of second patterns extend to the peripheral area,
The peripheral area includes a plurality of third vias that penetrate the substrate in a vertical direction and are connected to the plurality of second patterns. A cell area where a plurality of cells are arranged; and
It includes a peripheral area where a circuit for controlling the plurality of cells is placed,
The cell area is,
a plurality of first gate lines extending over the substrate;
a plurality of first patterns extending from a first wiring layer over the plurality of first gate lines; and
A plurality of second patterns extending in a first horizontal direction in a rear wiring layer below the substrate,
Each of the plurality of second patterns is configured to receive a control signal commonly provided to cells arranged in a row extending in the first horizontal direction among the plurality of cells. In claim 11,
The cell region further includes a plurality of vias, each vertically penetrating the substrate and each connected to the plurality of second patterns. In claim 12,
The integrated circuit further includes a plurality of vias that penetrate the substrate in a vertical direction in a region of the cell region excluding the plurality of cells and are respectively connected to the plurality of second patterns. In claim 13,
The cell area is,
at least one bit cell area in which bit cells among the plurality of cells are disposed; and
Includes a dummy area in which dummy cells are arranged among the plurality of cells,
The dummy area is an integrated circuit comprising the plurality of vias. In claim 14,
The at least one bit cell area includes a first bit cell area and a second bit cell area,
The plurality of second patterns penetrate the first bit cell area and the second bit cell area in the first horizontal direction,
The plurality of vias are disposed between the first bit cell area and the second bit cell area in the dummy area. In claim 14,
The plurality of second patterns extend to the peripheral area in the first horizontal direction,
The peripheral area further includes a plurality of vias, each vertically penetrating the substrate and each connected to the plurality of second patterns. A cell area where a plurality of cells are arranged; and
It is adjacent to the cell area and includes a peripheral area where a circuit for controlling the plurality of cells is disposed,
The cell area is,
a plurality of first gate lines extending over the substrate;
a plurality of first patterns extending from a first wiring layer over the plurality of first gate lines;
a plurality of second patterns extending in a first horizontal direction in a rear wiring layer under the substrate and configured to receive a first supply voltage provided to the plurality of cells; and
An integrated circuit comprising a plurality of first vias, each vertically penetrating the substrate and connected to one of the plurality of first patterns and one of the plurality of second patterns. In claim 17,
The plurality of second patterns extend to the peripheral area in the first horizontal direction. In claim 17,
The cell region further includes a plurality of third patterns extending in a second horizontal direction orthogonal to the first horizontal direction in the rear wiring layer,
An integrated circuit, wherein the plurality of third patterns are connected to the plurality of second patterns. In claim 17,
The cell region extends from the back wiring layer in the first horizontal direction and further includes a plurality of fourth patterns configured to receive a second supply voltage provided to the plurality of cells.

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