KR20240043929A - Apparatus for precharging of bit line - Google Patents

Abstract

The purpose of the present invention is to turn off only the precharge transistor corresponding to the selected column address during read/write operation, and keep the precharge transistor corresponding to the remaining column addresses turned on, thereby enabling read/write operation. After completing the process, we provide a bit line precharge device that prevents a large amount of current from flowing momentarily when precharging the bit lines (bl) and inverted bit lines (blb), thereby reducing the peak current. there is.
In order to achieve the above object, the present invention includes a plurality of multiplexing units provided for each column and in which a plurality of column memory cells are connected through a pair of bit lines (bl) and inverted bit lines (blb); a plurality of precharge units provided for each column and precharging the bit line (bl) and inverted bit line (blb) pairs in a standby state; And a sense amplifier in which the plurality of bit line (bl) and inverted bit line (blb) pairs are connected through the plurality of multiplexers. During a read/write operation, a sense amplifier is connected to the column selected from the plurality of precharge units. Only the corresponding precharge section is deactivated, and the precharge section corresponding to the remaining columns remains activated.

Description

Bit line precharge device {APPARATUS FOR PRECHARGING OF BIT LINE}

The present invention relates to a bit line precharge device, and more specifically, to a bit line precharge device that precharges bit line pairs of a large capacity memory used as a frame buffer memory.

Display devices used in electronic devices that display images such as TVs, laptop computers, monitors, and mobile devices include liquid crystal displays (LCDs) and organic light emitting devices (OLEDs). .

The display device may include a display panel having a plurality of pixels and a display drive integrated circuit (DDI) for applying electrical signals to the plurality of pixels, and the DDI provides electric signals to the plurality of pixels. The image can be implemented by .

The frame buffer memory used in DDI has a capacity of several Mb to tens of Mb, and the area occupied by the frame buffer memory in DDI is more than 50%. And to increase the read/write operation bandwidth, the number of input/output data lines is very large, more than 100.

In addition, the frame buffer memory used in DDI is a dual-port memory with two clocks (a writing clock and a reading clock) to enable simultaneous input and output, as shown in FIG. 1, for example, a dual-port Static Random Access Memory (SRAM). ) is used.

Dual port SRAM has an arbiter function that mediates the operation order to ensure stable operation of the dual port memory as a frame buffer memory by preventing collisions between the write and read signals when the write and read signals are input at the same time. This is provided.

As mentioned above, the dual-port SRAM used as a frame buffer memory in DDI must support high capacity, a large number of input/output data lines, and arbiter functions, so it consumes a lot of current during internal read/write operations in the memory, so it consumes a lot of power (power supply). VDD) and ground power noise are generated, causing DDI malfunction.

The operation of dual port SRAM is divided into read operation, write operation, and standby state. In the standby state without read/write operation, the word line is OFF, so the bit line (bl:bit line) and The transistor of the multiplexer 5 is isolated. And the bit line (bl) and the inverted bit line (blb:bit line bar) are pre-charged to 1.

As shown in FIGS. 2 and 3, precharging of bl and blb is performed through the precharge unit 3. Conventionally, the precharge unit 3 precharges bl and blb with an external power supply voltage (VDD). Precharges bl/blb based on the pcgen (pre-charge enable) signal, which is a precharge control signal.

The pcgen signal, which is a precharge control signal, is activated to low in standby state and deactivated to high during read/write operation, and all precharge units (3) connected to the multiplex unit (5) are precharged. Precharges bl/blb based on the pcgen signal, which is a control signal.

During a read/write operation, the pcgen signal is enabled in a high state, turning off the operation of all transistors (PMOS) of the precharge unit (3) that precharged bl and blb to the power supply voltage (VDD). I order it.

In this way, when the operation of the transistors (PMOS) of all precharge units (3) is turned off, all bl and blb connected to the multiplex unit (5) are in a floating state for a short time, and the word line (Word Line) When enabled, bl remains the power supply voltage (VDD) according to the SRAM cell 1 storage value (Q or Qb, for example, if Q is 1, Qb is 0), and the voltage level of blb gradually decreases.

In this case, after all bls and blbs of SRAM cells connected to the word line operate the bit line sense amplifier 7 according to the cell storage value, bls have a value close to the power supply voltage (VDD) and blbs have a value close to the ground voltage. .

When the read/write operation is completed and the pcgen signal switches from a high state to a low state, all blbs that have fallen to a value close to the ground voltage are grounded as the transistors (PMOS) of all precharge units (3) are turned on. At a value close to the voltage, it is precharged to the external power supply voltage (VDD) at once, causing a large current to flow instantaneously, and at this time, a peak current is generated, harming the stability of memory operation.

Registered Patent Publication No. 10-0847314 (announcement date 2008.07.21.)

The present invention was developed to solve the conventional problems described above. During read/write operations, only the precharge transistor corresponding to the selected column address is turned off, and the precharge corresponding to the remaining column addresses is turned off. By maintaining the turn-on state, the transistor prevents a large amount of current from momentarily flowing when precharging the bit lines (bl) and inverted bit lines (blb) after completing a read/write operation, thereby reducing the peak current. The purpose is to provide a bit line precharge device that can reduce bit line precharge.

The bit line precharge device according to the present invention for achieving the above-mentioned object is provided for each column, and a plurality of multiplexing units in which a plurality of column memory cells are connected through a bit line (bl) and inverted bit line (blb) pair. ; a plurality of precharge units provided for each column and precharging the bit line (bl) and inverted bit line (blb) pairs in a standby state; And a sense amplifier in which the plurality of bit line (bl) and inverted bit line (blb) pairs are connected through the plurality of multiplexers. During a read/write operation, a sense amplifier is connected to the column selected from the plurality of precharge units. Only the corresponding precharge section is deactivated, and the precharge section corresponding to the remaining columns remains activated.

Additionally, in the bit line precharge device according to the present invention, the plurality of precharge units include a pair of bit lines (bl) and inverted bit lines (blb) connected to memory cells in the remaining columns except the selected column during a read/write operation. It is characterized by precharging them.

Additionally, in the bit line precharge device according to the present invention, the plurality of precharge units, during a read/write operation, bit lines connected to memory cells in the remaining columns except for the column selected based on the bit line control signal and the column address signal. It is characterized by precharging (bl) and inverted bit line (blb) pairs.

In addition, in the bitline precharge device according to the present invention, it is provided for each column, receives a bitline control signal and a column address signal, performs logical operations, controls the operation of the correspondingly connected multiplexer, and controls the correspondingly connected precharge device. It is characterized in that it further includes a plurality of control signal generation units that generate and output control signals that control the operation of the charging unit.

Additionally, in the bitline precharge device according to the present invention, the control signal generator includes a NAND gate that receives the bitline control signal and the column address signal, respectively; and an inverter that receives the output signal of the NAND gate and outputs an inverted signal.

Additionally, in the bit line precharge device according to the present invention, the control signal generator applies the output signal of the NAND gate as a read operation control signal to the correspondingly connected multiplexer, and the output signal of the inverter is used as a write operation control signal. As an operation control signal, it is applied to the correspondingly connected multiplexing unit, while the output signal of the inverter is applied to the correspondingly connected precharge unit as a precharge control signal.

In addition, in the bit line precharge device according to the present invention, the precharge unit generates a pair of bit line (bl) and inverted bit line (blb) based on the precharge control signal applied from the control signal generator to which the precharge unit is connected. is precharged, and when the precharge control signal applied from the connected control signal generator is low during a read/write operation, the bit line (bl) and the inverted bit line (blb) pair are precharged. Do it as

Specific details of other embodiments are included in “Specific Details for Carrying Out the Invention” and the attached “Drawings.”

The advantages and/or features of the present invention and methods for achieving them will become clear by referring to the various embodiments described in detail below along with the accompanying drawings.

However, the present invention is not limited to the configuration of each embodiment disclosed below, but may also be implemented in various different forms. However, each embodiment disclosed in this specification is intended to ensure that the disclosure of the present invention is complete, and the present invention It is provided to fully inform those skilled in the art of the present invention, and it should be noted that the present invention is only defined by the scope of each claim.

According to the present invention, during a read/write operation, only the precharge transistor corresponding to the selected column address is turned off and the remaining precharge transistors are maintained in the turn-on state, so that the read/write operation is completed and converted to a standby state. When precharging the bl and blb pair with the power supply voltage (VDD), only bl and blb connected to the precharge transistor turned off corresponding to the selected column during read/write operation are charged to the power supply voltage (VDD) at a value close to the ground voltage. It is pre-charged.

Accordingly, it is possible to prevent a large amount of current from flowing momentarily, thereby reducing the peak current.

Figure 1 is a diagram schematically showing the configuration of DDI.
Figure 2 is a diagram schematically showing an SRAM including a bit line precharge device according to the prior art.
FIG. 3 is a diagram schematically showing the configuration of the precharge unit and the multiplexer unit of FIG. 2.
Figure 4 is a diagram schematically showing an SRAM including a bit line precharge device according to an embodiment of the present invention.
FIG. 5 is a diagram schematically showing the configuration of the precharge unit and multiplexer of FIG. 4.

Before explaining the present invention in detail, the terms or words used in this specification should not be construed as unconditionally limited to their ordinary or dictionary meanings, and the inventor of the present invention should not use the terms or words in order to explain his invention in the best way. It should be noted that the concepts of various terms can be appropriately defined and used, and furthermore, that these terms and words should be interpreted with meanings and concepts consistent with the technical idea of the present invention.

That is, the terms used in this specification are only used to describe preferred embodiments of the present invention, and are not used with the intention of specifically limiting the content of the present invention, and these terms refer to various possibilities of the present invention. It is important to note that this is a term defined with consideration in mind.

In addition, in this specification, it should be noted that singular expressions may include plural expressions unless the context clearly indicates a different meaning, and that even if similarly expressed in plural, they may include singular meanings. do.

Throughout this specification, when a component is described as “including” another component, it does not exclude any other component, but includes any other component, unless specifically stated to the contrary. It could mean that you can do it.

Furthermore, if a component is described as being "installed within or connected to" another component, it means that this component may be installed in direct connection or contact with the other component and may be installed in contact with the other component and may be installed in contact with the other component. It may be installed at a certain distance, and in the case where it is installed at a certain distance, there may be a third component or means for fixing or connecting the component to another component. It should be noted that the description of the components or means of 3 may be omitted.

On the other hand, when a component is described as being “directly connected” or “directly connected” to another component, it should be understood that no third component or means is present.

Likewise, other expressions that describe the relationship between components, such as "between" and "immediately between", or "neighboring" and "directly neighboring", have the same meaning. It should be interpreted as

In addition, in this specification, terms such as "one side", "other side", "one side", "the other side", "first", "second", etc., if used, refer to one component. It is used to clearly distinguish it from other components, and it should be noted that the meaning of the component is not limited by this term.

In addition, in this specification, terms related to position such as "top", "bottom", "left", "right", etc., if used, should be understood as indicating the relative position of the corresponding component in the corresponding drawing. Unless the absolute location is specified, these location-related terms should not be understood as referring to the absolute location.

Moreover, in the specification of the present invention, terms such as "... unit", "... unit", "module", "device", etc., when used, mean a unit capable of processing one or more functions or operations, which is hardware. Alternatively, it should be noted that it can be implemented through software, or a combination of hardware and software.

In addition, in this specification, when specifying the reference numeral for each component in each drawing, the same component has the same reference number even if the component is shown in different drawings, that is, the same reference is made throughout the specification. The symbols indicate the same component.

In the drawings attached to this specification, the size, position, connection relationship, etc. of each component constituting the present invention is exaggerated, reduced, or omitted in order to convey the idea of the present invention sufficiently clearly or for convenience of explanation. It may be described, and therefore its proportions or scale may not be exact.

In addition, hereinafter, in describing the present invention, detailed descriptions of configurations that are judged to unnecessarily obscure the gist of the present invention, for example, known technologies including prior art, may be omitted.

Hereinafter, a bit line precharge device according to a preferred embodiment of the present invention will be described in detail with reference to the attached drawings.

FIG. 4 is a diagram schematically showing an SRAM including a bitline precharge device according to an embodiment of the present invention, and FIG. 5 is a diagram schematically showing the configuration of the precharge unit and the multiplexer unit of FIG. 4.

As shown in FIG. 4, the multiplexer 30 is provided for each column, and a plurality of column memory cells 10 are connected through a pair of bit lines (bl) and inverted bit lines (blb).

The precharge unit 20 is provided for each column and can precharge a pair of bit lines (bl) and inverted bit lines (blb) in a standby state.

During a read/write operation, only the precharge unit 20 corresponding to the selected column among the plurality of precharge units 20 may be deactivated, and the precharge unit 20 corresponding to the remaining columns may remain activated.

Accordingly, during a read/write operation, the plurality of precharge units 20 pre-charge the bit line (bl) and inverted bit line (blb) pairs connected to the memory cells of the remaining columns except the selected column with the power supply voltage (VDD). It can be occupied.

And, during a read/write operation, the plurality of precharge units 20 are connected to the bit line (bl) and the inverted bit line (blb) connected to the remaining column memory cells except for the column memory cell selected based on the bit line control signal and the column address signal. ) pairs can be precharged with the power supply voltage (VDD).

During a read/write operation, the operation of deactivating only the precharge unit 20 corresponding to the selected column will be described in more detail below.

In the sense amplifier 40, pairs of bit lines (bl) and inverted bit lines (blb) may be connected through a plurality of multiplexers (30).

Meanwhile, the control signal generator 50 is provided for each column as shown in FIG. 5, and receives the bit line control signal (blen) and the column address signal (addr[3:0]) and performs logical operations to determine each Controls the operation of the multiplexing unit 30 connected to the control signal generating unit 50 or generates a control signal that controls the operation of the precharge unit 20 connected to each control signal generating unit 50. You can print it out.

Each control signal generator 50 includes a NAND gate 51 and a NAND gate 51 that receive a bit line control signal (blen:bit line enable) and a column address signal (addr[3:0]). ) may include an inverter 53 that receives the output signal and outputs an inverted signal.

In the embodiment of the present invention, the circuit configuration of the control signal generator 50 is implemented as a combination of the NAND gate 51 and the inverter 53, as shown in FIG. 5, but the circuit of the control signal generator 50 The configuration is not limited to this and can be implemented in various modifications.

The control signal generator 50 of the above-described configuration can use the output signal of the NAND gate 51 as a read operation control signal and apply it to the multiplexer 30.

Additionally, the output signal of the inverter 53 can be applied to the multiplexer 30 as a write operation control signal.

Additionally, the control signal generator 50 may apply the output signal of the inverter 53 to the precharge unit 20 as a precharge control signal (lpcg[3:0]).

The above-mentioned precharge unit 20 precharges the bit line (bl) and the inverted bit line (blb) pair based on the precharge control signal (lpcg[3:0]) applied from the control signal generator 50. However, during a read/write operation, if the precharge control signal (lpcg[3:0]) applied from the control signal generator 50 is low, it is activated to create a pair of bit line (bl) and inverted bit line (blb). It can be precharged.

Specifically, when a read/write operation starts in the standby state, the control signal generator 50 generates a precharge control signal ( lpcg[3:0]) is generated and output to the precharge unit 20.

In an embodiment of the present invention, four multiplexing units 30 are connected to each sense amplifier 40, and for read/write operations, the memory cell in the first column among the memory cells connected to the first sense amplifier 40 is The explanation is given using the selected case as an example.

The number of multiplexers 30 connected to the sense amplification unit 40 is not limited to 4, but may be connected in various variations such as 2, 8, or 16. Depending on the number of multiplexers 30 connected to the sense amplifier 40, the column address signal can also be changed to add[1:0], addr[7:0], addr[15:0], etc.

When a read/write operation begins in the standby state, the bit line control signal (blen) is activated from low to high, and the column address signal (addr[3:0]) is transmitted to the selected column (e.g., the first sense amplifier Only the address signal (e.g., addr[0]) of the first column (40) is activated from low to high, and the address signals of the remaining three unselected columns (e.g., addr[3:1]) are activated from low to high. It remains low.

Accordingly, the bit line control signal (blen) and the column address signal (e.g., the first column of the first sense amplifier 40) applied to the control signal generator 50 corresponding to the selected column (e.g., , addr[0]) all become high.

When both the bit line control signal (blen) and the column address signal (e.g., addr[0]) applied to the control signal generator 50 become high, the control signal generator 50 precharges in a high state. The corresponding precharge unit 20 outputs a control signal (for example, lpcg[0] is in a high state) and receives a precharge control signal in a high state (for example, lpcg[0] is in a high state). Turns off the transistor (PMOS) that precharges the bit line (bl) and the inverted bit line (blb) with the power supply voltage (VDD).

In this way, when the transistor (PMOS) of the pre-charge unit 20 is turned off, the bit line (bl) and the inverted bit line (blb) connected to the multiplexer 30 linked to the pre-charge unit 20 are It is in a floating state for a short period of time, and during read/write operations, the word line is enabled and the bit line (bl) is activated according to the SRAM cell storage value (Q or Qb, for example, if Q is 1, Qb is 0). has a power supply voltage (VDD), and the voltage level of the inverted bit line (blb) gradually decreases to a value close to the ground voltage.

Meanwhile, the bit line control signal (blen) applied to the control signal generator 50 corresponding to the remaining unselected columns becomes high, and the column address signal (eg, addr[3:1]) becomes low.

When the bit line control signal (blen) applied to the control signal generator 50 is high and the column address signal (e.g., addr[3:1]) is low, the control signal generator 50 is in a low state. outputs a precharge control signal (for example, lpcg[3:1] is in a low state), and the precharge unit ( 20) maintains the transistor (PMOS) in a turned-on state and precharges the bit line (bl) and the inverted bit line (blb) with the power supply voltage (VDD).

Afterwards, when the read/write operation of the memory cell is completed and switched to the standby state, the bit line control signal (blen) applied to the control signal generator 50 is deactivated from high to low. Accordingly, the precharge control signal (lpcg[0]) output from the control signal generator 50 corresponding to the selected column (e.g., the first column of the first sense amplifier 40) during the read/write operation. goes from high to low, and a precharge control signal in a low state (lpcg[0] is in a low state) is applied to the precharge unit 20 corresponding to the control signal generator 50.

During a read/write operation, a precharge control signal (lpcg[0]) in a low state is generated from the control signal generator 50 corresponding to the selected column (e.g., the first column of the first sense amplifier 40). The precharge unit 20, which has received the state), turns on the transistor (PMOS), and inverts the inverted bit line (blb) connected to the multiplexer 30 linked to the precharge unit 20 to a value close to the ground voltage. It is precharged with the external power supply voltage.

Meanwhile, the precharge control signal (lpcg[3:1]) output from the control signal generator 50 corresponding to the remaining columns not selected during the read/write operation maintains the low signal as is, and the corresponding control signal A precharge control signal in a low state (lpcg[3:1] is in a low state) is continuously applied to the precharge unit 20 corresponding to the generation unit 50.

The precharge unit 20 receives a low precharge control signal (lpcg[3:1] is low) from the control signal generator 50 corresponding to the remaining columns not selected during the read/write operation. The transistor (PMOS) is kept turned on, and the bit line (bl) and inverted bit line (blb) are precharged with the power supply voltage (VDD).

As described above, when the read/write operation of the memory cell is completed and switched to the standby state, the free signal corresponding to the column selected during the read/write operation (for example, the first column of the first sense amplifier 40) Only the transistor (PMOS) of the charge unit 20 is turned on, and only the inverted bit line (blb) connected to the multiplexer 30 linked to the pre-charge unit 20 is pre-charged by the external power supply voltage at a value close to the ground voltage. Charge it.

As described above, during a read/write operation, the precharge unit 20, which receives the low-state precharge control signal (lpcg[3:1]) from the control signal generator 50, continues to turn the transistor (PMOS). It is maintained in the ON state to precharge the bit line (bl) and the inverted bit line (blb) with the power supply voltage (VDD). At this time, the bit line (bl) and the inverted bit line (blb) are maintained at the power supply voltage (VDD). DC current flows from the transistor (PMOS) that precharges with the voltage (VDD) to the pull-down transistor (not shown) of the memory cell 10.

Here, the DC current flowing from the transistor (PMOS) of the precharge unit 20 to the pull-down transistor (not shown) of the memory cell 10 is wasted current.

However, the DC current flowing from the transistor (PMOS) of the precharge unit 20 to the pull-down transistor (not shown) of the memory cell 10 does not affect the stability of memory operation.

On the other hand, when the read/write operation is completed and switched to the standby state, the number of pre-charged bit lines (bl) and inverted bit lines (blb) can be greatly reduced, resulting in a peak current that instantaneously flows a large amount of current. The size of can be greatly reduced, and the peak current reduction effect becomes greater in proportion to the number of multiplexers 30 connected to one sense amplifier 40.

As seen above, in the present invention, only the transistor (PMOS) of the precharge unit 20 corresponding to the selected column is deactivated during a read/write operation, and when the read/write operation is completed and switched to the standby state, the read/write operation is completed and the transition to the standby state is performed. During the write operation, only the transistor (PMOS) of the precharge unit 20 corresponding to the selected column is activated, and the bit line (bl) and the inverted bit line (blb) connected to the transistor (PMOS) of the precharge unit 20 are activated. ) is precharged to the external power supply voltage (VDD) at a value close to the ground voltage.

Accordingly, it is possible to prevent a large amount of current from flowing momentarily, thereby reducing the peak current.

Above, various preferred embodiments of the present invention have been described by giving some examples, but the description of the various embodiments described in the "Detailed Contents for Carrying out the Invention" section is merely illustrative and the present invention Those skilled in the art will understand from the above description that the present invention can be implemented with various modifications or equivalent implementations of the present invention.

In addition, since the present invention can be implemented in various other forms, the present invention is not limited by the above description, and the above description is intended to make the disclosure of the present invention complete and is commonly used in the technical field to which the present invention pertains. It is provided only to fully inform those with knowledge of the scope of the present invention, and it should be noted that the present invention is only defined by each claim in the claims.

10. Memory cells,
20. Free Charge Branch,
30. Multiplexing Department,
40. Sense amplification unit,
50. Control signal generation unit,
51. NAND gate,
53. Inverter

Claims (8)

A plurality of multiplexing units provided for each column and connected to a plurality of column memory cells through a pair of bit lines (bl) and inverted bit lines (blb);
a plurality of precharge units provided for each column and precharging the bit line (bl) and inverted bit line (blb) pairs in a standby state; and
It includes a sense amplification unit to which the plurality of bit line (bl) and inverted bit line (blb) pairs are connected through the plurality of multiplexers,
During a read/write operation, only the precharge unit corresponding to the selected column among the plurality of precharge units is deactivated, and the precharge unit corresponding to the remaining columns remains activated,
Bitline precharge device.
According to paragraph 1,
The plurality of precharge units,
During a read/write operation, the bit line (bl) and inverted bit line (blb) pairs connected to the memory cells of the remaining columns except the selected column are precharged.
Bitline precharge device.
According to paragraph 1,
The plurality of precharge units,
During a read/write operation, the bit line (bl) and inverted bit line (blb) pairs connected to the memory cells of the remaining columns except the selected column are precharged based on the bit line control signal and the column address signal.
Bitline precharge device.
According to paragraph 1,
It is provided for each column, receives a bit line control signal and a column address signal, performs logical operations, controls the operation of the correspondingly connected multiplexer, and generates and outputs a control signal that controls the operation of the correspondingly connected precharge unit. Characterized in that it further includes a plurality of control signal generators,
Bitline precharge device.
According to paragraph 4,
The control signal generators, respectively,
A NAND gate that receives the bit line control signal and the column address signal; and
Characterized in that it includes an inverter that receives the output signal of the NAND gate and outputs an inverted signal.
Bitline precharge device.
According to clause 5,
The control signal generators, respectively,
Applying the output signal of the NAND gate as a read operation control signal to the correspondingly connected multiplexer,
The output signal of the inverter is applied as a write operation control signal to the correspondingly connected multiplexer,
Characterized in that the output signal of the inverter is applied as a precharge control signal to the correspondingly connected precharge unit,
Bitline precharge device.
According to clause 6,
Each of the precharge units,
The bit line (bl) and the inverted bit line (blb) pair are precharged based on the precharge control signal applied from the connected control signal generator,
During a read/write operation, if the precharge control signal applied from the connected control signal generator is low, the bit line (bl) and the inverted bit line (blb) pair are precharged.
Bitline precharge device.
During a read/write operation in a memory device, the precharge of the bit line (bl) and inverted bit line (blb) of the selected column is disabled, and the precharge of the bit line (bl) and inverted bit line (blb) of the unselected column is disabled. Keep the charge active,
When the read/write operation is completed and the bit line (bl) and the inverted bit line (blb) are precharged, the number of precharged bit lines (bl) and inverted bit lines (blb) is minimized to allow a large current to flow at the same time. to prevent,
Bitline precharge device.

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