KR20240043635A - Power management chip, electronic device having the same, and operating method thereof - Google Patents

Abstract

A method of operating an electronic device according to the present invention includes generating an idle state, selecting one of a plurality of low-power states in a low-power management module, and switching each of the plurality of devices to a low-power mode according to the selected low-power state. and entering the low-power state, wherein the selecting step may include selecting the low-power state by evaluating the time conditions of the idle state, power consumption, and a success rate of entering the previous low-power state.

Description

POWER MANAGEMENT CHIP, ELECTRONIC DEVICE HAVING THE SAME, AND OPERATING METHOD THEREOF}

The present invention relates to a power management chip, an electronic device incorporating the same, and a method of operating the same.

In general, mobile electronic devices such as smartphones, TVs, and tablet PCs have high hardware specifications and support good performance and fast speed. Mobile electronic devices provide various user interface environments to increase user convenience. However, as hardware specifications increase and functions and user interface environments become more diverse, the amount of power consumed by electronic devices increases, and the battery capacity of electronic devices continues to increase. Accordingly, the need to reduce power consumption of electronic devices to improve usability is increasing.

An object of the present invention is to provide a power management chip that reduces power consumption, an electronic device including the same, and a method of operating the same.

An object of the present invention is to provide a power management chip that improves performance, an electronic device including the same, and a method of operating the same.

A method of operating an electronic device according to an embodiment of the present invention includes generating an idle state; selecting one of a plurality of low power states in a low power management module; and entering each of the plurality of devices into a low-power mode according to the selected low-power state, wherein the selecting step includes evaluating the idle state time condition, power consumption, and success rate of entering the previous low-power state. It may include selecting a low power state.

A power management chip according to an embodiment of the present invention includes a special function register that stores setting data for low power management; A first table storing first data for each low power state; a second table storing second data for each device corresponding to a low power state; and logic to select one of a plurality of low-power states using the setting data, first data, and second data, and to determine the low-power entry success rate and priority of each of the plurality of devices according to the selected low-power state. May include circuits.

An electronic device according to an embodiment of the present invention includes a system on a chip; a buffer memory that temporarily stores data required for operation of the system-on-chip; a power management chip that manages power of the system-on-chip; A display device that displays display data; A touch panel that generates touch data; and a storage device for storing data from the system-on-chip, wherein the power management chip is based on the power consumption of each of the plurality of low-power states, the consumption time history until low-power entry, and the low-power entry success rate history, Selecting one of the low power states, and entering each of the system on chip, the buffer memory, the display device, the touch panel, and the storage device into a low power mode according to the selected low power state. .

A processor according to an embodiment of the present invention includes a first device; second device; central processing unit; and a power management unit that manages power of the first device, the second device, and the central processing unit, wherein the power management unit manages power consumption during idle time, average entry consumption time, and low-power entry success rate. Selecting one of a plurality of low-power states and controlling low-power processing operations of the first device, the second device, and the central processing unit according to the selected low-power state.

A power management chip, an electronic device including the same, and an operating method thereof according to an embodiment of the present invention can efficiently reduce power consumption based on past history of low-power states.

The power management chip, the electronic device including the same, and its operating method according to an embodiment of the present invention can estimate and select a power state that can save the most power when selecting a power state.

A power management chip, an electronic device including the same, and a method of operating the same according to an embodiment of the present invention consider the power consumption for each power state, the consumption time history until low power entry, and the low power entry success rate history for each power state. Comparison can be made by quantifying the level of power consumption.

A power management chip, an electronic device including the same, and a method of operating the same according to an embodiment of the present invention determine the processing order in consideration of the existing entry success rate of each device in a low-power processing operation, thereby minimizing the cost of entry failure. , efficient post-processing is possible.

The drawings attached below are intended to aid understanding of the present embodiment and provide examples along with a detailed description.
1 is a diagram showing an electronic device according to an embodiment.
Figure 2 is a diagram illustrating a low power state according to an embodiment of the present invention.
Figure 3 is a diagram illustrating the power management chip 130 according to an embodiment of the present invention.
Figure 4 is a diagram illustrating setting data stored in the special function register 131 according to an embodiment of the present invention.
Figure 5 is a diagram illustrating entries in the data table 132 for each low power state according to an embodiment of the present invention.
FIG. 6 is a diagram illustrating entries in the data table 133 for each device according to an embodiment of the present invention.
FIG. 7 is a diagram illustrating a logic circuit 134 according to an embodiment of the present invention.
Figure 8 is a flowchart exemplarily showing a method of operating an electronic device according to an embodiment of the present invention.
FIG. 9 is a flowchart illustrating a method of selecting a low power state of the electronic device 100 according to an embodiment of the present invention.
FIG. 10 is a flowchart illustrating an operation of entering a low-power state of the electronic device 100 according to an embodiment of the present invention.
Figure 11 is a diagram illustrating a computing system according to an embodiment of the present invention.
Figure 12 is a ladder diagram showing a low-power mode entry operation of a processor according to an embodiment of the present invention.
FIG. 13 is a diagram illustrating a mobile device 2000 according to an embodiment of the present invention.
Figure 14 is a diagram showing a neural network operation system 3000 according to an embodiment of the present invention.

Below, using the drawings, the content of the present invention will be described clearly and in detail so that a person skilled in the art can easily implement it.

A power management chip, an electronic device including the same, and a method of operating the same according to an embodiment of the present invention generate idle time, select a power state to enter, and operate each device in a predetermined order according to the selected power state. Low-power processing operations can be performed according to the processing requirements. Accordingly, when selecting a power state, the present invention can estimate and select a power state that can save the most power. In particular, the present invention considers the power consumption for each power state, the consumption time history until low power entry, and the low power entry success rate history, and can be compared by quantifying the degree of power consumption for each power state. In addition, the present invention determines the processing order in consideration of the existing entry success rate of each device in low-power processing operations, thereby minimizing entry failure costs and enabling efficient post-processing.

FIG. 1 is a diagram illustrating an electronic device 100 according to an embodiment of the present invention. Referring to FIG. 1, the electronic device 100 includes a system on a chip (SoC) 110, a buffer memory 120, a power management chip (130), a PMIC (PMIC), a display device (LCD) 140, a touch panel 150, It may include a storage device 170.

System-on-a-chip 110 includes at least one processor 111 (CPU), a memory controller 110, a performance controller 113 (PFMC), an activity monitor unit 114 (AMU), a clock management unit 115 (CMU), and a user. It may include an interface controller 116, a memory interface circuit 117, an accelerator 118, and a system bus 119. Meanwhile, it should be understood that the components of the electronic device 100 are not limited here.

The processor 111 may be implemented to execute software (application programs, operating systems, device drivers) to be executed in the electronic device 100. Additionally, the processor 111 may be implemented to execute an operating system (OS) loaded into the buffer memory 120. Additionally, the processor 111 can execute various application programs to be run based on an operating system (OS). The processor 111 may be implemented as a homogeneous multi-core processor or a heterogeneous multi-core processor.

Additionally, the processor 111 may be implemented as a computing component having at least two independently operable processor cores. Here, each of the cores can independently read and execute program instructions. Each of the cores may be composed of a plurality of power domains that operate by independent driving clocks and independent driving voltages. Additionally, the driving voltage and driving clock signal supplied to each of the multi-cores can be blocked or connected on a core-by-core basis. Blocking the driving voltage and clock signal provided to each power domain from a specific core can be called hot plug-out, and providing the driving voltage and clock to a specific core can be called hot plug-in. It can be called Hotplug-in.

Additionally, the frequency of the driving clock and the level of the driving voltage provided to each power domain may vary depending on the processing load of each core. That is, each core can be controlled using a Dynamic Voltage and Frequency Scaling (DVFS) method that increases the level of the driving clock frequency or driving voltage provided to the corresponding power domain as the time required to process tasks increases. Hot plug-in and hot plug-out can be performed by referring to the driving voltage of the processor 111 and the operating frequency of the driving clock adjusted through DVFS. To control the processor 111 in this manner, the kernel of the operating system (OS) can monitor the number of tasks in the run queue and the driving voltage and driving clock of the processor 111 at specific time intervals. Additionally, the kernel of the operating system (OS) can control hot plug-in or hot plug-out of the processor 111 with reference to the monitored information.

Memory controller 112 may be implemented to provide interfacing between buffer memory 120 and system-on-chip 110. Additionally, the memory controller 112 may access the buffer memory 120 according to a request from the processor 111 or another functional block (Intellectual Property: IP). For example, the memory controller 112 may write data to the buffer memory 120 according to a write request from the processor 111. Additionally, the memory controller 112 may read data from the buffer memory 120 in response to a read request from the processor 111 and transfer it to the processor 111 or the memory interface circuit 117 through the system bus 119.

The buffer memory 120 may load an operating system (OS) or basic application programs (Application Program) upon booting. For example, when the electronic device 100 boots, the OS image stored in the storage device 170 is loaded into the buffer memory 120 based on the boot sequence. All input/output operations of the electronic device 100 may be supported by the operating system (OS). Likewise, application programs selected by the user or to provide basic services may be loaded into the buffer memory 120. The buffer memory 120 may be used as a buffer memory to store image data provided from an image sensor such as a camera. The buffer memory 120 may be volatile memory such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM), or non-volatile memory such as PRAM, MRAM, ReRAM, FRAM, or NOR flash memory.

The performance controller 113 may be implemented to adjust the operating parameters of the system-on-chip 110 according to a control request provided from the kernel of an operating system (OS). For example, the function controller 113 may adjust the level of Dynamic Voltage Frequency Scaling (DVFS) to increase the performance of the system-on-chip 110. Additionally, the performance controller 113 can control the driving mode of a multi-core processor such as Big.LITTLE of the processor 111 according to the kernel's request. At this time, the performance controller 113 may internally include a performance table (PFMT) that sets the operating frequency of the driving voltage and driving clock. The performance controller 113 may control the AMU 114 and CMU 115 connected to the power management chip 130 to provide the driving voltage and driving clock specified for each power domain.

User interface controller 116 may be implemented to control user input and output from user interface devices. For example, the user interface controller 116 may display a keyboard screen for inputting data on the display device 140 (LCD) under the control of the processor 111. Additionally, the user interface controller 116 may control the display device 140 to display data requested by the user. The user interface controller 116 may decode data provided from a user input means, such as the touch panel 150, into user input data.

The storage interface circuit 117 may be implemented to access the storage device 170 according to a request from the processor 111. That is, the storage interface circuit 117 provides an interface between the system on chip 110 and the storage device 170. Data processed by the processor 111 may be stored in the storage device 170 through the storage interface circuit 117. Additionally, data stored in the storage device 170 may be provided to the processor 111 through the storage interface circuit 117. In an embodiment, the storage interface circuit 117 may include non-volatile memory express (NVMe), peripheral component interconnect express (PCIe), serial at attachment (SATA), small computer system interface (SCSI), and serial attached SCSI (SAS). , UAS (universal storage bus (USB) attached SCSI), iSCSI (internet small computer system interface), Fiber Channel, and FCoE (fiber channel over Ethernet) may be implemented.

The storage device 170 may be provided as a storage medium of the electronic device 100. The storage device 170 can store application programs, operating system images, and various data. The storage device 170 may be provided as a memory card (MMC, eMMC, SD, MicroSD, etc.). The storage device 170 includes NAND flash memory, vertical NAND flash memory, NOR flash memory, resistive random access memory (RRAM), and phase-change memory; It may include PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), or spin transfer torque random access memory (STT-RAM). In another embodiment, the storage device 170 may be an internal memory provided inside the system-on-chip 110.

The accelerator 118 may be provided as a separate functional block (IP) to improve the processing speed of multimedia or multimedia data. For example, the accelerator 118 improves the processing performance of text, audio, still images, animation, video, 2-dimensional data, or 3-dimensional data. It can be provided as a function block (IP) to do this. In embodiments, accelerator 118 may be implemented to accelerate low power management operations. The accelerator 118 can accelerate entry into a low-power mode using past power management history by driving a low-power acceleration module.

The system bus 119 is a bus for providing an on-chip network inside the system on chip 110. For example, the system bus 119 may include a data bus, an address bus, and a control bus. The data bus is the path along which data moves. Mainly, a memory access path to the buffer memory 120 or the storage device 170 will be provided. The address bus provides an address exchange path between functional blocks (IPs). The control bus provides a path to transfer control signals between functional blocks (IPs). However, the configuration of the system bus 119 is not limited to this and may further include mediation means for efficient management.

The power management chip 130 (PMIC) may be implemented to manage power provided to each of the internal components of the electronic device 100. The power management chip 130 may be implemented to provide a power control signal to the system-on-chip 110 in response. In particular, the power management chip 130 may be implemented to select an optimal low-power state among a plurality of low-power states using past power management history when entering a low-power mode. In an embodiment, the power management chip 130 determines the low-power state of the OS based on the power consumption in the corresponding low-power state among low-power states with a minimum required time less than the scheduled standby time and the existing low-power state entry success rate/entry consumption time. You can select . In an embodiment, the power management chip 130 may check and process whether a low power state is possible based on the existing low power state entry success rate and set priority for the low power state corresponding to each device.

Additionally, the power management chip 130 can select the optimal low-power state to enter by considering the scheduled time consumed in the low-power state, the existing actual consumption time, the scheduled power consumption, and the existing entry success rate. Additionally, when entering a low-power state, the power management chip 130 can process the devices in a determined order by considering the existing entry success rate and set priority of each device. For example, the power management chip 130 operates on the system-on-chip 110, buffer memory 120, display device 140, touch panel 150, and The low-power processing order of the storage device 170 may be determined.

Meanwhile, the power management chip 130 shown in FIG. 1 is disposed outside the system-on-chip 100, but it should be understood that the present invention is not limited thereto. The power management chip of the present invention may be provided as a functional block inside the system-on-chip 110, including a power management unit (PMU).

In order to minimize unnecessary power consumption, typical electronic devices select a low-power state with a minimum required time that is less than the standby time scheduled by the OS, and check and process whether the low-power state is possible for each device in a fixed order managed by the OS. . These electronic devices can enter low-power states with a guaranteed scheduled standby time. However, this waiting time is not optimal.

On the other hand, the electronic device 100 according to an embodiment of the present invention selects the low-power state of the OS using the past low-power state history, processes the low-power state of each device, and enters the low-power state while ensuring the scheduled standby time. can do. Additionally, when the electronic device 100 according to an embodiment of the present invention enters a low-power state, it can be expected to effectively reduce power based on the power to be consumed in the corresponding low-power state and the existing entry success rate and consumption time. In addition, even if the electronic device 100 according to an embodiment of the present invention cannot enter the low power state, it can more quickly determine whether entry is impossible by processing based on the existing entry success rate.

Figure 2 is a diagram illustrating a low power state according to an embodiment of the present invention. Referring to FIG. 2, the electronic device 100 displays a plurality of low-power states (S1 to Sk, k is 2) corresponding to whether each of the plurality of devices (DEV1 to DEVn, n is an integer of 2 or more) is active/inactive. You can enter a low-power mode according to any one of the above integers). Here, each of the low power states (S1 to Sk) may be called a sleep state. Sleep states generally include idle and power-gated states.

Meanwhile, the power management chip according to the present invention not only manages low power according to whether the device is activated or deactivated, but also manages low power according to whether the OS or application running in each active state of the device is executed or not executed. can do.

Figure 3 is a diagram illustrating the power management chip 130 according to an embodiment of the present invention. Referring to FIG. 3, the power management chip 130 may include a special function register 131 (SFR), a data table 132 for each low power state, a data table 133 for each device, and a logic circuit 134. .

The special function register 131 (SFR) may be implemented to store setting data for low power management.

The low-power state data table 132 (first table) may store state-specific data corresponding to each of a plurality of low-power states.

The device-specific data table 133 (second table) may store device-specific data according to the selected low power state.

The logic circuit 134 may be implemented to select a low-power state and perform an operation to enter the optimal low-power mode according to the selected low-power state.

The power management chip 130 according to an embodiment of the present invention may use a low-power state selection technique that selects based on power consumption in the low-power state, low-power state entry success rate, and low-power entry consumption time. In an embodiment, the power management chip 130 may determine a low-power processing order that adjusts the low-power processing order based on the success rate of entering the low-power state for each device and the set priority. In an embodiment, the power management chip 130 may determine a state that can maximize power savings given idle time and update the determined state in the special function register (SFR) 131. At this time, by quantifying all states based on the power consumption, entry consumption time, and entry success rate of each state, the power management chip 130 can determine the optimal power state after comparing each state.

Additionally, the power management chip 130 may determine the order of devices to be processed based on the low power entry success rate and set priority for each device and update the data table 133 for each device. The power management chip 130 may execute a low-power management module according to the low-power management operation described above. The low-power management module can update each table 132 and 133 based on these power processing results.

Figure 4 is a diagram illustrating setting data stored in the special function register 131 according to an embodiment of the present invention. Referring to FIG. 4, the special function register 131 may store a plurality of setting data (SFRD1 to SFRD10).

The first setting data (SFRD1) may store a value for setting whether to configure the low-power state data table 132 and the device-specific data table 133 in internal memory or external memory. In an embodiment, when the data table 132 for each low power state and the data table 133 for each device are configured in external memory, the setting data SFRD1 includes the starting address of the external memory area to be used and the number of entries in each table. can do.

The second setting data (SFRD2) may indicate a scheduled idle time (Idle Time). The operation of selecting the optimal low-power state based on the set idle time and the low-power state table 132 may be started or ended. The third setting data (SFRD3) may indicate the reference number of average consumption times to be used for selecting the low power state. For example, the average time spent may be calculated when the number of successes is greater than the reference number.

The fourth setting data (SFRD4) may indicate the reference number of entry success rates to be used for selecting the low power state. For example, when the number of successes + the number of failures is greater than the reference number, the entry success rate can be calculated. The fifth setting data (SFRD5) may indicate a correction value to be used for selecting a low power state. The sixth setting data (SFRD6) may indicate the current operating state and the selected low power state.

The seventh setting data (SFRD7) may indicate the time consumed to enter a low power state. You can instruct the start/end of actions to measure and update. The eighth setting data (SFRD8) may indicate the reference number of times to start calculating the device processing sequence. For example, when the sum of the number of successes + the number of failures of the entire device is greater than the reference number, the success rate may be calculated. The ninth setting data (SFRD9) may indicate whether to use priority in calculating device processing order.

The tenth setting data (SFRD10) may indicate the entry index of the first processing order among the devices. For example, when the sum of the number of successes + the number of failures is less than or equal to the reference number, the entry index of the first processing order may be set. In an embodiment, whether each device successfully enters low power may be reflected through a bit-map or the like. Additionally, IP internal data and each table can be initialized

Figure 5 is a diagram illustrating entries in the data table 132 for each low power state according to an embodiment of the present invention. Referring to FIG. 5, the data table 132 for each low-power state may include entries for each of the low-power states.

State ID is a unique number to distinguish low power states. Power consumption is the amount of power to be consumed in each state. This value is calculated based on the energy model. The power consumption value may be included in the binary of the low-power management module (SW) or calculated by the SW. Minimum holding time is the minimum holding time of a state. The minimum holding time can be included in the SW binary or calculated by SW. The average entry time is the cumulative average time until entry. The average entry consumption time may be updated by the power management chip 130 each time a corresponding state is selected and entered. The number of successes is the cumulative number of successes. The cumulative number of successes may be updated by the power management chip 130. The number of failures is the cumulative number of failures. The cumulative number of failures may be updated by the power management chip 130.

FIG. 6 is a diagram illustrating entries in the data table 133 for each device according to an embodiment of the present invention. Referring to FIG. 6, the device-specific data table 133 may include entries containing data for each device according to the selected low power state.

Device ID is a unique number to identify the device. Priority is the processing priority. Priorities can be set as needed. Priority can be used as an ordering factor. The number of successes is the cumulative number of successes. The number of successes can be used as an ordering factor. The number of failures is the cumulative number of failures. The number of failures can be used as an ordering factor. The next-order entry index determines the device processing order according to priority and entry success rate, and indicates the next-order device entry index of the corresponding device. If it is the first device, the next order entry index is 0.

FIG. 7 is a diagram illustrating a logic circuit 134 according to an embodiment of the present invention. Referring to FIG. 7, the logic circuit 134 includes a timer 134-1, a low-power state selection logic 134-2, a data table update logic for each low-power state 134-3, and a data table update logic for each device 134. -4) and may include device processing order update logic (134-5).

The timer 134-1 may be implemented to measure the time consumed to enter a low power state. The timer 134-1 may be started by the setting value of the special function register 131.

The low-power state selection logic 134-2 may be implemented to select a low-power state based on the time condition, power consumption, and success rate of the table. The low power state selection logic 134-2 may start operation based on the setting value of the special function register 131.

The data table update logic 134-3 for each low-power state may be implemented to calculate the average consumption time of the state entry corresponding to the measurement value when the timer 134-1 expires and update related information. When it is determined whether to enter a low-power state, the data table update logic 134-3 for each low-power state may update the entry success rate of the corresponding state entry. If the number of successes/number of failures values exceeds the expression range, the data table update logic 134-3 for each low-power state can be updated by right-shifting once each.

The device-specific data table update logic 134-4 may be implemented to update the number of successes/failures of the corresponding entry when the success or failure of the device is added by the special function register 131. If the number of successes/number of failures values exceeds the expression range, the data table update logic 134-4 for each device can be updated by right-shifting once each.

The device processing order update logic 134-5 may be implemented to calculate the device processing order based on table values for each device and update the next-order entry index of each entry after the status entry is updated.

Figure 8 is a flowchart exemplarily showing a method of operating an electronic device according to an embodiment of the present invention. Referring to FIG. 8, the electronic device 100 may operate as follows.

Idle time may occur in the electronic device 100 (S110). The power management module of the power management chip 130 may select one low power state among a plurality of low power states (S120). Here, the low-power state can be selected by considering the entry success rate and idle time of the existing low-power state. Each device may enter a low-power mode according to the low-power state selected under the control of the power management chip 130 (S130).

In embodiments, the low-power management module may be implemented in software, hardware, or firmware. In an embodiment, the low-power management module may be configured using a special function register. In an embodiment, a low-power state may be selected based on power consumption, low-power entry success rate, and low-power consumption time. In an embodiment, the low-power entry success rate may be calculated using the number of entry successes and entry failure counts of each of a plurality of devices in a low-power state.

In an embodiment, the electronic device 100 includes a first table having first data corresponding to each of a plurality of low power states and a second table having second data corresponding to each of the plurality of devices according to the selected low power state. The first data may include power consumption, minimum holding time, average entry time, number of successes, or number of failures, and the second data may include priority, number of successes, number of failures, or next entry index. . In an embodiment, after entering a low power mode, the first table and the second table may be updated. In an embodiment, the device with the highest entry failure probability among a plurality of devices may preferentially enter the low power mode. In an embodiment, the entry failure probability of each of a plurality of devices may be updated, and the processing priority of the device may be determined according to the entry failure probability.

FIG. 9 is a flowchart illustrating a method of selecting a low power state of the electronic device 100 according to an embodiment of the present invention.

The low-power management module of the power management chip 130 (see FIG. 1) can set a scheduled idle time through the special function register 131 (SFR) and start a low-power management operation (S121). Here, the low-power management module can be implemented in software/hardware/firmware. The state selection logic 134-2 of the low-power management module may select the optimal low-power state by evaluating time conditions, power consumption, and success rate, and update the selected low-power state in the special function register 131 (SFR) (S122) ). This low-power state selection operation process may be reflected in the operation status field of the special function register 131 (SFR). The specific operation of selecting a low power state is the same. Among the states with a minimum maintenance time smaller than the scheduled idle time, the state with the largest power consumption * (scheduled idle time - average entry consumption time) * correction value * entry success rate value can be selected. Here, the average entry consumption time may be applied when the number of successes is greater than the reference number of the special function register 131 (SFR). Additionally, the entry success rate can be applied when the number of successes + the number of failures is greater than the standard number of special function registers 131 (SFR).

Afterwards, the low-power management module checks whether the selection is complete through the operation status field of the special function register 131 (SFR) and then reads the value from the selected status field (S123). When the selected status field of the low power management module is read, the IP internal timer 133-2 can start operation.

FIG. 10 is a flowchart exemplarily showing a low-power mode entry operation of the electronic device 100 according to an embodiment of the present invention. Referring to FIG. 10, entering the low power mode may proceed as follows.

The low-power management module of the power management chip 130 can read the entry index of the first processing order from the special function register 131 (SFR) (S131). The low-power management module may perform low-power processing of the device (S132). The low-power management module can read the entry corresponding to the device-specific table by checking the next order index field value. The low-power management module can repeat the above-described process for all devices (S133). When a device fails to enter the low power mode, the failed entry index and success status are recorded in the special function register 131 (SFR), and the device can enter the resume process.

Meanwhile, when low-power processing for all devices is completed, the low-power management module can update the special function register 131 (SFR) with success status (S134). When the success of device processing is recorded in the special function register 131 (SFR), the operation of the IP internal timer 134-1 may be terminated. The data table update logic 134-3 for each device can update the number of successes or failures of the device depending on success. When the operation of the timer 134-1 ends, the data table update logic 134-3 for each low power state of the IP checks the consumed time, and updates the average consumed time of the entry corresponding to the consumed time and device processing. Depending on success or failure, the number of successes/failures of the entry can be updated. Meanwhile, after the number of successes or number of failures of the device is updated, if the sum of the number of successes + number of failures of all devices is greater than the reference number set in the special function register 131 (SFR), the device processing order update logic 134-5 Calculate the processing order of the device and update the next-order entry index of each entry corresponding to the calculated processing order.

Meanwhile, the electronic device 100 may extract data corresponding to the above-described low-power processing process of the low-power management module. Data that has been updated and used in the low-power processing described above can be extracted through memory access. Accordingly, if necessary, the entire low-power processing process can be tracked and the entire data can be extracted. This extracted data can be used for analysis of low-power operation.

Meanwhile, the present invention is applicable to RTOS (Real Time Operating System). RTOS assigns a fixed priority to all processes. The scheduler arranges the allocated processes in a ready queue according to priority.

Figure 11 is a diagram illustrating a computing system according to an embodiment of the present invention. Referring to FIG. 11 , computing system 900 may include a user interface layer 902, an application program layer 904, an RTOS system 906, and basic device hardware 914.

RTOS system 906 may include a task generator 908, a task scheduler 910, and a task synchronizer 912. The task generator 908 is configured to generate a plurality of tasks using a two-level stack method. The task scheduler 910 moves the stack pointer from the first level stack to the second level stack and determines whether the first task is preempted. If the first task is not preempted, the second level stack is assigned to the first task in the second state, and the task scheduler determines whether the first task is giving up control from the second state and waiting for resources. , the first task to be executed is scheduled. Task synchronizer 912 moves the stack pointer from the second level stack back to the first level stack when the first task gives up, providing the second level stack for use by the second task.

Meanwhile, although the above-described low-power management was described based on RTOS, the present invention is applicable to any environment that includes a power management function. In some cases, weights or other elements can be added or deleted from the calculation formula. Accordingly, the composition of table entries can also be flexible. If the power consumption of each device and the entire system can be accessed as digital data, it can be used as a calculation element and extracted into various meaningful data through additional processing.

Figure 12 is a ladder diagram showing a low-power management operation of a processor according to an embodiment of the present invention. Referring to FIG. 12, the low-power management operation of the processor may proceed as follows.

The CPU can generate idle time based on various environmental information (S10). Afterwards, the CPU can request low-power state management (LP MGMT) according to idle time from the PMU (S11). The PMU can select the optimal low-power state among low-power states using low-power tables according to LP MGMT request (S12). The PMU can output a CPU low power control signal (CPU_LP) corresponding to the optimal selected state to the CPU (S13). The CPU can feed back success/failure information on whether to enter the low power mode according to the CPU low power control signal (CPU_LP) to the PMU (S14). The PMU may output a first device low power control signal (DEV1_LP) corresponding to the optimal selected state to the first device (DEV1) (S15). The first device (DEV1) may feed back success/failure information on whether to enter the low power mode according to the first device low power control signal (DEV1_LP) to the PMU (S16). The PMU may output a second device low power control signal (DEV2_LP) corresponding to the optimally selected state to the second device (DEV2) (S17). The second device (DEV2) may feed back success/failure information on whether to enter the low power mode according to the second device low power control signal (DEV2_LP) to the PMU (S18).

Afterwards, the PMU can update the low-power table based on the success/failure information of CPU, DEV1, and DEV2 (S19).

Meanwhile, the low-power management technique of the present invention is applicable to mobile devices.

FIG. 13 is a diagram illustrating a mobile device 2000 according to an embodiment of the present invention. Referring to FIG. 13, the mobile device 2000 includes a power management integrated circuit (PMIC) 2100, an application processor (AP) 2200, an input device 2300, a display device 2400, and a memory device. It may include (2500) and a battery (2600).

The power management chip 2100 receives power from the battery 2600 and can supply and manage power to the AP 2200, the input device 2300, the display device 2400, or the memory device 2500. The mobile device 2000 may include at least one power management chip 2100. In an embodiment, the mobile device 2000 may supply power to the AP 2200, the input device 2300, the display device 2400, or the memory device 2500 using a single power management chip 2100. . In another embodiment, the mobile device 2000 includes a plurality of power management chips 2100 to individually supply power to the AP 2200, the input device 2300, the display device 2400, or the memory device 2500. ) may include.

Meanwhile, as explained in FIGS. 1 to 11, the power management chip 2100 manages low power using a low power table (data table by state, data table by device) that stores success/failure information of existing low power states. It can be implemented to perform.

The AP 2200 can control the overall operation of the mobile device 2000. For example, the AP 2200 may display data stored in the memory device 2500 through the display device 2400 according to an input signal generated by the input device 2300. The input device 2300 may be implemented as a pointing device such as a touch pad or computer mouse, a keypad, or a keyboard. The AP (2200) can monitor activity (performance/bottleneck) for each memory layer by executing the DVFS module and change the frequency/voltage of the memory layer according to the monitoring results.

The memory device 2500 may be implemented to store various data used by at least one component of the mobile device 2000, for example, input data or output data for software and commands related thereto. The memory device 2500 may include volatile memory or non-volatile memory. In an embodiment, the memory device 2500 may store information about task performance conditions corresponding to various tasks. For example, the mobile device 2000 may store task performance conditions corresponding to user identification information. The memory device 2500 may store load control information for various operations of the mobile device 2000.

The battery 2600 may be implemented as a rechargeable secondary battery. For example, the battery 2600 may be charged using power received through an interface circuit or power received through a wireless charging module.

The interface circuit can transmit power from an external power source to the power management chip 2100 by being connected to an external power source by a wire. The interface circuit may be implemented as a connector for connecting a cable for providing power, or as a cable for providing power and a connector for connecting the cable to an external power source. For example, the interface circuit may be implemented with various USB (universal serial bus) type connectors. However, it should be understood that there is no limitation on the type of connector. If direct current power is received from an external power source, the interface circuit can transfer the received direct current power to the power management chip 2100, or by converting the magnitude of the voltage. On the other hand, when receiving alternating current power from an external power source, the interface circuit can transmit it to the power management chip 2100 by converting it to direct current power or converting the magnitude of the voltage.

The wireless charging module can be implemented in the way defined in the WPC (Wireless Power Consortium) standard (or Qi standard) or the A4WP (Alliance for Wireless Power) standard (or AFA (air fuel alliance) standard). there is. The wireless charging module may include a coil in which induced electromotive force is generated by a magnetic field whose size changes over time formed around the coil. The wireless charging module may include at least one of a receiving coil, at least one capacitor, an impedance matching circuit, a rectifier, a DC-DC converter, or a communication circuit. The communication circuit may be implemented as an in-band communication circuit using an on/off keying modulation/demodulation method, or may be implemented as an out-of-band communication circuit (e.g., BLE communication module). . According to various embodiments, the wireless charging module may receive a beam-formed RF (Radio Frequency) wave based on an RF method.

In an embodiment, the interface circuit or wireless charging module may be connected to a charger. The battery 2600 may be charged using power adjusted by a charger. The charger or converter may be implemented as an element independent from the power management chip 2100, or may be implemented as at least part of the power management chip 2100. The battery 2600 may transmit stored power to the power management chip 2100. Power through the interface circuit or power through the wireless charging module may be delivered to the battery 2600 or may be delivered to the power management chip 2100.

Meanwhile, the present invention is applicable to a neural network operation system.

Figure 14 is a diagram showing a neural network operation system 3000 according to an embodiment of the present invention. Referring to FIG. 14, the neural network operation system 3000 may execute a neural network model. A neural network model is a model of the learning method in which the human brain processes information, and can refer to a model that can accurately recognize and determine objects or specific information from various user data such as voice, image, video, etc.

The neural network operation system 3000 is a mobile device such as a portable communication terminal (mobile phone), smart phone, tablet PC (tablet personal computer), wearable device, healthcare device, or IoT (internet of things) device. It could be a system. However, the neural network operation system 3000 is not necessarily limited to mobile systems, but may be used in vehicle equipment such as personal computers, laptop computers, servers, media players, or navigation. (automotive device), etc.

The neural network operation system 3000 may include a system bus 3001, a processor 3100, a memory controller 3200, and a memory device 3300. System bus 3001 may support communication between processor 3100, memory controller 3200, and memory device 3300.

The processor 3100 may perform a neural network operation using data stored in the memory device 3300. For example, a neural network operation may include reading data and weights for each node included in the neural network model, performing a convolution operation on the data and weights, and storing or outputting the operation results. Additionally, the processor 3100 includes a Central Processing Unit (CPU) 3110, a Graphic Processing Unit (GPU) 3120, a Neural Processing Unit (NPU) 3130, a Digital Signal Processor (DSP) 3140, an accelerator 3150, and a power supply. It may include a management unit 3160 (PMU).

The CPU 3110 may be a highly versatile computing device. The GPU 3120 may be a computing device optimized for parallel operations such as graphics processing. The NPU 3130 is an operation device optimized for neural network operations and may include logical blocks for executing unit operations mainly used in neural network operations, such as convolution operations. The DSP 3140 may be an arithmetic device optimized for real-time digital processing of analog signals. The accelerator 3150 may be a computing device to quickly perform a specific function. When the processor 3100 executes a neural network model, various hardware devices may operate together. For example, in order to execute a neural network model, heterogeneous computing devices such as the NPU 3130 as well as the CPU 3110 and GPU 3120 may operate together. In addition, the memory controller 3200 and the data bus 3001 may operate to read input data of the neural network model and store output data.

This is a diagram illustrating the hierarchical structure of a neural network operation system according to an embodiment of the present invention. A neural network computing system may include a hardware layer (HW), a system software layer (SW), and an application layer (APP). The hardware layer (HW) is the lowest layer of the neural network operation system and may include hardware devices such as a system bus, processor, and memory controller. A processor may include heterogeneous computing devices, such as CPU, GPU, NPU, DSP, and other accelerators. The system software layer (SW) manages the hardware devices of the hardware layer (HW) and can provide an abstracted platform.

For example, the system software layer (SW) can run a kernel such as Linux. The system software layer (SW) may include DVFS and neural network model executor. DVFS can determine the operating frequency of hardware devices for each memory layer using microarchitecture information. The neural network model executor can execute the neural network model using hardware devices operating at an operating frequency determined by DVFS. Additionally, the neural network model executor can output the actual execution time of the neural network model as a result of neural network model execution. Additionally, the system software layer (SW) may be driven by a processor. For example, the system software layer (SW) may be driven by the CPU. However, it should be understood that the computing device on which the system software layer (SW) can run is not limited to the CPU. The application layer (APP) may run on the system software layer (SW) and may include multiple neural network models and other applications. For example, other applications may include a camera application.

Power management unit 3160 (PMU) may be implemented to select and execute an optimal low power state based on past history during idle time, as described in FIGS. 1 to 13 . The power management unit 3160 may be implemented in software, hardware, or firmware. Additionally, the power management unit 3160 may cause the processor 3100 to enter a low-power mode by selecting an optimal low-power state using a neural network.

The memory controller 3200 may be implemented to control an operation of storing data received from the processor 3100 in the memory device 3300 and an operation of outputting data stored in the memory device 3300 to the processor 3100.

The memory device 3300 may be implemented to store data necessary for the processor 3100 to perform a neural network operation. For example, one or more neural network models that can be executed by the processor 3100 may be loaded into the memory device 3300. Additionally, the memory device 3300 may store input data and output data of a neural network model. The memory device 3300 may include volatile memory such as Dynamic Random Access Memory (DRAM), Synchronous DRAM (SDRAM), Static RAM (SRAM), Resistive RAM (RRAM), and non-volatile memory such as flash memory. You may.

The term “module” used in this disclosure may mean, for example, a unit that includes one or a combination of two or more of hardware, software, or firmware. “Module” may be used interchangeably with terms such as unit, logic, logical block, component, or circuit, for example. A “module” can be the smallest unit of integrated parts or a part thereof. A “module” may be the minimum unit or part of one that performs one or more functions. A “module” may be implemented mechanically or electronically. For example, a “module” according to the present disclosure is an Application-Specific Integrated Circuit (ASIC) chip, Field-Programmable Gate Arrays (FPGAs), or programmable logic device, known or to be developed in the future, that performs certain operations. logic device).

According to various embodiments, at least a portion of the device (e.g., modules or functions thereof) or method (e.g., operations) according to the present disclosure is stored in a computer-readable storage medium (e.g., in the form of a programming module). -can be implemented as instructions stored in readable storage media). When an instruction is executed by one or more processors, one or more processors may perform a function corresponding to the instruction. A computer-readable storage medium may be, for example, memory. At least a portion of the programming module may be implemented, for example, by a processor. At least a portion of a programming module may include, for example, modules, programs, routines, sets of instructions, or processes to perform one or more functions.

The present invention discloses a power management policy based on power consumption by power state and past history. The present invention can estimate and determine the Power State that can save the most power when entering low power. To achieve this, quantified numbers are needed to compare the low-power efficiency of each Power State. Quantified values according to an embodiment of the present invention can be calculated using power consumption, average entry consumption time, and entry success rate. For example, the calculation method may be determined as power consumption x (given idle time - average entry consumption time) x entry success rate x correction value. Additionally, accuracy can be improved by updating the entry consumption time and entry success rate at each low-power processing. The present invention reduces entry failure costs and enables quick post-processing during low-power processing. To achieve this, devices with a high probability of entry failure must be processed first.

The present invention updates the entry success rate of each device and provides processing priorities accordingly. The entry success rate and processing priority are updated for each device's entry success/failure. The low-power state selection method of the OS includes selecting a low-power state based on power consumption in the low-power state and the existing low-power state entry success rate/low-power entry consumption time. A method is used to select the optimal Power State based on the power consumption of the low-power state, entry consumption time, and entry success rate. Accuracy is improved by continuously updating entry consumption time and entry success rate.

The method of processing each device into a low-power state includes determining and processing the low-power processing order based on the existing low-power state entry success rate and set priority for each device. Priority is provided based on the entry success rate for each device. Accuracy is improved by continuously updating the entry success rate and priority.

The RTOS' low-power state (Idle Time) processing process generates Idle Time, and the role of the OS includes managing various programs and managing devices. If there is a period (Idle Time) in which no program is occupying the CPU, the OS may enter a low power state. This low-power state can be very important in power-consumption-sensitive products.

When selecting a Power State, as the Idle Time occurs in many different ways, the logically defined Power State can also exist in various ways. And depending on each power state, the device configuration included in low-power processing may vary. Depending on the situation, the processing process may vary even within the same device. Therefore, the time until actual entry may be different each time, and whether entry (success or failure) may also vary.

When performing low-power processing for each device, devices that will enter a low-power state are processed one by one according to the selected power state. Only when all relevant devices are processed into a low-power state can they enter the selected power state. If a specific device cannot enter the low-power state, it cannot transition to the selected power state, so all devices that have already entered the low-power state must be restored to their original state.

There is a table for the history of time spent until entry and the history of entry success rate. It has two data tables and is updated each time low power is entered. The state-specific data table manages the power consumption, minimum maintenance time, average entry consumption time, and number of success/failures for each state, which is used to calculate and quantify the power consumption of each state. The device-specific data table manages the low-power entry success rate for each device, which is used to determine the low-power processing order of each device.

Meanwhile, the contents of the present invention described above are only specific examples for carrying out the invention. The present invention will include not only concrete and practically usable means, but also technical ideas, which are abstract and conceptual ideas that can be used as technology in the future.

100: electronic device
110: System-on-Chip
120: buffer memory
130: Power management chip

Claims (20)

In a method of operating an electronic device,
generating an idle state;
selecting one of a plurality of low power states in a low power management module; and
Entering each of the plurality of devices into a low-power mode according to the selected low-power state,
The method of claim 1 , wherein the selecting step includes selecting the low power state by evaluating the time conditions of the idle state, power consumption, and entry success rate of previous low power states. According to claim 1,
A method wherein the low-power management module is implemented in software, hardware, or firmware. According to claim 1,
The method further includes configuring the low power management module using a special function register. According to claim 1,
The selection step is,
A method comprising selecting the low power state based on power consumption, low power entry success rate, and low power consumption time. According to claim 4,
The low-power entry success rate is calculated using the number of entry successes and entry failures of each of the plurality of devices in a low-power state. According to claim 1,
The electronic device includes a first table having first data corresponding to each of the plurality of low power states and a second table having second data corresponding to each of the plurality of devices according to the selected low power state,
The first data includes power consumption, minimum holding time, average entry time, number of successes or failures,
Wherein the second data includes priority, number of successes, number of failures, or next entry index. According to claim 6,
The step of entering the low power mode is,
determining a processing order for each of the plurality of devices according to the selected low power state; and
The method further includes entering each of the plurality of devices into a low power mode according to the processing order. According to claim 6,
After entering the low power mode, the method further includes updating the first table and the second table. According to claim 1,
The step of entering the low power mode is,
A method including the step of preferentially entering a low-power mode among the plurality of devices with the highest probability of entry failure. According to claim 1,
updating the entry failure probability of each of the plurality of devices; and
The method further includes determining a processing priority of the device according to the entry failure probability. A special function register that stores configuration data for low-power management;
A first table storing first data for each low-power state;
a second table storing second data for each device corresponding to a low power state; and
A logic circuit that selects one of a plurality of low-power states using the setting data, first data, and second data, and determines the low-power entry success rate and priority of each of the plurality of devices according to the selected low-power state. Power management chip containing. According to claim 11,
The setting data includes data indicating whether to configure the first table and the second table externally or internally, data indicating the number of entries in the first table and the second table, and idle time. data, data indicating the standard number of average consumption times, data indicating the standard number of low-power entry success rates, data indicating the correction value to be used for low-power state selection, data indicating the current operating state and selected state, and processing order. A power management chip comprising data indicating a reference number of times for calculation, or data indicating an entry index of the first processing order of the device. According to claim 11,
A power management chip wherein the logic circuit includes a timer for measuring consumption time to enter a low power state. According to claim 11,
The logic circuit includes a state selection logic that selects one of the plurality of low-power states based on time conditions, power consumption, and low-power entry success rate according to the first data and the second data. According to claim 11,
a data table update logic for each low-power state that calculates an average consumption time of a state entry, calculates an entry success rate of the state entry, and updates the first data according to the average consumption time and the entry success rate;
Device-specific data table update logic that updates the second data with the number of successes and number of failures of each of the plurality of devices according to the selected low power state; and
A power management chip comprising device processing order update logic that calculates a processing order of the plurality of devices according to the second data and updates a next-order entry index of each entry. system-on-a-chip;
a buffer memory that temporarily stores data required for operation of the system-on-chip;
a power management chip that manages power of the system-on-chip;
A display device that displays display data;
A touch panel that generates touch data; and
A storage device for storing data from the system-on-chip,
The power management chip selects one of the plurality of low power states based on the power consumption of each of the plurality of low power states, the consumption time history until low power entry, and the low power entry success rate history, and enters the selected low power state. Accordingly, an electronic device characterized in that each of the system on chip, the buffer memory, the display device, the touch panel, and the storage device enters a low power mode. According to claim 16,
The system-on-chip electronic device includes an accelerator that drives a low-power acceleration module to accelerate a low-power mode. According to claim 16,
The power management chip determines the low-power processing order of the system on chip, the buffer memory, the display device, the touch panel, and the storage device based on the low-power entry success rate and set priority for each device. Electronic devices. According to claim 16,
The electronic device is characterized in that the power management chip is disposed inside the system-on-chip. According to claim 16,
The power management chip is,
a first table having entries corresponding to each of the plurality of low power states; and
a second table corresponding to each of the system-on-chip, the buffer memory, the display device, the touch panel, and the storage device;
The electronic device, wherein the first table and the second table are updated after a low-power processing operation.

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