KR20240042592A - Semiconductor devices and manufacturing method thereof - Google Patents

Abstract

A semiconductor device of an exemplary embodiment includes a plate layer having a first region and a second region; They are stacked and spaced apart from each other along a first direction on the first area, extend to different lengths along a second direction perpendicular to the first direction on the second area, and have a top surface exposed upwardly in the second area. gate electrodes each including a pad area and a stacked area other than the pad area; interlayer insulating layers alternately stacked with the gate electrodes; Channel structures extending along the first direction and penetrating the gate electrodes on the first region and each including a channel layer; and electrically connected to the first gate electrode while penetrating the pad area of a first gate electrode, which is one of the gate electrodes, and penetrating the stacked area of a second gate electrode disposed below the first gate electrode. and a contact plug spaced apart from the second gate electrode, wherein the pad area extends from the stacked area and has a first thickness, and protrudes in the first direction over the base part, forming the pad area into the first direction. It may include a protruding portion extending to a second thickness greater than the first thickness, and the protruding portion may include a side surface that is concavely recessed toward the contact plug penetrating the pad area.

Description

Semiconductor device and manufacturing method thereof {SEMICONDUCTOR DEVICES AND MANUFACTURING METHOD THEREOF}

The present invention relates to semiconductor devices and methods for manufacturing the same.

In data storage systems that require data storage, semiconductor devices capable of storing high-capacity data are required. Accordingly, ways to increase the data storage capacity of semiconductor devices are being studied. For example, as one of the methods for increasing the data storage capacity of a semiconductor device, a semiconductor device including memory cells arranged three-dimensionally instead of memory cells arranged two-dimensionally has been proposed.

One of the technical tasks to be achieved by the present invention is to provide a semiconductor device that is easy to manufacture and has improved electrical characteristics and reliability.

A semiconductor device according to example embodiments includes a plate layer having a first region and a second region; They are stacked and spaced apart from each other along a first direction on the first area, extend to different lengths along a second direction perpendicular to the first direction on the second area, and have a top surface exposed upwardly in the second area. gate electrodes each including a pad area and a stacked area other than the pad area; interlayer insulating layers alternately stacked with the gate electrodes; Channel structures extending along the first direction and penetrating the gate electrodes on the first region and each including a channel layer; and electrically connected to the first gate electrode while penetrating the pad area of a first gate electrode, which is one of the gate electrodes, and penetrating the stacked area of a second gate electrode disposed below the first gate electrode. and a contact plug spaced apart from the second gate electrode, wherein the pad area extends from the stacked area and has a first thickness, and protrudes in the first direction over the base part, forming the pad area into the first direction. It may include a protruding portion extending to a second thickness greater than the first thickness, and the protruding portion may include a side surface that is concavely recessed toward the contact plug penetrating the pad area.

A method of manufacturing a semiconductor device according to example embodiments includes forming a mold structure alternately including a plurality of interlayer insulating layers and a plurality of sacrificial insulating layers on a plate layer; sequentially etching the mold structure to form a plurality of stepped structures in the plurality of sacrificial insulating layers; sequentially forming a first preliminary sacrificial layer and a second preliminary sacrificial layer on the plurality of step structures of the mold structure; The first preliminary sacrificial layer and the second preliminary sacrificial layer on the side surfaces of the stepped structure are etched, and only the upper surfaces of the plurality of sacrificial insulating layers are left to remain, so that the preliminary pad including the first sacrificial layer and the second sacrificial layer forming a region; and removing the preliminary pad area and the plurality of sacrificial insulating layers and filling the removed space with a conductive layer to form a plurality of gate electrodes including a pad area. The step of forming the preliminary pad area may include etching the upper surface of the first sacrificial layer to have a smaller area than the upper surface of the second sacrificial layer.

According to the present invention, when forming the sacrificial layer forming the pad area of the gate electrodes in multiple layers, silicon boronitride is included as the outermost sacrificial layer on the silicon nitride to prevent surface damage from the etchant when forming the pad area. A semiconductor device with improved reliability can be provided.

The various and beneficial advantages and effects of the present invention are not limited to the above-described content, and may be more easily understood through description of specific embodiments of the present invention.

1 is a schematic plan view of a semiconductor device according to example embodiments.
2A to 2B are schematic cross-sectional views of semiconductor devices according to example embodiments.
Figure 3 is an enlarged cross-sectional view of a portion of Figure 2A.
4 and 5 are cross-sectional views of semiconductor devices according to example embodiments.
6A to 6K are schematic cross-sectional views for explaining a method of manufacturing a semiconductor device according to example embodiments.
FIG. 7 is a diagram schematically showing a data storage system including a semiconductor device according to example embodiments.
8 is a perspective view schematically showing a data storage system including a semiconductor device according to an example embodiment.
9 is a cross-sectional view schematically showing a semiconductor package according to an exemplary embodiment.

Hereinafter, preferred embodiments of the present invention will be described with reference to the attached drawings. Hereinafter, terms such as 'upper', 'top', 'upper surface', 'top', 'lower', 'lower', 'lower surface', 'bottom', 'side', etc. are indicated with reference numerals and are referred to separately. Except, it may be understood that the reference is made based on the drawings.

1 is a schematic plan view of a semiconductor device according to example embodiments.

2A and 2B are schematic cross-sectional views of semiconductor devices according to example embodiments. Figures 2a and 2b show cross-sections along section lines I-I' and II-II' of Figure 1, respectively.

FIG. 3 is a partially enlarged view illustrating some areas of a semiconductor device according to example embodiments. FIG. 3 shows an enlarged view of area 'A' in FIG. 2A.

1 to 3, the semiconductor device 100 includes a peripheral circuit region (PERI), which is a first semiconductor structure including a substrate 201, and a cell region (PERI), which is a second semiconductor structure including a plate layer 101. CELL) may be included. The memory cell area CELL may be disposed on the peripheral circuit area PERI. In example embodiments, on the contrary, the cell area CELL may be disposed below the peripheral circuit area PERI.

The peripheral circuit region (PERI) includes the substrate 201, the impurity regions 205 and device isolation layers 210 within the substrate 201, the circuit elements 220 disposed on the substrate 201, and the peripheral region. It may include an insulating layer 290, a lower protective layer 298, lower contact plugs 270, and lower wiring lines 280.

The substrate 201 may have an upper surface extending in the x and y directions. An active area may be defined on the substrate 201 by device isolation layers 210 . Impurity regions 205 containing impurities may be disposed in a portion of the active region. The substrate 201 may include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. Substrate 201 may be provided as a bulk wafer or an epitaxial layer.

Circuit elements 220 may include planar transistors. Each circuit element 220 may include a circuit gate dielectric layer 222, a spacer layer 224, and a circuit gate electrode 225. Impurity regions 205 may be disposed as source/drain regions in the substrate 201 on both sides of the circuit gate electrode 225.

The peripheral area insulating layer 290 may be disposed on the circuit element 220 on the substrate 201. The peripheral area insulating layer 290 may include first and second peripheral area insulating layers 292 and 294, and the first and second peripheral area insulating layers 292 and 294 may each include a plurality of insulating layers. may include. The peripheral area insulating layer 290 may be made of an insulating material.

The lower protective layer 298 may be disposed on the upper surface of the uppermost third lower wiring lines 286 between the first and second peripheral area insulating layers 292 and 294. In example embodiments, the lower protective layer 298 may be further disposed on the top surfaces of the first and second lower wiring lines 282 and 284. The lower protective layer 298 may be a layer to prevent contamination of the lower wiring lines 280 disposed below by metal materials. The lower protective layer 298 may be made of an insulating material different from the surrounding area insulating layer 290 and may include, for example, silicon nitride.

The lower contact plugs 270 and lower wiring lines 280 may form a lower wiring structure electrically connected to the circuit elements 220 and the impurity regions 205. The lower contact plugs 270 may have a cylindrical shape, and the lower wiring lines 280 may have a line shape. The lower contact plugs 270 may include first to third lower contact plugs 272, 274, and 276. The first lower contact plugs 272 are disposed on the circuit elements 220 and the impurity regions 205, and the second lower contact plugs 274 are disposed on the first lower wiring lines 282. And the third lower contact plugs 276 may be disposed on the second lower wiring lines 284. The lower wiring lines 280 may include first to third lower wiring lines 282, 284, and 286. The first lower wiring lines 282 are disposed on the first lower contact plugs 272, the second lower wiring lines 284 are disposed on the second lower contact plugs 274, and the third lower wiring lines 282 are disposed on the first lower contact plugs 272. Lower wiring lines 286 may be disposed on the third lower contact plugs 276 . The lower contact plugs 270 and lower wiring lines 280 may include a conductive material, for example, tungsten (W), copper (Cu), aluminum (Al), etc., respectively. The configurations may further include a diffusion barrier. However, in example embodiments, the number of layers and arrangement of the lower contact plugs 270 and lower wiring lines 280 may vary.

The memory cell region CELL has first to third regions R1, R2, and R3, and includes a source structure SS, gate electrodes 130 stacked on the source structure SS, and gate electrodes ( 130), interlayer insulating layers 120 alternately stacked, channel structures CH arranged to penetrate the stacked structure of the gate electrodes 130 in the first region R1, and the gate electrodes 130. First and second separation regions MS1, MS2a, and MS2b extend through the stacked structure, and are connected to the pad regions 130P of the gate electrodes 130 in the second region R2 and extend vertically. may include contact plugs 170.

The memory cell region CELL includes the outer insulating layer 150E disposed outside the source structure SS, the substrate insulating layer 121, and the first region disposed below the gate electrodes 130 in the first region R1. The first and second horizontal conductive layers 102 and 104, the horizontal insulating layer 110 disposed below the gate electrodes 130 together with the second horizontal conductive layer 104 in the second region R2, and the gate Upper separation regions US penetrating a portion of the electrodes 130, support structures DCH disposed to penetrate the stacked structure of the gate electrodes 130 in the second region R2, and a memory cell region. through vias 175 extending from the (CELL) to the peripheral circuit area (PERI), upper contact plugs 180 on the channel structures (CH) and contact plugs 170, and gate electrodes 130. It may further include a covering cell region insulating layer 190.

In the memory cell region CELL, the first region R1 is an area where the gate electrodes 130 are vertically stacked and the channel structures CH are disposed, and may be an area where memory cells are disposed. The second region R2 is an area where the gate electrodes 130 extend to different lengths, and together with the third area R3, it corresponds to an area for electrically connecting the memory cells to the peripheral circuit area PERI. can do. The second region R2 may be disposed at at least one end of the first region R1 in at least one direction, for example, the x direction. The third area R3 is located outside the second area R2 and may be an area where the source structure SS is not disposed.

The source structure SS may include a plate layer 101, a first horizontal conductive layer 102, and a second horizontal conductive layer 104 sequentially stacked in the first region R1. The source structure SS may include a plate layer 101 and a second horizontal conductive layer 104 in the second region R2. However, in example embodiments, the number of conductive layers forming the source structure SS may vary.

The plate layer 101 has the shape of a plate and may function as at least part of the common source line of the semiconductor device 100. The plate layer 101 may have an upper surface extending in the x and y directions. The plate layer 101 may include a conductive material. For example, the plate layer 101 may include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. For example, Group IV semiconductors may include silicon, germanium, or silicon-germanium. The plate layer 101 may further include impurities. The plate layer 101 may be provided as a polycrystalline semiconductor layer such as a polycrystalline silicon layer or an epitaxial layer.

The first and second horizontal conductive layers 102 and 104 may be sequentially stacked and disposed on the upper surface of the plate layer 101 in the first region R1. The first horizontal conductive layer 102 may not extend into the second region R2, and the second horizontal conductive layer 104 may extend into the second region R2. The first horizontal conductive layer 102 may function as part of a common source line of the semiconductor device 100, for example, may function as a common source line together with the plate layer 101. As shown in the enlarged view in FIG. 2B, the first horizontal conductive layer 102 may be directly connected to the channel layer 140 around the channel layer 140. The second horizontal conductive layer 104 may contact the plate layer 101 in some areas of the second region R2 where the first horizontal conductive layer 102 and the horizontal insulating layer 110 are not disposed. .

The first and second horizontal conductive layers 102 and 104 may include a semiconductor material, for example, polycrystalline silicon. In this case, at least the first horizontal conductive layer 102 may be a layer doped with impurities of the same conductivity type as the plate layer 101, and the second horizontal conductive layer 104 may be a doped layer or a first horizontal conductive layer. It may be a layer containing impurities diffused from (102). However, the material of the second horizontal conductive layer 104 is not limited to semiconductor material, and may be replaced with an insulating layer.

The horizontal insulating layer 110 may be disposed on the plate layer 101 at the same level as the first horizontal conductive layer 102 in at least a portion of the second region R2. The horizontal insulating layer 110 may include first and second horizontal insulating layers 111 and 112 alternately stacked on the second region R2 of the plate layer 101 . The horizontal insulating layer 110 may be layers that remain after a portion of the horizontal insulating layer 110 is replaced with the first horizontal conductive layer 102 during the manufacturing process of the semiconductor device 100.

The horizontal insulating layer 110 may include silicon oxide, silicon nitride, silicon carbide, or silicon oxynitride. The first horizontal insulating layers 111 and the second horizontal insulating layers 112 may include different insulating materials. For example, the first horizontal insulating layers 111 may be made of the same material as the interlayer insulating layers 120, and the second horizontal insulating layer 112 may be made of a different material from the interlayer insulating layers 120. there is.

The substrate insulating layer 121 may be disposed to penetrate the plate layer 101, the horizontal insulating layer 110, and the second horizontal conductive layer 104 in the third region R3, and the outer insulating layer ( 150E) can be placed on. The substrate insulating layer 121 may be further disposed in the first region R1 and the second region R2, for example, in a region where through vias 175 are additionally disposed. The top surface of the substrate insulating layer 121 may be coplanar with the top surface of the source structure SS. The substrate insulating layer 121 may include an insulating material, for example, silicon oxide, silicon nitride, silicon carbide, or silicon oxynitride.

The gate electrodes 130 may be stacked on the plate layer 101 while being vertically spaced apart to form a stacked structure together with the interlayer insulating layers 120 . The stacked structure may include vertically stacked lower and upper stacked structures. However, depending on embodiments, the laminated structure may be composed of a single laminated structure.

The gate electrodes 130 include lower gate electrodes 130L forming the gate of the ground selection transistor, memory gate electrodes 130M forming a plurality of memory cells, and gates of the string selection transistors. It may include upper gate electrodes 130U forming the gate electrodes 130U. The number of memory gate electrodes 130M forming memory cells may be determined depending on the capacity of the semiconductor device 100. Depending on the embodiment, the number of upper and lower gate electrodes 130U and 130L may be one to four or more, respectively, and may have the same or different structure as the memory gate electrodes 130M. In example embodiments, the gate electrodes 130 are disposed above the upper gate electrodes 130U and/or below the lower gate electrodes 130L and generate a gate induced leakage current (GIDL). It may further include a gate electrode 130 forming an erase transistor used in an erase operation using a phenomenon. Additionally, some of the gate electrodes 130, for example, the memory gate electrodes 130M adjacent to the upper or lower gate electrodes 130U and 130L, may be dummy gate electrodes.

As shown in FIG. 1, the gate electrodes 130 are separated from each other in the y direction by first separation regions MS1 extending continuously from the first region R1 and the second region R2. can be placed. The gate electrodes 130 between the pair of first separation regions MS1 may form one memory block, but the scope of the memory block is not limited thereto. Some of the gate electrodes 130, for example, the memory gate electrodes 130M, may each form one layer within one memory block.

The gate electrodes 130 are vertically spaced apart from each other and stacked on the first region (R1) and the second region (R2) to form a stacked region, and are formed in different directions from the first region (R1) to the second region (R2). It may be extended in length to form a stepped structure in the form of steps in a portion of the second region R2. The gate electrodes 130 may be arranged to have a stepped structure in the y direction. Due to the step structure, the lower gate electrode 130 extends longer than the upper gate electrode 130, so that the upper gate electrode 130 extends from the interlayer insulating layers 120 and other gate electrodes 130. Each of the upper surfaces may have exposed areas, and these areas may be referred to as pad areas 130P. In each gate electrode 130, the pad area 130P may be an area including an end of the gate electrode 130 along the x-direction. The gate electrodes 130 may be respectively connected to the contact plugs 170 in the pad areas 130P. The gate electrodes 130 may have an increased thickness in the pad areas 130P.

Specifically, referring to FIG. 3, the gate electrode 130 has a first thickness t1 in the stacked region of the first region R1 and the second region R2, and has a first thickness t1 in the pad region 130P. It may have a second thickness (t2) greater than (t1). To this end, the pad area 130P extends from the stacked area of the gate electrode 130, and includes a base portion 130B having the same first thickness t1 and a protruding portion protruding in the z direction from the base portion 130B ( It can be defined as including 130PP). The second thickness t2 of the pad area 130P may be extended upward in the z direction from the reference surface ls, which is the upper surface of the base portion 130B having the first thickness t1. Accordingly, the pad area 130P may protrude from the reference surface ls by a third length t3 to form a protruding portion 130PP.

The third length t3 may satisfy 1/2 to 4/5 of the first thickness t1, but is not limited thereto. For example, when the first thickness t1 of the gate electrode 130 is 150 Å, the third length t3 may be approximately 75 Å to 120 Å. Accordingly, the second thickness t2, which is the total thickness of the pad area 130P, may satisfy 225 Å to 270 Å.

A gate groove gg may be formed between the side wall of the upper gate electrode 130, that is, the side wall of the stepped structure, and the pad area 130P of the current gate electrode 130, and the gate groove gg may be formed between the gate electrodes 130. After the etching process to form the step-shaped step structure of (130), sacrificial layers for forming the pad area 130P may be formed, and then side etching may be performed. The gate groove gg may be formed to be partially recessed from the upper surface of the base portion 130B of the gate electrode 130, that is, the reference surface ls, but otherwise, it is formed to satisfy the depth of the third length t3. It could be.

The pad area 130P protrudes upward in the z direction by a third length t3 from the reference surface ls, and has an inner side S1 connected from the gate groove gg to the top n2 of the pad area 130P. It may include an external side (S2) exposed to the side wall of the step structure. The inner side (S1) and the outer side (S2) may each include a curved surface.

The curved surface of the inner side S1 may be disposed throughout the inner side S1 from the reference surface ls to the top n2 of the pad area 130P, but is not limited thereto. For example, it may have an inclined surface whose diameter decreases from the reference surface ls to a predetermined level, have an inflection point n3 at the predetermined level, and be bent from the inclined surface to form a curved surface whose diameter increases up to the top n2. The predetermined level, that is, the inflection point n3, may be closer to the upper surface between the reference surface ls and the upper surface of the pad area 130P. The top n2 of the inner side S1 may be disposed to be closer to the upper gate electrode 130 than the inflection point n3. Accordingly, the inner side surface S1 may include a curved surface that is concavely recessed toward the contact plug 170 penetrating the inside.

With respect to the lower interlayer insulating layer 120, the base portion 130B of the pad area 130P has the same area as the lower interlayer insulating layer 120 so as to overlap in the z direction, and the outer side of the base portion 130B ( S2) and the side surfaces of the lower interlayer insulating layer 120 may be arranged in a straight line. In the protruding portion 130PP, the outer side S2 may be disposed to be closer to the contact plug 170 penetrating the inside than the outer side S2 of the base portion 130B. Accordingly, the outer side S2 may have a bent portion so that the protruding portion 130PP of the pad area 130P has a shorter length than the base portion 130B, but is not limited thereto. The outer side S2 of the pad area 130P may also include a curved surface. The outer side S2 of the protruding portion 130PP may have an inclined surface whose diameter decreases from the reference surface ls to a predetermined level, has an inflection point n3 at a predetermined level, and is bent from the inclined surface to the upper end n1. A curved surface with a larger diameter can be formed. The top n1 of the outer side S2 may overlap the side of the lower base portion 130B in the z-direction or may not protrude outward, but is not limited thereto.

As such, the top n2 of the inner side S1 and the top n1 of the outer side S2 of the pad area 130P may have a tip, but are not limited thereto, and may include a vertical portion. . This is formed depending on the etching speed of the sacrificial layers during the process, and can be changed depending on the residual thickness of silicon bonitride, which has strong resistance to etchant in the outermost layer.

The diameter of the protruding portion 130PP of the pad area 130P decreases in the z direction from the top (n1, n2) of both sides (S1, S2), that is, the upper surface, and then passes the inflection point (n3) and returns to the reference surface (ls). However, as the upper surface of the protruding part (130PP) overlaps perpendicularly with the pad area (130P), the area of the upper surface of the protruding part (130PP) can meet the area of the pad area (130P). there is. Accordingly, the pad area 130P includes curved sides that are concave inside, thereby preventing short circuits with neighboring gate electrodes 130. In addition, when stacking sacrificial layers to expand the thickness of the pad area 130P, silicon boronitride (SiBN) is placed on the outermost layer, thereby forming a high density of silicon bonitride during etching to form the gate groove gg. The bonding force can dramatically reduce defects caused by pits on the surface.

The gate electrodes 130 may include a metal material, for example, tungsten (W). Depending on the embodiment, the gate electrodes 130 may include polycrystalline silicon or metal silicide material. In example embodiments, the gate electrodes 130 may further include a diffusion barrier, for example, the diffusion barrier may include tungsten nitride (WN), tantalum nitride (TaN), or titanium nitride (TiN). , or a combination thereof.

Interlayer insulating layers 120 may be disposed between the gate electrodes 130 . Like the gate electrodes 130, the interlayer insulating layers 120 may be arranged to be spaced apart from each other in a direction perpendicular to the upper surface of the plate layer 101 and extend in the x-direction. The interlayer insulating layers 120 may include an insulating material such as silicon oxide or silicon nitride.

The channel structures CH each form one memory cell string, and may be arranged to be spaced apart from each other in rows and columns on the plate layer 101 in the first region R1. The channel structures CH may be arranged to form a grid pattern in the x-y plane or may be arranged in a zigzag shape in one direction. The channel structures CH have a pillar shape and may have inclined side surfaces that become narrower as they approach the plate layer 101 depending on the aspect ratio. Depending on embodiments, at least some of the channel structures CH disposed at the end of the first region R1 may be dummy channels.

The channel structures CH may include first and second channel structures CH1 and CH2 that are vertically stacked. The channel structures CH may have a shape in which the lower first channel structures CH1 and the upper second channel structures CH2 are connected, and may have a bent portion due to a difference in width in the connection area. However, depending on embodiments, the number of channel structures stacked along the z-direction may vary.

Each of the channel structures CH may include a channel layer 140, a gate dielectric layer 145, a channel buried insulating layer 147, and a channel pad 149 disposed within the channel hole. As shown in the enlarged view in FIG. 2B, the channel layer 140 may be formed in an annular shape surrounding the internal channel-filled insulating layer 147, but depending on the embodiment, the channel-filled insulating layer 147 Without this, it may have a pillar shape such as a cylinder or a prism. The channel layer 140 may be connected to the first horizontal conductive layer 102 at the bottom. The channel layer 140 may include a semiconductor material such as polycrystalline silicon or single crystalline silicon.

The gate dielectric layer 145 may be disposed between the gate electrodes 130 and the channel layer 140. Although not specifically shown, the gate dielectric layer 145 may include a tunneling layer, a charge storage layer, and a blocking layer sequentially stacked from the channel layer 140. The tunneling layer may tunnel charges into the charge storage layer and may include, for example, silicon oxide (SiO ₂ ), silicon nitride (Si ₃ N ₄ ), silicon oxynitride (SiON), or a combination thereof. there is. The charge storage layer may be a charge trap layer or a floating gate conductive layer. The blocking layer may include silicon oxide (SiO ₂ ), silicon nitride (Si ₃ N ₄ ), silicon oxynitride (SiON), a high-k dielectric material, or a combination thereof. In example embodiments, at least a portion of the gate dielectric layer 145 may extend in a horizontal direction along the gate electrodes 130 .

The channel pad 149 may be disposed only on the top of the upper second channel structure CH2. The channel pad 149 may include, for example, doped polycrystalline silicon.

The channel layer 140, the gate dielectric layer 145, and the channel buried insulating layer 147 may be connected to each other between the first channel structure CH1 and the second channel structure CH2. A relatively thick upper interlayer insulating layer 125 may be disposed between the first channel structure CH1 and the second channel structure CH2. However, the thickness and shape of the interlayer insulating layers 120 and the upper interlayer insulating layer 125 may vary in various embodiments.

The support structures DCH may be arranged to be spaced apart from each other in rows and columns on the plate layer 101 in the second region R2. As shown in FIG. 1, support structures DCH may be arranged to surround each contact plug 170 in four directions. However, in embodiments, the arrangement form of the support structures (DCH) may be changed in various ways. The support structures DCH have a pillar shape and may have inclined sides that become narrower as they approach the plate layer 101 depending on the aspect ratio.

The support structures (DCH) may have a circular, oval, or similar shape in the x-y plane. The diameter or maximum width of the support structures (DCH) may be larger than that of the channel structures (CH), but is not limited thereto. The support structures (DCH) may have the same or different internal structure as the channel structures (CH). For example, the support structures DCH may not include a conductive layer and may include an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride.

The first and second separation regions MS1, MS2a, and MS2b may be arranged to extend along the x-direction through the gate electrodes 130. The first and second separation regions MS1, MS2a, and MS2b may be arranged parallel to each other. The first and second separation regions MS1, MS2a, and MS2b penetrate the entire gate electrodes 130 stacked on the plate layer 101, and the first and second horizontal conductive layers 102 and 104 below. ) and further penetrate the horizontal insulating layer 110, and may be connected to the plate layer 101. The first separation regions MS1 extend as one along the x-direction, and the second separation regions MS2a and MS2b extend intermittently between the pair of first separation regions MS1 or only in some regions. can be placed. For example, the second central separation regions MS2a may extend as one in the first region R1 and may extend intermittently along the x-direction in the second region R2. The second auxiliary separation regions MS2b may be disposed only in the second region R2 and may extend intermittently along the x-direction. However, in embodiments, the arrangement order and number of the first and second separation regions MS1, MS2a, and MS2b are not limited to those shown in FIG. 1.

A separation insulating layer 105 may be disposed in the first and second separation regions MS1, MS2a, and MS2b. The isolation insulating layer 105 may have a shape whose width decreases toward the plate layer 101 due to its high aspect ratio, but is not limited to this and may have a side surface perpendicular to the upper surface of the plate layer 101. The isolation insulating layer 105 may include an insulating material, for example, silicon oxide, silicon nitride, or silicon oxynitride.

As shown in FIG. 1, the upper separation areas US are between the first separation areas MS1 and the second central separation area MS2a and the second central separation area in the first area R1. It may extend in the x direction between the fields MS2a. The upper separation regions US are formed through a portion of the second region R2 and the first region R1 so as to penetrate some of the gate electrodes 130 including the uppermost upper gate electrode 130U among the gate electrodes 130. ) can be placed in. The upper separation regions US may, for example, separate a total of three gate electrodes 130 from each other in the y direction, as shown in FIG. 2B. However, the number of gate electrodes 130 separated by the upper isolation regions US may vary in various embodiments. The upper separation regions US may include an upper separation insulating layer 103. The upper isolation insulating layer 103 may include an insulating material, for example, silicon oxide, silicon nitride, or silicon oxynitride.

The contact plugs 170 may be connected to the pad regions 130P of the uppermost gate electrodes 130 in the second region R2. The contact plugs 170 may penetrate at least a portion of the cell region insulating layer 190 and be connected to each of the pad regions 130P of the gate electrodes 130 exposed above. The contact plugs 170 penetrate the gate electrodes 130 below the pad regions 130P, and penetrate the horizontal insulating layer 110, the second horizontal conductive layer 104, and the plate layer 101. Thus, it can be connected to the lower wiring lines 280 in the peripheral circuit area (PERI). The contact plugs 170 may be spaced apart from the gate electrodes 130 below the pad regions 130P by the contact insulating layers 160 . The contact plugs 170 may be spaced apart from the plate layer 101, the horizontal insulating layer 110, and the second horizontal conductive layer 104 by the substrate insulating layer 121.

As shown in FIG. 2A, each of the contact plugs 170 has a vertical extension portion 170V extending along the z direction and a horizontal extension extending horizontally from the vertical extension portion 170V to contact the pad regions 130P. It may include part 170H. The horizontal extension part 170H is disposed along the circumference of the vertical extension part 170V, and the length from the side of the vertical extension part 170V to the other end may be shorter than the length of the lower contact insulating layers 160. . The gate electrode 130 extends to a first thickness t1 from the first region R1 toward the second region R2, and has a first thickness t1 in the pad regions 130P from the reference surface ls shown in FIG. 3. It may have a protruding portion 130PP in the z-direction to have a second thickness t2 greater than the thickness t1. The horizontal extension 170H may contact the pad area 130P where the gate electrode 130 has a second thickness t2.

The contact plugs 170 may include a conductive material, for example, at least one of tungsten (W), copper (Cu), aluminum (Al), and an alloy thereof. In some embodiments, the contact plugs 170 may include a barrier layer extending along the side and bottom surfaces, or may have an air gap therein.

The through via 175 is disposed outside the source structure SS, for example, the plate layer 101, and may extend through the memory cell region CELL into the peripheral circuit region PERI. The through via 175 may be arranged to connect the upper contact plugs 180 of the memory cell area (CELL) and the lower wiring lines 280 of the peripheral circuit area (PERI). The through via 175 may penetrate the cell region insulating layer 190, the substrate insulating layer 121, and the second peripheral region insulating layer 294. However, in some embodiments, the through via 175 forms sacrificial insulating layers 118 and interlayer insulating layers ( It may be arranged to penetrate the laminated structure of 120). The through via 175 may be disposed at substantially the same level as the contact plugs 170, but is not limited thereto. In some embodiments, the through via 175 may be arranged so that the upper area extends to the third lower wiring line 286 without the lower area.

The through via 175 may be deposited in the same process as the contact plugs 170 and may include the same material as the contact plugs 170 . The through via 175 may include a conductive material, for example, at least one of tungsten (W), copper (Cu), aluminum (Al), and alloys thereof.

The upper contact plugs 180 may form a cell wiring structure electrically connected to memory cells in the memory cell area CELL. The upper contact plugs 180 are connected to the channel structures (CH), contact plugs 170, and through vias 175, and may be electrically connected to the channel structures (CH) and the gate electrodes 130. there is. The upper contact plugs 180 are shown in a plug shape, but are not limited thereto and may have a line shape. In example embodiments, the number of plugs and wiring lines constituting the cell wiring structure may vary. The upper contact plugs 180 may include metal, for example, tungsten (W), copper (Cu), aluminum (Al), etc.

The cell region insulating layer 190 may be disposed to cover the stacked structure of the gate electrodes 130, the contact plugs 170, and the substrate insulating layer 121. The cell region insulating layer 190 may be made of an insulating material or may be made of a plurality of insulating layers.

FIG. 4 is a schematic cross-sectional view of a semiconductor device 100a according to example embodiments.

The semiconductor device of FIG. 4 is the same as the semiconductor device 100 of FIGS. 1 to 3 except that a first dummy structure DS1 and a second dummy structure DS2 are further formed in the third region R3. do.

The dummy structures DS1 and DS2 are disposed below the intermediate insulating layer 125 on the plate layer 101, and the first dummy structure DS1 and the plate layer 101 are disposed to be spaced apart from the lower laminated structure GS. ) and may include a second dummy structure DS2 disposed on the middle insulating layer 125 and spaced apart from the upper layered structure GS. The first dummy structure DS1 may be referred to as a 'first insulating structure', and the second dummy structure DS2 may be referred to as a 'second insulating structure'.

The first dummy structure DS1 may include first insulating layers 120 and second insulating layers 118 alternately stacked on the plate layer 101 . The first dummy structure DS1 may have steps in the form of steps. For example, the second insulating layers 118 may extend to different lengths to form a stepped structure. The second insulating layers 118 may form a step shape in which the lower second insulating layers 118 extend longer than the upper second insulating layers 118 due to the step structure. Like the second insulating layers 118, the first insulating layers 120 may have a stepped structure in the form of steps. The first dummy structure DS1 may have a shape where the upper width is smaller than the lower width due to the step shape.

The first dummy structure DS1 may be covered by the cell region insulating layer 190 together with the lower stacked structure GS. The first dummy structure DS1 may be arranged one or multiple times on the plate layer 101 .

The second dummy structure DS2 may include first insulating layers 120 and second insulating layers 118 alternately stacked on the first dummy structure DS1. The second dummy structure DS2 may have steps in the form of steps. For example, the second insulating layers 118 may extend to different lengths to form a stepped structure. The second insulating layers 118 may form a step shape in which the lower second insulating layers 118 extend longer than the upper second insulating layers 118 due to the step structure. Like the second insulating layers 118, the first insulating layers 120 may have a stepped structure in the form of steps. The second dummy structure DS2 may have a shape where the upper width is smaller than the lower width due to the step shape.

The second dummy structure DS2 is spaced apart from the upper stacked structure GS2 and the lower stacked structure GS1, and may be arranged spaced apart from the first dummy structure DS1. The second dummy structure DS2 may be arranged one or multiple times on the first dummy structure DS1.

The first insulating layers 120 are located at a height level corresponding to the first interlayer insulating layers 120, and may be formed simultaneously with substantially the same thickness and the same material as the first interlayer insulating layers 120. .

The second insulating layers 118 may be located at a height level corresponding to the gate electrodes 130 . The second insulating layers 118 may have substantially the same thickness as the gate electrodes 130 . The second insulating layers 118 may be formed of a different material from the gate electrodes 130, and a sacrificial insulating layer ( It may be the same material as 118).

The step structure of the first dummy structure DS1 and the second dummy structure DS2 may include a protruding portion on the second insulating layer 118, such as the pad area 130P of the gate electrode 130 in FIG. 3. there is.

A protruding portion including the first sacrificial layer 131 and the second sacrificial layer 132 may be disposed on the second insulating layer 118 exposed in the step structure.

When the second insulating layers 118 include silicon nitride and silicon oxynitride, the first sacrificial layer 131 and the second sacrificial layer 132 are sacrificial insulating layers 118. ) and may not have an etch selectivity with the sacrificial insulating layers 118. On the other hand, the second sacrificial layer 132 may include at least one of silicon boronitride and silicon carbonitride. Preferably, the second sacrificial layer 132 may include silicon bonitride. In an exemplary embodiment, the second insulating layers 118 and the first sacrificial layer 131 include silicon nitride, the first sacrificial layer 131 also includes silicon nitride, and the second sacrificial layer 132 It may include silicon bonitride.

The density of the first sacrificial layer 131 may be less than the density of the second sacrificial layer 132, and accordingly, the range of the etch rate for hydrofluoric acid (HF) of the first sacrificial layer 131 is It may be greater than the range of the etch rate for hydrofluoric acid (HF) of the second sacrificial layer 132. Accordingly, the etch rate of the second sacrificial layer 132 exposed on the outermost surface is smaller, so that the lower first sacrificial layer 131 remains and is etched to form a pad area 130P. That is, each protruding portion may be etched so that both sides of the first sacrificial layer 131 are recessed inward on the second insulating layer 118, and the second sacrificial layer remaining on the first sacrificial layer 131 may be etched. The area of the top surface of the layer 132 may be larger than the area of the top surface of the first sacrificial layer 131.

On the side of the pad area 130P, the first sacrificial layer 131 and the second sacrificial layer 132 are not disposed, and the adjacent pad area 130P and the first and second sacrificial layers 131 and 132 are cut. Thus, a gate groove gg may be formed between one pad area 130P and the adjacent first insulating layer 120. The gate groove gg may be formed by partially recessing the exposed upper surface of the second insulating layer 118, but is not limited thereto. In this way, the first sacrificial layer 131 may be disposed at the end of the second insulating layer 118, and the second sacrificial layer 132 may be disposed thereon. The second sacrificial layer 132 may satisfy a thickness of 10 to 20% of the first sacrificial layer 131 .

The first dummy structure DS1 may not overlap the second dummy structure DS2 in the vertical direction (eg, z-direction). The second dummy structure DS2 may not overlap the first dummy structure DS1 in the vertical direction.

By arranging the first and second dummy structures DS1 and DS2, process dispersion of the staircase structure can be minimized on both sides of the first and second stacked structures GS1 and GS2 along the x-direction. During the planarization process of the cell region insulating layer 190, a dishing phenomenon in which the upper part of the cell region insulating layer 190 is locally depressed downward toward the plate layer 101 can be minimized.

FIG. 5 is a schematic cross-sectional view of a semiconductor device 100b according to example embodiments. Figure 5 shows a cross section corresponding to Figure 2a.

Referring to FIG. 5 , the semiconductor device 100b may include a first semiconductor structure S1 and a second semiconductor structure S2 bonded using a wafer bonding method.

The description of the peripheral circuit area PERI described above with reference to FIGS. 1 to 3 may be applied to the first semiconductor structure S1. However, the first semiconductor structure S1 may further include first bonding vias 298 and first bonding metal layers 299, which are bonding structures. The first bonding vias 298 may be disposed on top of the uppermost circuit wiring lines 280 and connected to the circuit wiring lines 280 . At least a portion of the first bonding metal layers 299 may be connected to the first bonding vias 298 on the first bonding vias 298 . The first bonding metal layers 299 may be connected to the second bonding metal layers 199 of the second semiconductor structure S2. The bonding metal layers 299, together with the second bonding metal layers 199, may provide an electrical connection path for bonding the first semiconductor structure S1 and the second semiconductor structure S2. Some of the first bonding metal layers 299 may not be connected to the lower circuit wiring lines 280 and may be disposed only for bonding. The first bonding vias 298 and the first bonding metal layers 299 may include a conductive material, for example, copper (Cu). The first bonding insulating layer may be disposed around the first bonding metal layers 299 . The first bonding insulating layer may also function as a diffusion prevention layer of the first bonding metal layers 299 and may include, for example, at least one of SiN, SiON, SiCN, SiOC, SiOCN, and SiO.

For the second semiconductor structure S2, unless otherwise specified, the description of the memory cell area CELL described above with reference to FIGS. 1 to 3 may be applied. The second semiconductor structure S2 may include wiring lines, which are cell wiring structures, and may further include second bonding vias 198 and second bonding metal layers 199, which are bonding structures. The second semiconductor structure S2 may further include a passivation layer covering the upper surfaces of the second substrate 103 and the substrate insulating layer 123.

The second bonding vias 198 and the second bonding metal layers 199 may be connected to the plugs 180 and may be connected by a multilayer cell wiring structure (not shown). The second bonding vias 198 connect the cell wiring lines and the second bonding metal layers 199, and the second bonding metal layers 199 are connected to the first bonding metal layers 299 of the first semiconductor structure S1. ) can be combined with. The second bonding insulating layer may be connected to the first bonding insulating layer of the first semiconductor structure S1 by bonding. The second bonding vias 198 and the second bonding metal layers 199 may include a conductive material, for example, copper (Cu). For example, the second bonding insulating layer may include at least one of SiO, SiN, SiCN, SiOC, SiON, and SiOCN.

The first and second semiconductor structures S1 and S2 are formed by bonding the first bonding metal layers 299 and the second bonding metal layers 199 and bonding the first bonding insulating layer and the second bonding insulating layer. Can be bonded. The bonding of the first bonding metal layers 299 and the second bonding metal layers 199 may be, for example, copper (Cu)-copper (Cu) bonding, and the bonding of the first bonding insulating layer and the second bonding insulating layer may be, for example, copper (Cu)-copper (Cu) bonding. The bond may be a dielectric-dielectric bond, for example a SiCN-SiCN bond. The first and second semiconductor structures S1 and S2 may be bonded by hybrid bonding including copper (Cu)-copper (Cu) bonding and dielectric-dielectric bonding.

The passivation layer may be disposed on the upper surface of the second substrate 103 and may protect the semiconductor device 100b. The passivation layer may include at least one of insulating materials, such as silicon oxide, silicon nitride, and silicon carbide. The substrate insulating layer 123 may be widely disposed in the second region R2 and the third region R3 to cover the tops of the contact plugs 170 . However, in exemplary embodiments, the substrate insulating layer 122 may be arranged in various ways within the range of electrically separating the contact plugs 170 from the second substrate 103 .

In this embodiment, the second semiconductor structure S2 may not include the first and second horizontal conductive layers 102 and 104 (see FIG. 2B). The channel structures CH may be directly connected to the second substrate 103 with the channel layers 140 exposed through the top. However, the electrical connection form of the channel structures CH and the common source line may be changed in various embodiments, and it may be possible for the channel structures and the source structure to have the same structure as the embodiment of FIG. 2B.

6A to 6K are schematic cross-sectional views for explaining a method of manufacturing a semiconductor device according to example embodiments. FIGS. 6A to 6K show cross sections corresponding to FIG. 2A.

Referring to FIG. 6A, circuit elements 220, a lower wiring structure, and a peripheral region insulating layer 290 forming a peripheral circuit region (PERI) are formed on the substrate 201, and a second peripheral region insulating layer ( 294), openings may be formed.

First, device isolation layers 210 may be formed within the substrate 201, and a circuit gate dielectric layer 222 and a circuit gate electrode 225 may be sequentially formed on the substrate 201. The device isolation layers 210 may be formed by, for example, a shallow trench isolation (STI) process. The circuit gate dielectric layer 222 and the circuit gate electrode 225 may be formed using atomic layer deposition (ALD) or chemical vapor deposition (CVD). The circuit gate dielectric layer 222 may be formed of silicon oxide, and the circuit gate electrode 225 may be formed of at least one of polycrystalline silicon or a metal silicide layer, but is not limited thereto. Next, a spacer layer 224 and impurity regions 205 may be formed on both sidewalls of the circuit gate dielectric layer 222 and the circuit gate electrode 225. Depending on embodiments, the spacer layer 224 may be composed of multiple layers. The impurity regions 205 may be formed by performing an ion implantation process.

The lower contact plugs 270 of the lower wiring structure can be formed by forming a portion of the first peripheral area insulating layer 292, then removing a portion by etching, and then burying the first peripheral region insulating layer 292 with a conductive material. The lower wiring lines 280 can be formed, for example, by depositing a conductive material and then patterning it.

The first peripheral area insulating layer 292 may be composed of a plurality of insulating layers. The first peripheral area insulating layer 292 may be part of each step of forming the lower wiring structure. A lower protective layer 298 may be formed on the first peripheral area insulating layer 292 to cover the upper surface of the third lower wiring line 286. A second peripheral area insulating layer 294 may be formed on the lower protective layer 298. As a result, the entire peripheral circuit area (PERI) can be formed. Next, openings may be formed by partially removing the second peripheral area insulating layer 294. Openings may be formed in areas where the contact plugs 170 and through vias 175 of FIG. 2A are to be formed.

Referring to FIG. 6B, the plate layer 101 can be formed.

The openings may be filled with a material forming the plate layer 101 and the plate layer 101 may be formed on the top. As a result, pads CP may be formed. The pads CP may be a layer that is replaced with the lower region of the contact plugs 170 and the through via 175 of FIG. 2A through a subsequent process. The plate layer 101 may be made of, for example, polycrystalline silicon and may be formed through a CVD process.

A horizontal insulating layer 110 and a second horizontal conductive layer 104 are formed on the plate layer 101 and penetrate through the plate layer 101, the horizontal insulating layer 110, and the second horizontal conductive layer 104. Openings can be formed.

The first and second horizontal insulating layers 111 and 112 forming the horizontal insulating layer 110 may be alternately stacked on the plate layer 101. The horizontal insulating layer 110 may be a layer that is partially replaced with the first horizontal conductive layer 102 (see FIG. 2A) through a subsequent process. The first horizontal insulating layers 111 may include a material different from that of the second horizontal insulating layer 112 . For example, the first horizontal insulating layers 111 are made of the same material as the interlayer insulating layers 120, and the second horizontal insulating layers 112 are made of the same material as the subsequent sacrificial insulating layers 118. It can be done. The horizontal insulating layer 110 may be partially removed from some regions, for example, the second region R2, through a patterning process.

The second horizontal conductive layer 104 is formed on the horizontal insulating layer 110 and may be in contact with the plate layer 101 in the area where the horizontal insulating layer 110 has been removed. Accordingly, the second horizontal conductive layer 104 may be bent along the ends of the horizontal insulating layer 110, cover the ends, and extend onto the plate layer 101. The openings may be formed by partially removing the plate layer 101, the horizontal insulating layer 110, and the second horizontal conductive layer 104 so that the pads are exposed in the second region R2.

A substrate insulating layer 121 may be formed within the openings. The substrate insulating layer 121 is formed by depositing an insulating material that fills the openings and the area from which the plate layer 101, the horizontal insulating layer 110, and the second horizontal conductive layer 104 of the third region R3 were removed. Afterwards, it can be formed by performing a planarization process such as physical and chemical polishing (Chemical Mechanical Planarization, CMP).

Referring to FIG. 6C, the lower mold structure may be formed by alternately stacking sacrificial insulating layers 118 and interlayer insulating layers 120 on the second horizontal conductive layer 104.

The sacrificial insulating layers 118 may be a layer that is at least partially replaced with the gate electrodes 130 (see FIG. 2A) through a subsequent process. The sacrificial insulating layers 118 may be made of a material different from the interlayer insulating layers 120, and may be formed of a material that can be etched with etch selectivity under specific etching conditions with respect to the interlayer insulating layers 120. . For example, the interlayer insulating layer 120 may be made of at least one of silicon oxide and silicon nitride, and the sacrificial insulating layers 118 may be made of an interlayer insulating layer 120 selected from silicon, silicon oxide, silicon carbide, and silicon nitride. ) and may be made of other materials. In embodiments, the thicknesses of the interlayer insulating layers 120 may not all be the same. Next, photolithography is performed on the sacrificial insulating layers 118 using a mask layer so that the upper sacrificial insulating layers 118 extend shorter than the lower sacrificial insulating layers 118 in the second region R2. The process and etching process can be performed repeatedly. As a result, the sacrificial insulating layers 118 can form a stepped structure in the form of steps in predetermined units.

Referring to FIG. 6D, a first preliminary sacrificial layer 131P and a second preliminary sacrificial layer 132P are sequentially formed on the stepped structure of the sacrificial insulating layers 118 in the extended region R2. You can. A first preliminary sacrificial layer 131P and a second preliminary sacrificial layer 132P may be sequentially stacked on the sacrificial insulating layers 118 exposed in the step structure.

In example embodiments, the first preliminary sacrificial layer 131P or the second preliminary sacrificial layer 132P may include the same insulating material as the sacrificial insulating layers 118 . In other embodiments, the first preliminary sacrificial layer 131P or the second preliminary sacrificial layer 132P may include a material having an etch selectivity with respect to the sacrificial insulating layers 118 . For example, when the sacrificial insulating layers 118 include silicon nitride and silicon oxynitride, the first sacrificial layer 131 includes the same material as the sacrificial insulating layers 118, and the sacrificial insulating layers ( 118) and may not have an etch selectivity. On the other hand, the second preliminary sacrificial layer 132P may include at least one of silicon boronitride (SiBN) and silicon carbonitride (SiCN). Preferably, the second preliminary sacrificial layer 132P may include silicon boronitride. In an exemplary embodiment, the sacrificial insulating layers 118 may include silicon nitride, the first preliminary sacrificial layer 131P may also include silicon nitride, and the second preliminary sacrificial layer 132P may include silicon boronitride. You can.

The density of the first preliminary sacrificial layer 131P may be less than the density of the second preliminary sacrificial layer 132P, and accordingly, the etch rate of the first preliminary sacrificial layer 131P with respect to hydrofluoric acid (HF) The range of may be greater than the range of the etch rate for hydrofluoric acid (HF) of the second preliminary sacrificial layer 132P.

At this time, the first preliminary sacrificial layer 131P and the second preliminary sacrificial layer 132P have a thickness of the area disposed on the upper surface and the area disposed on the side of the horizontal sacrificial layer 118 according to the deposition direction in a stepped structure. may be stacked differently from each other.

Specifically, the first preliminary sacrificial layer 131P has a fourth thickness t4 on the upper surface of the sacrificial insulating layers 118, and has a fourth thickness t4 on the side of the sacrificial insulating layers 118. 5 It can be deposited to have a thickness (t5). The fourth thickness t4 may be smaller than the first thickness t1, which is the thickness of the sacrificial insulating layers 118, and may satisfy a thickness of 1/2 to 2/3 of the first thickness t1. there is. Additionally, the fifth thickness t5 may satisfy 40 to 60% of the fourth thickness t4, and may preferably satisfy approximately 1/2. For example, when the first thickness t1 of the sacrificial insulating layers 118 is about 150 Å, the fourth thickness t4 may be about 100 Å, and the fifth thickness t5 may be about 50 Å. It is not limited. Meanwhile, the second preliminary sacrificial layer 132P has a sixth thickness t6 on the top surface of the first preliminary sacrificial layer 131P, and has a thickness smaller than the sixth thickness t6 on the side of the first preliminary sacrificial layer 131P. It may be deposited to have a seventh thickness t7. The sixth thickness t6 may be substantially equal to the fourth thickness t4 and may be smaller than the first thickness t1, which is the thickness of the sacrificial insulating layers 118, with respect to the first thickness t1. It can meet thicknesses of 1/2 to 4/5. In addition, the seventh thickness t7 may be substantially the same as the fifth thickness t5, and may satisfy 40 to 60% of the sixth thickness t6, preferably about 1/2. You can. Accordingly, the sixth thickness t6 may be about 100 Å, and the seventh thickness t7 may be about 50 Å, but are not limited thereto. Accordingly, preliminary sacrificial layers 131P and 132P of approximately 200 Å may be stacked on the upper surface of the sacrificial insulating layers 118, and preliminary sacrificial layers 131P and 132P of approximately 100 Å may be stacked on the side surfaces of the sacrificial insulating layers 118. .

Referring to FIG. 6E, etching is performed with the preliminary sacrificial layers 131P and 132P stacked, thereby removing the preliminary sacrificial layers 131P and 132P disposed on the sides of the step-shaped step structure to form a gate groove. (gg) can be formed.

Specifically, when overall etching is performed with a specific etchant, for example, hydrofluoric acid (HF) solution, the preliminary sacrificial layers 131P and 132P on the side having a relatively thin thickness may be etched first.

At this time, preliminary sacrificial layers 131P and 132P having a thickness more than twice that of the side surface are disposed on the upper surface of the sacrificial insulating layer 118, and the second preliminary sacrificial layer 132P disposed on the outer surface is the first preliminary sacrificial layer. Since the etching rate for hydrofluoric acid is lower than that of the layer 131P, even if the second preliminary sacrificial layer 132P on the upper surface is removed by the thickness etched from the side while all of the second preliminary sacrificial layer 132P on the side is removed, a portion of the second preliminary sacrificial layer 132P on the side is removed. will remain. Additionally, while all of the exposed first preliminary sacrificial layer 131P is removed from the side surface, a portion of the second preliminary sacrificial layer 132P remaining on the upper surface may be etched. Accordingly, while all of the first and second preliminary sacrificial layers 131P and 132P are removed from the side, some of the second preliminary sacrificial layer 132P may not be completely removed but may remain on the top. At this time, the eighth thickness t8 of the remaining second preliminary sacrificial layer 132P may satisfy 10 to 20% of the sixth thickness t6. Accordingly, a preliminary pad area having the same shape as the protruding portion 130PP of the pad area 130P may be formed at the end of the sacrificial insulating layer 118 exposed in the stepped structure. As described in FIG. 3, the preliminary pad area is etched so that the first preliminary sacrificial layer 131P is recessed inward from the side of the sacrificial insulating layer 118 to form the first sacrificial layer 131, and the first sacrificial layer 131P is etched to form the first sacrificial layer 131. The upper ends (n1, n2) of the second sacrificial layer 132 remaining on (131) may be formed to have tips protruding outward. That is, since the etch rate of the first preliminary sacrificial layer 131P is higher than that of the second preliminary sacrificial layer 132P, the first sacrificial layer 131 is further etched from the lower part of the second sacrificial layer 132 from the outside. A side surface having a concavely depressed curved surface may be formed.

By this etching, both the second preliminary sacrificial layer 132P and the first preliminary sacrificial layer 131P are removed from the sidewall of the stepped structure, and the adjacent pad area 130P and the first and second sacrificial layers are removed. (131, 132) may be cut to form a gate groove (gg) between the inner side (S1) of one pad area (130P) and the side wall of the adjacent step structure. The gate groove gg may be formed by partially recessing the exposed upper surface of the sacrificial insulating layer 118, but is not limited thereto. When all of the preliminary pad areas are formed, the channel sacrificial layer 116 may be formed in the area where the channel structure CH of the first area R1 is disposed. The channel sacrificial layer 116 may be formed of a material such as silicon. A lower cell region insulating layer 190 may be formed to cover the lower mold structure.

Referring to FIG. 6F, the upper mold structure can be formed on the lower mold structure through the same process, and the channel structure (CH) can be formed.

The process of FIGS. 6B to 6E is repeated to form a first sacrificial layer 131 and a second sacrificial layer 132 in the stepped structure of the upper mold structure, which have a greater thickness than the other sacrificial insulating layers 118. Each spare pad area can be formed.

In this way, by applying materials with different densities and different etch rates for the same etchant to the first and second sacrificial layers 131 and 132, the shape of the pad area 130P is specified, and the shape of the pad area 130P is specified without separate plasma treatment. Selective removal of only the side may be possible. However, when the deposition thickness of the second sacrificial layer 132 is formed thinner, etch selectivity can be further enhanced by selectively changing the structure of the upper surface through plasma treatment, but the etch selectivity is not limited to this.

Next, an upper cell region insulating layer 190 covering the upper mold structure may be formed, and upper separation regions US (see FIG. 2B) may be formed. The upper separation regions US are formed by removing a predetermined number of sacrificial insulating layers 118 and interlayer insulating layers 120 from the top, and then depositing an insulating material to form the upper separation insulating layer 103 (FIG. 2b). It can be formed by forming (reference).

The channel structures (CH) can be formed by anisotropically etching the sacrificial insulating layers 118 and the interlayer insulating layers 120 using a mask layer, and can be formed by forming hole-shaped channel holes and then filling them. You can. The channel holes may be formed to recess a portion of the plate layer 101. Channel structures CH may be formed by sequentially forming at least a portion of the gate dielectric layer 145, the channel layer 140, the channel buried insulating layer 147, and the channel pad 149 in the channel holes. The gate dielectric layer 145 may be formed to have a uniform thickness using an ALD or CVD process. In this step, the gate dielectric layer 145 may be formed in whole or in part, and a portion extending perpendicular to the plate layer 101 along the channel structures CH may be formed in this step. A channel layer 140 may be formed on the gate dielectric layer 145 within the channel holes. The channel filling insulating layer 147 is formed to fill the channel holes and may be made of an insulating material. The channel pad 149 may be made of a conductive material, for example, polycrystalline silicon.

After forming the channel structures (CH), the support structures (DCH) (see FIG. 1) can also be formed in a similar manner. For example, the support structures DCH may be formed by forming support holes penetrating the laminated structure and then filling the support holes with an insulating material.

Referring to FIG. 6g, first contact holes OH1 may be formed.

The first contact holes OH1 may be formed in areas corresponding to the contact plugs 170 and through vias 175 of FIG. 2A. The first contact holes OH1 penetrate the cell region insulating layer 190, the sacrificial insulating layers 118, and the interlayer insulating layers 120 in areas corresponding to the contact plugs 170. , may be formed to penetrate the substrate insulating layer 121 from the bottom. The first contact holes OH1 may penetrate the cell region insulating layer 190 and the substrate insulating layer 121 in the area corresponding to the through via 175 . Pads CP may be exposed through bottom surfaces of the first contact holes OH1.

Referring to FIG. 6H , preliminary contact insulating layers 160p may be formed in the first contact holes OH1 and vertical sacrificial layers 119 may be formed.

Some of the sacrificial insulating layers 118 exposed through the first contact holes OH1 may be removed. Tunnel portions may be formed by removing the sacrificial insulating layers 118 to a predetermined length around the first contact holes OH1. The tunnel portions may be formed to have a relatively short length in the uppermost sacrificial insulating layers 118, and may be formed to have a relatively long length in the sacrificial insulating layers 118 below them.

Specifically, initially, the tunnel portions may be formed to be relatively long in the uppermost sacrificial insulating layers 118 . This may be due to the fact that the uppermost sacrificial insulating layers 118 include a region where the etching rate is relatively faster than that of the sacrificial insulating layers 118 below. Next, a separate sacrificial layer may be formed in the first contact holes OH1 and the tunnel portions. The sacrificial layer may be made of a material whose etch rate is slower than that of the sacrificial insulating layers 118. Next, the sacrificial layer and a portion of the sacrificial insulating layers 118 may be removed. At this time, the sacrificial layer remains at the uppermost part, and the sacrificial insulating layers 118 remain at the lower part after the sacrificial layer is removed. Some of this can be removed. As a result, the tunnel portions can ultimately be formed to have a relatively short length in the uppermost sacrificial insulating layers 118.

An insulating material may be deposited in the first contact holes OH1 and the tunnel portions to form preliminary contact insulating layers 160p. The preliminary contact insulating layers 160p may be formed on the sidewalls of the first contact holes OH1 and fill the tunnel portions. In the uppermost sacrificial insulating layers 118, the first contact holes OH1 may not completely fill the tunnel portions.

The vertical sacrificial layers 119 may fill the first contact holes OH1 and the uppermost tunnel portions. The vertical sacrificial layers 119 may include a material different from that of the preliminary contact insulating layers 160p, for example, polycrystalline silicon.

Referring to FIG. 6I, after forming the first horizontal conductive layer 102 and removing the sacrificial insulating layers 118, gate electrodes 130 may be formed.

First, it extends to the plate layer 101 through the sacrificial insulating layers 118 and the interlayer insulating layers 120 at the positions of the first and second separation regions MS1, MS2a, and MS2b (see FIG. 1). Openings can be formed. Next, an etch-back process is performed while forming separate sacrificial spacer layers in the openings to selectively remove the horizontal insulating layer 110 in the first region R1 and expose the gate dielectric layer 145. Parts of can also be removed together. After forming the first horizontal conductive layer 102 by depositing a conductive material in the area where the horizontal insulating layer 110 was removed, the sacrificial spacer layers may be removed from the openings. Through this process, the first horizontal conductive layer 102 may be formed in the first region R1.

Next, the sacrificial insulating layers 118, the first sacrificial layer 131, and the second sacrificial layer 132 are formed into the interlayer insulating layers 120 and the second horizontal conductive layer using, for example, wet etching. 104, and the preliminary contact insulating layers 160p may be selectively removed. The gate electrodes 130 may be formed by depositing a conductive material in areas where the sacrificial insulating layers 118 have been removed. The conductive material may include metal, polycrystalline silicon, or metal silicide material.

Accordingly, a pad area 130P made of a conductive material may be formed along the shape of the first and second sacrificial layers 131 and 132, and the conductive material in the pad area 130P may be formed in the inner contact plug 170. A side surface having a curved surface that is concavely depressed toward can be formed. In some embodiments, a portion of the gate dielectric layer 145 may be formed first before forming the gate electrodes 130 . After forming the gate electrodes 130, isolation insulating layers 105 may be formed in the openings formed in the first and second isolation regions MS1, MS2a, and MS2b.

Referring to FIG. 6J , the vertical sacrificial layers 119 may be removed and the exposed pads CP may be removed to form second contact holes OH2.

The vertical sacrificial layers 119 in the first contact holes OH1 can be selectively removed with respect to the interlayer insulating layers 120 and the gate electrodes 130. After the vertical sacrificial layers 119 are removed, some of the exposed preliminary contact insulating layers 160p may also be removed. At this time, all of the preliminary contact insulating layers 160p may be removed from the pad areas 130P, and may remain below them to form contact insulating layers 160. In the pad areas 130P, when the gate dielectric layer 145 is exposed after the preliminary contact insulating layers 160p are removed, the gate dielectric layer 145 may also be removed to expose the side surfaces of the gate electrodes 130. there is.

By removing the vertical sacrificial layers 119, the pads CP below may be exposed. The pads CP may be selectively removed with respect to the plate layer 101, the substrate insulating layer 121, and the peripheral area insulating layer 290. The pads CP may be removed by, for example, wet etching. As a result, second contact holes OH2 extending downward from the first contact holes OH1 may be formed.

Referring to FIG. 6K, contact plugs 170 and through vias 175 may be formed by depositing a conductive material in the second contact holes OH2.

Since the contact plugs 170 and the through via 175 are formed together in the same process step, they may have the same structure. The contact plugs 170 may be formed to have a horizontal extension portion 170H (see FIG. 3) in the pad areas 130P and may be formed in a vertical shape within the curved surface of the pad areas 130P. , a conductive material may be buried in the pad areas 130P of expanded thickness and may be physically and electrically connected to the gate electrode 130.

Next, referring to FIG. 2A together, the semiconductor device 100 is formed by forming the channel structures CH, contact plugs 170, and upper contact plugs 180 connected to the top of the through via 175. can be manufactured.

FIG. 7 is a diagram schematically showing a data storage system including a semiconductor device according to example embodiments.

Referring to FIG. 7 , the data storage system 1000 may include a semiconductor device 1100 and a controller 1200 electrically connected to the semiconductor device 1100. The data storage system 1000 may be a storage device including one or a plurality of semiconductor devices 1100 or an electronic device including a storage device. For example, the data storage system 1000 may be a solid state drive device (SSD) device, a universal serial bus (USB) device, a computing system, a medical device, or a communication device including one or a plurality of semiconductor devices 1100. .

The semiconductor device 1100 may be a non-volatile memory device, for example, the NAND flash memory device described above with reference to FIGS. 1 to 5 . The semiconductor device 1100 may include a first structure 1100F and a second structure 1100S on the first structure 1100F. In example embodiments, the first structure 1100F may be placed next to the second structure 1100S. The first structure 1100F may be a peripheral circuit structure including a decoder circuit 1110, a page buffer 1120, and a logic circuit 1130. The second structure 1100S includes a bit line (BL), a common source line (CSL), word lines (WL), first and second gate upper lines (UL1, UL2), and first and second gate lower lines. It may be a memory cell structure including lines LL1 and LL2, and memory cell strings CSTR between the bit line BL and the common source line CSL.

In the second structure 1100S, each memory cell string CSTR includes lower transistors LT1 and LT2 adjacent to the common source line CSL and upper transistors UT1 and UT1 adjacent to the bit line BL. UT2), and a plurality of memory cell transistors (MCT) disposed between the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2. The number of lower transistors LT1 and LT2 and the number of upper transistors UT1 and UT2 may vary depending on embodiments.

In example embodiments, the upper transistors UT1 and UT2 may include a string select transistor, and the lower transistors LT1 and LT2 may include a ground select transistor. The gate lower lines LL1 and LL2 may be gate electrodes of the lower transistors LT1 and LT2, respectively. The word lines WL may be gate electrodes of the memory cell transistors MCT, and the upper gate lines UL1 and UL2 may be gate electrodes of the upper transistors UT1 and UT2, respectively.

In example embodiments, the lower transistors LT1 and LT2 may include a lower erase control transistor LT1 and a ground selection transistor LT2 connected in series. The upper transistors UT1 and UT2 may include a string select transistor UT1 and an upper erase control transistor UT2 connected in series. At least one of the lower erase control transistor LT1 and the upper erase control transistor UT2 may be used in an erase operation to erase data stored in the memory cell transistors MCT using the GIDL phenomenon.

The common source line (CSL), the first and second gate lower lines (LL1, LL2), the word lines (WL), and the first and second gate upper lines (UL1, UL2) are connected to the first structure ( It may be electrically connected to the decoder circuit 1110 through first connection wires 1115 extending to the second structure 1100S within 1100F. The bit lines BL may be electrically connected to the page buffer 1120 through second connection wires 1125 extending from the first structure 1100F to the second structure 1100S.

In the first structure 1100F, the decoder circuit 1110 and the page buffer 1120 may perform a control operation on at least one selected memory cell transistor among the plurality of memory cell transistors (MCT). The decoder circuit 1110 and page buffer 1120 may be controlled by the logic circuit 1130. The semiconductor device 1100 may communicate with the controller 1200 through the input/output pad 1101 that is electrically connected to the logic circuit 1130. The input/output pad 1101 may be electrically connected to the logic circuit 1130 through an input/output connection wire 1135 extending from the first structure 1100F to the second structure 1100S.

The controller 1200 may include a processor 1210, a NAND controller 1220, and a host interface 1230. Depending on embodiments, the data storage system 1000 may include a plurality of semiconductor devices 1100, and in this case, the controller 1200 may control the plurality of semiconductor devices 1100.

The processor 1210 may control the overall operation of the data storage system 1000, including the controller 1200. The processor 1210 may operate according to predetermined firmware and may control the NAND controller 1220 to access the semiconductor device 1100. The NAND controller 1220 may include a controller interface 1221 that processes communication with the semiconductor device 1100. Through the controller interface 1221, control commands for controlling the semiconductor device 1100, data to be written to the memory cell transistors (MCT) of the semiconductor device 1100, and memory cell transistors (MCT) of the semiconductor device 1100. Data to be read from MCT) may be transmitted. The host interface 1230 may provide a communication function between the data storage system 1000 and an external host. When receiving a control command from an external host through the host interface 1230, the processor 1210 may control the semiconductor device 1100 in response to the control command.

8 is a perspective view schematically showing a data storage system including a semiconductor device according to an example embodiment.

Referring to FIG. 8, a data storage system 2000 according to an exemplary embodiment of the present invention includes a main board 2001, a controller 2002 mounted on the main board 2001, one or more semiconductor packages 2003, and DRAM (2004). The semiconductor package 2003 and the DRAM 2004 may be connected to the controller 2002 through wiring patterns 2005 formed on the main substrate 2001.

The main board 2001 may include a connector 2006 including a plurality of pins coupled to an external host. The number and arrangement of the plurality of pins in the connector 2006 may vary depending on the communication interface between the data storage system 2000 and the external host. In example embodiments, the data storage system 2000 may include Universal Serial Bus (USB), Peripheral Component Interconnect Express (PCI-Express), Serial Advanced Technology Attachment (SATA), M-Phy for Universal Flash Storage (UFS), etc. It can communicate with an external host according to any one of the interfaces. In example embodiments, the data storage system 2000 may operate with power supplied from an external host through the connector 2006. The data storage system 2000 may further include a Power Management Integrated Circuit (PMIC) that distributes power supplied from the external host to the controller 2002 and the semiconductor package 2003.

The controller 2002 can write data to the semiconductor package 2003 or read data from the semiconductor package 2003, and can improve the operating speed of the data storage system 2000.

DRAM (2004) may be a buffer memory to alleviate the speed difference between the semiconductor package (2003), which is a data storage space, and an external host. The DRAM 2004 included in the data storage system 2000 may operate as a type of cache memory and may provide space for temporarily storing data during control operations for the semiconductor package 2003. When the data storage system 2000 includes the DRAM 2004, the controller 2002 may further include a DRAM controller for controlling the DRAM 2004 in addition to a NAND controller for controlling the semiconductor package 2003.

The semiconductor package 2003 may include first and second semiconductor packages 2003a and 2003b that are spaced apart from each other. The first and second semiconductor packages 2003a and 2003b may each include a plurality of semiconductor chips 2200. Each of the first and second semiconductor packages 2003a and 2003b includes a package substrate 2100, semiconductor chips 2200 on the package substrate 2100, and adhesive layers 2300 disposed on the lower surfaces of each of the semiconductor chips 2200. ), a connection structure 2400 that electrically connects the semiconductor chips 2200 and the package substrate 2100, and a molding layer 2500 that covers the semiconductor chips 2200 and the connection structure 2400 on the package substrate 2100. It can be included.

The package substrate 2100 may be a printed circuit board including upper package pads 2130. Each semiconductor chip 2200 may include an input/output pad 2210. The input/output pad 2210 may correspond to the input/output pad 1101 of FIG. 7 . Each of the semiconductor chips 2200 may include gate stacked structures 3210 and channel structures 3220. Each of the semiconductor chips 2200 may include the semiconductor device described above with reference to FIGS. 1 to 5 .

In example embodiments, the connection structure 2400 may be a bonding wire that electrically connects the input/output pad 2210 and the top pads 2130 of the package. Accordingly, in each of the first and second semiconductor packages 2003a and 2003b, the semiconductor chips 2200 may be electrically connected to each other using a bonding wire method, and the package upper pads 2130 of the package substrate 2100 and Can be electrically connected. According to embodiments, in each of the first and second semiconductor packages 2003a and 2003b, the semiconductor chips 2200 use a through electrode (Through Silicon Via, TSV) instead of the bonding wire-type connection structure 2400. They may be electrically connected to each other by a connection structure including a.

In example embodiments, the controller 2002 and the semiconductor chips 2200 may be included in one package. In an exemplary embodiment, the controller 2002 and the semiconductor chips 2200 are mounted on a separate interposer board different from the main board 2001, and the controller 2002 and the semiconductor chips are connected by wiring formed on the interposer board. (2200) may be connected to each other.

9 is a cross-sectional view schematically showing a semiconductor package according to an exemplary embodiment. FIG. 9 illustrates an exemplary embodiment of the semiconductor package 2003 of FIG. 8 and conceptually shows a region where the semiconductor package 2003 of FIG. 8 is cut along the cutting line III-III'.

Referring to FIG. 9, in the semiconductor package 2003, the package substrate 2100 may be a printed circuit board. The package substrate 2100 includes a package substrate body 2120, package upper pads 2130 disposed on the upper surface of the package substrate body 2120 (see FIG. 8), and disposed on the lower surface of the package substrate body 2120. It may include lower pads 2125 exposed through or through the lower surface, and internal wires 2135 electrically connecting the upper pads 2130 and the lower pads 2125 inside the package substrate body 2120. You can. The lower pads 2125 may be connected to the wiring patterns 2005 of the main board 2001 of the data storage system 2000 as shown in FIG. 8 through conductive connectors 2800.

Each of the semiconductor chips 2200 may include a semiconductor substrate 3010 and a first structure 3100 and a second structure 3200 that are sequentially stacked on the semiconductor substrate 3010. The first structure 3100 may include a peripheral circuit area including peripheral wires 3110. The second structure 3200 includes a common source line 3205, a gate stacked structure 3210 on the common source line 3205, channel structures 3220 penetrating the gate stacked structure 3210, and channel structures 3220. It may include bit lines 3240 electrically connected to and contact plugs 3235 electrically connected to word lines WL of the gate stacked structure 3210 (see FIG. 7 ). As described above with reference to FIGS. 1 to 5 , a plurality of gate electrodes 130 in each of the semiconductor chips 2200 may be commonly connected to one contact plug 170 .

Each of the semiconductor chips 2200 may include a through wiring 3245 that is electrically connected to the peripheral wirings 3110 of the first structure 3100 and extends into the second structure 3200. The through wiring 3245 may be disposed outside the gate stacked structure 3210 and may be further disposed to penetrate the gate stacked structure 3210. Each of the semiconductor chips 2200 may further include an input/output pad 2210 (see FIG. 7 ) that is electrically connected to the peripheral wires 3110 of the first structure 3100 .

CH: channel structure MS: separation zone
DSH: Support structure 170: Contact plug
R1: first area R2: second area
R3: Third region 101: Plate layer
120: interlayer insulating layer 130: gate electrode
130P: Pad area 140: Channel layer
145: Gate dielectric layer 150: Buried insulating layer
147: Channel pad 118: Interlayer sacrificial layer
131: first sacrificial layer 132: second sacrificial layer

Claims (10)

a plate layer having a first region and a second region;
They are stacked and spaced apart from each other along a first direction on the first area, extend to different lengths along a second direction perpendicular to the first direction on the second area, and have a top surface exposed upwardly in the second area. Gate electrodes each including a pad area and a stacked area other than the pad area;
interlayer insulating layers alternately stacked with the gate electrodes;
Channel structures extending along the first direction and penetrating the gate electrodes on the first region and each including a channel layer; and
It penetrates the pad area of a first gate electrode, which is one of the gate electrodes, and is electrically connected to the first gate electrode, and penetrates the stacked area of a second gate electrode disposed below the first gate electrode. Contact plug spaced apart from the second gate electrode
Includes,
The pad region includes a base portion extending from the stacked region and having a first thickness, and a protruding portion that protrudes above the base portion in the first direction to expand the pad region to a second thickness greater than the first thickness. And
The protruding portion includes a side that is concavely recessed toward the contact plug penetrating the pad area.
semiconductor device.
According to paragraph 1,
A semiconductor device wherein the thickness of the protruding portion is smaller than the first thickness of the base portion.
According to paragraph 1,
A semiconductor device wherein, in the first direction, an upper surface of the protruding portion is disposed within an upper surface of the base portion.
According to paragraph 1,
A side surface of the protruding portion includes an inflection point located at the shortest distance from the contact plug, and the inflection point is located closer to the upper surface of the protruding portion between the upper surface of the protruding portion and the upper surface of the base portion.
forming a mold structure alternately including a plurality of interlayer insulating layers and a plurality of sacrificial insulating layers on a plate layer;
sequentially etching the mold structure to form a plurality of stepped structures in the plurality of sacrificial insulating layers;
sequentially forming a first preliminary sacrificial layer and a second preliminary sacrificial layer on the plurality of step structures of the mold structure;
The first preliminary sacrificial layer and the second preliminary sacrificial layer on the side surfaces of the step structure are etched, and only the upper surfaces of the plurality of sacrificial insulating layers are left to remain, so that the preliminary pad area includes the first sacrificial layer and the second sacrificial layer. forming a; and
forming a plurality of gate electrodes including a pad region by removing the preliminary pad region and the plurality of sacrificial insulating layers and filling the removed space with a conductive layer; Includes,
The step of forming the preliminary pad area is,
A method of manufacturing a semiconductor device in which the upper surface of the first sacrificial layer is etched to have a smaller area than the upper surface of the second sacrificial layer.
According to clause 5,
The second preliminary sacrificial layer has a higher density than the first preliminary sacrificial layer and, in forming the preliminary pad region, includes a material having a lower etch rate than the first preliminary sacrificial layer.
According to clause 5,
A method of manufacturing a semiconductor device, wherein the second preliminary sacrificial layer is laminated to the same thickness as the first preliminary sacrificial layer.
According to clause 5,
A method of manufacturing a semiconductor device wherein the second preliminary sacrificial layer includes silicon bonitride.
According to clause 8,
A method of manufacturing a semiconductor device, wherein the first preliminary sacrificial layer and the sacrificial insulating layer include the same material.
According to clause 5,
The step of forming the preliminary pad area is,
Etching from the surface so that the second preliminary sacrificial layer has a thinner thickness than the first preliminary sacrificial layer,
A method of manufacturing a semiconductor device wherein a gate groove is formed between a side of the step structure and the preliminary pad area.

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