KR20240041880A - Semiconductor device and electronic system including the same - Google Patents

Abstract

A semiconductor device according to an embodiment of the present invention includes a gate stacked structure including conductive patterns and insulating patterns alternately stacked with each other, a memory channel structure penetrating the gate stacked structure, and a source structure on the gate stacked structure. . The source structure includes a first source layer and a second source layer covering a portion of the upper surface of the first source layer. The first source layer includes an n-type oxide semiconductor. The second source layer includes a p-type oxide semiconductor.

Description

Semiconductor device and electronic system including the same {SEMICONDUCTOR DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME}

Embodiments of the present invention relate to a semiconductor device and an electronic system including the same, and more specifically, to a semiconductor device including a source layer and an electronic system including the same.

Semiconductor devices are attracting attention as important elements in the electronics industry due to characteristics such as miniaturization, multi-functionality, and/or low manufacturing cost. Semiconductor devices can be divided into semiconductor memory devices that store logical data, semiconductor logic devices that operate and process logical data, and hybrid semiconductor devices that include memory elements and logic elements.

Recently, as electronic devices become faster and consume less power, semiconductor devices embedded in them are also required to have faster operating speeds and/or lower operating voltages, and more highly integrated semiconductor devices are needed to meet these requirements. However, as the high integration of semiconductor devices becomes more severe, the electrical characteristics and production yield of semiconductor devices may decrease. Accordingly, much research is being conducted to improve the electrical characteristics and production yield of semiconductor devices.

Embodiments of the present invention aim to provide a semiconductor device with improved electrical characteristics and reliability and an electronic system including the same.

The problem to be solved by the present invention is not limited to the problems mentioned above, and other problems not mentioned can be clearly understood by those skilled in the art from the description below.

A semiconductor device according to an embodiment of the present invention includes a gate stacked structure including conductive patterns and insulating patterns alternately stacked with each other, a memory channel structure penetrating the gate stacked structure, and a source structure on the gate stacked structure, , the source structure includes a first source layer and a second source layer covering a portion of the upper surface of the first source layer on the first source layer, the first source layer includes an n-type oxide semiconductor, and the second source layer The film may include a p-type oxide semiconductor.

An electronic system according to another embodiment of the present invention includes a main board, a semiconductor device on the main board, and a controller electrically connected to the semiconductor device on the main board, wherein the semiconductor device includes a peripheral circuit structure and a peripheral circuit structure. A memory cell structure comprising a gate stacked structure including conductive patterns and insulating patterns alternately stacked with each other, a memory channel structure penetrating the gate stacked structure, a source structure on the gate stacked structure, and Includes a first via and a second via electrically connected to the source structure, the source structure includes a first source layer and a second source layer covering a portion of the upper surface of the first source layer, the first source layer It includes a first section covered by the second source layer and a second section exposed from the second source layer, the first via is provided on the first section, and the second via is on the second section. Provided, the first source layer and the second source layer may each include different amorphous oxides.

A semiconductor device according to the present invention may include a first source layer and a second source layer on a gate stacked structure. At this time, the first source layer and the second source layer may include n-type and p-type oxide semiconductors, respectively. As a result, formation of a depletion region in the source film is prevented, thereby preventing leakage current from occurring by supplying electrons to the channel film through a via in contact with the first source film during a program operation of the semiconductor device. You can. As a result, the electrical characteristics and reliability of the semiconductor device can be improved.

FIG. 1A is a diagram schematically showing an electronic system including a semiconductor device according to some embodiments of the present invention.
FIG. 1B is a perspective view schematically showing an electronic system including a semiconductor device according to some embodiments of the present invention.
1C and 1D are cross-sectional views schematically showing semiconductor packages according to some embodiments of the present invention.
2 is a plan view of a semiconductor device according to some embodiments of the present invention.
FIG. 3 is a cross-sectional view taken along line A-A' in FIG. 2.
Figure 4a is an enlarged view of the CU portion of Figure 3.
Figure 4b is an enlarged view of the CU portion of Figure 3, according to some embodiments of the present invention.
5A to 5F are cross-sectional views showing the manufacturing process of a semiconductor device according to some embodiments of the present invention.

Hereinafter, the present invention will be described in detail by explaining embodiments of the present invention with reference to the accompanying drawings.

FIG. 1A is a diagram schematically showing an electronic system including a three-dimensional semiconductor memory device according to an embodiment of the present invention.

Referring to FIG. 1A, the electronic system 1000 according to an embodiment of the present invention may include a 3D semiconductor memory device 1100 and a controller 1200 electrically connected to the 3D semiconductor memory device 1100. . The electronic system 1000 may be a storage device including one or a plurality of three-dimensional semiconductor memory devices 1100 or an electronic device including a storage device. For example, the electronic system 1000 may be a solid state drive device (SSD) device, a universal serial bus (USB) device, a computing system, a medical device, or a communication device including one or a plurality of three-dimensional semiconductor memory devices 1100. You can.

The 3D semiconductor memory device 1100 may be a non-volatile memory device, for example, a 3D NAND flash memory device as will be described later. The three-dimensional semiconductor memory device 1100 may include a first area 1100F and a second area 1100S on the first area 1100F. However, unlike shown, the first area 1100F may be placed next to the second area 1100S. The first area 1100F may be a peripheral circuit area including a decoder circuit 1110, a page buffer 1120, and a logic circuit 1130. The second area 1100S includes bit lines BL, common source line CSL, word lines WL, first lines LL1 and LL2, second lines UL1 and UL2, and bit lines. It may be a memory cell area including memory cell strings (CSTR) between the fields (BL) and the common source line (CSL).

In the second area 1100S, each memory cell string CSTR includes first transistors LT1 and LT2 adjacent to the common source line CSL and second transistors adjacent to the bit lines BL. (UT1, UT2) and a plurality of memory cell transistors (MCT) disposed between the first transistors (LT1, LT2) and the second transistors (UT1, UT2). The number of first transistors LT1 and LT2 and the number of second transistors UT1 and UT2 may vary depending on embodiments. The memory cell strings CSTR may be located between the common source line CSL and the first area 1100F.

For example, the second transistors UT1 and UT2 may include a string selection transistor, and the first transistors LT1 and LT2 may include a ground selection transistor. The first lines LL1 and LL2 may be gate electrodes of the first transistors LT1 and LT2. The word lines WL may be gate electrodes of the memory cell transistors MCT, and the second lines UL1 and UL2 may be gate electrodes of the second transistors UT1 and UT2.

For example, the first transistors LT1 and LT2 may include a first erase control transistor LT1 and a ground selection transistor LT2 connected in series. For example, the second transistors UT1 and UT2 may include a string select transistor UT1 and a second erase control transistor UT2 connected in series. At least one of the first erase control transistor LT1 and the second erase control transistor UT2 erases data stored in the memory cell transistors (MCT) using a gate induced leakage current (Gate Induce Drain Leakage, GIDL) phenomenon. It can be used in an erase operation.

The common source line (CSL), first lines (LL1, LL2), word lines (WL), and second lines (UL1, UL2) extend from the first area (1100F) to the second area (1100S) It may be electrically connected to the decoder circuit 1110 through first connection wires 1115. The bit lines BL may be electrically connected to the page buffer 1120 through second connection wires 1125 extending from the first area 1100F to the second area 1100S.

In the first area 1100F, the decoder circuit 1110 and the page buffer 1120 may perform a control operation on at least one selected memory cell transistor among the plurality of memory cell transistors (MCT). The decoder circuit 1110 and page buffer 1120 may be controlled by the logic circuit 1130. The 3D semiconductor memory device 1100 can communicate with the controller 1200 through the input/output pad 1101 that is electrically connected to the logic circuit 1130. The input/output pad 1101 may be electrically connected to the logic circuit 1130 through an input/output connection wire 1135 extending from the first area 1100F to the second area 1100S.

The controller 1200 may include a processor 1210, a NAND controller 1220, and a host interface 1230. Depending on embodiments, the electronic system 1000 may include a plurality of 3D semiconductor memory devices 1100, in which case the controller 1200 controls the plurality of 3D semiconductor memory devices 1100. can do.

The processor 1210 may control the overall operation of the electronic system 1000, including the controller 1200. The processor 1210 may operate according to predetermined firmware and may control the NAND controller 1220 to access the 3D semiconductor memory device 1100. The NAND controller 1220 may include a NAND interface 1221 that processes communication with the 3D semiconductor memory device 1100. Through the NAND interface 1221, control commands for controlling the 3D semiconductor memory device 1100, data to be written to the memory cell transistors (MCT) of the 3D semiconductor memory device 1100, and 3D semiconductor memory device 1100. Data to be read from the memory cell transistors (MCT) of 1100 may be transmitted. The host interface 1230 may provide a communication function between the electronic system 1000 and an external host. When receiving a control command from an external host through the host interface 1230, the processor 1210 can control the 3D semiconductor memory device 1100 in response to the control command.

FIG. 1B is a perspective view schematically showing an electronic system including a three-dimensional semiconductor memory device according to an embodiment of the present invention.

Referring to FIG. 1B, the electronic system 2000 according to an embodiment of the present invention includes a main board 2001, a controller 2002 mounted on the main board 2001, one or more semiconductor packages 2003, and DRAM 2004. ) may include. The semiconductor package 2003 and the DRAM 2004 may be connected to the controller 2002 through wiring patterns 2005 provided on the main board 2001.

The main board 2001 may include a connector 2006 including a plurality of pins coupled to an external host. The number and arrangement of a plurality of pins in the connector 2006 may vary depending on the communication interface between the electronic system 2000 and an external host. The electronic system 2000 includes interfaces such as, for example, Universal Serial Bus (USB), Peripheral Component Interconnect Express (PCI-Express), Serial Advanced Technology Attachment (SATA), and M-Phy for Universal Flash Storage (UFS). You can communicate with an external host according to any one of the following. The electronic system 2000 may operate, for example, with power supplied from an external host through the connector 2006. The electronic system 2000 may further include a Power Management Integrated Circuit (PMIC) that distributes power supplied from an external host to the controller 2002 and the semiconductor package 2003.

The controller 2002 can write data to the semiconductor package 2003 or read data from the semiconductor package 2003, and can improve the operating speed of the electronic system 2000.

DRAM (2004) may be a buffer memory to alleviate the speed difference between the semiconductor package (2003), which is a data storage space, and an external host. The DRAM 2004 included in the electronic system 2000 may operate as a type of cache memory and may provide a space for temporarily storing data during control operations for the semiconductor package 2003. When the electronic system 2000 includes the DRAM 2004, the controller 2002 may further include a DRAM controller for controlling the DRAM 2004 in addition to a NAND controller for controlling the semiconductor package 2003.

The semiconductor package 2003 may include first and second semiconductor packages 2003a and 2003b that are spaced apart from each other. The first and second semiconductor packages 2003a and 2003b may each include a plurality of semiconductor chips 2200. Each of the first and second semiconductor packages 2003a and 2003b includes a package substrate 2100, semiconductor chips 2200 on the package substrate 2100, and adhesive layers 2300 disposed on the lower surfaces of each of the semiconductor chips 2200. ), connection structures 2400 that electrically connect the semiconductor chips 2200 and the package substrate 2100, and a molding layer 2500 that covers the semiconductor chips 2200 and the connection structures 2400 on the package substrate 2100. may include.

The package substrate 2100 may be a printed circuit board including upper package pads 2130. Each semiconductor chip 2200 may include input/output pads 2210. Each of the input/output pads 2210 may correspond to the input/output pad 1101 of FIG. 1 . Each of the semiconductor chips 2200 may include gate stacked structures 3210 and memory channel structures 3220. Each of the semiconductor chips 2200 may include a three-dimensional semiconductor memory device as will be described later.

The connection structures 2400 may be, for example, bonding wires that electrically connect the input/output pads 2210 and the top pads of the package 2130. Accordingly, in each of the first and second semiconductor packages 2003a and 2003b, the semiconductor chips 2200 may be electrically connected to each other using a bonding wire method, and the package upper pads 2130 of the package substrate 2100 and Can be electrically connected. According to embodiments, in each of the first and second semiconductor packages 2003a and 2003b, the semiconductor chips 2200 are connected to through electrodes (Through Silicon Via) instead of bonding wire-type connection structures 2400. They may be electrically connected to each other.

Unlike shown, the controller 2002 and the semiconductor chips 2200 may be included in one package. The controller 2002 and the semiconductor chips 2200 may be mounted on a separate interposer board different from the main board 2001, and the controller 2002 and the semiconductor chips 2200 may be connected to each other through wiring provided on the interposer board. there is.

FIGS. 1C and 1D are cross-sectional views illustrating a semiconductor package including a three-dimensional semiconductor memory device according to an embodiment of the present invention. FIGS. 1C and 1D are cross-sectional views taken along lines I-I' and II-II' of FIG. 1B, respectively. Each corresponds to

1C and 1D, the semiconductor package 2003 includes a package substrate 2100, a plurality of semiconductor chips 2200 on the package substrate 2100, and a molding layer covering the package substrate 2100 and the semiconductor chips 2200. It may include (2500).

The package substrate 2100 includes a package substrate body 2120, upper pads 2130 disposed on or exposed through the upper surface of the package substrate body 2120, and a lower surface of the package substrate body 2120. It may include lower pads 2125 disposed or exposed through the lower surface and internal wires 2135 electrically connecting the upper pads 2130 and the lower pads 2125 inside the package substrate body 2120. You can. The upper pads 2130 may be electrically connected to the connection structures 2400. The lower pads 2125 may be connected to the wiring patterns 2005 of the main board 2001 of the electronic system 2000 shown in FIG. 2 through conductive connectors 2800.

Referring to FIGS. 1B and 1C , one sidewall of the semiconductor chips 2200 may not be aligned with each other, and other sidewalls of the semiconductor chips 2200 may be aligned with each other. The semiconductor chips 2200 may be electrically connected to each other by connection structures 2400 in the form of bonding wires. Each of the semiconductor chips 2200 may include substantially the same components.

Each of the semiconductor chips 2200 may include a semiconductor substrate 4010, a first structure 4100 on the semiconductor substrate 4010, and a second structure 4200 on the first structure 4100. The second structure 4200 may be coupled to the first structure 4100 using a wafer bonding method.

The first structure 4100 may include peripheral circuit wires 4110 and first bonding pads 4150. The second structure 4200 includes a common source line 4205, a gate stacked structure 4210 between the common source line 4205 and the first structure 4100, and a memory channel structure penetrating the gate stacked structure 4210 ( 4220, the isolation structures 4230, and second bonding pads 4250 that are electrically connected to the word lines (WL in FIG. 1) of the memory channel structures 4220 and the gate stacked structure 4210, respectively. It can be included. For example, the second bonding pads 4250 are gate connection lines electrically connected to the bit lines 4240 and word lines (WL in FIG. 1) electrically connected to the memory channel structures 4220. They may be electrically connected to the memory channel structures 4220 and word lines (WL in FIG. 1), respectively, through s 4235. The first bonding pads 4150 of the first structure 4100 and the second bonding pads 4250 of the second structure 4200 may be coupled while contacting each other. The joined portions of the first bonding pads 4150 and the second bonding pads 4250 may include, for example, copper (Cu).

Each of the semiconductor chips 2200 may further include an input/output pad 2210 and an input/output connection wire 4265 below the input/output pad 2210. The input/output connection wire 4265 may be electrically connected to some of the second bonding pads 4250 and some of the peripheral circuit wires 4110.

2 is a plan view of a semiconductor device according to some embodiments of the present invention. FIG. 3 is a cross-sectional view taken along line A-A' in FIG. 2. Figure 4a is an enlarged view of the CU portion of Figure 3.

Referring to FIGS. 2 to 4A , the semiconductor device may include a peripheral circuit structure (PST) and a memory cell structure (CST) on the peripheral circuit structure (PST).

The peripheral circuit structure (PST) may include the substrate 100 . The substrate 100 may have the shape of a plate extending along a plane defined by the first direction D1 and the second direction D2.

In this specification, the first direction D1 is defined as a direction parallel to the top surface of the substrate SUB. The second direction D2 is parallel to the top surface of the substrate SUB and is defined as a direction perpendicular to the first direction D1. The third direction D3 is defined as a direction perpendicular to the top surface of the substrate SUB.

The substrate 100 may be, for example, a semiconductor substrate, an insulator substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate. The semiconductor substrate may include, for example, silicon, germanium, silicon-germanium, GaP or GaAs.

The peripheral circuit structure (PST) may further include a peripheral circuit insulating layer 110 on the substrate 100. The peripheral circuit insulating film 110 may include an insulating material. In some embodiments, the peripheral circuit insulating layer 110 may be a multilayer including a plurality of insulating layers.

The peripheral circuit structure (PST) may further include peripheral transistors 101. Peripheral transistors 101 may be provided between the substrate 100 and the peripheral circuit insulating layer 110. In some embodiments, the peripheral transistor 101 may include source/drain regions, a gate electrode, and a gate insulating film. Device isolation films 103 may be provided within the substrate 100. Peripheral transistors 101 may be disposed between the device isolation films 103. The device isolation film 103 may include an insulating material. In some embodiments, the device isolation layer 103 may be a multilayer including a plurality of insulating layers.

The peripheral circuit structure (PST) may further include peripheral contacts 105 and peripheral conductive lines 106. The peripheral contacts 105 and peripheral conductive lines 106 may be electrically connected to the peripheral transistor 101. Peripheral contacts 105 and peripheral conductive lines 106 may be provided within the peripheral circuit insulating layer 110 . The peripheral contacts 105 and peripheral conductive lines 106 may include a conductive material.

The peripheral circuit structure (PST) may further include a first bonding insulating layer 121. The first bonding insulating layer 121 may be provided on the peripheral circuit insulating layer 110 . The first bonding insulating film 121 may include an insulating material. In some embodiments, the first bonding insulating layer 121 may be a multilayer including a plurality of insulating layers.

The peripheral circuit structure PST may further include first bonding pads 122. The first bonding pad 122 may be provided on the peripheral contact 105. The first bonding pad 122 may be electrically connected to the peripheral transistor 101 through the peripheral contact 105 and the peripheral conductive line 106. First bonding pads 122 may be provided in the first bonding insulating layer 121 . The first bonding pads 122 may include a conductive material.

The memory cell structure (CST) includes a lower wiring structure (LST), a first gate stacked structure (GST1), a second gate stacked structure (GST2), a third gate stacked structure (GST3), memory channel structures (CS), and a separate It may include structures DS, source structures SST, barrier film BM, via structures VST, upper vias UV, and cover insulating film 150.

The lower wiring structure LST may be provided on the first bonding insulating layer 121 . The lower interconnection structure (LST) includes a second bonding insulating film 131, second bonding pads 132, a first interlayer insulating film 133, connection contacts 134, a second interlayer insulating film 135, and bit lines. 136 , a third interlayer insulating film 137 and bit line contacts 138 .

The second bonding insulating layer 131 may be provided on the first bonding insulating layer 121. The second bonding insulating film 131 may include an insulating material. In some embodiments, the second bonding insulating layer 131 may include the same insulating material as the first bonding insulating layer 121. In some embodiments, the second bonding insulating layer 131 may be a multilayer including a plurality of insulating layers.

The second bonding pad 132 may be provided on the first bonding pad 122. Second bonding pads 132 may be provided in the second bonding insulating layer 131 . The second bonding pads 132 may include a conductive material.

The second bonding insulating layer 131 may be bonded to the first bonding insulating layer 121 through a wafer bonding process. The second bonding pad 132 may be bonded to the first bonding pad 122 through a wafer bonding process. The peripheral circuit structure (PST) and the memory cell structure (CST) may be hybrid bonded.

The first interlayer insulating film 133 may be provided on the second bonding insulating film 131. The first interlayer insulating film 133 may include an insulating material. In some embodiments, the first interlayer insulating film 133 may be a multilayer including a plurality of insulating films.

The connection contact 134 may be provided on the second bonding pad 132. The connection contact 134 may be provided in the first interlayer insulating film 133. The connection contact 134 may include a conductive material.

The second interlayer insulating film 135 may be provided on the first interlayer insulating film 133. The second interlayer insulating film 135 may include an insulating material. In some embodiments, the second interlayer insulating layer 135 may be a multilayer including a plurality of insulating layers.

A bit line 136 may be provided on the connection contact 134. Bit lines 136 may be provided within the second interlayer insulating film 135 . The bit lines 136 may extend in the first direction D1. The bit lines 136 may be arranged in the second direction D2. The bit lines 136 may include a conductive material.

The third interlayer insulating film 137 may be provided on the second interlayer insulating film 135 . The third interlayer insulating film 137 may include an insulating material. In some embodiments, the third interlayer insulating film 137 may be a multilayer including a plurality of insulating films.

Bit line contact 138 may be provided on bit line 136. Bit line contacts 138 may be provided within the third interlayer insulating film 137 . Bit line contacts 138 may include a conductive material.

The number of interlayer insulating films 133, 135, and 137 may not be limited to that shown. In some embodiments, the number of interlayer insulating films 133, 135, and 137 may be 2 or less or 4 or more. In some embodiments, instead of the connection contact 134 electrically connecting the bit line 136 and the second bonding pad 132, the bit line 136 and the second bonding pad 132 are electrically connected. A plurality of connecting conductive structures may be provided.

A first gate stacked structure (GST1) may be provided on the third interlayer insulating film 137. The second gate stacked structure GST2 may be provided on the first gate stacked structure GST1. The third gate stacked structure (GST3) may be provided on the second gate stacked structure (GST2). The number of gate stacked structures (GST1, GST2, GST3) may not be limited to that shown. In some embodiments, the number of gate stacked structures GST1, GST2, and GST3 may be 2 or less or 4 or more.

Each of the first to third gate stacked structures GST1, GST2, and GST3 may include insulating patterns IP and conductive patterns CP that are alternately stacked along the third direction D3. The insulating patterns (IP) may include an insulating material. As an example, the insulating patterns IP may include, but are not limited to, oxide or a low dielectric material. Conductive patterns CP may include a conductive material. As an example, the conductive patterns CP may include at least one of a doped semiconductor, metal, conductive metal nitride, or transition metal, but may not be limited thereto.

The insulating pattern IP disposed at the top of the insulating patterns IP of the third gate stacked structure GST3 may be defined as the upper insulating pattern UIP. The upper insulating pattern (UIP) may contact the source structure (SST).

The memory channel structures CS may extend in the third direction D3 and penetrate the first gate stacked structure GST1, the second gate stacked structure GST2, and the third gate stacked structure GST3. Each of the memory channel structures CS may include an insulating capping layer 189, a channel layer 187 surrounding the insulating capping layer 189, and a memory layer 183 surrounding the channel layer 187. The insulating capping layer 189 and the channel layer 187 may penetrate the first gate stacked structure (GST1), the second gate stacked structure (GST2), and the third gate stacked structure (GST3). The insulating capping layer 189, the channel layer 187, and the memory layer 183 may be surrounded by first to third gate stacked structures GST1, GST2, and GST3.

The insulating capping film 189 may include an insulating material. As an example, the insulating capping film 189 may include oxide, but may not be limited thereto. The channel films 187 may include a conductive material. As an example, the channel film 187 may include undoped polysilicon, but may not be limited thereto.

The memory layer 183 can store data. The memory layer 183 includes a tunnel insulating layer (TL) surrounding the channel layer 187, a data storage layer (DL) surrounding the tunnel insulating layer (TL), and a blocking layer (BO) surrounding the data storage layer (DL). It can be included.

The tunnel insulating layer TL may include, for example, an oxide (eg, SiO, AlO, or HfO), but may not be limited thereto. In some embodiments, the data storage layer DL may include a material capable of trapping charges. As an example, the data storage layer DL may include nitride (eg, SiN), but may not be limited thereto. In some embodiments, the data storage layer DL may include a ferroelectric material, a floating gate electrode, or conductive nano dots. The blocking film BO may include, for example, an oxide (eg, SiO, AlO, or HfO), but may not be limited thereto.

Each memory channel structure CS may further include a bit line pad 185. The bit line pad 185 includes the bit line contact 138, the bit line 136, the connection contact 134, the second bonding pad 132, the first bonding pad 122, the peripheral conductive line 106, and the peripheral conductive line 106. It can be electrically connected to the peripheral transistor 101 through the contact 105. The bit line pad 185 may include a conductive material. As an example, the bit line pad 185 may include polysilicon or metal, but may not be limited thereto.

The separation structures DS may extend in the third direction D3 and penetrate the first to third gate stacked structures GST1, GST2, and GST3. The separation structures DS may extend in the first direction D1. The separation structure DS may include an insulating material. In some embodiments, the separation structure DS may further include a conductive material surrounded by an insulating material.

A source structure (SST) may be provided on the third gate stacked structure (GST3), the memory layer 183, and the channel layer 187.

The source structure (SST) may include a first source layer 401 and a second source layer 402 on the first source layer 401. Specifically, the top surface of the memory layer 183 may contact the first source layer. The top of the channel layer 187 and the top of the insulating capping layer 189 may penetrate a portion of the first source layer 401 and the second source layer 402. The top surface of the separation structure DS may be in contact with the first source layer 401.

At this time, as shown in FIG. 4A, the first source layer 401 may include a first section RE1 and a second section RE. The first section RE1 may be an area exposed from the second source layer 402. Specifically, the first section RE1 may be an area of the first source layer 401 that directly contacts the cover insulating layer 150, which will be described later. The second section RE2 may be an area covered by the second source layer 402. The arrangement and number of the first section RE1 and the second section RE2 are not limited to those shown and may be changed and combined in various ways.

The first source layer 401 and the second source layer 402 may include different amorphous oxides. That is, the first source layer 401 and the second source layer 402 may include an n-type oxide semiconductor and a p-type oxide semiconductor, respectively. As an example, the first source film 401 is made of indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), and indium tungsten oxide (IWO). It may contain at least one or more. The second source layer 402 may include at least one of copper oxide (CuO), tin oxide (SnO), and nickel oxide (NiO).

The first source layer 401 may have a first thickness TH1. The second source layer 402 may have a second thickness TH2. The first thickness (TH1) and the second thickness (TH2) may be 50 nm to 100 nm.

A cover insulating layer 150 may be provided on the source structure (SST). The cover insulating film 150 may include an insulating material.

A first via (VST1) and a second via (VST2) penetrating the cover insulating layer 150 may be provided on the third gate stacked structure (GST3).

The first via (VST1) is provided on the first section (RE1) and may contact the first source layer 401. The second via VST2 may be provided on the second section RE2 and may contact the second source layer 402 . The first via (VST1) and the second via (VST2) may include a conductive material.

Figure 4b is an enlarged view of the CU portion of Figure 3, according to some embodiments of the present invention. Description of parts overlapping with FIG. 4A will be omitted.

Referring to FIG. 4B , the separation structure DS and the first via VST1 may overlap in the third direction D3. That is, the lower and upper surfaces of a partial region of the first source layer 401 may contact the separation structure DS and the first via VST1, respectively.

The source layer of the semiconductor device according to the comparative example was composed of polysilicon having regions doped with n-type and p-type impurities. As a result, during the program operation of the semiconductor device, the depletion region in the source film expands and holes move from the n-type polysilicon region to the p-type polysilicon region along the grain boundaries of polysilicon, causing a leakage current. There was.

On the other hand, a semiconductor device according to an embodiment of the present invention may include a first source layer and a second source layer on the gate stacked structure. The first source layer may include an n-type oxide semiconductor, and the second source layer may include a p-type oxide semiconductor. At this time, the semiconductor device may supply electrons to the channel layer through the first via in contact with the first source layer during program and read operations. The semiconductor device can implement bulk erase by supplying holes to the channel layer through a second via that contacts the second source layer during an erase operation. That is, since a depletion region is not formed during a program operation in the semiconductor device according to an embodiment of the present invention, leakage current phenomenon can be prevented and electrical reliability and characteristics can be improved.

5A to 5F are cross-sectional views showing the manufacturing process of a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 5A, the first gate stacked structure (GST1), the second gate stacked structure (GST2), the third gate stacked structure (GST3), the lower wiring structure (LST), and the peripheral circuit structure (PST) can be formed. there is.

Memory channel structures CS and separation structures DS may be formed penetrating the first to third gate stacked structures GST1, GST2, and GST3. Forming the memory channel structure (CS) includes a blocking layer (BO), a data storage layer (DL), a tunnel insulating layer (TL), a channel layer 187, an insulating capping layer 189, and a bit line pad 185. It may include forming.

Afterwards, the sacrificial substrate 301 can be formed. The sacrificial substrate 301 may be provided on the third gate stacked structure (GST3), the memory channel structure (CS), and the separation structure (DS). The sacrificial substrate 301 may be, for example, a semiconductor substrate, an insulator substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate.

Referring to FIG. 5B, the sacrificial substrate 301 may be removed. The sacrificial substrate 301 may be removed to expose the top of the memory channel structure (CS), the top of the separation structure (DS), and the top of the third gate stacked structure (GST3). In some embodiments, the sacrificial substrate 301 may be removed through a grinding process.

The memory layer 183 of the memory channel structure CS may be etched. The memory layer 183 may be etched to expose the channel layer 187. Etching the memory layer 183 may include etching the blocking layer BO, etching the data storage layer DL, and etching the tunnel insulating layer TL. As the etching process of the memory layer 183 is performed, the top surface of the upper insulating pattern (UIP), the top surface of the memory layer 183, the top surface of the separation structure (DS), the top surface of the channel layer 187, and the insulating capping layer The upper part of (189) may be exposed.

Referring to FIG. 5C, the first source layer 401 may be formed on the third gate stacked structure GST3. The first source layer 401 may conformally cover the upper insulating pattern (UIP), the top surface of the memory layer 183, and the upper region of the channel layer 187. Forming the first source layer 401 may be performed through a physical vapor deposition process.

Referring to FIG. 5D, a portion of the first source layer 401 covering the upper area of the channel layer 187 may be removed. As a portion of the first source layer 401 is removed, the upper region of the channel layer 187 may be exposed.

Referring to FIG. 5E, a second source layer 402 may be formed on the first source layer 401. The second source layer 402 may conformally cover the upper area of the first source layer 401 and the channel layer 187. Forming the second source layer 402 may be performed through a physical vapor deposition process.

Referring to FIGS. 4A and 5F , a portion of the second source layer 402 may be removed. Removing part of the second source layer 402 involves forming a mask pattern that defines the area where the first section RE1 will be formed, and using the mask pattern as an etch mask to form the second source layer 402. This may include etching and removing the mask pattern. As a portion of the second source layer 402 is removed and a portion of the first source layer 401 is exposed, the first section RE1 of the first source layer 401 may be defined as shown in FIG. 4A. . As the first section RE1 is defined, a second section RE2 of the first source layer 401 covered with the second source layer 402 may be defined. As a result, a source structure (SST) including the first source layer 401 and the second source layer 402 may be formed.

Thereafter, although not shown, a cover insulating layer 150 may be formed on the source structure (SST). 3 by forming a first via (VST1) that penetrates the cover insulating layer (150) and contacts the first source layer (401) and a second via (VST2) that contacts the second source layer (402). Semiconductor devices can be completed.

In the manufacturing process of the semiconductor device according to the comparative example, a source layer was formed using polysilicon and then impurities were injected into the source layer. Afterwards, a heat treatment process such as a laser annealing process was performed on the source film to activate the impurities and crystallize polysilicon. As a result, there was a problem in that the interconnection structures formed under the source layer were deteriorated due to the heat generated in the heat treatment process.

On the other hand, in the manufacturing process of the semiconductor device according to the embodiment of the present invention, the heat treatment process was omitted by forming the source layer using an oxide semiconductor with high mobility. As a result, the electrical reliability of the semiconductor device can be improved by preventing deterioration of the interconnection structures formed under the source layer, and the semiconductor device manufacturing process can be simplified.

Above, embodiments of the present invention have been described with reference to the attached drawings, but those skilled in the art will understand that the present invention can be implemented in other specific forms without changing the technical idea or essential features. You will understand that it exists. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive.

100: Substrate PST: Peripheral circuit structure
CST: memory cell structure 401: first source film
402: Second source act

Claims (10)

A gate stacked structure including conductive patterns and insulating patterns alternately stacked with each other;
a memory channel structure penetrating the gate stacked structure;
Comprising a source structure on the gate stacked structure,
The source structure includes a first source layer and a second source layer covering a portion of the upper surface of the first source layer on the first source layer,
The first source layer includes an n-type oxide semiconductor,
A semiconductor device wherein the second source layer includes a p-type oxide semiconductor.
According to clause 1,
The first source layer includes at least one of indium-gallium-zinc oxide, indium-zinc oxide, and indium-tungsten oxide,
The semiconductor device wherein the second source layer includes at least one of copper oxide, tin oxide, and nickel oxide.
According to clause 1,
The memory channel structure is:
insulating capping film;
a channel film surrounding the insulating capping film; and
Includes a memory film on the channel film,
The memory layer includes a data storage layer,
A semiconductor device wherein the upper surface of the memory layer is in contact with the first source layer.
According to clause 1,
Comprising a first via and a second via on the gate stacked structure,
The first via contacts the first source layer,
The second via is in contact with a second source layer.
According to clause 4,
Further comprising a separation structure penetrating the gate stacked structure,
A semiconductor device wherein the separation structure vertically overlaps the first via.
According to clause 1,
A semiconductor device wherein the first source layer and the second source layer have a thickness of 50 nm to 100 nm.
main board;
a semiconductor device on the main substrate; and
A controller electrically connected to the semiconductor device on the main board,
The semiconductor device is:
Peripheral circuit structure; and
Comprising a memory cell structure on the peripheral circuit structure,
The memory cell structure is:
A gate stacked structure including conductive patterns and insulating patterns alternately stacked with each other;
a memory channel structure penetrating the gate stacked structure;
a source structure on the gate stacked structure; and
Includes a first via and a second via electrically connected to the source structure,
The source structure includes a first source layer and a second source layer covering a portion of the upper surface of the first source layer,
The first source film is:
A first section covered by the second source layer, and
Includes a second section exposed from the second source layer,
The first via is provided on the first section,
The second via is provided on the second section,
The first source layer and the second source layer each include different amorphous oxides.
According to clause 7,
An electronic system wherein an insulating pattern disposed at the top of the insulating patterns of the gate stacked structure is in contact with the first source layer.
According to clause 7,
Further comprising a separation structure penetrating the gate stacked structure,
An electronic system wherein an upper surface of the separation structure is in contact with the first source layer.
According to clause 7,
The first source layer includes at least one of indium-gallium-zinc oxide, indium-zinc oxide, and indium-tungsten oxide,
The second source layer is an electronic system comprising at least one of copper oxide, tin oxide, and nickel oxide.