KR20240038900A - Light emitting display device - Google Patents

Abstract

According to embodiments, a light emitting display device includes a substrate; A first semiconductor layer including a first semiconductor for a driving transistor and a first semiconductor for a polycrystalline switching transistor; A first gate conductive layer including a gate electrode of the driving transistor overlapping at least a portion of the first semiconductor for the driving transistor and a gate electrode of the polycrystalline switching transistor overlapping at least a portion of the first semiconductor for the polycrystalline switching transistor; a second gate conductive layer overlapping at least a portion of the gate electrode of the driving transistor and including one electrode of a sustain capacitor having an opening; a second semiconductor layer including a second semiconductor for an oxide switching transistor; a third gate conductive layer including a gate electrode of the oxide switching transistor overlapping at least a portion of the second semiconductor for the oxide switching transistor; and an additional signal line electrically connected to the gate electrode of the polycrystalline switching transistor, wherein the first gate conductive layer is formed of a material containing molybdenum, and the additional signal line includes a low-resistance material.

Description

Light emitting display device {LIGHT EMITTING DISPLAY DEVICE}

This disclosure relates to a light emitting display device.

A display device is a device that displays a screen and includes a liquid crystal display (LCD) and an organic light emitting diode (OLED). These display devices are used in various electronic devices such as mobile phones, navigation devices, digital cameras, e-books, portable game consoles, and various terminals.

A display device may include a plurality of pixels arranged in row and column directions. Within each pixel, various elements, such as transistors and capacitors, and various wiring capable of supplying signals to these elements may be located.

Various elements such as transistors and capacitors are controlled by signals applied at various timings to display images, and light-emitting display devices are controlled to emit light of specific luminance to display images.

Embodiments are intended to provide a light emitting display device capable of high-speed driving.

In the embodiments, dehydrogenation is performed smoothly during the process in a polycrystalline semiconductor, thereby ensuring constant characteristics of the driving transistor.

A light emitting display device according to an embodiment includes a substrate; A first semiconductor layer including a first semiconductor for a driving transistor and a first semiconductor for a polycrystalline switching transistor; A first gate conductive layer including a gate electrode of the driving transistor overlapping at least a portion of the first semiconductor for the driving transistor and a gate electrode of the polycrystalline switching transistor overlapping at least a portion of the first semiconductor for the polycrystalline switching transistor; a second gate conductive layer overlapping at least a portion of the gate electrode of the driving transistor and including one electrode of a sustain capacitor having an opening; a second semiconductor layer including a second semiconductor for an oxide switching transistor; a third gate conductive layer including a gate electrode of the oxide switching transistor overlapping at least a portion of the second semiconductor for the oxide switching transistor; and an additional signal line electrically connected to the gate electrode of the polycrystalline switching transistor, wherein the first gate conductive layer is formed of a material containing molybdenum, and the additional signal line includes a low-resistance material.

The additional signal line may be formed of a double layer, with the lower layer containing aluminum and the upper layer containing titanium.

The second gate conductive layer may be formed of a material containing molybdenum.

The gate electrode of the oxide switching transistor may be formed of a material containing molybdenum.

a first gate insulating layer covering the first semiconductor layer; a second gate insulating film covering the gate electrode of the polycrystalline switching transistor; and an additional second gate insulating film covering the one electrode of the sustain capacitor, wherein the additional signal line is connected to the polycrystalline switching transistor through the second gate insulating film and an additional contact hole located in the additional second gate insulating film. It can be electrically connected to the gate electrode.

a first interlayer insulating film covering the additional signal line; a third gate insulating layer covering the second semiconductor layer; And it may further include a second interlayer insulating film covering the third gate conductive layer.

It is located on the second interlayer insulating film and may further include a connecting member connecting the first semiconductor for the driving transistor and the second semiconductor for the oxide switching transistor.

It may further include a connection member located on the second interlayer insulating layer and electrically connected to the gate electrode of the driving transistor.

It further includes an additional connection member formed on the same layer and made of the same material as the additional signal line, wherein the connection member is electrically connected to the gate electrode of the driving transistor through the gate electrode of the driving transistor and the additional connection member. Can be electrically connected.

The additional signal line may be located on a layer higher than the third gate conductive layer.

a first gate insulating layer covering the first semiconductor layer; a second gate insulating film covering the gate electrode of the polycrystalline switching transistor; a first interlayer insulating film covering the second gate conductive layer; a third gate insulating layer covering the second semiconductor layer; and an additional third gate insulating layer covering the third gate conductive layer, and the additional signal line may be located on the third additional gate insulating layer.

The additional signal line is electrically connected to the gate electrode of the polycrystalline switching transistor through the second gate insulating film, the first interlayer insulating film, the third gate insulating film, and an additional contact hole formed in the additional third gate insulating film. You can.

It further includes an additional signal line for an oxide transistor formed of the same material and on the same layer as the additional signal line, and the additional signal line for the oxide transistor may be electrically connected to the gate electrode of the oxide switching transistor.

The additional signal line for the oxide transistor may be electrically connected to the gate electrode of the oxide switching transistor through an additional contact hole formed in the third additional gate insulating film.

A light emitting display device according to an embodiment includes a substrate; A first semiconductor layer including a first semiconductor for a driving transistor and a first semiconductor for a polycrystalline switching transistor; A first gate conductive layer including a gate electrode of the driving transistor overlapping at least a portion of the first semiconductor for the driving transistor and a gate electrode of the polycrystalline switching transistor overlapping at least a portion of the first semiconductor for the polycrystalline switching transistor; a second gate conductive layer overlapping at least a portion of the gate electrode of the driving transistor and including an additional signal line electrically connected to one electrode of a sustain capacitor having an opening and the gate electrode of the polycrystalline switching transistor; a second semiconductor layer including a second semiconductor for an oxide switching transistor; And a third gate conductive layer including a gate electrode of the oxide switching transistor overlapping at least a portion of the second semiconductor for the oxide switching transistor, wherein the first gate conductive layer is formed of a material containing molybdenum, The second gate conductive layer includes a low-resistance material.

The one electrode of the sustain capacitor included in the second gate conductive layer and the additional signal line may be formed of a double layer, with the lower layer containing copper and the upper layer containing titanium.

The gate electrode of the oxide switching transistor may be formed of a material containing molybdenum.

a first gate insulating layer covering the first semiconductor layer; and a second gate insulating film covering the gate electrode of the polycrystalline switching transistor, wherein the additional signal line can be electrically connected to the gate electrode of the polycrystalline switching transistor through an additional contact hole located in the second gate insulating film. there is.

It may further include a connecting member connecting the first semiconductor for the driving transistor and the second semiconductor for the oxide switching transistor.

It may further include a connection member electrically connected to the gate electrode of the driving transistor.

According to embodiments, a signal line connected to the gate electrode is formed using a low-resistance material that is different from the gate electrode, allowing the light emitting display device to be driven at high speed.

By forming the gate electrode with a material containing molybdenum (Mo), hydrogen can be sufficiently removed from the semiconductor layer included in the polycrystalline transistor during the process, and the characteristics of the driving transistor can be formed consistently.

1 is a circuit diagram of one pixel included in a light emitting display device according to an embodiment.
Figure 2 is a cross-sectional view of a portion of a light emitting display device according to an embodiment.
FIG. 3 is a plan view of a portion of the light emitting display device according to the embodiment of FIG. 2 .
FIG. 4 is a diagram schematically showing a method of manufacturing a light emitting display device according to the embodiment of FIG. 2 .
Figures 5 and 6 are diagrams comparing differences between comparative examples and examples.
FIG. 7 is a diagram illustrating a change in scan voltage according to frequency in a light emitting display device according to an embodiment.
Figure 8 is a cross-sectional view of a portion of a light emitting display device according to another embodiment.
FIG. 9 is a diagram schematically showing a method of manufacturing a light emitting display device according to the embodiment of FIG. 8.
Figure 10 is a cross-sectional view of a portion of a light emitting display device according to another embodiment.
FIG. 11 is a diagram schematically showing a method of manufacturing a light emitting display device according to the embodiment of FIG. 10 .
Figure 12 is a cross-sectional view of a portion of a light emitting display device according to another embodiment.
FIG. 13 is a diagram schematically showing a method of manufacturing a light emitting display device according to the embodiment of FIG. 12 .
FIG. 14 is a diagram illustrating a cross-sectional structure of a light emitting display device according to an embodiment.

Hereinafter, with reference to the attached drawings, various embodiments of the present invention will be described in detail so that those skilled in the art can easily implement the present invention. The invention may be implemented in many different forms and is not limited to the embodiments described herein.

In order to clearly explain the present invention, parts that are not relevant to the description are omitted, and identical or similar components are assigned the same reference numerals throughout the specification.

In addition, the size and thickness of each component shown in the drawings are arbitrarily shown for convenience of explanation, so the present invention is not necessarily limited to what is shown. In the drawing, the thickness is enlarged to clearly express various layers and regions. And in the drawings, for convenience of explanation, the thicknesses of some layers and regions are exaggerated.

Additionally, when a part, such as a layer, membrane, region, plate, component, etc., is said to be "on" or "on" another part, this means not only when it is "directly above" another part, but also when there is another part in between. Also includes. Conversely, when a part is said to be “right on top” of another part, it means that there is no other part in between. In addition, being “on” or “on” a reference part means being located above or below the reference part, and does not necessarily mean being located “above” or “on” the direction opposite to gravity. .

In addition, throughout the specification, when a part is said to "include" a certain component, this means that it may further include other components rather than excluding other components, unless specifically stated to the contrary.

In addition, throughout the specification, when referring to “on a plane,” this means when the target portion is viewed from above, and when referring to “in cross section,” this means when a cross section of the target portion is cut vertically and viewed from the side.

In addition, throughout the specification, when "connected" is used, this does not mean only when two or more components are directly connected, but when two or more components are indirectly connected through other components, they are physically connected. This may include not only the case of being connected or electrically connected, but also the case where each part, which is referred to by different names depending on location or function, is substantially connected to each other.

In addition, throughout the specification, when a portion such as a wiring, layer, film, region, plate, or component is said to “extend in the first or second direction,” this means only a straight shape extending in that direction. Rather, it is a structure that extends overall along the first or second direction, and also includes a structure that is bent at some part, has a zigzag structure, or extends while including a curved structure.

In addition, electronic devices (e.g., mobile phones, TVs, monitors, laptop computers, etc.) containing display devices, display panels, etc. described in the specification, or display devices, display panels, etc. manufactured by the manufacturing method described in the specification. Electronic devices included herein are also not excluded from the scope of rights of this specification.

The present invention described below can be applied to various light emitting display devices, and hereinafter, an embodiment of one of various pixel structures will be examined through FIG. 1.

1 is a circuit diagram of one pixel included in a light emitting display device according to an embodiment.

One pixel according to one embodiment includes a plurality of transistors (T1, T2, T3, T4, T5, T6) connected to several wires (127, 128, 151, 152, 153, 155, 171, 172, 741). , T7), a sustain capacitor (Cst), a boost capacitor (C _boost ), and a light emitting diode (LED). Here, transistors and capacitors excluding light emitting diodes (LEDs) constitute the pixel circuit unit. Depending on the embodiment, the boost capacitor (C _boost ) may be omitted. Meanwhile, depending on the embodiment, an additional capacitor or an additional boost capacitor may be formed.

A plurality of wires 127, 128, 151, 152, 153, 155, 171, 172, and 741 are connected to one pixel (PX). The plurality of wires include a first initialization voltage line 127, a second initialization voltage line 128, a first scan line 151, a second scan line 152, an initialization control line 153, a light emission control line 155, It includes a data line 171, a driving voltage line 172, and a common voltage line 741.

The first scan line 151 is connected to a scan driver (not shown) and transmits the first scan signal GW to the second transistor T2 and the seventh transistor T7. A voltage of opposite polarity to the voltage applied to the first scan line 151 may be applied to the second scan line 152 at the same timing as the signal of the first scan line 151. For example, when a negative voltage is applied to the first scan line 151, a positive voltage may be applied to the second scan line 152. The second scan line 152 transmits the second scan signal GC to the third transistor T3. The initialization control line 153 transmits the initialization control signal GI to the fourth transistor T4. The emission control line 155 transmits the emission control signal EM to the fifth transistor T5 and the sixth transistor T6.

The data line 171 is a wire that transmits the data voltage (DATA) generated by the data driver (not shown), and the size of the light-emitting current transmitted to the light-emitting diode (LED) changes accordingly, causing the light-emitting diode (LED) to emit light. Luminance also changes. The driving voltage line 172 applies the driving voltage ELVDD. The first initialization voltage line 127 transmits the first initialization voltage (VINT), and the second initialization voltage line 128 transmits the second initialization voltage (VAINT). The common voltage line 741 applies the common voltage (ELVSS) to the cathode of the light emitting diode (LED). In this embodiment, the voltage applied to the driving voltage line 172, the first and second initialization voltage lines 127 and 128, and the common voltage line 741 may each be a constant voltage.

The driving transistor (T1; also referred to as the first transistor) is a p-type transistor and has a silicon semiconductor (hereinafter also referred to as a polycrystalline semiconductor or first semiconductor) as a semiconductor layer. It is a transistor that adjusts the size of the light emitting current output to the anode of the light emitting diode (LED) according to the size of the voltage of the gate electrode of the driving transistor (T1) (i.e., the voltage stored in the sustain capacitor (Cst)). Since the brightness of the light emitting diode (LED) is adjusted according to the size of the light emitting current output to the anode electrode of the light emitting diode (LED), the light emitting brightness of the light emitting diode (LED) can be adjusted according to the data voltage (DATA) applied to the pixel. . To this end, the first electrode of the driving transistor T1 is arranged to receive the driving voltage ELVDD and is connected to the driving voltage line 172 via the fifth transistor T5. Additionally, the first electrode of the driving transistor T1 is connected to the second electrode of the second transistor T2 to receive the data voltage DATA. Meanwhile, the second electrode of the driving transistor (T1) outputs a light emitting current to the light emitting diode (LED) and is connected to the anode of the light emitting diode (LED) via the sixth transistor (T6; hereinafter also referred to as the output control transistor). there is. Additionally, the second electrode of the driving transistor T1 is connected to the third transistor T3, and transmits the data voltage DATA applied to the first electrode to the third transistor T3. Meanwhile, the gate electrode of the driving transistor T1 is connected to one electrode (hereinafter referred to as the 'second storage electrode') of the storage capacitor Cst. The other electrode (hereinafter referred to as 'first maintenance electrode') of the sustain capacitor (Cst) receives the driving voltage (ELVDD). Accordingly, the voltage of the gate electrode of the driving transistor (T1) changes according to the voltage stored in the sustain capacitor (Cst), and the light emission current output by the driving transistor (T1) changes accordingly. The maintenance capacitor Cst serves to keep the voltage of the gate electrode of the driving transistor T1 constant during one frame. Meanwhile, the gate electrode of the driving transistor T1 is also connected to the third transistor T3, so that the data voltage DATA applied to the first electrode of the driving transistor T1 passes through the third transistor T3 and is connected to the third transistor T3. ) can be transmitted to the gate electrode. Meanwhile, the gate electrode of the driving transistor T1 is also connected to the fourth transistor T4 and can be initialized by receiving the first initialization voltage VINT.

The second transistor T2 is a p-type transistor and has a silicon semiconductor as a semiconductor layer. The second transistor T2 is a transistor that receives the data voltage (DATA) into the pixel. The gate electrode of the second transistor T2 is connected to the first scan line 151 and one electrode of the boost capacitor C _boost (hereinafter referred to as 'lower boost electrode'). The other electrode of the boost capacitor (C _boost ) is connected to the gate electrode of the driving transistor (T1) and the second sustain electrode of the sustain capacitor (Cst). Meanwhile, the first electrode of the second transistor T2 is connected to the data line 171, and the second electrode of the second transistor T2 is connected to the first electrode of the driving transistor T1. When the second transistor (T2) is turned on by the negative voltage of the first scan signal (GW) transmitted through the first scan line 151, the data voltage (DATA) transmitted through the data line 171 This is transmitted to the first electrode of the driving transistor (T1), and finally, the data voltage (DATA) is transmitted to the gate electrode of the driving transistor (T1) and stored in the sustain capacitor (Cst).

The third transistor T3 is an n-type transistor and has an oxide semiconductor (hereinafter also referred to as a second semiconductor) as a semiconductor layer. The third transistor T3 electrically connects the second electrode of the driving transistor T1 to the gate electrode of the driving transistor T1. As a result, the data voltage DATA is compensated by the threshold voltage of the driving transistor T1 and then stored in the second sustain electrode of the sustain capacitor Cst. The gate electrode of the third transistor T3 is connected to the second scan line 152, and the first electrode of the third transistor T3 is connected to the second electrode of the driving transistor T1. The second electrode of the third transistor (T3) is the second sustain electrode of the sustain capacitor (Cst), the gate electrode of the driving transistor (T1), and the other electrode of the boost capacitor (C _boost ) (hereinafter referred to as 'upper boost electrode'). is connected to The third transistor (T3) is turned on by the positive voltage of the second scan signal (GC) received through the second scan line 152, and the gate electrode of the driving transistor (T1) and the The second electrode is connected, and the voltage applied to the gate electrode of the driving transistor (T1) is transferred to the second sustain electrode of the sustain capacitor (Cst) and stored in the sustain capacitor (Cst). At this time, the voltage stored in the maintenance capacitor (Cst) is the voltage of the gate electrode of the driving transistor (T1) when the driving transistor (T1) is turned off, so that the threshold voltage (Vth) value of the driving transistor (T1) is stored. It is stored in a compensated state.

The fourth transistor T4 is an n-type transistor and has an oxide semiconductor as a semiconductor layer. The fourth transistor T4 serves to initialize the gate electrode of the driving transistor T1 and the second sustain electrode of the sustain capacitor Cst. The gate electrode of the fourth transistor T4 is connected to the initialization control line 153, and the first electrode of the fourth transistor T4 is connected to the first initialization voltage line 127. The second electrode of the fourth transistor T4 is the second electrode of the third transistor T3, the second sustain electrode of the sustain capacitor Cst, the gate electrode of the driving transistor T1, and the boost capacitor C _boost . It is connected to the upper boost electrode. The fourth transistor (T4) is turned on by the positive polarity voltage of the initialization control signal (GI) received through the initialization control line 153. At this time, the first initialization voltage (VINT) is applied to the driving transistor (T1). It is initialized by passing it to the gate electrode, the second sustain electrode of the sustain capacitor (Cst), and the upper boost electrode of the boost capacitor (C _boost ).

The fifth transistor (T5) and the sixth transistor (T6) are p-type transistors and have a silicon semiconductor as a semiconductor layer.

The fifth transistor T5 serves to transmit the driving voltage ELVDD to the driving transistor T1. The gate electrode of the fifth transistor T5 is connected to the emission control line 155, the first electrode of the fifth transistor T5 is connected to the driving voltage line 172, and the first electrode of the fifth transistor T5 is connected to the driving voltage line 172. The second electrode is connected to the first electrode of the driving transistor (T1).

The sixth transistor (T6) serves to transfer the light emission current output from the driving transistor (T1) to the light emitting diode (LED). The gate electrode of the sixth transistor (T6) is connected to the light emission control line 155, the first electrode of the sixth transistor (T6) is connected to the second electrode of the driving transistor (T1), and the sixth transistor ( The second electrode of T6) is connected to the anode of the light emitting diode (LED).

The seventh transistor T7 is a p-type or n-type transistor, and may have a silicon semiconductor or an oxide semiconductor as a semiconductor layer. In the embodiment of FIG. 26, the seventh transistor T7 is a p-type transistor and has a silicon semiconductor. Includes. The seventh transistor (T7) serves to initialize the anode of the light emitting diode (LED). The gate electrode of the seventh transistor T7 is connected to the first scan line 151, the first electrode of the seventh transistor T7 is connected to the anode of the light emitting diode (LED), and the seventh transistor T7 ) The second electrode is connected to the second initialization voltage line 128. Here, the gate electrode of the seventh transistor (T7) is connected to the first scan line 151 of the previous pixel, and the first scan line 151 is the same as the gate electrode of the second transistor (T2) belonging to the same pixel (PX). ), but may be connected to the first scan line 151, which is the same as the gate electrode of the second transistor T2 of the front pixel PX. When the seventh transistor T7 is turned on by the negative voltage of the first scan line 151, the second initialization voltage VAINT is applied to the anode of the light emitting diode (LED) and initialized. Meanwhile, the gate electrode of the seventh transistor T7 may be connected to a separate bypass control line through which the bypass signal GB is transmitted, and may be controlled through a separate wire from the first scan line 151. Additionally, depending on the embodiment, the second initialization voltage line 128 to which the second initialization voltage VAINT is applied may be the same as the first initialization voltage line 127 to which the first initialization voltage VINT is applied.

Although one pixel (PX) has been described as including seven transistors (T1 to T7) and two capacitors (sustaining capacitor (Cst) and boost capacitor (C _boost )), it is not limited thereto and may vary depending on the embodiment. The boost capacitor (C _boost ) may be excluded. Additionally, depending on the embodiment, an additional boost capacitor may be formed between the gate electrode of the third transistor T3 and the gate electrode of the driving transistor T1. In addition, although the third transistor and the fourth transistor are formed as n-type transistors in an embodiment, only one of them may be formed as an n-type transistor, or the other transistor (for example, the seventh transistor, etc.) may be formed as an n-type transistor.

As described above, the pixel of a light emitting display device contains two types of semiconductors located in different layers, and the two types of semiconductors are polycrystalline semiconductors (also called first semiconductors) and oxide semiconductors (also called second semiconductors), respectively. . These are each included in a transistor, and hereinafter, a transistor containing a polycrystalline semiconductor is referred to as a polycrystalline transistor, and a transistor containing an oxide semiconductor is referred to as an oxide transistor. In this way, one pixel may include a polycrystalline transistor and an oxide transistor, and the driving transistor T1, which provides driving current to the light emitting diode (LED), is formed of a polycrystalline transistor. All transistors except the driving transistor (T1) are also called switching transistors, and switching transistors can be divided into polycrystalline switching transistors and oxide switching transistors.

Hereinafter, a cross-sectional view of a light-emitting display device according to an embodiment will be looked at through FIG. 2.

Figure 2 is a cross-sectional view of a portion of a light emitting display device according to an embodiment.

In Figure 2, a driving transistor, a polycrystalline switching transistor, and an oxide switching transistor are representatively shown. Here, the polycrystalline switching transistor may be one of the second transistor (T2), the fifth transistor (T5), the sixth transistor (T6), and the seventh transistor (T7) of FIG. 1, and the oxide switching transistor may be one of the first transistor (T7) of FIG. 1. It may be one of the third transistor (T3) and the fourth transistor (T4). Depending on the embodiment, the seventh transistor T7 may be formed as an oxide switching transistor.

According to Figure 2, the substrate 110, barrier layer 110-1, and buffer layer 111 are formed sequentially. The substrate 110 may include a material that has rigid properties and does not bend, such as glass, or may include a flexible material that can bend, such as plastic or polyimide. A barrier layer 110-1 is located on the substrate 110, and depending on the embodiment, the barrier layer 110-1 may be omitted.

A buffer layer 111 covering the barrier layer 110-1 is located on top of the barrier layer 110-1. The buffer layer 111 serves to block impurity elements from penetrating into the first semiconductor layer ACT1, and may be an inorganic insulating film containing silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiONx). Depending on the embodiment, a metal layer (see BML in FIG. 14) may be formed between the barrier layer 110-1 and the buffer layer 111.

A first semiconductor layer (ACT1) formed of a polycrystalline semiconductor (P-Si) is located on the buffer layer 111. In FIG. 2, the first semiconductor layer ACT1 includes the first semiconductor of the driving transistor (ACT1-1; hereinafter also referred to as the first semiconductor for the driving transistor) and the first semiconductor of the polycrystalline switching transistor (ACT1-2; also referred to as the first semiconductor for the polycrystalline switching transistor). 1 (also called semiconductors) are shown separately. Here, the polycrystalline switching transistor may be one of the second transistor (T2), the fifth transistor (T5), the sixth transistor (T6), and the seventh transistor (T7) of FIG. 1. Each of the first semiconductor layers (ACT1) includes a channel and a first region and a second region located on both sides of the channel, and the first region and the second region have conductive layer characteristics by plasma treatment or doping, thereby forming the first region of the polycrystalline transistor. It can serve as the first electrode and the second electrode.

A first gate insulating layer 141 may be positioned on the first semiconductor layer ACT1. The first gate insulating layer 141 may be an inorganic insulating layer containing silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiONx).

A first gate conductive layer including gate electrodes (GE1 and GE2) of the polycrystalline transistor may be positioned on the first gate insulating film 141. The first gate conductive layer is shown divided into a gate electrode (GE1) of the driving transistor and a gate electrode (GE2) of the polycrystalline switching transistor.

The gate electrode GE1 of the driving transistor and the gate electrode GE2 of the polycrystalline switching transistor according to the embodiment of FIG. 1 are located on the same layer (first gate insulating film 141) and are made of the same material. That is, the gate electrode (GE1) of the driving transistor and the gate electrode (GE2) of the polycrystalline switching transistor are formed of a material containing molybdenum (Mo) and may be formed as a single layer or multiple layers. In one embodiment, the gate electrode (GE1) of the driving transistor and the gate electrode (GE2) of the polycrystalline switching transistor may be formed of a single layer of molybdenum (Mo). Here, the gate electrodes (GE1, GE2) of molybdenum (Mo) have the advantage of ensuring that the characteristics of the transistor are constant by easily dehydrogenating during the process, as shown in FIG. 4. In particular, the characteristics of the driving transistor are constant. This ensures that a constant output current can be generated.

After forming the first gate conductive layer, a plasma treatment or doping process may be performed to make the exposed area of the first semiconductor layer conductive. That is, the first semiconductor layer ACT1 covered by the first gate conductive layer is not conductive, and the portion of the first semiconductor layer ACT1 not covered by the first gate conductive layer has the same characteristics as the conductive layer. You can.

A second gate insulating layer 142 may be positioned on the first gate conductive layer and the first gate insulating layer 141. The second gate insulating film 142 may be an inorganic insulating film containing silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiONx).

A second gate conductive layer including one electrode (CE) of the sustain capacitor (Cst) may be positioned on the second gate insulating film 142. One electrode (CE) of the sustain capacitor (Cst) overlaps the gate electrode (GE1) of the driving transistor to form the sustain capacitor (Cst), and an opening (CEop) overlaps a portion of the gate electrode (GE1) of the driving transistor. You can have it. Depending on the embodiment, the second gate conductive layer may further include a scan line, a control line, or a voltage line. The second gate conductive layer may include a metal or metal alloy such as copper (Cu), molybdenum (Mo), aluminum (Al), or titanium (Ti), and may be composed of a single layer or multiple layers. The second gate conductive layer according to one embodiment may be formed of a single layer of molybdenum (Mo).

An additional second gate insulating layer 142-1 may be positioned on the second gate conductive layer. The additional second gate insulating layer 142-1 may be an inorganic insulating layer containing silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiONx).

An additional conductive layer including an additional signal line ASL1 may be positioned on the second additional gate insulating layer 142-1. The additional signal line ASL1 is electrically connected to the gate electrode GE2 of the polycrystalline switching transistor through the second gate insulating film 142 and the contact hole located in the additional second gate insulating film 142-1. The additional signal line (ASL1) includes a low-resistance material such as aluminum (Al) or copper (Cu). The additional signal line (ASL1) according to one embodiment is formed of a double layer, and the lower layer is formed of aluminum (Al), The upper layer may be formed of titanium (Ti). Referring to Figure 7, molybdenum (Mo) has the disadvantage of causing a signal delay when driven at 240Hz, so in Figure 2, it is electrically connected to the gate electrode (GE2) of the polycrystalline switching transistor, and contains a metal with low resistance characteristics. It further includes an additional signal line (ASL1) to ensure that a scan signal with a sufficient voltage value is transmitted even during high-speed driving at 240Hz and to prevent problems with delay due to resistance.

A first interlayer insulating film 161 may be positioned on the additional conductive layer. The first interlayer insulating film 161 may include an inorganic insulating film containing silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiONx). Depending on the embodiment, the inorganic insulating material may be formed thickly. .

A second semiconductor layer including a second semiconductor (ACT2; hereinafter also referred to as a second semiconductor for oxide switching transistor) including the channel, first region, and second region of the oxide transistor will be located on the first interlayer insulating film 161. You can.

A third gate insulating layer 143 may be located on the second semiconductor layer. The third gate insulating layer 143 may be located on the entire surface of the second semiconductor layer and the first interlayer insulating layer 161. The third gate insulating layer 143 may include an inorganic insulating layer containing silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiONx).

A third gate conductive layer including the gate electrode GE3 of the oxide transistor (or oxide switching transistor) may be positioned on the third gate insulating film 143. The gate electrode (GE3) of the oxide transistor may overlap the channel. The third gate conductive layer may further include a scan line or a control line. The third gate conductive layer may contain a metal or metal alloy such as copper (Cu), molybdenum (Mo), aluminum (Al), or titanium (Ti), and may be composed of a single layer or multiple layers. The third gate conductive layer according to one embodiment may be formed as a single layer made of molybdenum (Mo).

After forming the third gate conductive layer, a plasma treatment or doping process may be performed to make the exposed area of the second semiconductor ACT2 conductive. That is, the second semiconductor ACT2 covered by the third gate conductive layer is not conductive, and the portion of the second semiconductor ACT2 not covered by the third gate conductive layer may have the same characteristics as the conductive layer. .

A second interlayer insulating film 162 may be positioned on the third gate conductive layer. The second interlayer insulating film 162 may have a single-layer or multi-layer structure. The second interlayer insulating film 162 may include an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), or silicon nitride (SiOxNy), and may include an organic material depending on the embodiment.

A first data conductive layer including a connection member that can be connected to the first and second regions of each of the polycrystalline transistor and the oxide transistor may be positioned on the second interlayer insulating film 162.

In FIG. 2, the first data conductive layer includes a connecting member (SE1) connected to the first region of the driving transistor, a connecting member (DE1) connected to the second region of the driving transistor, and a connecting member (DE1) connected to the gate electrode of the driving transistor. CM2), connecting members (SE2, DE2) connected to each of the first and second regions of the polycrystalline switching transistor, and connecting members (SE3, DE3) connected to each of the first and second regions of the oxide switching transistor. A connection member SE3 connected to the first region of the oxide switching transistor and a connection member DE1 connected to the second region of the driving transistor are integrally connected to form the connection member CM1. That is, the first semiconductor ACT1-1 for the driving transistor and the second semiconductor ACT2 for the oxide switching transistor may be connected to each other by the connecting member CM1.

The first data conductive layer may include a metal or metal alloy such as aluminum (Al), copper (Cu), molybdenum (Mo), titanium (Ti), and may be composed of a single layer or multiple layers.

An organic layer may be located on the first data conductive layer, and an anode may be located on the organic layer. The above structure of the first data conductive layer is examined in FIG. 14.

In the above, the cross-sectional structure was examined, and below, the schematic planar structure of the polycrystalline switching transistor is examined with reference to FIG. 3 centered on the additional signal line (ASL1).

FIG. 3 is a plan view of a portion of the light emitting display device according to the embodiment of FIG. 2 .

Referring to FIG. 3, the first semiconductor (ACT1-2) of the polycrystalline switching transistor extends in one direction, the gate electrode (GE2) of the polycrystalline switching transistor extends in a direction perpendicular to this, and the gate electrode of the polycrystalline switching transistor (GE2) extends in one direction. An additional signal line (ASL1) extends in a direction perpendicular to the electrode (GE2). The additional signal line (ASL1) and the gate electrode (GE2) of the polycrystalline switching transistor are electrically connected through the opening (D-CNT). The additional signal line ASL1 extends to the non-display area of the light emitting display device and can receive a scan signal from a scan driver (not shown). In contrast, the first semiconductor (ACT1-2) and gate electrode (GE2) of the polycrystalline switching transistor can be located only within one pixel. Since the direction of each part (ASL1, GE2, ACT1_2) shown in FIG. 3 is an arrangement direction according to one embodiment, they may be arranged in a direction different from that of FIG. 3.

The structures of FIGS. 2 and 3 as described above can be formed using the same manufacturing method as that of FIG. 4.

FIG. 4 is a diagram schematically showing a method of manufacturing a light emitting display device according to the embodiment of FIG. 2 .

In Figure 4, it is shown divided into a semiconductor or conductor stacking step (DEP1 to DEP7), an etching step (ET1 to ET8), and an insulating film stacking step (IDEP1 to IDEP5), with the step located at a lower position being performed first. It is showing.

Specifically, according to the manufacturing method of FIG. 4, the first semiconductor (ACT1) is stacked (DEP1), the first semiconductor (ACT1) is etched (ET1), and then the first gate insulating film 141 is stacked (IDEP1). do.

After that, the first gate conductive layer (GAT1) is stacked (DEP2), the first gate conductive layer (GAT1) is etched (ET2), and the second gate insulating film 142 is stacked (IDEP2). Here, the gate electrode (GE1) of the driving transistor and the gate electrode (GE2) of the polycrystalline switching transistor included in the first gate conductive layer (GAT1) may both be formed of the same material, and may be made of a material containing molybdenum (Mo). can be formed.

After that, the second gate conductive layer (GAT2) is stacked (DEP3), the second gate conductive layer (GAT2) is etched (ET3), and an additional second gate insulating film 142-1 is stacked (IDEP2-1). )do. Here, the second gate conductive layer (GAT2) may include various metals, and the second gate conductive layer (GAT2) according to one embodiment may be formed of a material containing molybdenum (Mo).

Afterwards, an additional contact hole (CNT1) is formed (ET3-1) in the second gate insulating layer 142 and the additional second gate insulating layer 142-1. The gate electrode (GE2) of the polycrystalline switching transistor may be exposed by the additional contact hole (CNT1).

After that, an additional conductive layer (CMTL) is stacked (DEP4), the additional conductive layer (CMTL) is etched (ET4), and then the first interlayer insulating film 161 is stacked (IDEP3). Here, the additional conductive layer (CMTL) may include a low-resistance metal, and in one embodiment, may be formed as a double layer, with the lower layer being formed of aluminum (Al) and the upper layer being formed of titanium (Ti).

Afterwards, the second semiconductor (ACT2) is stacked (DEP5), the second semiconductor (ACT2) is etched (ET5), and the third gate insulating film 143 is stacked (IDEP4). After that, the third gate conductive layer (GAT3) is stacked (DEP6), the third gate conductive layer (GAT3) is etched (ET6), and then the second interlayer insulating film 162 is stacked (IDEP5). Here, the third gate conductive layer (GAT3) may include various metals, and in one embodiment, may be formed as a single layer made of a material containing molybdenum (Mo).

Afterwards, the first gate insulating film 141, the second gate insulating film 142, the second additional gate insulating film 142-1, the first interlayer insulating film 161, the third gate insulating film 143, and the second interlayer. A contact hole (CNT2) is formed (ET7) in at least one of the insulating films 162. Here, the contact hole (CNT2) can be divided into two end contact holes, and the first contact hole includes the first semiconductor (ACT1), the first gate conductive layer (GAT1), the second gate conductive layer (GAT2), and the additional contact hole. It is a contact hole that exposes the conductive layer (CMTL), and the second contact hole may be a contact hole that exposes the second semiconductor (ACT2) and the third gate conductive layer (GAT3). Depending on the embodiment, the first contact hole and the second contact hole may be formed in different processes.

Afterwards, the first data conductive layer is stacked (DEP7) and the first data conductive layer is etched (ET8).

The structure of the upper part of the first data conductive layer is examined in FIG. 14.

Hereinafter, through FIGS. 5 and 6, the characteristics of the case where the gate electrode of the driving transistor is formed of molybdenum (Mo) will be compared with the comparative example.

Figures 5 and 6 are diagrams comparing differences between comparative examples and examples.

Figure 5 is an example in which the gate electrode of the driving transistor is formed of molybdenum (Mo), and Figure 6 is a comparative example in which the gate electrode of the driving transistor is formed of aluminum (Al), a low-resistance metal, rather than molybdenum (Mo).

Referring to Figure 6, which is a comparative example, due to the gate electrode formed of aluminum (Al), hydrogen located within the first semiconductor (ACT1) is not removed to the outside through the opening (PCNT) formed in the insulating film. In contrast, referring to FIG. 5, which is an embodiment, the gate electrode of the driving transistor made of molybdenum (Mo) does not prevent hydrogen located within the first semiconductor (ACT1) from being discharged to the outside through the opening (PCNT). As a result, the dehydrogenation phenomenon of the first semiconductor (ACT1) sufficiently occurs, so the driving range of the driving transistor can be secured consistently, and the characteristics of the driving transistor also have the advantage of being constant.

On the other hand, when the gate electrode is formed of molybdenum (Mo), there are disadvantages that may occur during high-speed driving, which will be examined in Figure 7.

FIG. 7 is a diagram illustrating a change in scan voltage according to frequency in a light emitting display device according to an embodiment.

Figure 7 shows the characteristics of the scan signal (GW) according to the driving frequency for an embodiment in which the signal line is formed of molybdenum (Mo) and an embodiment in which the signal line is formed of aluminum (Al). Additionally, Figure 7(A) shows a case of operating at a driving frequency of 120 Hz, and Figure 7(B) shows a case of operating at a driving frequency of 240 Hz.

Referring to Figure 7(A), at a driving frequency of 120Hz, the signal line is formed of molybdenum (Mo) or aluminum (Al), or the scan signal (GW) has a voltage below a certain level for more than a certain period of time and is driven at 120Hz. You can confirm that there is no problem.

However, referring to FIG. 7(B), at a driving frequency of 240Hz, the scan signal (GW) transmitted through a signal line made of aluminum (Al) has a voltage below a certain level for a certain period of time, so there is no problem in driving at 240Hz. The scan signal (GW) transmitted through a signal line made of molybdenum (Mo) is difficult to operate as a scan signal because the voltage is not low enough, resulting in a problem in which the data voltage (DATA) is not sufficiently charged when driven at 240Hz. Therefore, in this embodiment in which the gate electrode of the transistor is made of molybdenum (Mo) for 240Hz and equivalent high-speed driving, an additional signal line (ASL1) with low resistance is formed to prevent the signal from being delayed, thereby enabling high-speed driving at 240Hz. It can be made possible. Here, the additional signal line ASL1 includes a low-resistance material such as aluminum (Al) or copper (Cu), and the additional signal line ASL1 according to one embodiment is formed of a double layer, and the lower layer is formed of aluminum (Al). and the upper layer may be formed of titanium (Ti).

Summarizing the characteristics of FIGS. 5 and 7, in this embodiment, the gate electrode of the driving transistor (T1), which is one of the polycrystalline transistors, is formed of a material containing molybdenum (Mo) to facilitate dehydrogenation, and the polycrystalline transistor is made of a material containing molybdenum (Mo). The gate electrode of at least one transistor among the switching transistors is made of a material containing molybdenum (Mo), but is electrically connected to it and forms an additional signal line (ASL1) containing a low-resistance material, so that it can be operated even at high speed of 240 Hz. Avoid problems with signal delay and low charging rates. In this embodiment, aluminum (Al) or copper (Cu) can be used as a material having low resistance.

Hereinafter, another modified embodiment different from FIGS. 2 and 4 will be looked at through FIGS. 8 to 13, and first, the embodiment of FIGS. 8 and 9 will be looked at.

FIG. 8 is a cross-sectional view of a portion of a light-emitting display device according to another embodiment, and FIG. 9 is a diagram schematically showing a method of manufacturing a light-emitting display device according to the embodiment of FIG. 8.

8 and 9, unlike the embodiment of FIGS. 2 and 4, an additional connection member (ASL2) is further formed on the additional conductive layer (CMTL), and the gate of the driving transistor is connected through the additional connection member (ASL2). Connect the electrode (GE1) and the connecting member (CM2).

Referring to FIG. 8, unlike FIG. 2, in addition to the additional signal line ASL1, an additional connection member ASL2 is formed in the additional conductive layer located on the additional second gate insulating film 142-1. The additional connection member ASL2 is electrically connected to the gate electrode GE1 of the driving transistor through the second gate insulating layer 142 and the contact hole located in the additional second gate insulating layer 142-1. The additional connection member ASL2, like the additional signal line ASL1, includes a low-resistance material such as aluminum (Al) or copper (Cu), and the additional signal line ASL1 according to one embodiment is formed of a double layer, with the lower layer It may be formed of aluminum (Al), and the upper layer may be formed of titanium (Ti).

The additional connection member ASL2 is covered with a first interlayer insulating film 161, a third gate insulating film 143, and a second interlayer insulating film 162, and the first interlayer insulating film 161 and the third gate insulating film 143 , and is connected to the connection member CM2 located in the first data conductive layer by a contact hole formed in the second interlayer insulating film 162. As a result, the gate electrode (GE1) of the driving transistor and the connection member (CM2) are connected through the additional connection member (ASL2).

The embodiments of FIGS. 8 and 9 are no different from the embodiments of FIGS. 2 and 4 in overall process, so FIGS. 9 and 4 may include the same steps.

The differences between the embodiment of FIG. 9 and FIG. 4 are explained as follows.

In the step of forming the additional contact hole (CNT1) (ET3-1) in FIG. 9, the additional contact hole (CNT1) is formed in the second gate insulating film 142 and the additional second gate insulating film 142-1 to form the polycrystalline switching transistor. The gate electrode (GE2) of the driving transistor as well as the gate electrode (GE1) of the driving transistor may be exposed.

Thereafter, in the step of stacking (DEP4) the additional conductive layer (CMTL) and etching (ET4) the additional conductive layer (CMTL), not only the additional signal line (ASL1) but also the additional connection member (ASL2) is formed. The additional connection member ASL2 may be connected to the gate electrode GE1 of the driving transistor through the second gate insulating layer 142 and the additional contact hole CNT1 in the second additional gate insulating layer 142-1.

Thereafter, in the step of forming the contact hole (CNT2) (ET7), the upper surface of the additional connecting member (ASL2) is exposed to the contact hole (CNT2) at the position where the connecting member (CM2) is to be formed. Afterwards, a connection member (CM2) is formed in the step of stacking the first data conductive layer (DEP7) and etching the first data conductive layer (ET8). As a result, the connection member (CM2) and the additional connection member (ASL2) are connected, and the additional connection member (ASL2) is connected to the gate electrode (GE1) of the driving transistor, so that the connection member (CM2) is connected to the gate electrode (GE1) of the driving transistor. ) can be connected to.

All other steps may be the same as those described in FIG. 4, and the embodiments of FIGS. 8 and 9 may have all the features of the embodiments of FIGS. 2 and 3.

Hereinafter, the embodiments of FIGS. 10 and 11 will be looked at in detail.

FIG. 10 is a cross-sectional view of a portion of a light-emitting display device according to another embodiment, and FIG. 11 is a diagram schematically showing a method of manufacturing a light-emitting display device according to the embodiment of FIG. 10 .

In the embodiment of FIG. 10, unlike the embodiment of FIG. 2, an additional conductive layer is formed between the third gate conductive layer and the first data conductive layer, and two additional signal lines (ASL1 and ASL3) are formed to perform polycrystalline switching, respectively. It has a structure in which the gate electrode (GE2) of the transistor is connected to the gate electrode (GE3) of the oxide switching transistor.

Looking at the embodiment of FIG. 10 in detail, it is as follows, and some overlapping contents among the contents described in FIGS. 2 and 4 have been omitted.

According to Figure 10, the substrate 110, barrier layer 110-1, and buffer layer 111 are formed sequentially. Depending on the embodiment, the barrier layer 110-1 may be omitted. A buffer layer 111 covering the barrier layer 110-1 is located on top of the barrier layer 110-1. The buffer layer 111 may serve to block impurity elements from penetrating into the first semiconductor layer ACT1. Depending on the embodiment, a metal layer (see BML in FIG. 14) may be formed between the barrier layer 110-1 and the buffer layer 111.

A first semiconductor layer (ACT1) formed of a polycrystalline semiconductor (P-Si) is located on the buffer layer 111. In FIG. 8, the first semiconductor layer (ACT1) is shown divided into a first semiconductor (ACT1-1) of the driving transistor and a first semiconductor (ACT1-2) of the polycrystalline switching transistor. Here, the polycrystalline switching transistor may be one of the second transistor (T2), the fifth transistor (T5), the sixth transistor (T6), and the seventh transistor (T7) of FIG. 1. Each of the first semiconductor layers (ACT1) includes a channel and a first region and a second region located on both sides of the channel, and the first region and the second region have conductive layer characteristics by plasma treatment or doping, thereby forming the first region of the polycrystalline transistor. It can serve as the first electrode and the second electrode.

A first gate insulating layer 141 may be positioned on the first semiconductor layer ACT1.

A first gate conductive layer including gate electrodes (GE1 and GE2) of the polycrystalline transistor may be positioned on the first gate insulating film 141. The first gate conductive layer is shown divided into a gate electrode (GE1) of the driving transistor and a gate electrode (GE2) of the polycrystalline switching transistor. Here, the gate electrode (GE1) of the driving transistor and the gate electrode (GE2) of the polycrystalline switching transistor are made of a material containing molybdenum (Mo) and may be formed as a single layer or multiple layers. In one embodiment, the gate electrode (GE1) of the driving transistor and the gate electrode (GE2) of the polycrystalline switching transistor may be formed of a single layer of molybdenum (Mo). Here, the gate electrodes (GE1, GE2) of molybdenum (Mo) have the advantage of ensuring that the characteristics of the transistor are constant by easily dehydrogenating during the process, as shown in FIG. 4. In particular, the characteristics of the driving transistor are constant. This ensures that a constant output current can be generated.

After forming the first gate conductive layer, a plasma treatment or doping process may be performed to make the exposed area of the first semiconductor layer conductive. That is, the first semiconductor layer ACT1 covered by the first gate conductive layer is not conductive, and the portion of the first semiconductor layer ACT1 not covered by the first gate conductive layer has the same characteristics as the conductive layer. You can.

A second gate insulating layer 142 may be positioned on the first gate conductive layer and the first gate insulating layer 141.

A second gate conductive layer including one electrode (CE) of the sustain capacitor (Cst) may be positioned on the second gate insulating film 142. One electrode (CE) of the sustain capacitor (Cst) overlaps the gate electrode (GE1) of the driving transistor to form the sustain capacitor (Cst), and an opening (CEop) overlaps a portion of the gate electrode (GE1) of the driving transistor. You can have it. Depending on the embodiment, the second gate conductive layer may further include a scan line, a control line, or a voltage line. The second gate conductive layer may include a metal or metal alloy such as copper (Cu), molybdenum (Mo), aluminum (Al), titanium (Ti), and may be composed of a single layer or multiple layers. The second gate conductive layer according to the example may be formed of a single layer of molybdenum (Mo).

A first interlayer insulating film 161 may be positioned on the second gate conductive layer.

A second semiconductor layer (oxide semiconductor layer) including a second semiconductor (ACT2) including a channel, a first region, and a second region of the oxide transistor may be located on the first interlayer insulating film 161.

A third gate insulating layer 143 may be located on the second semiconductor layer. The third gate insulating layer 143 may be located on the entire surface of the second semiconductor layer and the first interlayer insulating layer 161.

A third gate conductive layer including the gate electrode (GE3) of the oxide transistor may be positioned on the third gate insulating film 143. The gate electrode (GE3) of the oxide transistor may overlap the channel. The third gate conductive layer may further include a scan line or a control line. The third gate conductive layer may include a metal or metal alloy such as copper (Cu), molybdenum (Mo), aluminum (Al), titanium (Ti), and may be composed of a single layer or multiple layers. The third gate conductive layer according to the example may be formed as a single layer made of molybdenum (Mo).

After forming the third gate conductive layer, a plasma treatment or doping process may be performed to make the exposed area of the second semiconductor ACT2 conductive. That is, the second semiconductor ACT2 covered by the third gate conductive layer is not conductive, and the portion of the second semiconductor ACT2 not covered by the third gate conductive layer may have the same characteristics as the conductive layer. .

An additional third gate insulating layer 143-1 may be located on the third gate conductive layer. The additional third gate insulating layer 143-1 may include an inorganic insulating layer including silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiONx).

An additional conductive layer including two additional signal lines ASL1 and ASL3 may be located on the third additional gate insulating layer 143-1. The two additional signal lines (ASL1 and ASL3) are electrically connected to the gate electrode (GE2) of the polycrystalline switching transistor and the gate electrode (GE3) of the oxide switching transistor, respectively. Specifically, the additional signal line ASL1 connects the contact holes located in the second gate insulating film 142, the first interlayer insulating film 161, the third gate insulating film 143, and the additional third gate insulating film 143-1. It is electrically connected to the gate electrode (GE2) of the polycrystalline switching transistor. In addition, the additional signal line (ASL3; hereinafter also referred to as the additional signal line for oxide transistor) is electrically connected to the gate electrode (GE3) of the oxide switching transistor through a contact hole located in the third additional gate insulating film 143-1. The additional signal lines (ASL1, ASL3) include a low-resistance material such as aluminum (Al) or copper (Cu). The additional signal lines (ASL1, ASL3) according to one embodiment are formed of a double layer, and the lower layer is aluminum (Al). and the upper layer may be formed of titanium (Ti). Referring to FIG. 7, molybdenum (Mo) has the disadvantage of causing signal delay when driven at 240 Hz, so in FIG. 10, it is electrically connected to the gate electrode (GE2) of the polycrystalline switching transistor and the gate electrode (GE3) of the oxide switching transistor, respectively. It is connected and further includes additional signal lines (ASL1, ASL3) containing metal with low resistance characteristics, so that a scan signal with a sufficient voltage value is transmitted even when driving at high speed of 240Hz, and there is a problem of delay due to resistance. Avoid doing so.

A second interlayer insulating film 162 may be positioned on the additional conductive layer. The second interlayer insulating film 162 may have a single-layer or multi-layer structure.

A first data conductive layer including a connection member that can be connected to the first and second regions of each of the polycrystalline transistor and the oxide transistor may be positioned on the second interlayer insulating film 162.

In FIG. 10, the first data conductive layer includes a connection member (SE1) connected to the first region of the driving transistor, a connection member (DE1) connected to the second region of the driving transistor, and a connection member (DE1) connected to the gate electrode of the driving transistor. CM2), connecting members (SE2, DE2) connected to each of the first and second regions of the polycrystalline switching transistor, and connecting members (SE3, DE3) connected to each of the first and second regions of the oxide switching transistor. The connection member SE3 connected to the first region of the oxide switching transistor and the connection member DE1 connected to the second region of the driving transistor may have a structure in which they are integrally connected.

An organic layer may be located on the first data conductive layer, and an anode may be located on the organic layer. The above structure of the first data conductive layer is examined in FIG. 14.

In the above, the cross-sectional structure was examined, and the planar structure may have the same structure as that in FIG. 3.

The structure of FIG. 10 as described above can be formed by the same manufacturing method as that of FIG. 11.

In Figure 11, the semiconductor or conductor stacking steps (DEP1 to DEP7), the etching steps (ET1 to ET8), and the insulating film stacking steps (IDEP1 to IDEP5) are shown, with the steps located at lower positions being performed first. It is showing.

Specifically, according to the manufacturing method of FIG. 11, the first semiconductor (ACT1) is stacked (DEP1), the first semiconductor (ACT1) is etched (ET1), and then the first gate insulating film 141 is stacked (IDEP1). do.

After that, the first gate conductive layer (GAT1) is stacked (DEP2), the first gate conductive layer (GAT1) is etched (ET2), and the second gate insulating film 142 is stacked (IDEP2). Here, the gate electrode (GE1) of the driving transistor and the gate electrode (GE2) of the polycrystalline switching transistor included in the first gate conductive layer (GAT1) may both be formed of the same material, and may be made of a material containing molybdenum (Mo). can be formed.

After that, the second gate conductive layer (GAT2) is stacked (DEP3), the second gate conductive layer (GAT2) is etched (ET3), and the first interlayer insulating film 161 is stacked (IDEP3). Here, the second gate conductive layer (GAT2) may include various metals, and the second gate conductive layer (GAT2) according to one embodiment may be formed of a material containing molybdenum (Mo).

Afterwards, the second semiconductor (ACT2) is stacked (DEP4), the second semiconductor (ACT2) is etched (ET4), and the third gate insulating film 143 is stacked (IDEP4). After that, the third gate conductive layer (GAT3) is stacked (DEP5), the third gate conductive layer (GAT3) is etched (ET5), and an additional third gate insulating layer 143-1 is stacked (IDEP4-1). )do. Here, the third gate conductive layer (GAT3) may include various metals, and in one embodiment, may be formed as a single layer made of a material containing molybdenum (Mo).

Thereafter, the contact hole (CNT1) is located in at least some of the insulating films of the second gate insulating film 142, the first interlayer insulating film 161, the third gate insulating film 143, and the additional third gate insulating film 143-1. ) to form (ET5-1). The gate electrode GE2 of the polycrystalline switching transistor and the gate electrode GE3 of the oxide switching transistor may be exposed by the additional contact hole CNT1.

After that, an additional conductive layer (CMTL) is stacked (DEP6), the additional conductive layer (CMTL) is etched (ET6), and then the second interlayer insulating film 162 is stacked (IDEP5). Here, the additional conductive layer (CMTL) may include a low-resistance metal, and in one embodiment, may be formed as a double layer, with the lower layer being formed of aluminum (Al) and the upper layer being formed of titanium (Ti).

Afterwards, the first gate insulating film 141, the second gate insulating film 142, the first interlayer insulating film 161, the third gate insulating film 143, the additional third gate insulating film 143-1, and the second interlayer. A contact hole (CNT2) is formed (ET7) in at least one of the insulating films 162. Here, the contact hole (CNT2) can be divided into two end contact holes, and the first contact hole exposes the first semiconductor (ACT1), the first gate conductive layer (GAT1), and the second gate conductive layer (GAT2). The first contact hole may be a contact hole, and the second contact hole may be a contact hole exposing the second semiconductor ACT2, the third gate conductive layer GAT3, and the additional conductive layer CMTL. Depending on the embodiment, the first contact hole and the second contact hole may be formed in different processes.

Afterwards, the first data conductive layer is stacked (DEP7) and the first data conductive layer is etched (ET8).

The structure of the upper part of the first data conductive layer is examined in FIG. 14.

10 and 11, the gate electrode of the driving transistor T1, which is one of the polycrystalline transistors, is formed of a material containing molybdenum (Mo) to facilitate dehydrogenation, and at least one transistor among the switching transistors The gate electrode is made of a material containing molybdenum (Mo), but is electrically connected to it and forms an additional signal line (ASL1) containing a low-resistance material to prevent signal delay and lower charging rate even when driven at high speeds of 240Hz. Make sure no problems arise. In this embodiment, aluminum (Al) or copper (Cu) can be used as a low-resistance material.

Hereinafter, the embodiments of FIGS. 12 and 13 will be looked at in detail, and some of the overlapping content described in FIGS. 2 and 4 will be omitted.

FIG. 12 is a cross-sectional view of a portion of a light-emitting display device according to another embodiment, and FIG. 13 is a diagram schematically showing a method of manufacturing a light-emitting display device according to the embodiment of FIG. 12 .

12 , unlike the embodiment of FIG. 2 , an additional conductive layer is not formed, and the second gate conductive layer is formed to include a low-resistance material and an additional signal line ASL1 is formed in the second gate conductive layer. Thus, it has a structure connected to the gate electrode (GE2) of the polycrystalline switching transistor. Additionally, this may be an embodiment that uses copper (Cu) as a low-resistance material.

According to FIG. 12, the substrate 110, barrier layer 110-1, and buffer layer 111 are formed sequentially. Depending on the embodiment, the barrier layer 110-1 may be omitted. A buffer layer 111 covering the barrier layer 110-1 is located on top of the barrier layer 110-1. The buffer layer 111 may serve to block impurity elements from penetrating into the first semiconductor layer ACT1. Depending on the embodiment, a metal layer (see BML in FIG. 14) may be formed between the barrier layer 110-1 and the buffer layer 111.

A first semiconductor layer (ACT1) formed of a polycrystalline semiconductor (P-Si) is located on the buffer layer 111. In FIG. 12, the first semiconductor layer (ACT1) is shown divided into a first semiconductor (ACT1-1) of the driving transistor and a first semiconductor (ACT1-2) of the polycrystalline switching transistor. Here, the polycrystalline switching transistor may be one of the second transistor (T2), the fifth transistor (T5), the sixth transistor (T6), and the seventh transistor (T7) of FIG. 1. Each of the first semiconductor layers (ACT1) includes a channel and a first region and a second region located on both sides of the channel, and the first region and the second region have conductive layer characteristics by plasma treatment or doping, thereby forming the first region of the polycrystalline transistor. It can serve as the first electrode and the second electrode.

A first gate insulating layer 141 may be positioned on the first semiconductor layer ACT1.

A first gate conductive layer including gate electrodes (GE1 and GE2) of the polycrystalline transistor may be positioned on the first gate insulating film 141. The first gate conductive layer is shown divided into a gate electrode (GE1) of the driving transistor and a gate electrode (GE2) of the polycrystalline switching transistor.

The gate electrode GE1 of the driving transistor and the gate electrode GE2 of the polycrystalline switching transistor according to the embodiment of FIG. 1 are located on the same layer (first gate insulating film 141) and are made of the same material. That is, the gate electrode (GE1) of the driving transistor and the gate electrode (GE2) of the polycrystalline switching transistor are made of a material containing molybdenum (Mo) and may be formed as a single layer or multiple layers. In one embodiment, the gate electrode (GE1) of the driving transistor and the gate electrode (GE2) of the polycrystalline switching transistor may be formed of a single layer of molybdenum (Mo). Here, the gate electrodes (GE1, GE2) of molybdenum (Mo) have the advantage of ensuring that the characteristics of the transistor are constant by easily dehydrogenating during the process, as shown in FIG. 4. In particular, the characteristics of the driving transistor are constant. This ensures that a constant output current can be generated.

After forming the first gate conductive layer, a plasma treatment or doping process may be performed to make the exposed area of the first semiconductor layer conductive. That is, the first semiconductor layer ACT1 covered by the first gate conductive layer is not conductive, and the portion of the first semiconductor layer ACT1 not covered by the first gate conductive layer has the same characteristics as the conductive layer. You can.

A second gate insulating layer 142 may be positioned on the first gate conductive layer and the first gate insulating layer 141.

A second gate conductive layer including one electrode (CE) of the sustain capacitor (Cst) and an additional signal line (ASL1) may be positioned on the second gate insulating layer 142. One electrode (CE) of the sustain capacitor (Cst) overlaps the gate electrode (GE1) of the driving transistor to form the sustain capacitor (Cst), and an opening (CEop) overlaps a portion of the gate electrode (GE1) of the driving transistor. You can have it. The additional signal line ASL1 may be connected to the gate electrode GE2 of the polycrystalline switching transistor through a contact hole located in the second gate insulating film 142. Depending on the embodiment, the second gate conductive layer may further include a scan line, a control line, or a voltage line. The second gate conductive layer includes a low-resistance material such as aluminum (Al) or copper (Cu), and the additional signal line (ASL1) and the second gate conductive layer according to one embodiment are formed as a double layer, and the lower layer is copper ( Cu), and the upper layer may be formed of titanium (Ti). Referring to Figure 7, in the case of molybdenum (Mo), there is a disadvantage in that signal delay occurs when driven at 240 Hz, so in Figure 12, it is electrically connected to the gate electrode (GE2) of the polycrystalline switching transistor and contains a metal with low resistance characteristics. It further includes an additional signal line (ASL1) to ensure that a scan signal with a sufficient voltage value is transmitted even during high-speed driving at 240Hz and to prevent problems with delay due to resistance.

A first interlayer insulating film 161 may be positioned on the second gate conductive layer.

A second semiconductor layer (oxide semiconductor layer) including a second semiconductor (ACT2) including a channel, a first region, and a second region of the oxide transistor may be located on the first interlayer insulating film 161.

A third gate insulating layer 143 may be located on the second semiconductor layer. The third gate insulating layer 143 may be located on the entire surface of the second semiconductor layer and the first interlayer insulating layer 161.

A third gate conductive layer including the gate electrode (GE3) of the oxide transistor may be positioned on the third gate insulating film 143. The gate electrode (GE3) of the oxide transistor may overlap the channel. The third gate conductive layer may further include a scan line or a control line. The third gate conductive layer may contain a metal or metal alloy such as copper (Cu), molybdenum (Mo), aluminum (Al), or titanium (Ti), and may be composed of a single layer or multiple layers. The third gate conductive layer according to one embodiment may be formed as a single layer made of molybdenum (Mo).

After forming the third gate conductive layer, a plasma treatment or doping process may be performed to make the exposed area of the second semiconductor ACT2 conductive. That is, the second semiconductor ACT2 covered by the third gate conductive layer is not conductive, and the portion of the second semiconductor ACT2 not covered by the third gate conductive layer may have the same characteristics as the conductive layer. .

A second interlayer insulating film 162 may be positioned on the third gate conductive layer. The second interlayer insulating film 162 may have a single-layer or multi-layer structure.

A first data conductive layer including a connection member that can be connected to the first and second regions of each of the polycrystalline transistor and the oxide transistor may be positioned on the second interlayer insulating film 162.

In FIG. 12, the first data conductive layer includes a connection member (SE1) connected to the first region of the driving transistor, a connection member (DE1) connected to the second region of the driving transistor, and a connection member (DE1) connected to the gate electrode of the driving transistor. CM2), connecting members (SE2, DE2) connected to each of the first and second regions of the polycrystalline switching transistor, and connecting members (SE3, DE3) connected to each of the first and second regions of the oxide switching transistor. The connection member SE3 connected to the first region of the oxide switching transistor and the connection member DE1 connected to the second region of the driving transistor may have a structure in which they are integrally connected.

An organic layer may be located on the first data conductive layer, and an anode may be located on the organic layer. The above structure of the first data conductive layer is examined in FIG. 14.

In the above, the cross-sectional structure was examined, and the planar structure may have the same structure as that in FIG. 3.

The structure of FIG. 12 as described above can be formed by the same manufacturing method as that of FIG. 13.

In Figure 13, the semiconductor or conductor stacking steps (DEP1 to DEP6), the etching steps (ET1 to ET7), and the insulating film stacking steps (IDEP1 to IDEP5) are shown, with the lower the step being performed first. It is showing.

Specifically, according to the manufacturing method of FIG. 13, the first semiconductor (ACT1) is stacked (DEP1), the first semiconductor (ACT1) is etched (ET1), and then the first gate insulating film 141 is stacked (IDEP1). do.

After that, the first gate conductive layer (GAT1) is stacked (DEP2), the first gate conductive layer (GAT1) is etched (ET2), and the second gate insulating film 142 is stacked (IDEP2). Here, the gate electrode (GE1) of the driving transistor and the gate electrode (GE2) of the polycrystalline switching transistor included in the first gate conductive layer (GAT1) may both be formed of the same material, and may be made of a material containing molybdenum (Mo). can be formed.

Afterwards, an additional contact hole (CNT1) is formed in the second gate insulating film 142 (ET2-1). The gate electrode (GE2) of the polycrystalline switching transistor may be exposed by the additional contact hole (CNT1).

After that, the second gate conductive layer (GAT2) is stacked (DEP3), the second gate conductive layer (GAT2) is etched (ET3), and the first interlayer insulating film 161 is stacked (IDEP3). Here, the second gate conductive layer (GAT2) may include a low-resistance metal, and in one embodiment, may be formed as a double layer, with the lower layer being formed of copper (Cu) and the upper layer being formed of titanium (Ti). .

Afterwards, the second semiconductor (ACT2) is stacked (DEP4), the second semiconductor (ACT2) is etched (ET4), and the third gate insulating film 143 is stacked (IDEP4). After that, the third gate conductive layer (GAT3) is stacked (DEP5), the third gate conductive layer (GAT3) is etched (ET5), and then the second interlayer insulating film 162 is stacked (IDEP5). Here, the third gate conductive layer (GAT3) may include various metals, and in one embodiment, may be formed as a single layer made of a material containing molybdenum (Mo).

Afterwards, contact is made to at least one of the first gate insulating film 141, the second gate insulating film 142, the first interlayer insulating film 161, the third gate insulating film 143, and the second interlayer insulating film 162. A hole (CNT2) is formed (ET6). Here, the contact hole (CNT2) can be divided into two end contact holes, and the first contact hole exposes the first semiconductor (ACT1), the first gate conductive layer (GAT1), and the second gate conductive layer (GAT2). The first contact hole may be a contact hole, and the second contact hole may be a contact hole exposing the second semiconductor ACT2 and the third gate conductive layer GAT3. Depending on the embodiment, the first contact hole and the second contact hole may be formed in different processes.

Afterwards, the first data conductive layer is stacked (DEP6) and the first data conductive layer is etched (ET7).

The structure of the upper part of the first data conductive layer is examined in FIG. 14.

12 and 13, the gate electrode of the driving transistor T1, which is one of the polycrystalline transistors, is formed of a material containing molybdenum (Mo) to facilitate dehydrogenation, and at least one of the polycrystalline switching transistors The gate electrode of the transistor is made of a material containing molybdenum (Mo), but is electrically connected to it and forms an additional signal line (ASL1) containing a low-resistance material, resulting in signal delay and reduced charging rate even when driven at high speeds of 240Hz. Prevent problems from occurring. In this embodiment, aluminum (Al) or copper (Cu) can be used as a material having low resistance.

In the above, we looked at various modified embodiments. Hereinafter, the overall cross-sectional structure of the light emitting display device according to an embodiment will be examined through FIG. 14.

FIG. 14 is a diagram illustrating a cross-sectional structure of a light emitting display device according to an embodiment.

In Figure 14, only the driving transistor is formed of a polycrystalline transistor, and is shown based on the embodiment of Figure 2. However, the embodiments according to FIGS. 8, 10, 12, and other modifications may be equally applied.

A detailed look at the overall structure of the light emitting display device is as follows.

A light-emitting display device can be largely divided into a lower panel layer and an upper panel layer. The lower panel layer is where the light-emitting diodes and pixel circuitry that make up the pixel are located, and may even include an encapsulation layer 400 that covers it. Here, the pixel circuit unit includes the second organic layer 182 and the third organic layer 183, and refers to the lower part thereof, the light emitting diode is the upper part of the third organic layer 183, and the encapsulation layer 400 ) may refer to a configuration located at the bottom of. The structure located on top of the encapsulation layer 400 may correspond to the upper panel layer, and depending on the embodiment, may further include a color filter or a color conversion layer. Additionally, depending on the embodiment, the third organic layer 183 may not be included.

Referring to FIG. 14, a metal layer (BML) is located on the substrate 110.

The substrate 110 may include a material that has rigid properties and does not bend, such as glass, or may include a flexible material that can bend, such as plastic or polyimide. In the case of a flexible substrate, as shown in FIG. 14, it may have a double-layer structure of polyimide and a barrier layer formed of an inorganic insulating material thereon.

The metal layer (BML) may be formed at a position in the subsequent first semiconductor layer (ACT1) that overlaps the channel of the driving transistor on a plane, and is also called a lower shielding layer. The metal layer (BML) may include a metal or metal alloy such as copper (Cu), molybdenum (Mo), aluminum (Al), or titanium (Ti). Here, the driving transistor may refer to a transistor that generates current to be transmitted to the light emitting diode.

A buffer layer 111 covering the substrate 110 and the metal layer (BML) is located on the substrate 110. The buffer layer 111 serves to block impurity elements from penetrating into the first semiconductor layer ACT1, and may be an inorganic insulating film containing silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiONx).

A first semiconductor layer (ACT1) formed of a silicon semiconductor (for example, a polycrystalline semiconductor (P-Si)) is located on the buffer layer 111. The first semiconductor layer (ACT1) is a channel of a polycrystalline transistor including a driving transistor and It includes a first region and a second region located on both sides. Here, the polycrystalline transistor may include not only a driving transistor but also a plurality of polycrystalline switching transistors. In addition, plasma is formed on both sides of the channel of the first semiconductor layer (ACT1). By processing or doping, the region has conductive layer properties and can function as the first and second electrodes of a transistor.

A first gate insulating layer 141 may be positioned on the first semiconductor layer ACT1. The first gate insulating layer 141 may be an inorganic insulating layer containing silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiONx).

A first gate conductive layer including the gate electrode (GE1) of the polycrystalline transistor may be positioned on the first gate insulating layer 141. In addition to the gate electrode (GE1) of the polycrystalline transistor, the first gate conductive layer may be formed with a scan line or an emission control line. Here, the first gate conductive layer may be formed of a material containing molybdenum (Mo), and depending on the embodiment, may be formed of a single layer formed of a material containing molybdenum (Mo).

After forming the first gate conductive layer, a plasma treatment or doping process may be performed to make the exposed area of the first semiconductor layer conductive. That is, the first semiconductor layer ACT1 covered by the first gate conductive layer is not conductive, and the portion of the first semiconductor layer ACT1 not covered by the first gate conductive layer has the same characteristics as the conductive layer. You can.

A second gate insulating layer 142 may be positioned on the first gate conductive layer and the first gate insulating layer 141. The second gate insulating film 142 may be an inorganic insulating film containing silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiONx).

A second gate conductive layer including one electrode (CE) of the sustain capacitor (Cst) may be positioned on the second gate insulating film 142. One electrode (CE) of the sustain capacitor (Cst) overlaps the gate electrode (GE1) of the driving transistor to form the sustain capacitor (Cst).

Depending on the embodiment, the second gate conductive layer may further include a lower shielding layer (BML-1) of the oxide transistor. When an additional conductive layer (CMTL) is formed as in the embodiment of FIGS. 8 and 9, the lower shielding layer (BML-1) of the oxide transistor may be formed of the additional conductive layer (CMTL). The lower shielding layer (BML-1) of the oxide transistor is located below the channel of each oxide transistor and may serve to shield from light or electromagnetic interference provided to the channel from below.

Depending on the embodiment, the second gate conductive layer (GAT2) may further include a scan line, a control line, or a voltage line. The second gate conductive layer (GAT2) may include a metal or metal alloy such as copper (Cu), molybdenum (Mo), aluminum (Al), or titanium (Ti), and may be composed of a single layer or multiple layers. .

A first interlayer insulating layer 161 may be positioned on the second gate conductive layer (GAT2). The first interlayer insulating film 161 may include an inorganic insulating film containing silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiONx). Depending on the embodiment, the inorganic insulating material may be formed thickly. .

A second semiconductor layer (oxide semiconductor layer) including a second semiconductor (ACT2) including a channel, a first region, and a second region of the oxide transistor may be located on the first interlayer insulating film 161.

A third gate insulating layer 143 may be located on the second semiconductor layer. The third gate insulating layer 143 may be located on the entire surface of the second semiconductor layer and the first interlayer insulating layer 161. The third gate insulating layer 143 may include an inorganic insulating layer containing silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiONx).

A third gate conductive layer including the gate electrode (GE3) of the oxide transistor may be positioned on the third gate insulating film 143. The gate electrode (GE3) of the oxide transistor may overlap the channel. The third gate conductive layer may further include a scan line or a control line. The third gate conductive layer may contain a metal or metal alloy such as copper (Cu), molybdenum (Mo), aluminum (Al), or titanium (Ti), and may be composed of a single layer or multiple layers. Depending on the embodiment, the third gate conductive layer may be formed as a single layer made of a material containing molybdenum (Mo).

A second interlayer insulating film 162 may be positioned on the third gate conductive layer. The second interlayer insulating film 162 may have a single-layer or multi-layer structure. The second interlayer insulating film 162 may include an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), or silicon nitride (SiOxNy), and may include an organic material depending on the embodiment.

A first data conductive layer including a connection member that can be connected to the first and second regions of each of the polycrystalline transistor and the oxide transistor may be positioned on the second interlayer insulating film 162. The first data conductive layer may include a metal or metal alloy such as aluminum (Al), copper (Cu), molybdenum (Mo), titanium (Ti), and may be composed of a single layer or multiple layers.

A first organic layer 181 may be positioned on the first data conductive layer. The first organic layer 181 may be an organic insulating layer containing an organic material, and the organic material includes one or more materials selected from the group consisting of polyimide, polyamide, acrylic resin, benzocyclobutene, and phenol resin. can do.

A second data conductive layer including an anode connection member (ACM2) may be positioned on the first organic layer 181. The second data conductive layer may include a data line or a driving voltage line. The second data conductive layer may include a metal or metal alloy such as aluminum (Al), copper (Cu), molybdenum (Mo), or titanium (Ti), and may be composed of a single layer or multiple layers. The anode connection member ACM2 is connected to the first data conductive layer through the opening OP3 located in the first organic layer 181.

A second organic layer 182 and a third organic layer 183 are located on the second data conductive layer, and an anode connection opening OP4 is provided in the second organic layer 182 and the third organic layer 183. It is formed. The anode connection member (ACM2) is electrically connected to the anode (Anode) through the anode connection opening (OP4). The second organic layer 182 and the third organic layer 183 may be organic insulating layers and may include one or more materials selected from the group consisting of polyimide, polyamide, acrylic resin, benzocyclobutene, and phenol resin. You can. Depending on the embodiment, the third organic layer 183 may be omitted.

A pixel defining film 380 may be positioned on the anode and has an opening OP exposing the anode and covers at least a portion of the anode. The pixel defining layer 380 may be a black pixel defining layer formed of a black organic material to prevent light applied from the outside from being reflected back to the outside. Depending on the embodiment, the pixel defining layer 380 may be formed of a transparent organic material.

A spacer 385 is located on the pixel defining layer 380. The spacer 385 may be formed of a transparent organic insulating material. Depending on the embodiment, the spacer 385 may be formed of a positive type transparent organic material. The spacer 385 may include two parts 385-1 and 385-2 of different heights, with the high part 385-1 serving as a spacer and the low height part 385-2 ) can improve the adhesion characteristics between the spacer and the pixel defining layer 380.

A functional layer (FL) and a cathode are sequentially formed on the anode, spacer 385, and pixel defining layer 380, and the functional layer (FL) and cathode are formed over the entire area. can be located The light emitting layer (EML) is located between the functional layers (FL), and the light emitting layer (EML) may be located only within the opening (OP) of the pixel defining layer 380. Hereinafter, the functional layer (FL) and the light emitting layer (EML) can be combined to refer to the intermediate layer. The functional layer (FL) may include at least one of auxiliary layers such as an electron injection layer, an electron transport layer, a hole transport layer, and a hole injection layer, and the hole injection layer and the hole transport layer may be located below the light emitting layer (EML). layer is located, and an electron transport layer and an electron injection layer may be located on top of the light emitting layer (EML).

An encapsulation layer 400 is located on the cathode. The encapsulation layer 400 includes at least one inorganic layer and at least one organic layer, and may have a triple-layer structure including a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer. The encapsulation layer 400 may be used to protect the light emitting layer (EML) from moisture or oxygen that may enter from the outside. Depending on the embodiment, the encapsulation layer 400 may include a structure in which an inorganic layer and an organic layer are further sequentially stacked.

Sensing insulating layers 501, 510, 511 and a plurality of sensing electrodes 540, 541 are positioned on the encapsulation layer 400 for touch detection. In the embodiment of FIG. 14, touch can be sensed in a capacitive manner using two sensing electrodes 540 and 541.

Specifically, a first sensing insulating layer 501 is formed on the encapsulation layer 400, and a plurality of sensing electrodes 540 and 541 are formed thereon. The plurality of sensing electrodes 540 and 541 may be insulated with the second sensing insulating layer 510 interposed therebetween, and some of them may be electrically connected through an opening located in the sensing insulating layer 510. Here, the sensing electrodes 540 and 541 are made of metal or metal alloy such as aluminum (Al), copper (Cu), silver (Ag), gold (Au), molybdenum (Mo), titanium (Ti), and tantalum (Ta). It may include a single layer or multiple layers. A third sensing insulating layer 511 is formed on the sensing electrode 540.

Although no configuration is shown on the third sensing insulating layer 511 in FIG. 14, a film including a polarizer is attached to reduce reflection of external light, or a color filter or color conversion layer is added to improve color quality. can be formed. A light blocking member may be positioned between the color filter or the color conversion layer. In addition, depending on the embodiment, a layer formed with a material capable of absorbing light of some wavelengths of external light (hereinafter referred to as a reflection adjustment material) may be further included. Additionally, depending on the embodiment, the front surface of the light emitting display device may be flattened by covering it with an additional organic layer (also called a planarization layer).

In Figure 14, a total of three organic layers 181, 182, and 183 are formed, and an embodiment in which an anode connection opening is formed in the second organic layer and the third organic layer is examined. However, at least two organic layers may be formed, and in this case, the anode connection opening may be located in the upper organic layer located away from the substrate, and the lower organic layer opening may be located in the lower organic layer.

The structure of FIG. 14 as described above corresponds to the embodiment of FIGS. 2 and 3, but can be applied in the same manner to the modified embodiment of FIGS. 8 to 13, except for modified portions.

Although the embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements made by those skilled in the art using the basic concept of the present invention defined in the following claims are also possible. It falls within the scope of rights.

T1, T2, T3, T4, T5, T6, T7: Transistors
LED: Light emitting diode ACT1: First semiconductor
ACT1-1: First semiconductor for driving transistor
ACT1-2: First semiconductor for polycrystalline switching transistor
ACT2: Second semiconductor CE: One electrode of sustaining capacitor
GE1, GE2: Gate electrode of polycrystalline transistor
GE3: Gate electrode of transistor CNT1, CNT2: Contact hole
GAT1: first gate conductive layer GAT1_1: first gate conductive layer
GAT1_2: 1-2 gate conductive layer GAT2: 2nd gate conductive layer
GAT3: Third gate conductive layer CMTL: Additional conductive layer
CM1, CM2, SE1, SE2, SE3, DE1, DE2, DE3: Connection members
110: Substrate 110-1: Barrier layer
111: buffer layer 141: first gate insulating film
142: second gate insulating film 142-1: additional second gate insulating film
143: third gate insulating film 161: first interlayer insulating film
162: second interlayer insulating film 181, 182, 183: organic film
380: Pixel definition film 385: Spacer
400: Encapsulation layer 501, 510, 511: Sensing insulating layer
540, 541: Sensing electrode ACM2: Anode connection member
BML: metal layer BML-1: lower shielding layer
EML: Emissive layer FL: Functional layer
143-1: Additional third gate insulating film ASL1, ASL3: Additional signal line
ASL2: Absence of additional connection

Claims (20)

Board;
A first semiconductor layer including a first semiconductor for a driving transistor and a first semiconductor for a polycrystalline switching transistor;
A first gate conductive layer including a gate electrode of the driving transistor overlapping at least a portion of the first semiconductor for the driving transistor and a gate electrode of the polycrystalline switching transistor overlapping at least a portion of the first semiconductor for the polycrystalline switching transistor;
a second gate conductive layer overlapping at least a portion of the gate electrode of the driving transistor and including one electrode of a sustain capacitor having an opening;
a second semiconductor layer including a second semiconductor for an oxide switching transistor;
a third gate conductive layer including a gate electrode of the oxide switching transistor overlapping at least a portion of the second semiconductor for the oxide switching transistor; and
It includes an additional signal line electrically connected to the gate electrode of the polycrystalline switching transistor,
The first gate conductive layer is formed of a material containing molybdenum,
A light emitting display device wherein the additional signal line includes a low-resistance material. In paragraph 1:
The additional signal line is formed of a double layer, wherein the lower layer includes aluminum and the upper layer includes titanium. In paragraph 2,
The second gate conductive layer is a light emitting display device formed of a material containing molybdenum. In paragraph 3,
A light emitting display device wherein the gate electrode of the oxide switching transistor is formed of a material containing molybdenum. In paragraph 2,
a first gate insulating layer covering the first semiconductor layer;
a second gate insulating film covering the gate electrode of the polycrystalline switching transistor; and
Further comprising an additional second gate insulating film covering the one electrode of the sustain capacitor,
The additional signal line is electrically connected to the gate electrode of the polycrystalline switching transistor through the second gate insulating layer and an additional contact hole located in the additional second gate insulating layer. In paragraph 5,
a first interlayer insulating film covering the additional signal line;
a third gate insulating layer covering the second semiconductor layer; and
The light emitting display device further includes a second interlayer insulating film covering the third gate conductive layer. In paragraph 6:
The light emitting display device further includes a connecting member located on the second interlayer insulating layer and connecting the first semiconductor for the driving transistor and the second semiconductor for the oxide switching transistor. In paragraph 7:
The light emitting display device further includes a connection member located on the second interlayer insulating layer and electrically connected to the gate electrode of the driving transistor. In paragraph 8:
It further includes an additional connection member formed of the same material on the same layer as the additional signal line,
A light emitting display device wherein a connection member electrically connected to the gate electrode of the driving transistor is electrically connected to the gate electrode of the driving transistor through the additional connection member. In paragraph 2,
The additional signal line is located on a layer higher than the third gate conductive layer. In paragraph 10:
a first gate insulating layer covering the first semiconductor layer;
a second gate insulating film covering the gate electrode of the polycrystalline switching transistor;
a first interlayer insulating film covering the second gate conductive layer;
a third gate insulating layer covering the second semiconductor layer; and
It further includes an additional third gate insulating layer covering the third gate conductive layer,
The additional signal line is located on the third additional gate insulating layer. In paragraph 11:
The additional signal line is electrically connected to the gate electrode of the polycrystalline switching transistor through the second gate insulating film, the first interlayer insulating film, the third gate insulating film, and an additional contact hole formed in the additional third gate insulating film. A light emitting display device. In paragraph 12:
It further includes an additional signal line for an oxide transistor made of the same material as the additional signal line and formed in the same layer,
A light emitting display device wherein the additional signal line for the oxide transistor is electrically connected to the gate electrode of the oxide switching transistor. In paragraph 13:
A light emitting display device in which the additional signal line for the oxide transistor is electrically connected to the gate electrode of the oxide switching transistor through an additional contact hole formed in the third additional gate insulating film. Board;
A first semiconductor layer including a first semiconductor for a driving transistor and a first semiconductor for a polycrystalline switching transistor;
A first gate conductive layer including a gate electrode of the driving transistor overlapping at least a portion of the first semiconductor for the driving transistor and a gate electrode of the polycrystalline switching transistor overlapping at least a portion of the first semiconductor for the polycrystalline switching transistor;
a second gate conductive layer overlapping at least a portion of the gate electrode of the driving transistor and including an additional signal line electrically connected to one electrode of a sustain capacitor having an opening and the gate electrode of the polycrystalline switching transistor;
a second semiconductor layer including a second semiconductor for an oxide switching transistor; and
A third gate conductive layer including a gate electrode of the oxide switching transistor overlapping at least a portion of the second semiconductor for the oxide switching transistor,
The first gate conductive layer is formed of a material containing molybdenum,
The second gate conductive layer includes a low-resistance material. In paragraph 15:
The light emitting display device includes the one electrode of the sustain capacitor included in the second gate conductive layer and the additional signal line, wherein the lower layer includes copper and the upper layer includes titanium. In paragraph 16:
A light emitting display device wherein the gate electrode of the oxide switching transistor is formed of a material containing molybdenum. In paragraph 15:
a first gate insulating layer covering the first semiconductor layer; and
It further includes a second gate insulating film covering the gate electrode of the polycrystalline switching transistor,
The light emitting display device wherein the additional signal line is electrically connected to the gate electrode of the polycrystalline switching transistor through an additional contact hole located in the second gate insulating film. In paragraph 15:
The light emitting display device further includes a connection member connecting the first semiconductor for the driving transistor and the second semiconductor for the oxide switching transistor. In paragraph 19:
A light emitting display device further comprising a connection member electrically connected to the gate electrode of the driving transistor.

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