KR20240038544A - Preamble detection circuit, operation method thereof, and memory device - Google Patents

Abstract

A preamble detection circuit, method of operation thereof, and memory device are disclosed. A preamble detection circuit according to the technical idea of the present disclosure includes a comparison circuit configured to compare the level of a data strobe signal and the level of a reference voltage and output a comparison signal, and a comparison circuit configured to output a comparison signal based on the comparison signal, and a preamble period corresponding to the data strobe signal based on the comparison signal. and a reset signal generating circuit configured to output a reset signal having a pulse width.

Description

Preamble detection circuit, method of operation thereof, and memory device {PREAMBLE DETECTION CIRCUIT, OPERATION METHOD THEREOF, AND MEMORY DEVICE}

The technical idea of the present disclosure relates to electronic devices, and more specifically, to a preamble detection circuit, a method of operating the same, and a memory device.

Semiconductor memories are widely used to store data in various electronic devices such as computers, wireless communication devices, cameras, digital displays, etc. Data is stored by programming various states of the semiconductor memory. To access stored data, at least one stored state of the semiconductor memory can be read or sensed. To store data, the device's components can record or program the state of a semiconductor memory.

Various types of semiconductor memories exist. Volatile memory such as DRAM can lose its stored state when disconnected from an external power source. Additionally, the state of the semiconductor memory may deteriorate over time, causing unrecoverable memory errors or other problems.

The technical idea of the present disclosure is to prevent malfunctions in reset and initialization of the interface, reduce variation in command delay and data strobe signal delay, and improve signal integrity (SI) and power integrity (PI) of the device. A preamble detection circuit for improvement, a method of operating the same, and a memory device are provided.

A preamble detection circuit according to the technical idea of the present disclosure includes a comparison circuit configured to compare the level of a data strobe signal and the level of a reference voltage and output a comparison signal; and a reset signal generating circuit configured to output a reset signal having a pulse width corresponding to a preamble period of the data strobe signal based on the comparison signal.

In addition, a method of operating a preamble detection circuit according to the technical idea of the present disclosure includes generating a comparison signal indicating the result of comparison between the level of the data strobe signal and the level of the reference voltage; and generating, based on the comparison signal, a reset signal having a pulse width corresponding to the preamble period of the data strobe signal.

In addition, a memory device according to the technical idea of the present disclosure includes a data strobe buffer configured to buffer a data strobe signal provided from the outside; and a preamble detection circuit configured to output a reset signal having a pulse width corresponding to a preamble period of the data strobe signal, based on the data strobe signal and the reference voltage.

According to the technical idea of the present disclosure, there is an effect of reducing the variation of the delay of the command and the delay of the data strobe signal due to PSIJ (Power Supply noise Induced Jitter)/PVT (Process, Voltage and Temperature).

In addition, according to the technical idea of the present disclosure, by preventing the occurrence of tDQSS, there is an effect of preventing malfunctions in reset and initialization of the interface.

In addition, according to the technical idea of the present disclosure, there is an effect of improving SI (Signal Integrity) and PI (Power Integrity) of the device.

The effects that can be obtained from the embodiments of the present disclosure are not limited to the effects mentioned above, and other effects not mentioned can be explained to those skilled in the art from the following description. Can be clearly derived and understood. That is, unintended effects resulting from implementing the embodiments of the present disclosure may also be derived by a person skilled in the art from the embodiments of the present disclosure.

1 is a diagram for explaining a memory system according to example embodiments of the present disclosure.
FIG. 2 is a diagram for explaining an interface circuit according to example embodiments of the present disclosure.
3 to 6 are diagrams for explaining a preamble detection circuit according to example embodiments of the present disclosure.
FIG. 7 is a graph illustrating a data strobe signal and an inverted data strobe signal for generating a reset signal according to example embodiments of the present disclosure.
FIG. 8 is a flowchart illustrating a method of operating a preamble detection circuit according to example embodiments of the present disclosure.
FIG. 9 is a flowchart for explaining the operation method of the preamble detection circuit shown in FIG. 3.
FIG. 10 is a flowchart for explaining the operation method of the preamble detection circuit shown in FIG. 4.
FIG. 11 is a flowchart for explaining the operation method of the preamble detection circuit shown in FIG. 5.
12 is a diagram illustrating an electronic system according to example embodiments of the present disclosure.
FIG. 13 is a diagram for explaining a computing system according to example embodiments of the present disclosure.

Hereinafter, embodiments of the present disclosure will be described in detail with reference to the attached drawings.

1 is a diagram for explaining a memory system according to example embodiments of the present disclosure.

Referring to FIG. 1, the memory system 100 is an integrated circuit, an electronic device or system, a smart phone, a tablet PC, a computer, a server, a work station, a portable communication terminal, a Personal Digital Assistant (PDA), or a Portable Multimedia Player (PMP). , and other suitable computers, etc. may refer to a computing device, a virtual machine, or a virtual computing device thereof. Alternatively, the memory system 100 may be some of the components included in a computing system, such as a graphics card. Depending on the embodiment, the memory system 100 is divided into Unbuffered Dual In-line Memory Module (UDIMM), Registered DIMM (RDIMM), Load Reduced DIMM (LRDIMM), Fully Buffered DIMM (FBDIMM), Small Outline DIMM (SODIMM), etc. It can be implemented.

The memory system 100 may include a memory controller 110 and a memory device 120.

The memory controller 110 may be provided to initialize and/or control the operation characteristics of the memory device 120. In order for the memory controller 110 to interact normally with the memory device 120, various algorithms that configure the memory controller 110 may be included in the memory controller 110. For example, codes representing the frequency, timing, driving, detailed operating parameters, etc. of the memory device 120 may be set. Memory training of the memory device 120 may be performed according to these codes.

The memory controller 110 may be communicatively connected to the memory device 120 through a memory bus. A clock signal (CLK), a command/address signal (CA), data (DQ), and a data strobe signal (DQS) may be provided through one signal line between the memory controller 110 and the memory device 120. . Signal lines between the memory controller 110 and the memory device 120 may be connected through connectors. Connectors may be implemented as pins, balls, signal lines, or other hardware components.

The clock signal CLK may be transmitted from the memory controller 110 to the memory device 120 through a clock signal line of the memory bus.

The command/address signal (CA) may be transmitted from the memory controller 110 to the memory device 120 through the command/address signal line of the memory bus.

Data (DQ) and data strobe signal (DQS) are transmitted from the memory controller 110 to the memory device 120 or through the data bus and data strobe signal line of the memory bus composed of bidirectional signal lines. ) can be transmitted from the memory controller 110. The data strobe signal (DQS) can be used to sample data (DQ).

Although not shown, a chip select signal may be provided between the memory controller 110 and the memory device 120. The chip select signal may be transmitted from the memory controller 110 to the memory device 120 through a chip select line of the memory bus. The chip select signal activated at logic high may indicate that the command/address signal (CA) transmitted through the command/address signal line is a command.

The memory device 120 may write or read data DQ under the control of the memory controller 110.

The memory device 120 may include an interface circuit 121, a reference voltage generator 122, a memory cell array 123, and a control logic circuit 224.

The interface circuit 121 may receive a data strobe signal (DQS) and data (DQ) from the memory controller 110. Alternatively, the interface circuit 121 may transmit the data strobe signal (DQS) and data (DQ) to the memory controller 110.

In some embodiments, the interface circuit 121 may output a reset signal to detect a preamble period of the data strobe signal (DQS) based on the data strobe signal (DQS) and the reference voltage.

The reference voltage generator 122 may generate a reference voltage. The reference voltage generator 122 may provide a reference voltage to the interface circuit 121.

The memory cell array 123 may include a plurality of word lines, a plurality of bit lines, and a plurality of memory cells. A plurality of memory cells may be formed at points where word lines and bit lines intersect. Each memory cell may be a volatile memory cell (eg, Dynamic Random Access Memory (DRAM) cell, Static RAM (SRAM) cell, etc.). However, it is not limited to this.

The control logic circuit 124 may receive the clock signal CLK through a clock signal line of the memory bus and control the operation timing of the memory device 120. The operation timing of the memory device 120 may be provided based on a signal provided to the memory device 120, for example, a strobe signal, in addition to the clock signal CLK. The control logic circuit 220 may receive a command/address (CA) received through a command/address signal line, and generate control signals to perform various memory operations within the memory device 120 in response to the command. there is.

According to the above, there is an effect of reducing the variation of the delay of the command and the delay of the data strobe signal due to PSIJ (Power Supply noise Induced Jitter)/PVT (Process, Voltage and Temperature).

According to the above, by preventing the occurrence of tDQSS (e.g. "Write Command to first DQS transition time", i.e., the delay time corresponding to the rising edge of the clock where the write command is input to the first rising edge of the data strobe signal), It has the effect of preventing malfunctions in interface reset and initialization.

According to the above, there is an effect of improving the reset variation of the divider and equalizer included in the interface.

According to the above, there is an effect of strengthening the competitiveness of the device by strengthening durability according to changes in the PVT of the device.

According to the above, there is an effect of improving SI (Signal Integrity) and PI (Power Integrity) of the device.

FIG. 2 is a diagram for explaining an interface circuit according to example embodiments of the present disclosure.

Referring to FIG. 2, the interface circuit 200 may be included in the interface circuit 121 shown in FIG. 1.

The interface circuit 200 may include a data strobe buffer 210, a data strobe detector 220, a decision feedback equalization (DFE) 230, and a data strobe divider 240.

The data strobe buffer 210 may buffer a data strobe signal (DQS) provided from the outside. The data strobe buffer 210 may include a DFE 230 and a data strobe divider 240 to store the buffered data strobe signal DQS.

The data strobe detector 220 may output a reset signal (RST) based on the data strobe signal (DQS) and the reference voltage (VREF). The reset signal (RST) may have a pulse width corresponding to the preamble period of the data strobe signal (DQS). The signal level corresponding to the pulse width may be, for example, a logic high level. However, it is not limited to this. The reset signal (RST) may be provided to each of the DFE 230 and the data strobe divider 240.

Since the data strobe detector 220 outputs a reset signal to detect the preamble period, the data strobe detector 220 may be referred to as a preamble detection circuit.

The DFE 230 is a non-linear equalizer that can cancel or reduce the ISI for currently sampled data (DQ) using previously sampled data (DQ). The DFE 230 may be reset in response to a pulse of the reset signal RST. That is, the DFE 230 can be initialized in the preamble period of the data strobe signal (DQS). After the preamble period, the DFE 230 may output restored data CDQ based on the data DQ and the data strobe signal DQS. In other words, the DFE 230 can restore a distorted signal to its original shape. DFE 230 may be referred to as an equalizer.

The data strobe divider 240 may be reset in response to a pulse of the reset signal (RST). That is, the data strobe divider 240 can be initialized in the preamble period of the data strobe signal DQS. After the preamble period, the data strobe divider 240 may divide the buffered data strobe signal (DQS). Additionally, the data strobe divider 240 may output a divided data strobe signal (DDQS). The data strobe divider 240 may be referred to as a divider.

3 to 6 are diagrams for explaining a preamble detection circuit according to example embodiments of the present disclosure.

Referring to Figures 3 to 6, each of the preamble detection circuits 300, 400, 500, and 600 shown in Figures 3 to 6 may be included in the interface circuit 200 shown in Figure 2. Each of the preamble detection circuits 300, 400, 500, and 600 shown in FIGS. 3 to 6 may correspond to the data strobe detector 220 shown in FIG. 2.

Referring to FIG. 3, the preamble detection circuit 300 may include a comparison circuit 310 and a reset signal generation circuit 320.

The comparison circuit 310 may compare the level of the data strobe signal DQS and the level of the reference voltage VREF and output a comparison signal (eg, COMPS 1 and/or COMPS 2).

In some embodiments, the comparison circuit 310 may include a first comparator 311 and a second comparator 313.

The first comparator 311 may receive a data strobe signal (DQS) and a reference voltage (VREF), and output a first comparison signal (COMPS 1). The first comparison signal COMPS 1 may be a signal representing a comparison result between the data strobe signal DQS and the reference voltage VREF. The first comparison signal COMPS 1 may be transmitted to the reset signal generation circuit 320.

When the level of the data strobe signal DQS is lower than the level of the reference voltage VREF, the first comparison signal COMPS 1 may have a first logic level (eg, a logic high level). Meanwhile, when the level of the data strobe signal (DQS) is higher than the level of the reference voltage (VREF), the first comparison signal (COMPS 1) has a second logic level (e.g., logic low level) lower than the first logic level. You can. However, it is not limited to this.

The second comparator 313 may receive the inverted data strobe signal (DQSB) and the reference voltage (VREF), and output a second comparison signal (COMPS 2). The inverted data strobe signal (DQSB) may be an inverted signal of the data strobe signal (DQS). The second comparison signal COMPS 2 may be a signal representing the result of comparison between the inverted data strobe signal DQSB and the reference voltage VREF. The second comparison signal COMPS 2 may be transmitted to the reset signal generation circuit 320.

The level of the inverted data strobe signal (DQSB) may be higher than the level of the reference voltage (VREF). In this case, the second comparison signal COMPS 2 may have a second logic level (eg, logic low level) that is lower than the first logic level.

In some embodiments, the first comparator 311 and the second comparator 313 may be configured and implemented as a buffer (“BUF” shown in FIG. 3).

The reset signal generation circuit 320 may output a reset signal RST based on a comparison signal (eg, COMPS 1 and/or COMPS 2). The reset signal (RST) may have a pulse width corresponding to the preamble period of the data strobe signal (DQS).

In some embodiments, the reset signal generation circuit 320 may include an OR operation gate. The OR operation gate may calculate the OR between the logic level of the first comparison signal (COMPS 1) and the logic level of the second comparison signal (COMPS 2) and output the calculation result as a reset signal (RST). Since the second comparison signal (COMPS 2) may have a second logic level (e.g., logic low level), the operation result output as the reset signal (RST) may correspond to the logic level of the first comparison signal (COMPS 1). You can. That is, the logic level of the reset signal (RST) may follow the logic level of the first comparison signal (COMPS 1).

Referring to FIG. 4 , the preamble detection circuit 400 may include a comparison circuit 410 and a reset signal generation circuit 420.

In some embodiments, the comparison circuit 410 may include a first comparator 411, a first amplifier 412, a second comparator 413, and a second amplifier 414.

The first comparator 411 may receive a data strobe signal (DQS) and a reference voltage (VREF) and output a first comparison signal (COMPS 1) to the first amplifier 412. The first comparator 411 may be the same as the first comparator 311 shown in FIG. 3.

The first amplifier 412 may amplify the first comparison signal (COMPS 1) output from the first comparator 411. Additionally, the first amplifier 412 may output the amplified first comparison signal (COMPS 1'). The amplified first comparison signal COMPS 1' may be provided to the reset signal generation circuit 420.

The second comparator 413 may receive an inverted data strobe signal (DQSB) and a reference voltage (VREF) and output a second comparison signal (COMPS 2) to the second amplifier 414. The second comparator 413 may be the same as the first comparator 313 shown in FIG. 3.

The second amplifier 414 may amplify the second comparison signal (COMPS 2) output from the second comparator 413. Additionally, the second amplifier 414 may output the amplified second comparison signal COMPS 2′. The amplified second comparison signal COMPS 2' may be provided to the reset signal generation circuit 420.

In some embodiments, first amplifier 412 and second amplifier 414 may be implemented with transistors, such as CML2CMOS. However, it is not limited to this.

The reset signal generation circuit 420 may be similar to the reset signal generation circuit 320 shown in FIG. 3 . In some embodiments, the reset signal generation circuit 420 may include an OR operation gate. The OR operation gate shown in FIG. 4 can calculate the OR between the logic level of the amplified first comparison signal (COMPS 1') and the logic level of the amplified second comparison signal (COMPS 2'). Additionally, the reset signal generation circuit 420 may output the operation result as a reset signal (RST).

Referring to FIG. 5 , the preamble detection circuit 500 may include a comparison circuit 510 and a reset signal generation circuit 520.

In some embodiments, the comparison circuit 510 is a comparator that compares the level of the data strobe signal DQS and the level of the reference voltage VREF and outputs the comparison signal COMPS to the reset signal generation circuit 520. can do. For example, the comparison circuit 510 may be comprised of the first comparator 311 shown in FIG. 3 .

When the level of the data strobe signal (DQS) is lower than the level of the reference voltage (VREF), the comparison signal (COMPS) may have a first logic level. Meanwhile, the level of the data strobe signal (DQS) is lower than the level of the reference voltage (VREF). When the level is higher than , the comparison signal COMPS may have a second logic level lower than the first logic level.

In some embodiments, the reset signal generation circuit 520 may sample the logic level of the comparison signal COMPS in response to the clock signal CLK input from the outside. The clock signal CLK input from the outside may be the clock signal CK shown in FIG. 1. The reset signal generation circuit 520 may sample the logic level of the comparison signal COMPS at an edge (eg, rising edge and/or falling edge) of the clock signal CLK. The reset signal generation circuit 520 may output the sampling result as a reset signal (RST). The sampling result output as the reset signal (RST) may correspond to the logic level of the comparison signal (COMPS). That is, the logic level of the reset signal (RST) may follow the logic level of the comparison signal (COMPS).

Referring to FIG. 6 , the preamble detection circuit 600 may include a resistor (R), a capacitor (C), an operation amplifier 610, and an amplifier 620.

The data strobe signal DQS may flow to the first node N1 through the resistor R.

The operation amplifier 610 may be connected to a node connected to the ground (GND), a first node (N1) to which the data strobe signal (DQS) is applied, and a second node (N2) to which an output signal is applied. The operation amplifier 610 may receive a signal and a ground (GND) applied to the first node (N1) and apply an output signal to the second node (N2).

The capacitor C may be connected between the first node N1 and the second node N2.

The amplifier 620 may be connected to the node to which the reference voltage VREF is applied, the second node N2, and the node to which the reset signal RST is applied. The amplifier 620 may receive the signal applied to the second node N2 and the reference voltage VREF and output a reset signal RST.

FIG. 7 is a graph illustrating a data strobe signal and an inverted data strobe signal for generating a reset signal according to example embodiments of the present disclosure.

Referring to FIG. 7, after the first time t1, the level of the data strobe signal DQS may decrease. At this time, the inverted data strobe signal (DQSB) may ripple. The level of the data strobe signal (DQS) may be higher than the level of the reference voltage (VREF). At this time, the logic level of the reset signal RST may be a second logic level (eg, logic low level) lower than the first logic level (eg, logic high level).

At the second time t2, the level of the data strobe signal DQS may be lower than the level of the reference voltage VREF. At this time, the logic level of the comparison signal (eg, COMP shown in FIG. 5) may be the first logic level (eg, logic high level). And, the reset signal (RST) may rise. That is, when the level of the data strobe signal DQS is lower than the level of the reference voltage VREF, a rising edge RE may occur in the reset signal RST. From the time the rising edge (RE) of the reset signal (RST) occurs, the preamble period (PREA) of the data strobe signal (DQS) may begin.

After the second time t2, the level of the data strobe signal DQS may further decrease and then increase again. From the second time t2 to the third time t3, since the level of the data strobe signal DQS is lower than the level of the reference voltage VREF, the logic level of the reset signal RST maintains the second logic level. You can.

At the third time t3, the level of the data strobe signal DQS may be higher than the level of the reference voltage VREF. At this time, the logic level of the comparison signal (eg, COMP shown in FIG. 5) may be the second logic level. And, the reset signal (RST) may fall. That is, when the level of the data strobe signal DQS is higher than the level of the reference voltage VREF, the falling edge FE of the reset signal RST may occur. From the time the falling edge (FE) of the reset signal (RST) occurs, the preamble period (PREA) of the data strobe signal (DQS) may end.

The preamble period (PREA) of the data strobe signal (DQS) may be a period corresponding to the occurrence of the rising edge (RE) of the reset signal (RST) until the falling edge (FE) of the reset signal (RST) occurs. there is.

Referring to FIGS. 2 and 7 , when the rising edge (RE) of the reset signal (RST) occurs, the DFE 230 and the data strobe divider 240 may be reset or initialized. During the preamble period (PREA) of the data strobe signal (DQS), the DFE 230 and the data strobe divider 240 may have preset initial settings. When the falling edge FE of the reset signal RST occurs, the DFE 230 and the data strobe divider 240 may perform normal operation.

After the third time t3, the data strobe signal DQS and the inverted data strobe signal DQSB may be toggled.

At the fourth time t4 after the third time t3, the level of the data strobe signal DQS may decrease to lower than the level of the reference voltage VREF. At this time, a rising edge (RE) may occur in the reset signal (RST).

At the fifth time t5 after the fourth time t4, the level of the data strobe signal DQS may increase and become higher than the level of the reference voltage VREF. At this time, a falling edge (FE) may occur in the reset signal (RST).

After the fifth time t5, the data strobe signal DQS and the inverted data strobe signal DQSB may be toggled.

FIG. 8 is a flowchart illustrating a method of operating a preamble detection circuit according to example embodiments of the present disclosure.

Referring to FIG. 8, in step S810, a step of generating a comparison signal representing a comparison result between the level of the data strobe signal and the level of the reference voltage is performed.

Embodiments for step S810 may include embodiments of the comparison circuits 310, 410, and 510 shown in FIGS. 3 to 5 or some embodiments of the operation amplifier 610 and amplifier 620 shown in FIG. 6. Same as described above.

In step S820, based on the comparison signal, generating a reset signal with a pulse width corresponding to the preamble period of the data strobe signal is performed.

Embodiments for step S820 are as described above for some embodiments of the reset signal generation circuits 320, 420, and 520 shown in FIGS. 3 to 5 or some embodiments of the amplifier 620 shown in FIG. 6. .

In some embodiments, the reset signal may rise when the level of the data strobe signal becomes less than the level of the reference voltage. Alternatively, when the level of the data strobe signal is higher than the level of the reference voltage, the reset signal may fall.

In some embodiments, the reset signal is input to at least one of a divider (e.g., data strobe divider 240 shown in FIG. 2) and an equalizer (e.g., DFE 230 shown in FIG. 2). It can be. The divider and equalizer can each be initialized in the preamble period of the data strobe signal.

FIG. 9 is a flowchart for explaining the operation method of the preamble detection circuit shown in FIG. 3.

3, 8, and 9, in some embodiments, step S810 may include step S910, step S920, and step S930, and step S820 may include step S940, and step S950.

In step S910, receiving a data strobe signal, a reference voltage, and an inverted data strobe signal are performed. For example, with reference to FIG. 3 , the first comparator 311 may receive a data strobe signal (DQS) and a reference voltage (VREF). Additionally, the second comparator 313 may receive the inverted data strobe signal (DQSB) and the reference voltage (VREF).

In step S920, outputting a first comparison signal representing a comparison result between the data strobe signal and the reference voltage is performed. For example, with reference to FIG. 3 , the first comparator 311 may output a first comparison signal (COMPS 1).

In step S930, outputting a second comparison signal representing a comparison result between the inverted data strobe signal and the reference voltage is performed. For example, with reference to FIG. 3 , the second comparator 313 may output a second comparison signal (COMPS 2).

In step S940, calculating an OR between the logic level of the first comparison signal and the logic level of the second comparison signal is performed. For example, with reference to FIG. 3, the reset signal generation circuit 320 implemented as an OR operation gate calculates the OR between the logic level of the first comparison signal (COMPS 1) and the logic level of the second comparison signal (COMPS 2). can do.

In step S950, a step of outputting the operation result as a reset signal is performed. For example, with reference to FIG. 3, if either the logic level of the first comparison signal (COMPS 1) or the logic level of the second comparison signal (COMPS 2) is a logic high level, the result of the OR operation is logic high. It's a level. Alternatively, if the logic level of the first comparison signal COMPS 1 and the logic level of the second comparison signal COMPS 2 are both a logic low level, the result of the OR operation is a logic low level. The reset signal RST may have a logic high level or a logic low level depending on the result of the OR operation.

FIG. 10 is a flowchart for explaining the operation method of the preamble detection circuit shown in FIG. 4.

4, 8, and 10, in some embodiments, step S810 includes step S1010, step S1021, step S1022, step S1031, and step S1032, and step S820 includes step S1040, and step S1050. may include.

Step S1010 may be the same as step S910. Step S1021 may be the same as step S920.

In step S1022, amplifying the first comparison signal is performed. For example, referring to FIG. 4, the first amplifier 412 amplifies the first comparison signal (COMPS 1) output from the first comparator 411 and outputs the amplified first comparison signal (COMPS 1'). can do.

Step S1031 may be the same as step S930.

In step S1032, amplifying the second comparison signal is performed. For example, referring to FIG. 4, the second amplifier 414 amplifies the second comparison signal (COMPS 2) output from the second comparator 413 and outputs the amplified second comparison signal (COMPS 2'). can do.

In step S1040, calculating an OR between the logic level of the amplified first comparison signal and the logic level of the amplified second comparison signal is performed. For example, with reference to FIG. 4 , the reset signal generation circuit 420 implemented as an OR operation gate has the logic level of the amplified first comparison signal (COMPS 1') and the amplified second comparison signal (COMPS 2'). Logical sums between logic levels can be calculated.

In step S1050, a step of outputting the operation result as a reset signal is performed. For example, with reference to FIG. 4 , the reset signal generation circuit 420 may output the operation result as a reset signal (RST).

FIG. 11 is a flowchart for explaining the operation method of the preamble detection circuit shown in FIG. 5.

Referring to FIGS. 5, 8, and 11, the operating method of the preamble detection circuit shown in FIG. 11 may include steps S810 and S820.

In some embodiments, step S820 may include steps S1110 and S1120.

In step S1110, sampling the logic level of the comparison signal in response to a clock signal input from the outside is performed. For example, with reference to FIG. 5 , the reset signal generation circuit 520 may sample the logic level of the comparison signal COMPS at an edge (eg, rising edge) of the clock signal CLK.

In step S1120, outputting the sampling result as a reset signal is performed. For example, with reference to FIG. 5 , the reset signal generation circuit 520 may output the sampling result as a reset signal (RST). The logic level of the reset signal (RST) may follow the logic level of the comparison signal (COMPS).

12 is a diagram illustrating an electronic system according to example embodiments of the present disclosure.

Referring to FIG. 12, the system 1000 is a laptop computer, mobile phone, smart phone, tablet personal computer, wearable device, healthcare device, or Internet of Things (IOT). Of Things) can be implemented as a device. Additionally, the system 1000 may be implemented as a server or personal computer.

Electronic system 1000 includes a camera 1100, a display 1200, an audio processor 1300, a modem 1400, volatile memories 1500a, 1500b, flash memories 1600a, 1600b, and I/O devices. (1700a, 1700b) and an application processor (Application Processor, 1800, hereinafter referred to as “AP”).

The camera 1100 can capture still images or moving images under user control.

The audio processor 1300 may process audio data included in flash memory devices 1600a and 1600b or network content.

The modem 1400 modulates and transmits signals for wired/wireless data transmission and reception, and can be demodulated to restore the original signal at the receiving end.

I/O devices 1700a and 1700b may include devices that provide digital input and/or output functions.

The AP 1800 can control the overall operation of the electronic system 1000. The AP 1800 may control the display 1200 to display part of the content. When a user input is received through the I/O devices 1700a and 1700b, the AP 1800 may perform a control operation corresponding to the user input. The AP 1800 may include an accelerator 1820, which is a dedicated circuit for AI (Artificial Intelligence) data operation. A volatile memory 1500b may be additionally installed in the accelerator 1820. The accelerator 1820 may be a functional block that specializes in performing a specific function of the AP 1800. The accelerator 1820 may include a graphics processing unit (GPU), a neural processing unit (NPU), and a data processing unit (DPU). GPU may be a block that specializes in graphics data processing. NPU may be a block for professionally performing AI calculations and inference. A DPU may be a block that specializes in data transmission.

The AP 1800 can control the volatile memories 1500a and 1500b through commands and mode register settings (eg, MRS) that comply with the JEDEC standard. Alternatively, the AP 1800 may set a DRAM interface protocol to use company-specific functions such as low voltage/high speed/reliability and CRC (Cyclic Redundancy Check)/ECC (Error Correction Code) functions.

The controller 1810 included in the AP 1800 may correspond to the memory controller 110 described above with reference to FIG. 1 .

The volatile memories 1500a and 1500b have relatively smaller latency and bandwidth than the I/O devices 1700a and 1700b or the flash memories 1600a and 1600b. The volatile memories 1500a and 1500b are initialized when the electronic system 1000 is powered on, and the operating system and application data are loaded and used as a temporary storage location for the operating system and application data or as an execution space for various software codes. You can.

In the volatile memories 1500a and 1500b, addition/subtraction/multiplication/division arithmetic operations, vector operations, address operations, or FFT (Fast Fourier Transform) operations may be performed. Additionally, a function used for inference may be performed within the volatile memories 1500a and 1500b.

Each of the volatile memories 1500a and 1500b may correspond to the memory device 120 described above with reference to FIG. 1 .

The flash memories 1600a and 1600b can store photos taken through the camera 1100 or store data transmitted over a data network. The flash memories 1600a and 1600b may have a capacity larger than that of the volatile memories 1500a and 1500b.

FIG. 13 is a diagram for explaining a computing system according to example embodiments of the present disclosure.

Referring to FIG. 13, the computing system 1300 may include a host 1310, a memory module 1320, and a Basic Input/Output System (BIOS) memory 1350 mounted on the board 1301. .

The host 1310 may include the memory controller 110 shown in FIG. 1 .

The host 1310 may be communicatively connected to the memory module 1320 through the memory bus 1340.

The host 1310 may operate as a functional block that performs general computer operations within the computing system 1300. The host 1310 may correspond to a central processing unit (CPU), a digital signal processor (DSP), or an application processor (AP).

Host 1310 may be configured to execute one or more machine-executable instructions or pieces of software, firmware, or combinations thereof. The host 1310 may be connected to the BIOS memory 1350 through various interfaces such as a serial peripheral interface (Serial Peripheral Interface) or a low pin count bus.

BIOS memory 1350 may store BIOS code for booting the computing system 1300. The BIOS memory 1350 may be implemented as a non-volatile memory device such as flash memory. The BIOS code is a POST code and/or a part of the POST code that detects hardware of the computing system 1300, such as the board 1301, memory module 1320, keyboard, disk drive, etc., and checks whether they operate normally. The BIOS code may include a memory reference code (MRC) for initialization of the memory module 1320. MRC may include various algorithms configured to enable the host 1310 to normally interoperate with the memory module 1320.

By the MRC executed by the host 1310, SPD data stored in the SPD (Serial Presence Detect) memory device 1304 of the memory module 1320 is read through the memory bus 1340, and memory is stored using the SPD data. Frequency, timing, driving, detailed operation parameters, etc. for controlling the module 1320 may be set. SPD data may include the type of memory module 1320, the type of memory device included in the memory module 1320, operation timing information, manufacturing information, revision code, serial number, etc. BIST and/or memory training of the memory module 1320 may be performed by the MRC code.

The memory module 1320 is configured to perform a processing function and may include a processing device 1330 coupled to the printed circuit board 1302, a plurality of memory devices 1321 to 1329, and an SPD memory device 1304. there is. For example, the memory module 1320 may be implemented as Registered DIMM (RDIMM), Load Reduced DIMM (LRDIMM), Fully Buffered DIMM (FBDIMM), Small Outline DIMM (SODIMM), etc.

The processing device 1330 may include a Registered Clock Driver (RCD).

The memory devices 1321 to 1329 can write data or read data. Exemplarily, the memory devices 1321 to 1329 may be DRAM devices. However, the scope of the present invention is not limited thereto, and the memory devices 1321 to 1329 include SDRAM (Synchronous DRAM), DDR SDRAM (Double Data Rate SDRAM), LPDDR SDRAM (Low Power Double Data Rate SDRAM), and GDDR SDRAM. It may be any one of volatile memory devices such as (Graphics Double Data Rate SDRAM), DDR2 SDRAM, DDR3 SDRAM, DDR4 SDRAM, and DDR5 SDRAM.

Each of the memory devices 1321 to 1329 may correspond to the memory device 120 described above with reference to FIG. 1 .

The memory bus 1340 may be implemented as one channel or a plurality of channels including a plurality of signal lines between the host 1310 and the connecting pins 1306 of the memory module 1320. The memory bus 1340 may be composed of command/address signal lines for transmitting commands/addresses and data lines for transmitting data.

It is obvious to those skilled in the art that the structure of the present disclosure can be modified or changed in various ways without departing from the scope or technical spirit of the present disclosure. In view of the foregoing, it is believed that the present disclosure includes modifications and modifications of the present disclosure if such modifications and variations fall within the scope of the following claims and equivalents.

As above, exemplary embodiments have been disclosed in the drawings and specification. Although embodiments have been described in this specification using specific terminology, this is only used for the purpose of explaining the technical idea of the present disclosure and is not used to limit the meaning or scope of the present disclosure as set forth in the claims. . Therefore, those skilled in the art will understand that various modifications and other equivalent embodiments are possible therefrom. Therefore, the true technical protection scope of the present disclosure should be determined by the technical spirit of the attached patent claims.

Claims (10)

a comparison circuit configured to compare the level of the data strobe signal and the level of the reference voltage and output a comparison signal; and
A preamble detection circuit comprising a reset signal generating circuit configured to output a reset signal having a pulse width corresponding to a preamble period of the data strobe signal based on the comparison signal. According to claim 1,
The comparison circuit is,
a first comparator that receives the data strobe signal and the reference voltage and outputs a first comparison signal indicating a comparison result between the data strobe signal and the reference voltage; and
A second comparator that receives an inverted data strobe signal in which the data strobe signal is inverted and the reference voltage, and outputs a second comparison signal indicating a result of comparison between the inverted data strobe signal and the reference voltage,
The reset signal generating circuit,
A preamble detection circuit comprising an OR operation gate that calculates an OR between the logic level of the first comparison signal and the logic level of the second comparison signal, and outputs the operation result as the reset signal. According to clause 2,
The first comparison signal is,
When the level of the data strobe signal is lower than the level of the reference voltage, it has a first logic level,
When the level of the data strobe signal is higher than the level of the reference voltage, it has a second logic level lower than the first logic level,
The calculation result output as the reset signal is,
A preamble detection circuit, characterized in that it corresponds to the logic level of the first comparison signal. According to clause 2,
The comparison circuit is,
a first amplifier that amplifies the first comparison signal output from the first comparator and provides the amplified first comparison signal to the OR operation gate; and
A preamble detection circuit further comprising a second amplifier that amplifies the second comparison signal output from the second comparator and provides the amplified second comparison signal to the OR operation gate. According to claim 1,
The reset signal generating circuit,
A preamble detection circuit comprising a sampler that samples the logic level of the comparison signal in response to a clock signal input from the outside and outputs the sampling result as the reset signal. According to clause 5,
The comparison signal is,
When the level of the data strobe signal is lower than the level of the reference voltage, it has a first logic level,
When the level of the data strobe signal is higher than the level of the reference voltage, it has a second logic level lower than the first logic level,
The sampling result output as the reset signal is,
A preamble detection circuit, characterized in that it corresponds to the logic level of the comparison signal. According to claim 1,
The reset signal is,
When the level of the data strobe signal becomes lower than the level of the reference voltage, rising,
A preamble detection circuit characterized in that it falls when the level of the data strobe signal is higher than the level of the reference voltage. According to claim 1,
The reset signal is,
A preamble detection circuit, characterized in that it is input to at least one of a divider and an equalizer each initialized in the preamble period. generating a comparison signal representing the result of comparison between the level of the data strobe signal and the level of the reference voltage; and
A method of operating a preamble detection circuit, comprising generating a reset signal having a pulse width corresponding to a preamble period of the data strobe signal, based on the comparison signal. a data strobe buffer configured to buffer a data strobe signal provided from the outside; and
A memory device comprising a preamble detection circuit configured to output, based on the data strobe signal and a reference voltage, a reset signal having a pulse width corresponding to a preamble period of the data strobe signal.

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