KR20240035778A - Semiconductor device - Google Patents

Abstract

A semiconductor device according to some embodiments of the present invention includes a bit line extending in a first direction; a channel film on the bit line; and a gate structure on the channel film. The gate structure includes: a gate insulating layer on the channel layer; a first word line and a second word line on the gate insulating layer; and a gate capping layer on the first word line and the second word line. The channel film includes: a lower channel portion in contact with the bit line; and a first upper channel portion and a second upper channel portion spaced apart from each other with the gate structure therebetween, and the first upper channel portion and the second upper channel portion are inclined with respect to the lower channel portion.

Description

Semiconductor device {SEMICONDUCTOR DEVICE}

Embodiments of the present invention relate to semiconductor devices, and more particularly, to semiconductor devices including a channel film.

As the design rules of semiconductor devices are decreasing, manufacturing technology is being developed to improve the integration of semiconductor devices and improve operation speed and yield. Accordingly, a transistor with a vertical channel was proposed to expand the transistor's integration, resistance, and current driving ability.

Embodiments of the present invention aim to provide a semiconductor device with improved electrical characteristics and reliability.

A semiconductor device according to some embodiments includes a bit line extending in a first direction; a channel film on the bit line; and a gate structure on the channel film, wherein the gate structure includes: a gate insulating film on the channel film; a first word line and a second word line on the gate insulating layer; and a gate capping layer on the first word line and the second word line, wherein the channel layer includes: a lower channel portion in contact with the bit line; and a first upper channel portion and a second upper channel portion spaced apart from each other with the gate structure therebetween, and the first upper channel portion and the second upper channel portion may be inclined with respect to the lower channel portion.

A semiconductor device according to some embodiments includes a bit line extending in a first direction; a channel film on the bit line; A gate structure on the channel film; a data contact connected to the channel membrane; a landing pad on the data contact; and a data storage pattern connected to the landing pad, wherein the gate structure includes: a gate insulating layer in contact with the channel layer; a first word line and a second word line on the gate insulating layer; a gate capping layer on the first and second word lines; and a molding layer on the gate capping layer, wherein the data contact includes a protrusion protruding toward the first word line, and the width of the protrusion of the data contact in the first direction may increase as the level decreases. there is.

In semiconductor devices according to embodiments of the present invention, as part of the channel film and part of the gate insulating film are inclined, the width of the word line formed on the channel film and the gate insulating film may increase. Accordingly, the resistance of the word line is reduced, and the electrical characteristics of the semiconductor device can be improved.

In semiconductor devices according to embodiments of the present invention, as a portion of the channel layer and a portion of the gate insulating layer are inclined, the insulating layer may be further etched when forming a data contact, thereby increasing the width of the formed data contact. Accordingly, the electrical characteristics of the semiconductor device can be improved.

1 is a block diagram of a semiconductor device according to some embodiments.
2 and 3 are schematic perspective views of semiconductor devices according to some embodiments.
4 is a plan view of a semiconductor device according to some embodiments.
Figure 5 is a cross-sectional view taken along line A-A' in Figure 4.
Figure 6 is a cross-sectional view taken along line B-B' in Figure 4.
Figure 7 is an enlarged view of area E in Figure 5.
8 is a cross-sectional view of a semiconductor device according to some embodiments.
9 is a cross-sectional view of a semiconductor device according to some embodiments.
10A, 10B, 10C, 10D, and 10E are diagrams for explaining a method of manufacturing a semiconductor device according to some embodiments.

Hereinafter, a semiconductor device and a manufacturing method thereof according to embodiments of the present invention will be described in detail with reference to the drawings.

1 is a block diagram of a semiconductor device according to some embodiments.

Referring to FIG. 1 , the semiconductor device may include a memory cell array 1, a row decoder 2, a sense amplifier 3, a column decoder 4, and control logic 5.

The memory cell array 1 may include a plurality of memory cells MC arranged two-dimensionally or three-dimensionally. Each of the memory cells MC may be connected between the word line WL and the bit line BL that intersect each other.

Each memory cell MC may include a selection element TR and a data storage element DS. The selection device (TR) and the data storage device (DS) may be electrically connected to each other. The selection device (TR) may be connected to both the word line (WL) and the bit line (BL). In other words, the selection element TR may be provided at a point where the word line WL and the bit line BL intersect each other.

The selection device (TR) may include a field effect transistor. The data storage device (DS) may include a capacitor, a magnetic tunnel junction pattern, or a variable resistor. For example, the gate terminal of the transistor that is the selection element (TR) may be connected to the word line (WL), and the source/drain terminals of the transistor may be connected to the bit line (BL) and the data storage element (DS), respectively.

The row decoder 2 can decode an externally input address and select one of the word lines WL of the memory cell array 1. The address decoded in the row decoder 2 may be provided to a row driver (not shown), and the row driver applies a predetermined voltage to the selected word line (WL) and the unselected word lines (WL) in response to control of the control circuits. ) can be provided respectively.

The sense amplifier 3 may detect and amplify the voltage difference between the bit line BL and the reference bit line selected according to the address decoded from the column decoder 4 and output the amplified voltage difference.

The column decoder 4 may provide a data transmission path between the sense amplifier 3 and an external device (eg, a memory controller). The column decoder 4 can decode an externally input address and select one of the bit lines BL.

The control logic 5 may generate a control signal that controls the operation of writing or reading data into the memory cell array 1.

2 and 3 are schematic perspective views of semiconductor devices according to some embodiments.

Referring to FIGS. 2 and 3 , the semiconductor device may include a peripheral circuit structure (PS) and a cell array structure (CS) connected to the peripheral circuit structure (PS).

The peripheral circuit structure PS may include a core and peripheral circuits formed on the substrate SUB. Core and peripheral circuits may include row and column decoders 2, 4, sense amplifier 3, and control logics 5 described with reference to FIG. 1.

The cell array structure CS may include a memory cell array (1 in FIG. 1) including memory cells (MC in FIG. 1) arranged two-dimensionally or three-dimensionally. As described above, each of the memory cells (MC in FIG. 1) may include a selection element (TR) and a data storage element (DS).

In some embodiments, the selection element TR of each memory cell (MC in FIG. 1) may include a vertical channel transistor (VCT). The vertical channel transistor may include a channel whose lengthwise direction is perpendicular to the top surface of the substrate SUB. The data storage element DS of each memory cell (MC in FIG. 1) may include a capacitor.

In the embodiment according to FIG. 2, the peripheral circuit structure PS may be provided on the substrate SUB, and the cell array structure CS may be provided on the peripheral circuit structure PS.

In the embodiment according to FIG. 3, the peripheral circuit structure PS may be provided on the first substrate SUB1, and the cell array structure CS may be provided on the second substrate SUB2. The first substrate SUB1 and the second substrate SUB2 may face each other.

First metal pads LMP may be provided at the top of the peripheral circuit structure PS. The first metal pads LMP may be electrically connected to the core and peripheral circuits (2, 3, 4, and 5 in FIG. 1).

Second metal pads UMP may be provided at the bottom of the cell array structure CS. The second metal pads UMP may be electrically connected to the memory cell array (1 in FIG. 1). The second metal pads UMP may directly contact and bond to the first metal pads LMP of the peripheral circuit structure PS.

4 is a plan view of a semiconductor device according to some embodiments. Figure 5 is a cross-sectional view taken along line A-A' in Figure 4. Figure 6 is a cross-sectional view taken along line B-B' in Figure 4. Figure 7 is an enlarged view of area E in Figure 5.

Referring to FIGS. 4 to 7 , a first lower insulating layer LIL1 may be provided on the substrate SUB. The substrate SUB may have the shape of a plate extending along a plane defined by the first direction D1 and the second direction D2. The first direction D1 and the second direction D2 may intersect each other. For example, the first direction D1 and the second direction D2 may be horizontal directions orthogonal to each other. The first lower insulating layer LIL1 may include an insulating material. As an example, the first lower insulating layer LIL1 may include oxide.

In some embodiments, the peripheral circuit structure PS described with reference to FIG. 2 may be provided between the substrate SUB and the first lower insulating layer LIL1. In some embodiments, an integrated circuit such as a logic element may be provided between the substrate SUB and the first lower insulating layer LIL1.

A second lower insulating layer LIL2 may be provided on the first lower insulating layer LIL1. The second lower insulating layer LIL2 may be stacked on the first lower insulating layer LIL1 in the third direction D3. The third direction D3 may intersect the first direction D1 and the second direction D2. For example, the third direction D3 may be a vertical direction orthogonal to the first direction D1 and the second direction D2.

A plurality of bit lines BL may be provided in the second lower insulating layer LIL2. The bit lines BL may extend in the first direction D1. The bit lines BL may be arranged along the second direction D2. The bit lines BL may be spaced apart from each other in the second direction D2.

The bit lines BL may include a conductive material. For example, the bit lines BL may be made of a doped semiconductor material (e.g., doped silicon, doped germanium, etc.), a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.), or a metal (e.g., For example, tungsten, titanium, tantalum, etc.), and a metal-semiconductor compound (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.). The bit line BL may be a single conductive layer or multiple conductive layers. The second lower insulating layer LIL2 may include an insulating material. As an example, the second lower insulating layer LIL2 may include nitride.

Channel layers (ACP) may be provided on the bit lines (BL) and the second lower insulating layer (LIL2). A plurality of channel films (ACP) may be in contact with one bit line (BL). Channel films ACP provided on one bit line BL may be arranged along the first direction D1.

The channel film (ACP) may include a lower channel portion (DA), a first upper channel portion (UA1), and a second upper channel portion (UA2). The lower channel portion DA may be provided on the upper surface of the bit line BL. The lower channel portion DA may extend in the first direction D1. The first upper channel portion UA1 and the second upper channel portion UA2 may be provided on the lower channel portion DA. The first upper channel part UA1 and the second upper channel part UA2 may be connected to the lower channel part DA. The first upper channel portion UA1 and the second upper channel portion UA2 may be spaced apart from each other in the first direction D1. The first upper channel portion UA1 may extend in the fourth direction D4. The fourth direction D4 may intersect the first direction D1, the second direction D2, and the third direction D3. For example, the fourth direction D4 may be a horizontal direction that intersects the first direction D1 and the third direction D3 and is perpendicular to the second direction D2. The second upper channel portion UA2 may extend in the fifth direction D5. The fifth direction D5 may intersect the first direction D1, the third direction D3, and the fourth direction D4. As an example, the fifth direction D5 may be a horizontal direction that intersects the first direction D1, the third direction D3, and the fourth direction D4, and is perpendicular to the second direction D2.

The channel film (ACP) may include a semiconductor material. As an example, the channel film (ACP) may include an oxide semiconductor material. The oxide semiconductor may include at least one of InGaZnO, InGaSiO, InSnZnO, InZnO, ZnO, ZnSnO, ZnON, ZrZnSnO, SnO, HfInZnO, GaZnSnO, AlZnSnO, YbGaZnO, and InGaO, but is not limited thereto. As an example, the channel film (ACP) may include Indium Gallium Zinc Oxide (IGZO). The channel film (ACP) may include a single layer or multiple layers of the oxide semiconductor. The channel film (ACP) may include an amorphous, crystalline, or polycrystalline oxide semiconductor. In some embodiments, the channel film (ACP) may have a band gap energy greater than that of silicon. For example, the channel film (ACP) may have a band gap energy of about 1.5 eV to 5.6 eV. For example, the channel film (ACP) may have optimal channel performance when it has a bandgap energy of about 2.0 eV to 4.0 eV. For example, the channel film (ACP) may be polycrystalline or amorphous, but is not limited thereto. In exemplary embodiments, the channel film (ACP) may include a two-dimensional semiconductor material, for example, the two-dimensional semiconductor material may be graphene, carbon nanotube, or a combination thereof. may include.

Gate structures (GST) may be provided. The gate structure (GST) may be provided on the channel film (ACP). The gate structures GST may extend in the second direction D2. The gate structures GST may be arranged in the first direction D1. The gate structures GST may be arranged to be spaced apart from each other in the first direction D1.

The gate structure (GST) may include a gate insulating layer (GO), a first word line (WL1), a second word line (WL2), a gate capping layer (GP), and a molding layer (MD). The gate insulating layer (GO), first word line (WL1), second word line (WL2), gate capping layer (GP), and molding layer (MD) included in one gate structure (GST) are channel layer (ACP). It may be provided between the first upper channel part (UA1) and the second upper channel part (UA2).

The gate insulating layer (GO) may be in contact with the channel layer (ACP). The gate insulating layer GO may include a horizontal portion DO, a first extension portion UO1, and a second extension portion UO2. The horizontal portion DO may extend in the first direction D1. The horizontal portion DO may be in contact with the upper surface of the lower channel portion DA of the channel film ACP. The first extension part UO1 and the second extension part UO2 may be provided on the horizontal part DO. The first extension part UO1 and the second extension part UO2 may be connected to the horizontal part DO. The first extension part UO1 and the second extension part UO2 may be spaced apart from each other in the first direction D1. The first extension UO1 may extend in the fourth direction D4. The outer wall (UO1_OS) of the first extension part (UO1) may be in contact with the first upper channel part (UA1) of the channel film (ACP). The second extension UO2 may extend in the fifth direction D5. The outer wall (UO2_OS) of the second extension part (UO2) may be in contact with the second upper channel part (UA2) of the channel film (ACP).

The gate insulating film (GO) may include an insulating material. As an example, the gate insulating layer GO may include oxide. In some embodiments, the gate insulating layer GO may include at least one of silicon oxide, silicon oxynitride, and a high dielectric material having a higher dielectric constant than silicon oxide. The high dielectric material may include metal oxide or metal oxynitride. For example, the high dielectric material that can be used as the gate insulating film (GO) may include at least one of HfO ₂ , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO ₂ and Al ₂ O ₃ , but is not limited thereto.

The first word line (WL1) and the second word line (WL2) may be provided on the gate insulating layer (GO). The lower surfaces of the first word line WL1 and the second word line WL2 may contact the upper surface of the horizontal portion DO of the gate insulating layer GO. The first word line WL1 and the second word line WL2 may be spaced apart from each other in the first direction D1. The first word line WL1 and the second word line WL2 may extend in the second direction D2. The inner wall of the first word line WL1 and the inner wall of the second word line WL2 may face each other. Adjacent sidewalls of the first word line WL1 and the second word line WL2 may be inner sidewalls of the first word line WL1 and the second word line WL2. The outer wall of the first word line WL1 may be opposed to the inner wall of the first word line WL1. The outer wall of the second word line WL2 may be opposed to the inner wall of the second word line WL2. The inner and outer walls of the first word line WL1 may extend in the second direction D2, and the inner and outer walls of the second word line WL2 may extend in the second direction D2. The outer wall of the first word line WL1 may contact the inner wall UO1_IS of the first extension UO1 of the gate insulating layer GO. The outer wall of the second word line WL2 may contact the inner wall UO2_IS of the second extension UO2 of the gate insulating layer GO. The first word line WL1 and the second word line WL2 may be spaced apart from each other in the first direction D1. The first word line WL1 and the second word line WL2 may extend in the second direction D2.

The outer wall of the first word line WL1 may be inclined with respect to the lower surface of the first word line WL1. The outer wall of the second word line WL2 may be inclined with respect to the lower surface of the second word line WL2. For example, the angle between the outer wall and the lower surface of the first word line WL1 and the angle between the outer wall and the lower surface of the second word line WL2 may be greater than 90 degrees and less than 180 degrees. The distance between the outer wall of the first word line WL1 and the outer wall of the second word line WL2 may increase as the level increases. The width of the first word line WL1 in the first direction D1 and the width of the second word line WL2 in the first direction D1 may decrease as the level decreases.

The first word line (WL1) and the second word line (WL2) may include a conductive material. The first word line (WL1) and the second word line (WL2) are, for example, doped polysilicon, metal (e.g., Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co ), conductive metal nitride (e.g., TiN, TaN, WN, NbN, TiAlN, TiSiN, TaSiN, RuTiN), conductive metal silicide, or conductive metal oxide, but is not limited thereto. The first word line WL1 and the second word line WL2 may include a single layer or multiple layers of the above-described materials. In some embodiments, the first word line (WL1) and the second word line (WL2) may include a two-dimensional semiconductor material. For example, the two-dimensional semiconductor material may be graphene or carbon nanomaterial. It may include a tube (carbon nanotube) or a combination thereof.

A gate capping layer (GP) may be provided on the gate insulating layer (GO), the first word line (WL1), and the second word line (WL2). The gate capping layer GP may conformally cover the gate insulating layer GO, the first word line WL1, and the second word line WL2. The gate capping layer GP may contact the inner wall and top surface of the first word line WL1 and the inner wall and top surface of the second word line WL2. The gate capping film GP is in contact with the upper surface of the horizontal part DO of the gate insulating film GO, the inner wall UO1_IS of the first extension part UO1, and the inner wall UO2_IS of the second extension part UO2. You can. The gate capping layer (GP) may include an insulating material. As an example, the gate capping film (GP) may include nitride.

A molding layer (MD) may be included on the gate capping layer (GP). The molding film (MD) may be in contact with the gate capping film (GP). The molding film (MD) may include an insulating material. As an example, the molding film MD may include oxide.

First insulating films ILD1 and second insulating films ILD2 may be provided. The first insulating layer ILD1 and the second insulating layer ILD2 may be provided between adjacent gate structures GST. The first insulating layer ILD1 may contact adjacent channel layers ACP. The first insulating layer ILD1 and the second insulating layer ILD2 may include an insulating material. For example, the first insulating layer ILD1 may include oxide, and the second insulating layer ILD2 may include nitride.

Data contacts (BC) may be provided. The data contact (BC) includes a channel layer (ACP), a gate insulating layer (GO), a gate capping layer (GP), a gate capping layer (GP), a molding layer (MD), a first insulating layer (ILD1), and a second insulating layer (ILD2). ) can be accessed. The data contact BC may be connected to the first upper channel part UA1 or the second upper channel part UA2 of the channel film ACP. The data contacts BC may be arranged in a matrix form, spaced apart in the first direction D1 or the second direction D2.

Landing pads (LP) may be provided. A landing pad (LP) may be provided on the data contact (BC). The landing pad LP may be spaced apart from the gate insulating layer GO and the gate capping layer GP. The landing pads LP may be arranged in a matrix form, spaced apart in the first direction D1 or the second direction D2. The landing pad (LP) may be connected to the channel film (ACP) by a data contact (BC).

From a plan view, the landing pads LP may be spaced apart from each other in the first and second directions D1 and D2 and may be arranged in various shapes such as a matrix shape, a zigzag shape, or a honeycomb shape. . From a two-dimensional perspective, each of the landing pads LP may have various shapes, such as circular, oval, rectangular, square, diamond, or hexagonal shapes.

The data contact (BC) and landing pad (LP) may include a conductive material. Data contacts (BC) and landing pads (LP) are doped silicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbM, TiAl, TiAlN, TiSi, It may be made of TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuOx, or a combination thereof, but is not limited thereto.

An upper insulating layer (UIL) may be provided between the landing pads LP. The upper insulating layer UIL may be provided on the gate structures GST, data contacts BC, and second insulating layers ILD2. The upper insulating layer UIL may separate the landing pads LP from each other. The upper insulating layers (UIL) may include an insulating material. As an example, the upper insulating films (UIL) may include oxide. In some embodiments, the upper insulating layer UIL may be a multilayer including a plurality of insulating layers.

Data storage patterns (DSP) may be provided on each of the landing pads (LP). The data storage pattern (DSP) may be electrically connected to the channel film (ACP) through data contacts (BC) and landing pads (LP).

In some embodiments, the data storage patterns DSP may be a capacitor and may include lower and upper electrodes, and a capacitor dielectric layer interposed between them. In this case, the lower electrode may be in contact with the landing pad LP, and the lower electrode may have various shapes, such as circular, oval, rectangular, square, diamond, or hexagonal, in plan view.

In some embodiments, the data storage pattern (DSP) may be a variable resistance pattern that can be switched between two resistance states by electrical pulses. For example, data storage patterns (DSPs) are phase-change materials whose crystal state changes depending on the amount of current, perovskite compounds, transition metal oxides, and magnetic materials. It may include magnetic materials, ferromagnetic materials, or antiferromagnetic materials.

The first upper channel portion UA1 and the second upper channel portion UA2 of the channel film ACP may be inclined with respect to the lower channel portion DA. The inner wall of the first upper channel portion UA1 and the inner wall of the second upper channel portion UA2 may be in contact with the gate insulating layer GO. For example, the angle between the inner wall of the first upper channel portion (UA1) and the upper surface of the lower channel portion (DA), and the angle between the inner wall of the second upper channel portion (UA2) and the upper surface of the lower channel portion (DA) The angle can be greater than 90 degrees and less than 180 degrees. The distance D between the first upper channel part UA1 and the second upper channel part UA2 may increase as the level increases.

The first upper channel portion UA1 may include a top surface UA1_U and a side wall UA1_T. The upper surface (UA1_U) of the first upper channel portion (UA1) may be parallel to the first direction (D1). The side wall UA1_T of the first upper channel portion UA1 may be parallel to the third direction D3. The top surface (UA1_U) and the side wall (UA1_T) of the first upper channel portion (UA1) may intersect. The top surface (UA1_U) and the side wall (UA1_T) of the first upper channel portion (UA1) may be in contact with the data contact (BC).

The second upper channel portion UA2 may include a top surface UA2_U and a side wall UA2_T. The upper surface (UA2_U) of the second upper channel portion (UA2) may be parallel to the first direction (D1). The side wall UA2_T of the second upper channel portion UA2 may be parallel to the third direction D3. The upper surface (UA2_U) and the side wall (UA2_T) of the second upper channel portion (UA2) may intersect. The upper surface (UA2_U) and the side wall (UA2_T) of the second upper channel portion (UA2) may be in contact with the data contact (BC).

The first extension UO1 of the gate insulating layer GO may include an inner wall UO1_IS, an outer wall UO1_OS, and a top surface UO1_U. The inner wall UO1_IS of the first extension UO1 may contact the outer wall of the first word line WL1. The outer wall (UO1_OS) of the first extension part (UO1) may contact the first upper channel part (UA1) and the data contact (BC) of the channel film (ACP). The upper surface (UO1_U) of the first extension part (UO1) may connect the inner wall (UO1_IS) and the outer wall (UO1_OS) of the first extension part (UO1). The upper surface (UO1_U) of the first extension part (UO1) may be in contact with the data contact (BC).

The second extension UO2 of the gate insulating layer GO may include an inner wall UO2_IS, an outer wall UO2_OS, and a top surface UO2_U. The inner wall UO2_IS of the second extension UO2 may contact the outer wall of the second word line WL2. The outer wall (UO2_OS) of the second extension part (UO2) may contact the second upper channel part (UA2) and the data contact (BC) of the channel film (ACP). The upper surface (UO2_U) of the second extension part (UO2) may connect the inner wall (UO2_IS) and the outer wall (UO2_OS) of the second extension part (UO2). The upper surface (UO2_U) of the second extension part (UO2) may be in contact with the data contact (BC).

The first extension portion UO1 and the second extension portion UO2 of the gate insulating layer GO may be inclined with respect to the horizontal portion DO of the gate insulating layer GO. For example, the angle between the inner wall (UO1_IS) of the first extension (UO1) and the top surface of the horizontal portion (DO), and the inner wall (UO2_IS) of the second extension portion (UO2) and the upper surface of the horizontal portion (DO) The angle between them can be greater than 90 degrees and less than 180 degrees. The distance between the first extension part (UO1) and the second extension part (UO2) may increase as the level increases.

The gate capping layer (GP) may include a surface (GP_S) in contact with the data contact (BC). The surface GP_S of the gate capping film GP is connected to the top surface UO1_U of the first extension part UO1 of the gate insulating film GO or the top surface UO1_U of the second extension part UO2 of the gate insulating film GO. It is possible to achieve coexistence.

The data contact (BC) may include a protrusion (BC_IN). The protrusion BC_IN of the data contact BC may protrude toward the first word line WL1 or the second word line WL2. The protrusion BC_IN of the data contact BC corresponds to the upper surface UA1_U of the first upper channel part UA1 of the channel film ACP or the upper surface UA2_U of the second upper channel part UA2 of the channel film ACP. can be accessed. The protrusion BC_IN of the data contact BC may be in contact with the outer wall UO1_OS of the first extension UO1 of the gate insulating layer GO or the outer wall UO2_OS of the second extension UO2 of the gate insulating layer GO. You can. The protrusion BC_IN of the data contact BC is connected to the upper surface UA1_U of the first upper channel part UA1 of the channel film ACP and the outer wall UO1_OS of the first extension part UO1 of the gate insulating film GO. Alternatively, it may be defined by the upper surface UA2_U of the second upper channel part UA2 of the channel film ACP and the outer wall UO2_OS of the second extension part UO2 of the gate insulating film GO. The width of the protrusion BC_IN of the data contact BC in the first direction D1 may increase as the level decreases.

The level of the top surface UA1_U of the first upper channel portion UA1 of the channel film ACP may be higher than the level of the top surface of the first word line WL1. The level of the top surface UA2_U of the second upper channel unit UA2 may be higher than the level of the top surface of the second word line WL2. The top surface level of the first word line WL1 and the top surface level of the second word line WL2 may be higher than the bottom level of the data contact BC.

A semiconductor device according to some embodiments has a word line (WL) formed on the channel layer (ACP) and the gate insulating layer (GO) as a portion of the channel layer (ACP) and a portion of the gate insulating layer (GO) are inclined. The width may increase. Accordingly, the resistance of the word line WL may be reduced, thereby improving the electrical characteristics of the semiconductor device.

In the semiconductor device according to some embodiments, as a portion of the channel layer (ACP) and a portion of the gate insulating layer (GO) are inclined, the first insulating layer (ILD1) is further etched when forming the data contact (BC), thereby forming the semiconductor device. The width of data contact (BC) may increase. Accordingly, the electrical characteristics of the semiconductor device can be improved.

8 is a cross-sectional view of a semiconductor device according to some embodiments. The semiconductor device according to FIG. 8 may be similar to the semiconductor device according to FIGS. 4 to 7, except as described below.

Referring to FIG. 8, the data contact BC may not include the protrusion BC_IN. The first upper channel portion UA1 and the second upper channel portion UA2 of the channel film ACP may not include the upper surfaces UA1_U and UA2_U. The outer wall UO1_OS of the first extension UO1 of the gate insulating layer GO may be completely covered by the first upper channel portion UA1 of the channel layer ACP. The outer wall UO1_OS of the first extension UO1 of the gate insulating layer GO may be spaced apart from the data contact BC. The outer wall (UO2_OS) of the second extension portion (UO2) of the gate insulating layer (GO) may be completely covered by the second upper channel portion (UA2) of the channel layer (ACP). The outer wall UO2_OS of the second extension UO2 of the gate insulating layer GO may be spaced apart from the data contact BC.

9 is a cross-sectional view of a semiconductor device according to some embodiments. The semiconductor device according to FIG. 9 may be similar to the semiconductor device according to FIGS. 4 to 7, except as described below.

Referring to FIG. 9 , it may further include third insulating layers ILD3. The third insulating layer ILD3 may be provided between the bit line BL and the first insulating layer ILD1. The gate structure GST may be disposed between adjacent third insulating layers. The third insulating layer ILD3 may be in contact with the top surface of the bit line BL. The third insulating layer ILD3 may contact the channel layers ACP adjacent to each other in the first direction D1. The third insulating layer ILD3 may include an insulating material. As an example, the third insulating layer ILD3 may include nitride.

10A, 10B, 10C, 10D, and 10E are diagrams for explaining a method of manufacturing a semiconductor device according to some embodiments. Figures 10a to 10e may correspond to Figure 5.

Referring to FIG. 10A , the first lower insulating layer LIL1 may be formed on the substrate SUB. A second lower insulating layer LIL2 may be formed on the first lower insulating layer LIL1. Bit lines BL may be formed in the second lower insulating layer LIL2. Forming the bit lines BL may include forming trenches by etching the second lower insulating layer LIL2 and forming bit lines BL filling the trenches. Channel layers ACP, first insulating layers ILD1, and second insulating layers ILD2 may be formed on the bit lines BL and the second lower insulating layer LIL2.

A preliminary gate insulating layer (pGO) may be formed on the channel layers (ACP) and the second insulating layers (ILD2). The preliminary gate insulating layer pGO may conformally cover the channel layers ACP and the second insulating layers ILD2. The preliminary gate insulating layer (pGO) may include an insulating material.

A preliminary word line (pWL) may be formed on the preliminary gate insulating layer (pGO). The spare word line (pWL) may include a conductive material.

Referring to FIG. 10b, part of the spare word line (pWL) can be removed. A portion of the preliminary word line pWL may be removed to form first word lines WL1 and second word lines WL2. A portion of the preliminary word line (pWL) may be removed, exposing the preliminary gate insulating layer (pGO). Removing part of the preliminary word line (pWL) includes forming a photoresist film on the preliminary word line (pWL), patterning the preliminary word line (pWL) using the photoresist film as an etch mask, and patterning the preliminary word line (pWL). This may include chamfering the word line (pWL). In some embodiments, patterning the preliminary word line (pWL) may be performed through a dry etch process. In some embodiments, chamfering the preliminary word line (pWL) may be performed through a wet etch process.

Referring to FIG. 10C, a preliminary gate capping layer (pGP) may be formed on the preliminary gate insulating layer (pGO), the first word lines (WL1), and the second word lines (WL2). The preliminary gate capping layer (pGP) may conformally cover the preliminary gate insulating layer (pGO), the first word lines (WL1), and the second word lines (WL2). The preliminary gate capping layer (pGP) may include an insulating material.

A molding layer (MD) may be formed on the preliminary gate capping layer (pGP). The molding film (MD) may fill the trench defined by the surface of the preliminary gate capping film (pGP).

Referring to FIG. 10D, a portion of the first insulating layer (ILD1), a portion of the second insulating layer (ILD2), a portion of the channel layer (ACP), a portion of the preliminary gate insulating layer (pGO), and a portion of the preliminary gate capping layer (pGP) And a portion of the molding film (MD) may be removed. A portion of the first insulating layer (ILD1), a portion of the second insulating layer (ILD2), a portion of the channel layer (ACP), a portion of the preliminary gate insulating layer (pGO), a portion of the preliminary gate capping layer (pGP), and the molding layer (MD) A portion of may be removed to form an opening (op). The opening (op) is a portion of the first insulating layer (ILD1), a portion of the second insulating layer (ILD2), a portion of the channel layer (ACP), a portion of the preliminary gate insulating layer (pGO), a portion of the preliminary gate capping layer (pGP), and It may be defined by a surface formed by removing a portion of the molding film (MD). A portion of the preliminary gate insulating layer (pGO) may be removed to form the gate insulating layer (GO). A portion of the preliminary gate capping layer (pGP) may be removed to form the gate capping layer (GP). A gate insulating layer (GO) and a gate capping layer (GP) may be formed to define a gate structure (GST). In some embodiments, a portion of the first insulating layer (ILD1), a portion of the second insulating layer (ILD2), a portion of the channel layer (ACP), a portion of the preliminary gate insulating layer (pGO), and the preliminary gate capping layer (pGP). Part of the molding film (MD) may be removed through a dry etching process.

Referring to FIG. 10E, data contacts BC may be formed. The data contact BC may be formed by filling the opening op with a conductive material.

Referring again to FIG. 5 , the gate structures GST, the second insulating layers ILD2, and the upper insulating layer UIL may be formed on the data contacts BC. A process of removing part of the upper insulating film (UIL) may be performed. Landing pads LP may be formed. The landing pad LP may fill the empty space formed by removing a portion of the upper insulating layer UIL. Data storage patterns (DSP) connected to the landing pads LP may be formed.

Above, embodiments of the present invention have been described with reference to the attached drawings, but those skilled in the art will understand that the present invention can be implemented in other specific forms without changing the technical idea or essential features. You will understand that it exists. Therefore, the embodiments described above should be understood in all respects as illustrative and not restrictive.

Claims (10)

a bit line extending in a first direction;
a channel film on the bit line; and
Includes a gate structure on the channel film,
The gate structure is:
a gate insulating layer on the channel layer;
a first word line and a second word line on the gate insulating layer; and
Includes a gate capping film on the first word line and the second word line,
The channel membrane is:
a lower channel portion in contact with the bit line; and
Comprising a first upper channel portion and a second upper channel portion spaced apart from each other with the gate structure interposed therebetween,
The first upper channel portion and the second upper channel portion are inclined with respect to the lower channel portion. According to claim 1,
Further comprising a data contact connected to the channel membrane,
The first upper channel portion includes an upper surface parallel to the first direction and a side wall parallel to a second direction intersecting the first direction,
The top surface and the sidewall of the first upper channel portion are in contact with the data contact. According to claim 1,
A semiconductor device wherein the width of the first word line in the first direction and the width of the second word line in the first direction become smaller as the level decreases. According to claim 1,
Further comprising a data contact connected to the channel membrane,
The gate insulating film is:
a horizontal portion in contact with the lower channel portion;
a first extension portion between the first word line and the first upper channel portion; and
Comprising a second extension between the second word line and the second upper channel portion,
The first extension:
an inner wall in contact with the first word line;
an outer wall in contact with the first upper channel portion; and
It includes an upper surface connecting the inner wall and the outer wall,
A semiconductor device wherein an upper surface of the first extension part is in contact with the data contact. According to clause 4,
The gate capping film includes a surface in contact with the data contact,
The semiconductor device wherein the surface of the gate capping film is coplanar with the top surface of the first extension. According to clause 4,
The semiconductor device wherein the outer wall of the first extension portion is completely covered by the first upper channel portion. According to clause 4,
The data contact includes a protrusion protruding toward the first word line,
The protrusion of the data contact contacts the outer wall of the first extension portion. According to clause 7,
The first upper channel portion of the channel film includes an upper surface in contact with the protrusion of the data contact,
The outer wall of the first extension portion is inclined with respect to the upper surface of the first upper channel portion. According to claim 1,
A semiconductor device wherein the distance between the first upper channel portion and the second upper channel portion increases as the level increases. a bit line extending in a first direction;
a channel film on the bit line;
A gate structure on the channel film;
a data contact connected to the channel membrane;
a landing pad on the data contact; and
Includes a data storage pattern connected to the landing pad,
The gate structure is:
a gate insulating layer in contact with the channel layer;
a first word line and a second word line on the gate insulating layer;
a gate capping layer on the first and second word lines; and
Includes a molding film on the gate capping film,
The data contact includes a protrusion protruding toward the first word line,
A semiconductor device wherein the width of the protrusion of the data contact in the first direction increases as the level decreases.

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