KR20240034615A - Processor and soft error detection method thereof - Google Patents

Abstract

A soft error detection apparatus and method are disclosed. A soft error detection apparatus according to an embodiment of the present invention includes the steps of duplicating an original branch instruction into a duplicate branch instruction; executing a first set of instructions including the replication branch instruction; executing a second instruction set including the original branch instruction; and determining whether an error exists in execution of the original branch instruction based on execution results of the first instruction set and the second instruction set.

Description

Processor and its soft error detection method {PROCESSOR AND SOFT ERROR DETECTION METHOD THEREOF}

The present invention relates to an error detection method, and to a processor and its soft error detection method.

A soft error, or transient fault, is when the bit value stored in a semiconductor device such as a transistor changes from “0” to “1” or vice versa due to external factors, regardless of a permanent defect in the hardware, such as the collision of neutrons or alpha particles. On the contrary, it means an error that is overturned. Damage to bit values due to soft errors can cause fatal malfunctions in processor operation.

Accordingly, it is required to accurately detect soft errors before they lead to fatal malfunctions in the operation of the device or system.

The present invention is intended to solve the above-mentioned problems, and seeks to provide a processor and a soft error detection method thereof that can accurately detect soft errors and prevent malfunctions due to soft errors.

A soft error detection device according to an embodiment of the present invention for solving the above technical problem includes: replicating an original branch instruction into a duplicate branch instruction; executing a first set of instructions including the replication branch instruction; executing a second instruction set including the original branch instruction; and determining whether an error exists in execution of the original branch instruction based on execution results of the first instruction set and the second instruction set.

Before and after executing the first instruction set, determining whether an error exists in execution of the replication branch instruction using a global signature value for the current instruction block in which the first instruction set is executed may be further included.

Determining whether an error exists in execution of the replication branch instruction may include corrupting the global signature value; and restoring the damaged global signature value.

The step of corrupting the global signature value includes subtracting a damaged value from the global signature value, and the step of restoring the damaged global signature value includes adding a restored value to the damaged global signature value. can do.

The damage value and the restoration value are the same and may each be set to unique values.

The step of determining whether an error exists in execution of the replication branch instruction may further include comparing the global signature value before damage and the global signature value after restoration.

Based on the operation mode, the step of determining whether an error exists in execution of the replication branch instruction may be optionally performed.

Executing the first instruction set includes setting a runtime signature value corresponding to a branch instruction block branched by execution of the original branch instruction to a first value; executing the replication branch instruction; maintaining the runtime signature value as the first value when the branch condition of the replication branch instruction is satisfied; and changing the runtime signature value from the first value to the second value if the branch condition of the replication branch instruction is not satisfied.

The first value is an exclusive OR value of a unique signature value for the current instruction block in which the replication branch instruction is executed and a unique signature value of one of the branch instruction blocks branched as a result of execution of the second instruction set, and the first The value 2 may be an exclusive OR value of the unique signature value for the current instruction block and the unique signature value of another one of the branch instruction blocks.

Executing the first instruction set includes, when the branch condition of the replication branch instruction is satisfied, the program counter of the current instruction block in which the replication branch instruction is executed, the first instruction set of the current instruction block, and the second instruction set. It may further include moving to an area located between instruction sets.

The runtime signature value may indicate the difference between the unique signature value of the current instruction block and the branch instruction block.

Executing the second instruction set includes moving to a first branch instruction block among branch instruction blocks when the branch condition of the original branch instruction is satisfied; and if the branch condition of the original branch instruction is not satisfied, moving to a second branch instruction block among the branch instruction blocks.

The step of determining whether an error exists in the execution of the original branch instruction includes exclusive-ORing a global signature value for the current instruction block and a runtime signature value corresponding to the first branch instruction block or the second branch instruction block. step; Comparing the exclusive OR value with a unique signature value of the first branch instruction block or the second branch instruction block; and generating an error detection result for execution of the original branch instruction based on the comparison result.

Execution of the first instruction set and execution of the second instruction set may be performed independently of each other.

The soft error detection method can be applied to CHITIN (Comprehensive In-Thread Instruction replication technique against transient faults) or SWIFT (Software Implemented Fault Tolerance) among software-based instruction duplication techniques.

The soft error detection method can be performed on a processor operating with an instruction set architecture that does not support instructions for conditionally updating register values.

The processor according to an embodiment of the present invention to solve the above technical problem operates using the soft error detection method and outputs an error detection signal when an error exists in execution of the original branch instruction.

A soft error detection method according to an embodiment of the present invention to solve the above technical problem includes the steps of damaging the global signature value of the current instruction block; executing a replication branch instruction corresponding to the original branch instruction; restoring the damaged global signature value; Comparing a value before damage and a value after restoration of the global signature value; and detecting whether an error exists in execution of the replication branch instruction based on the comparison result.

The replication branch instruction has the same branch condition as the original branch instruction, and before executing the replication branch instruction, the current instruction block in which the replication branch instruction is executed and the branch instruction block branched by the original branch instruction are unique. Setting a runtime signature value indicating a difference between the signature values as a first value; As a result of executing the replication branch instruction, if the branch condition of the replication branch instruction is satisfied, the runtime signature value is maintained as the first value, and if the branch condition of the replication branch instruction is not satisfied, the runtime signature value is maintained. changing a second value different from the first value; and detecting whether an error exists in execution of the original branch instruction based on the runtime signature value according to an execution result of the duplicate branch instruction.

The replication branch instruction has a different branch condition from the original branch instruction, and if the branch condition of the replication branch instruction is not satisfied, the current instruction block in which the replication branch instruction is executed and the branch branched by the original branch instruction Setting a runtime signature value indicating the difference between the unique signature value of the instruction block as a first value; As a result of executing the original branch instruction, if the branch condition of the original branch instruction is not satisfied, changing the runtime signature value to a second value different from the first value; and detecting whether an error exists in execution of the original branch instruction based on the runtime signature value according to the execution result of the branch instruction and the original branch instruction.

According to the processor and its soft error detection method according to an embodiment of the present invention, soft errors can be accurately detected without using conditional calculation operations, thereby preventing malfunctions due to soft errors and improving operational reliability.

1 is a diagram showing a soft error detection method according to an embodiment of the present invention.
Figure 2 is a diagram illustrating a processor that detects a soft error using a soft error detection method according to an embodiment of the present invention.
Figure 3 is a diagram showing an instruction block according to an embodiment of the present invention.
Figures 4A and 4B are diagrams showing examples of soft errors, respectively.
Figure 5 is a diagram showing a processor according to an embodiment of the present invention in which a soft error detection unit is integrated with a compiler.
Figure 6 is a diagram showing a soft error detection method according to an embodiment of the present invention.
Figure 7 is a diagram showing a current instruction block and a branch instruction block according to an embodiment of the present invention.
Figure 8 is a diagram showing steps for executing a first instruction set according to an embodiment of the present invention.
Figures 9A to 9C are diagrams showing the movement position of the program counter when an error occurs in a copy branch instruction according to an embodiment of the present invention.
Figure 10 is a diagram showing the step of determining whether an error exists in the execution of an original branch instruction according to an embodiment of the present invention.
Figure 11 is a diagram showing a soft error detection method according to an embodiment of the present invention.
FIG. 12 is a diagram showing a current instruction block and a branch instruction block operating using the soft error detection method of FIG. 11.
Figure 13 is a diagram showing a soft error detection method according to an embodiment of the present invention.
FIG. 14 is a diagram showing a current instruction block and a branch instruction block operating using the soft error detection method of FIG. 13.

Hereinafter, embodiments of the present invention will be described clearly and in detail so that a person skilled in the art can easily practice the present invention.

FIG. 1 is a diagram showing a soft error detection method 100 according to an embodiment of the present invention, and FIG. 2 is a diagram showing a processor 200 that detects a soft error using the soft error detection method 100 according to an embodiment of the present invention. 3 is a diagram showing a command block (CBK) according to an embodiment of the present invention.

Referring to Figures 1 to 3, the soft error detection method 100 and processor 200 according to an embodiment of the present invention can detect soft errors that exist in the execution of an application. Accordingly, the operational reliability of the processor 200 executing the application can be guaranteed. The application may be a program that can be executed by the processor 200 according to an embodiment of the present invention, or software such as a software module or software component. An application can consist of multiple commands. A soft error refers to a temporary error in which the bit value stored in a semiconductor device is unintentionally changed due to external factors, regardless of a permanent defect in the hardware. One of the external factors causing soft errors can be the effect of neutrons in the air.

The soft error detection method 100 according to an embodiment of the present invention includes copying an original branch instruction (OBC) into a clone branch instruction (CBC) (S120), a first instruction set including the clone branch instruction (CBC) (CS1) (S140), executing the second instruction set (CS2) including the original branch instruction (OBC) (S160), and the first instruction set (CS1) and the second instruction set (CS2) ) includes a step (S180) of determining whether an error exists in the execution of the original branch instruction (OBC) based on whether an error exists in the execution of the original branch instruction (OBC).

The original branch instruction (OBC) may be one of the original instructions. A clone branch instruction (CBC) may be one of the clone instructions that is copied to the original instruction. The original and duplicate instructions include the 'ADD' (addition) instruction, 'MULT' (multiplication) instruction, 'XOR' (exclusive OR) instruction, 'STR' (save) instruction, and 'JUMP' instruction required for the execution of the application. Various commands may be included, such as the 'BRANCH' command, the 'COMPARE' command, and the 'MOV' (movement) command. A branch instruction refers to an instruction used to change the flow of instruction execution or call another routine, such as the 'BRANCH' instruction or the 'JUMP' instruction. Accordingly, the program counter after executing the branch instruction may not be continuous with the program counter for the corresponding instruction, or the instruction flow may change to an instruction block different from the instruction block in which the corresponding instruction is executed.

For example, if a replication branch instruction (CBC) in the current instruction block (CBK) is executed at the PCx+1), it can be moved to a location corresponding to another program counter in the current instruction block (CBK) indicated by the replication branch instruction (CBC). Alternatively, the instruction flow may be moved to another instruction block after the clone branch instruction (CBC) of the current instruction block (CBK) is executed. The current instruction block (CBK) is one of the instruction blocks (BK1 to BKn) and may refer to the instruction block (BK1 to BKn) where the original instruction and duplicate instruction executed at the current time are located.

The first instruction set (CS1) may include other instructions along with the replication branch instruction (CBC). The second instruction set (CS2) may include other instructions along with the original branch instruction (OBC). A first instruction set (CS1) including a clone branch instruction (CBC) and a second instruction set (CS2) including an original branch instruction (OBC) may be included together in the current instruction block (CBK). That is, the clone branch instruction (CBC) can be copied into the same instruction block as the original branch instruction (OBC). However, it is not limited to this, and according to the algorithm applied to the soft error detection method 100 or the processor 200 according to an embodiment of the present invention to detect a soft error, the first instruction set (CS1) and the second instruction set (CS1) The instruction set (CS2) may be located in different instruction blocks.

Figures 4A and 4B are diagrams showing examples of soft errors, respectively.

First, referring to FIGS. 2 and 4A, the soft error detection unit 260 according to an embodiment of the present invention can detect soft errors in the data flow. Soft errors for data flow are errors that damage data values and do not cause movement of the program counter or instruction blocks (BK1 to BKn).

Figure 4A shows 'ADD' in which the original instruction adds the second original value (R2) stored in the second register to the first original value (R1) stored in the first register and stores the original result value (R3) in the third register. ' An example of a command is shown. At this time, by separately performing the same 'ADD' command for the first duplicate value (R1*), which duplicates the first original value (R1), and the second duplicate value (R2*), which duplicates the second original value (R2) , the original command can be copied with a clone command. In the example of Figure 4A, let's say that the result value of the original instruction, that is, the original result value (R3), is damaged due to an error. The occurrence of an error can be detected by comparing the original result value (R3) of the original instruction and the duplicate result value (R3*) of the duplicate instruction.

Next, referring to FIGS. 2 and 4B, as a result of executing the 'BRANCH' instruction indicating movement from the current instruction block (CBK) to the first instruction block (BK1), the second instruction block (BK1) rather than the first instruction block (BK1) An error may occur when moving to the command block (BK2). These errors are defined as soft errors for control flow. Unlike the case of data flow, a soft error for control flow refers to an error that causes damage to the execution order or execution location of the program.

Therefore, it may not be easier to detect errors in the control flow compared to errors in the data flow. In other words, branch instructions that cause control flow may be more vulnerable to errors. Figure 4B shows soft errors for control flow, particularly Worng-Direction errors. Among the soft errors in the control flow, an Unwanted-Jump error may occur in which the instruction block (BK1~BKn) is moved to the wrong location within the moved instruction block (BK1~BKn) even though the instruction block (BK1~BKn) is moved as instructed by the original branch instruction (OBC). You can.

Referring again to FIGS. 1 to 3, the soft error detection method 100 and processor 200 according to an embodiment of the present invention can detect both the soft errors for the data flow and the soft errors for the control flow described above. there is. Additionally, the soft error detection method 100 and processor 200 according to an embodiment of the present invention can accurately detect soft errors even when soft errors occur simultaneously in data flow and control flow.

As a method to protect the system from soft errors, it can be divided into hardware-based techniques and software-based techniques. The soft error detection method 100 and processor 200 according to an embodiment of the present invention may be related to the latter. At this time, a software-based soft error detection method means that there is no change in hardware or that the change is only minimal. The soft error detection method 100 and processor 200 according to an embodiment of the present invention detect soft errors based on software, and can accurately detect soft errors without using conditional calculation operations.

The processor 200 according to an embodiment of the present invention includes a processor core 220, a compiler 240, instruction blocks (BK1 to BKn), and a soft error detection unit 260, and detects soft errors according to an embodiment of the present invention. The detection method 100 can accurately detect soft errors. The processor 200 may be a central processing unit, an application processor, or a dedicated processor such as a graphics processor, a data processor, and a communication processor. The processor 200 according to an embodiment of the present invention may be included in various processor-based devices or systems. For example, the processor 200 according to an embodiment of the present invention may be included in a navigation device, a communication device, a mobile phone, a computer, a portable computer, etc.

The processor core 220 executes a first instruction set (CS1) including a copy branch instruction (CBC) and a second instruction set (CS2) including an original branch instruction (OBC) (S140, S180). The processor core 220 is based on the Instruction Set Architecture (ISA) of RISC-V (Reduced Instruction Set Computer-V) and can process original instructions and duplicate instructions for executing required applications. Alternatively, the processor core 220 may execute an application based on a Complex Instruction Set Computer (CISC) or Advanced RISC Machine (ARM) structure.

The processor core 220 may include an arithmetic logic unit (ALU), a register set, and a controller for executing original instructions and duplicate instructions. The processor core 220 may be provided as a multi-core.

The compiler 240 converts the source code of the application into machine language so that the processor core 220 can execute the original instructions. The duplicate instruction may be generated through duplication of the original instruction converted into a machine language or assembly language version by the compiler 240 (S120). That is, replication of the original instruction into a duplicate instruction may be performed by the compiler 240. The same applies to the original branch instruction (OBC) and clone branch instruction (CBC), which belong to the original instruction and clone instruction, respectively.

The compiler 240 may perform compilation at runtime. The compiler 240 may be logic implemented as hardware such as circuits, programmable logic, etc., firmware, software, or a combination thereof. The compiler 240 may also decompose the application into a plurality of instruction blocks (BK1 to BKn) and perform numbering for each instruction block (BK1 to BKn) to optimize execution of the application. For example, each instruction block (BK1 to BKn) may be numbered as a first instruction block (BK1) to an n-th instruction block (BKn).

To optimize the operation of the compiler 240, a control flow graph representing all paths that can be traversed during execution of an application may be used. Each instruction block (BK1 to BKn) can be processed in the form of a node in the control flow graph.

The instruction blocks (BK1 to BKn) represent the flow of instructions for executing an application required by the processor 200. Instruction blocks (BK1 to BKn) each contain at least an 'ADD' instruction, a 'MULT' instruction, a 'XOR' instruction, a 'STR' instruction, a 'JUMP' instruction, a 'BRANCH' instruction, a 'COMPARE' instruction, and a 'MOV' instruction. It may contain one or more instructions. The instruction blocks (BK1 to BKn) may be basic blocks. In this case, instruction blocks (BK1 to BKn) can be divided into entry points and exit points. In other words, the instruction block (BK1 to BKn) can be defined as a straight code string with no branches entering the corresponding instruction block (BK1 to BKn) other than the entry point, and no branch exiting other than the exit point. . However, if the instruction block (BK1 to BKn) includes a branch instruction, it can be exited through the branch instruction.

The soft error detection unit 260 determines whether an error exists in the execution of the first command set (CS1) and the second command set (CS2) (S180). That is, the soft error detection unit 260 determines whether an error exists in the execution of the replication branch instruction (CBC) from the execution result of the first instruction set (CS1) (S160), and determines whether the first instruction set (CS1) and the second instruction are Based on the execution result of the set (CS2), it can be determined whether an error exists in the execution of the original branch instruction (OBC) (S150). The soft error detection unit 260 may output a determination result of whether an error exists in the execution of the first command set (CS1) and the second command set (CS2) as an error detection signal (XED).

The soft error detection unit 260 may be logic implemented by hardware such as a circuit, programmable logic, firmware, software, or a combination thereof. Figure 2 shows an example in which the soft error detection unit 260 is provided as a separate module from the compiler 240. However, it is not limited to this.

FIG. 5 is a diagram showing the processor 200 according to an embodiment of the present invention in which the soft error detection unit 260 is integrated with the compiler 240.

Referring to FIG. 5, the soft error detection unit 260 of the processor 200 according to an embodiment of the present invention may be provided as an integrated module with the compiler 240. At this time, the soft error detection unit 260 performs error handling for at least one of the three phases constituting the compiler 240, that is, the front end, optimizer, and back end. It can be implemented with logic.

Referring again to FIGS. 1 to 3, the current instruction block (CBK) can be divided into four areas. At this time, the first command set CS1 may be located in the second area RG2, and the second command set CS2 may be located in the fourth area RG4. In addition to the second area RG2 and the fourth area RG4, other commands other than the first command set CS1 and the second command set CS2 may be located.

The first signature value (SIG1) represents a unique signature value for the current instruction block (CBK). The unique signature value can be set to a unique value for each instruction block (BK1 to BKn). For example, the unique signature value for the first instruction block (BK1) and the unique signature value for the second instruction block (BK2) may be set differently.

The soft error detection method 100 and the processor 200 according to an embodiment of the present invention can more accurately detect soft errors by using the global signature value corresponding to the unique signature value. Hereinafter, a method for detecting soft errors using a unique signature value according to an embodiment of the present invention will be described in detail.

FIG. 6 is a diagram showing a soft error detection method 100 according to an embodiment of the present invention, and FIG. 7 is a diagram showing a current instruction block (CBK) and a branch instruction block (BBK) according to an embodiment of the present invention.

Referring to FIGS. 6 and 7, the soft error detection method 100 of FIG. 6, similar to FIG. 1, includes a step of replicating the original branch instruction (OBC) to a replication branch instruction (CBC) (S120), and a replication branch instruction ( Executing the first instruction set (CS1) including the CBC (S140), executing the second instruction set (CS2) including the original branch instruction (OBC) (S160), and the first instruction set (S160) It includes a step (S180) of determining whether an error exists in the execution of the original branch instruction (OBC) based on whether an error exists in the execution of the CS1) and the second instruction set (CS2). Furthermore, the soft error detection method 100 of FIG. 6 may further include a step (S130) of determining whether an error exists in the execution of the copy branch instruction (CBC) before and after executing the first instruction set (CS1). .

In the step (S130) of determining whether an error exists in the execution of the replication branch instruction (CBC), the error can be detected using the global signature value. To this end, the step of determining whether an error exists in the execution of the replication branch instruction (CBC) (S130) includes the step of damaging the global signature value (GSR) for the current instruction block (CBK) (S132), and restoring a damaged global signature value (GSR) (S134). The step S130 of determining whether an error exists in the execution of the copy branch instruction (CBC) may be performed by the soft error detection unit 260.

As described above, according to an embodiment of the present invention, a unique signature value is assigned to each instruction block. For example, the unique signature value for the current instruction block (CBK) is set to the first signature value (SIG1), and the unique signature value for the first branch instruction block (BBK1) is set to the 2-1 signature value (SIG2- 1), and the unique signature value for the second branch instruction block (BBK2) may be set to the 2-2 signature value (SIG2-2).

The global signature value (GSR) may be the same value as the first signature value (SIG1) of the current command block (CBK) in which the command is executed at the current time. The global signature value (GSR) can be updated with the unique signature value of the instruction block that changes at the time the instruction block in which the instruction is executed changes. The global signature value (GSR) may be stored in one of the processor registers (not shown) included in the processor 200 of FIG. 2.

The step of subtracting the damage value (DV) from the global signature value (GSR) (S132), that is, the subtraction instruction for subtracting the damage value (DV) from the global signature value (GSR), may be executed before the first instruction set (CS1). At this time, the subtraction instruction for subtracting the damage value (DV) from the global signature value (GSR) may be located in the second region RG2 along with the first instruction set (CS1).

Damage value (DV) can be set to a value that satisfies the following conditions. First, the damaged global signature value (GSR) must not overlap with the unique signature value of other instruction blocks included in the application. For example, if the unique signature values of the command blocks included in the application are set to have a difference of "100", the damage value (DV) must be set to a value other than "100". Second, the damage value (DV) should not overlap with the damage values of other instruction blocks included in the application. For example, if the damage value in the first instruction block is "10", the damage value in the second instruction block must be set to a value other than "10".

After corrupting the global signature value (GSR), the first instruction set (CS1) may be executed (S140).

Figure 8 is a diagram showing a step (S140) of executing the first instruction set (CS1) according to an embodiment of the present invention.

Referring to Figures 7 and 8, the step (S140) of executing the first instruction set (CS1) according to an embodiment of the present invention is to set a runtime signature value (RTS) to the first value (VA1). Setting step (S141), executing the replication branch instruction (CBC) (S142), if the branch condition of the replication branch instruction (CBC) is satisfied (“Y” in S143), the runtime signature value (RTS) is set to the first value. A step of maintaining (VA1) (S144) and, if the branch condition of the replication branch instruction (CBC) is not satisfied (“N” in S143), changing the runtime signature value (RTS) to a second value (VA2) ( S145) may be included.

The runtime signature value (RTS) may be a value representing the difference between the unique signature value of the current instruction block (CBK) and the branch instruction block (BBK). At this time, the first value VA1 is an exclusive OR value of the unique signature values of the current instruction block CBK and the first branch instruction block BBK1, and the second value VA2 is a value obtained by exclusive ORing the unique signature values of the current instruction block CBK and the first branch instruction block BBK1. It may be an exclusive OR value of the unique signature value of the second branch instruction block (BBK2). That is, the first value VA1 is set by exclusive ORing the first signature value (SIG1) of the current instruction block (CBK) and the 2-1 signature value (SIG2-1) of the first branch instruction block (BBK1). You can.

The first value VA1 may be set prior to execution of the replication branch instruction (CBC) (S141). As described above, the runtime signature value (RTS) may be stored in one of the processor registers (not shown) of the processor 200 of FIG. 2. In the present application, changing the runtime signature value (RTS) to the second value (VA2) (S145) does not mean changing the value of the register storing the runtime signature value (RTS), but storing it in a different register. This may be interpreted to mean that the second value VA2 stored in one of the first value VA1 and the second value VA2 of the runtime signature value RTS is used.

In the step S142 of executing the replication branch instruction (CBC), the value of the program counter may vary depending on whether the replication branch condition is established. For example, a first duplicate value (R1*) that duplicates the first original value (R1) stored in the first register and a second duplicate value (R2*) that duplicates the second original value (R2) stored in the second register. ) is equal, the program counter can branch to an arbitrary area of the current instruction block (CBK). For example, by executing a replication branch instruction (CBC), the program counter may branch to the third region (RG3) between the first instruction set (CS1) and the second instruction set (CS2) (S146). On the other hand, when the first replication value (R1*) and the second replication value (R2*) are different, the program counter may indicate the location of the next instruction of the replication branch instruction (CBC). Accordingly, the step (S145) of changing the above-described runtime signature value (RTS) to the second value (VA2) may be performed.

Referring again to FIGS. 6 and 7, the step (S130) of determining whether an error exists in the execution of the copy branch instruction (CBC) according to an embodiment of the present invention is performed after the first instruction set (CS1) is executed, A step (S134) of restoring a damaged global signature value (GSR) may be included. For example, a damaged global signature value (GSR) can be restored by adding a restoration value (RV). The addition instruction for adding the restoration value (RV) to the damaged global signature value (GSR) may be executed before the second instruction set (CS2).

The addition instruction for adding the restoration value (RV) to the damaged global signature value (GSR) may be located in the fourth region (RG4) of the current instruction block (CBK) along with the second instruction set (CS2). The restoration value (RV) may be the same as the damage value (DV). In this case, the restoration value (RV) may be subject to the same conditions as the damage value (DV).

The step (S130) of determining whether an error exists in the execution of a replication branch instruction (CBC) according to an embodiment of the present invention is a step of comparing the global signature value (GSR) before damage and the global signature value (GSR) after restoration. (S136) may be further included. If damage and restoration of the global signature value (GSR) are performed normally, the global signature value (GSR) for the current instruction block (CBK) after restoration may be the same as the global signature value (GSR) before damage. On the other hand, if the global signature value (GSR) before damage and after restoration is not the same, it may be detected that an error in the replication branch instruction (CBC) exists. This will be explained.

Figures 9A to 9C are diagrams showing the movement position of the program counter when an error occurs in the copy branch instruction (CBC) according to an embodiment of the present invention.

First, referring to FIGS. 6 and 9A, when an error occurs in the replication branch instruction (CBC), the program counter branched by the replication branch instruction (CBC) is in the third region (RG3) of the current instruction block (CBK). It may be moved to the first area RG1. As described above, when the replication branch instruction (CBC) is executed normally, the program counter may move to the third region (RG3). The third area RG3 may be provided between the second area RG2 where the first instruction set CS1 is located and the fourth area RG4 where the second instruction set CS2 is located. Accordingly, the step of damaging the global signature value (GSR) (S132) and the step of restoring the damaged global signature value (GSR) (S134) may not be executed normally once.

Therefore, by comparing the global signature value (GSR) before damage and after restoration (S136), an error in the replication branch instruction (CBC) can be detected. For example, as an error exists in the replication branch instruction (CBC) and the program counter is moved to the first region rather than the third region (RG3), the step (S132) of corrupting the global signature value (GSR) is performed twice. The step S134 of restoring the damaged global signature value (GSR) may be executed once. Accordingly, when the damage value (DV) and the restored value (RV) are “10”, the global signature value (GSR) before damage may be greater than the restored global signature value (GSR) by “10”.

Next, referring to FIGS. 6 and 9B, due to a soft error, the program counter branched by the copy branch instruction (CBC) is moved to the fourth region (RG4) rather than the third region (RG3) of the current instruction block (CBK). can be moved As the program counter is moved to the fourth region due to an error in the replication branch instruction (CBC), the step S132 for corrupting the global signature value (GSR) is executed once and restores the corrupted global signature value (GSR). The command step (S134) may not be executed even once. Accordingly, when the damage value (DV) and the restored value (RV) are “10”, the global signature value (GSR) before damage may be greater than the restored global signature value (GSR) by “10”.

Next, referring to FIGS. 6 and 9C, due to a soft error, the program counter branched by the replication branch instruction (CBC) is not in the third region (RG3) of the current instruction block (CBK), but is in the replication branch instruction (CBC). It may be moved to the second area RG2 where the first command set CS1 including . For example, the program counter may be moved to a position before or after the replication branch instruction (CBC) in the second region (RG2). In this case, the step of damaging the global signature value (GSR) (S132) may be executed once, and the step of restoring the damaged global signature value (GSR) (S134) may not be executed once. Accordingly, when the damage value (DV) and the restored value (RV) are “10”, the global signature value (GSR) before damage may be greater than the restored global signature value (GSR) by “10”.

Referring again to FIGS. 6 and 7, the soft error detection method 100 according to an embodiment of the present invention restores a damaged global signature value (GSR) and then executes a second instruction including an original branch instruction (OBC). Set (CS2) can be executed (S160). As a result of executing the second instruction set (CS2), if the first original value (R1) of the first register and the second original value (R2) of the second register are the same, it is moved to the first branch instruction block (BBK1) ( Branch if (R1 == R2) BBK1), otherwise it can be moved (Jump BBK2) to the second branch instruction block (BBK2). This may be a control flow that cannot enter the first branch instruction block BBK1 or the second branch instruction block BBK2 except through a BRANCH instruction or JUMP instruction in the current instruction block CBK. Therefore, if the first original value (R1) and the second original value (R2) are the same, the program counter is branched to the first branch instruction block (BBK1), and if not the same, the program counter is moved to the second branch instruction block (BBK2). You can.

Figure 10 is a diagram showing a step (S180) of determining whether an error exists in the execution of an original branch instruction (OBC) according to an embodiment of the present invention.

Referring to FIGS. 6, 7, and 10, when execution of the second instruction set (CS2) is completed (S120 to S160), the soft error detection method 100 according to an embodiment of the present invention detects the first instruction set Based on the execution results of the (CS1) and the second instruction set (CS2), an operation is performed to determine whether an error exists in the execution of the original branch instruction (OBC) (S180). The step (S180) of determining whether an error exists in the execution of the original branch instruction (OBC) may be performed using the global signature value (GSR) and runtime signature value (RTS) in the branch instruction block (BBK).

For example, the step of determining whether an error exists in the execution of the original branch instruction (OBC) (S180) includes the step of exclusive ORing the global signature value (GSR) and the runtime signature value (RTS) (S182), and the exclusive OR of the global signature value (GSR) and the runtime signature value (RTS). A step (S184) of comparing a result with unique signature values (SIG2-1, SIG2-2) for the branch instruction block (BBK) and error detection results for execution of the original branch instruction (OBC) based on the comparison result. It may include a step of generating (S186).

For example, if the branch condition of the original branch instruction (OBC) is satisfied and you want to branch to the first branch instruction block (BBK1), the first value (VA1) of the global signature value (GSR) and runtime signature value (RTS) The result of exclusive ORing can be compared with the 2-1 signature value (SIG2-1) of the first branch instruction block (BBK1). Or, if the branch condition of the original branch instruction (OBC) is not satisfied and you want to move to the second branch instruction block (BBK2), the second value (VA2) of the global signature value (GSR) and runtime signature value (RTS) The result of exclusive ORing can be compared with the 2-1 signature value (SIG2-1) of the second branch instruction block (BBK2).

The global signature value (GSR) that is exclusive-ORed with the runtime signature value (RTS) may be the same as the first signature value (SIG1) because the program counter still represents the current instruction block (CBK) at the time of performing the exclusive-OR. You can. The error detection result according to the comparison result may be an error detection signal (XED) output from the soft error detection unit 260 of FIG. 2.

In this way, according to the soft error detection method 100 according to an embodiment of the present invention, both the data flow and the control flow can be protected by utilizing the redundancy of the data flow. The same applies to the processor 200 of FIG. 2 to which the soft error detection method 100 according to an embodiment of the present invention is applied.

That is, in order to prevent the vulnerability of the original branch instruction (OBC), that is, errors in the control flow from not being detected, the soft error detection method 100 according to an embodiment of the present invention duplicates the original branch instruction (OBC). A clone branch instruction (CBC) allows you to create a kind of right-of-way to the branch instruction block (BBK) that you want to branch to by the original branch instruction (OBC). A kind of right of passage can represent the basis for determining whether an error has occurred and the branch instruction block (BBK) can be entered normally. A type of right-of-way can be created by unique signature values (SIG1, SIG2-1, SIG2-2), global signature values (GSR), and runtime signature values (RTS).

In this case, for example, even though the first original value (R1) and the second original value (R2) are the same and must be moved to the first branch instruction block (BBK1), the first original value is lost due to a soft error occurring in the data flow. Even if (R1) is damaged and the first original value (R1) and the second original value (R2) are not the same and are incorrectly moved to the second branch instruction block (BBK2), an error in the control flow can be detected. In other words, execution (S140) of the first instruction set (CS1) and execution (S160) of the second instruction set (CS2) according to an embodiment of the present invention may be performed independently of each other. That is, the result (S140) of executing the first instruction set (CS1) may not affect the result (S160) of executing the second instruction set (CS2).

Additionally, since error detection (S130) for the copy branch instruction (CBC) is performed separately, soft errors for the original branch instruction (OBC) can be more accurately detected. If an error occurs in the replication branch instruction (CBC), the right-of-way itself is created incorrectly, so it may be difficult to accurately detect the error. On the other hand, the replication branch instruction (CBC) is also a branch instruction and may have a high vulnerability to the errors described above.

The soft error detection method 100 according to an embodiment of the present invention solves the vulnerability caused by soft error detection in an instruction set structure that does not support conditional calculation instructions such as RISC-V by using the most basic instructions, addition and subtraction instructions. You can. The same applies to the processor 200 of FIG. 2 to which the soft error detection method 100 according to an embodiment of the present invention is applied.

Conditional calculation instructions refer to instructions that conditionally update register values, such as 'move_equal', 'move_notEqual', etc. In the case of an instruction set structure in which conditional instructions are supported, there is no vulnerability to replication branch instructions (CBC), because the operations required to execute conditional instructions are operations on the data flow. To perform conditional instructions, a conditional exclusive OR operation and a conditional register copy operation may be required. Therefore, even if a soft error occurs in a conditional instruction, the program counter does not change like in jump and branch operations. As described above, in the case of a control flow that causes a change in the program counter, there may be a higher vulnerability to errors compared to a data flow.

Although not shown, the program counter branched by the copy branch instruction (CBC) may be moved to an instruction block other than the current instruction block (CBK) due to a soft error. In this case, the error can be detected by a method for detecting errors in the original command, which will be described later. Additionally, depending on the operation mode of the processor core 220 of FIG. 2, a step (S130) of determining whether an error exists in the execution of the copy branch instruction (CBC) of FIG. 6 or the like may be selectively performed. For example, if the error occurrence rate is stable below the reference value in any operation mode, the original branch is performed on the assumption that the replication branch instruction (CBC) was executed normally without performing an error check on the replication branch instruction (CBC). Instructions (OBC) can be executed.

FIG. 11 is a diagram showing a soft error detection method 100 according to an embodiment of the present invention, and FIG. 12 shows a current instruction block (CBK) and a branch instruction block (BBK) operating with the soft error detection method 100 of FIG. 11. ) This is a drawing showing.

11 and 12, the soft error detection method 100 according to an embodiment of the present invention includes a step of damaging the global signature value (GSR) of the current instruction block (CBK) (S132), and an original branch instruction (OBC). ) and executing a replication branch instruction (CBC) with the same branch conditions (S142-2), restoring the damaged global signature value (GSR) (S134), the value before damage and after restoration of the global signature value (GSR). It may include comparing values (S136) and detecting whether an error exists in the execution of the replication branch instruction (CBC) based on the comparison result (S138). The soft error detection method 100 according to an embodiment of the present invention can also perform the following operations.

FIG. 12 shows a case where the damage value (DV) and restoration value (RV) are each “10”. In addition, the first signature value (SIG1) of the current instruction block (CBK) is "00110000", the 2-1 signature value (SIG2-1) for the first branch instruction block (BBK1) is "01100000", and the The 2-2 signature value (SIG2-2) for the second branch instruction block (BBK2) may be set to “10000000”. Accordingly, the global signature value (GSR) representing the unique signature value of the current instruction block (CBK) indicated by the current point in time, that is, the program counter, may also be set to “00110000”.

Before the first instruction set (CS1) including the replication branch instruction (CBC) is executed, the global signature value (GSR) can be damaged by subtracting "10" from the global signature value (GSR) (S132). . In this case, the corrupted global signature value (GSR) becomes “00101100”. After the replication branch instruction (CBC) is executed. The global signature value (GSR) is restored by adding a restoration value (RV) “10” to the damaged global signature value (GSR) “00101100” (S134). As a result of comparing the global signature value (GSR) before damage and the restored global signature value (GSR) (S136), the values are all the same as "00110000", so there is no error in the execution of the replication branch instruction (CBC). It can be judged that it is (S138).

At this time, before executing the replication branch instruction (CBC), the unique signature value of the current instruction block (CBK) where the replication branch instruction (CBC) is executed and the branch instruction block (BBK) branched by the original branch instruction (OBC). A runtime signature value (RTS) indicating the difference may be set as the first value (S141). Figure 12 shows an example where the first value is “01010000”. When the branch condition is satisfied, that is, when the first replication value (R1*) and the second replication value (R2*) are the same, the program counter may be moved to the third region (RG3) of the current instruction block (CBK). At this time, the runtime signature value (RTS) is confirmed as the first value, “01010000” (S144).

On the other hand, if the branch condition is not satisfied as a result of executing the replication branch instruction (CBC), the runtime signature value (RTS) is changed to a second value that is different from the first value (S145). In other words, if the branch condition of the replication branch instruction (CBC) is not satisfied, that is, if the first replication value (R1*) and the second replication value (R2*) are different, the program counter is incremented by one and the runtime signature value ( RTS) is confirmed as the second value, “10110000”. The first value of the runtime signature value (RTS) may correspond to the 2-1 branch instruction block BBK1, and the second value may correspond to the 2-2 branch instruction block BBK2.

Based on the runtime signature value (RTS) determined as a result of execution of the copy branch instruction (CBC), it can be detected whether an error exists in the execution of the original branch instruction (OBC) (S180-2).

First, the original branch instruction (OBC) is executed. When the branch condition of the original branch instruction (OBC) is satisfied, that is, when the first original value (R1) and the second original value (R2) are the same, the program count will be moved to the first branch instruction block (BBK1). At this time, exclusive OR is performed on the global signature value (GSR) “00110000” and the runtime signature value (RTS) “01010000”. It can be seen that the result of the exclusive OR is “01100000”, which is the same as the 2-1 signature value (SIG2-1) for the first branch instruction block (BBK1) to be branched. Accordingly, it can be confirmed that there is no error in the execution of the original branch instruction (OBC).

If an error exists in the first original value (R1) and the first original value (R1) and the second original value (R2) are treated as different, the program counter is converted to the second branch instruction according to the execution of the original branch instruction (OBC). It will be moved to block (BBK2). However, "01100000", which is the result of exclusive OR for the global signature value (GSR) "00110000" and the runtime signature value (RTS) "01010000", is the 2-2 command for the second branch instruction block (BBK2) to be branched. It is different from the signature value (SIG2-2) “10000000”. Accordingly, it may be detected that an error occurred in the execution of the original branch instruction (OBC).

Figures 11 and 12 may be an example of a case where CHITIN (Comprehensive In-Thread Instruction replication technique against transient faults), one of the software-based instruction duplication techniques, is applied. However, it is not limited to this. The soft error detection method according to an embodiment of the present invention can be applied to various software-based instruction duplication techniques other than CHITIN.

FIG. 13 is a diagram showing a soft error detection method 100 according to an embodiment of the present invention, and FIG. 14 shows the current instruction block (CBK) and branch instruction block (BBK) operating with the soft error detection method 100 of FIG. 13. ) This is a drawing showing.

13 and 14, the soft error detection method 100 according to an embodiment of the present invention includes a step of damaging the global signature value (GSR) of the current instruction block (CBK) (S132), and an original branch instruction (OBC). ) and executing replication branch instructions (CBC) with different branch conditions (S142-4), restoring the damaged global signature value (GSR) (S134), the value before damage and after restoration of the global signature value (GSR) It may include comparing values (S136) and detecting whether an error exists in the execution of the replication branch instruction (CBC) based on the comparison result (S138). The soft error detection method 100 according to an embodiment of the present invention can also perform the following operations.

The unique signature values (SIG1, SIG2-1, SIG2-2), global signature values (GSR), and runtime signature values (RTS) for the current instruction block (CBK) and branch instruction block (BBK) in Figure 14 are all shown in Figure 14. It may be equal to 12. However, in the case of FIGS. 13 and 14, the branch conditions of the original branch instruction (OBC) and the branch conditions of the copy branch instruction (CBC) are different. For example, if the original branch instruction (OBC) is a branch condition that determines whether the first original value (R1) and the second original value (R2) are the same, the replication branch instruction (CBC) is the first replication value (R1*). And whether the second replication value (R2*) is different may be a branching condition.

Before the first instruction set (CS1) including the replication branch instruction (CBC) is executed, the global signature value (GSR) can be damaged by subtracting "10" from the global signature value (GSR) (S132). . In this case, the corrupted global signature value (GSR) becomes “00101100”. After the replication branch instruction (CBC) is executed. The global signature value (GSR) is restored by adding a restoration value (RV) “10” to the damaged global signature value (GSR) “00101100” (S134). As a result of comparing the global signature value (GSR) before damage and the restored global signature value (GSR) (S136), the values are all the same as "00110000", so there is no error in the execution of the replication branch instruction (CBC). It can be judged that it is (S138).

At this time, if the branch condition of the replication branch instruction (CBC) is not satisfied, the runtime signature value (RTS) may be set as the first value. For example, if the first replication value (R1*) and the second replication value (R2*) are the same and the branch condition of the replication branch instruction (CBC) is not satisfied, the runtime signature value (RTS) is the first value. It can be confirmed as “01010000”. On the other hand, if the branch condition of the replication branch instruction (CBC) is satisfied and the branch condition of the original branch instruction (OBC) is not satisfied as a result of execution of the original branch instruction (OBC), the runtime signature value (RTS) is the first value. It may be set to a second value different from (S145-2). For example, if the first replication value (R1*) and the second replication value (R2*) are different and the first original value (R1) and the second original value (R2) are not the same, the runtime signature value (RTS ) can be confirmed as the second value, “10110000”.

That is, the position in the current instruction block (CBK) for the first value "01010000" among the runtime signature values (RTS) is set after the replication branch instruction (CBC), and the second value "10110000" among the runtime signature values (RTS). The position in the current instruction block (CBK) for may be set after the original branch instruction (OBC).

In addition, an operation (S180- 4) may be the same as the case of FIGS. 11 and 12 described above. Figures 13 and 14 may be an example of when SWIFT (Software Implemented Fault Tolerance), one of the software-based instruction duplication techniques, is applied.

Although representative embodiments of the present invention have been described in detail above, those skilled in the art will understand that various modifications can be made to the above-described embodiments without departing from the scope of the present invention. . For example, in the above, the step (S132) of corrupting the global signature value (GSR) is performed by subtracting the corruption value (DV) from the global signature value (GSR), and adding this to the restoration value (RV) to obtain the damaged global signature. Although it has been described that the step (S134) of restoring the value (GSR) is performed, it is not limited thereto. According to the soft error detection method 100 and the processor 200 according to an embodiment of the present invention, a step (S132) of corrupting the global signature value (GSR) by adding a corruption value (DV) to the global signature value (GSR). is performed, and a step (S134) of restoring the damaged global signature value (GSR) by subtracting it from the restoration value (RV) may be performed. Furthermore, the step of damaging the global signature value (GSR) (S132) and the step of restoring the damaged global signature value (GSR) (S134) involve damage and restoration operations through various operations such as division or multiplication in addition to subtraction or addition. You can also perform .

Therefore, the scope of the present invention should not be limited to the described embodiments, but should be determined not only by the claims described later but also by equivalents to the claims.

100: Soft error detection method
200: processor
OBC, CBC: Original branch instruction, replication branch instruction
CBK, BBK: Current instruction block, branch instruction block
XED: Error detection signal
SIG: Unique signature value
GSR: Global signature value
RTS: Runtime signature value

Claims (20)

replicating the original branch instruction into a duplicate branch instruction;
executing a first set of instructions including the replication branch instruction;
executing a second instruction set including the original branch instruction; and
A soft error detection method including; determining whether an error exists in execution of the original branch instruction based on execution results of the first instruction set and the second instruction set. In claim 1,
Before and after executing the first instruction set, determining whether an error exists in execution of the replication branch instruction using a global signature value for the current instruction block in which the first instruction set is executed; soft error further comprising: Detection method. According to clause 2,
The step of determining whether an error exists in the execution of the replication branch instruction is:
Corrupting the global signature value; and
A soft error detection method comprising: restoring the damaged global signature value. According to clause 2,
The step of damaging the global signature value is,
Comprising: subtracting a corruption value from the global signature value,
The step of restoring the damaged global signature value is,
A soft error detection method comprising adding a restored value to the damaged global signature value. According to clause 4,
The damage value and the restoration value are,
Soft error detection methods that are identical to each other and each set to a unique value. According to clause 2,
The step of determining whether an error exists in the execution of the replication branch instruction is:
A soft error detection method further comprising comparing the global signature value before damage and the global signature value after restoration. According to claim 1,
A soft error detection method that selectively performs the step of determining whether an error exists in execution of the replication branch instruction based on the operation mode. According to claim 1,
The step of executing the first instruction set is:
Setting a runtime signature value corresponding to a branch instruction block branched by execution of the original branch instruction to a first value;
executing the replication branch instruction;
maintaining the runtime signature value as the first value when the branch condition of the replication branch instruction is satisfied; and
If the branch condition of the replication branch instruction is not satisfied, changing the runtime signature value from the first value to the second value. According to clause 8,
The first value is,
It is an exclusive OR value of a unique signature value for the current instruction block in which the replication branch instruction is executed and a unique signature value of one of the branch instruction blocks branched as a result of execution of the second instruction set,
The second value is,
A soft error detection method in which the value is an exclusive OR of the unique signature value for the current instruction block and the unique signature value of another one of the branch instruction blocks. According to clause 8,
The step of executing the first instruction set is:
If the branch condition of the replication branch instruction is satisfied, moving the program counter of the current instruction block in which the replication branch instruction is executed to an area located between the first instruction set and the second instruction set of the current instruction block. A soft error detection method further including ;. According to clause 8,
The runtime signature value is,
A soft error detection method that indicates the difference between the unique signature value of the current instruction block and the branch instruction block. According to claim 1,
The step of executing the second instruction set is,
moving to a first branch instruction block among branch instruction blocks when the branch condition of the original branch instruction is satisfied; and
A soft error detection method comprising: moving to a second branch instruction block among the branch instruction blocks if the branch condition of the original branch instruction is not satisfied. According to claim 12,
The step of determining whether an error exists in the execution of the original branch instruction is:
Exclusively ORing a global signature value for the current instruction block and a runtime signature value corresponding to the first branch instruction block or the second branch instruction block;
Comparing the exclusive OR value with a unique signature value of the first branch instruction block or the second branch instruction block; and
A soft error detection method comprising: generating an error detection result for execution of the original branch instruction based on the comparison result. According to claim 1,
A soft error detection method in which execution of the first instruction set and execution of the second instruction set are performed independently of each other. According to claim 1,
The soft error detection method is,
A soft error detection method applied to CHITIN (Comprehensive In-Thread Instruction replication technique against transient faults) or SWIFT (Software Implemented Fault Tolerance) among software-based instruction duplication techniques. According to claim 1,
The soft error detection method is,
A soft error detection method performed on a processor operating with an instruction set architecture that does not support instructions that conditionally update register values. A processor that operates using the soft error detection method of claim 1 and outputs an error detection signal when an error exists in execution of the original branch instruction. Corrupting the global signature value of the current instruction block;
executing a replication branch instruction corresponding to the original branch instruction;
restoring the damaged global signature value;
Comparing a value before damage and a value after restoration of the global signature value; and
A soft error detection method comprising: detecting whether an error exists in execution of the replication branch instruction based on the comparison result. According to clause 18,
The replication branch instruction has the same branch conditions as the original branch instruction,
Before executing the replication branch instruction, a runtime signature value indicating the difference between the unique signature value of the current instruction block in which the replication branch instruction is executed and the branch instruction block branched by the original branch instruction is set to the first value. steps;
As a result of executing the replication branch instruction, if the branch condition of the replication branch instruction is satisfied, the runtime signature value is maintained as the first value, and if the branch condition of the replication branch instruction is not satisfied, the runtime signature value is maintained. changing to a second value different from the first value; and
A soft error detection method further comprising detecting whether an error exists in execution of the original branch instruction based on the runtime signature value according to an execution result of the duplicate branch instruction. According to clause 18,
The replication branch instruction has different branch conditions from the original branch instruction,
If the branch condition of the replication branch instruction is not satisfied, a runtime signature value indicating the difference between the unique signature value of the current instruction block in which the replication branch instruction is executed and the branch instruction block branched by the original branch instruction, setting it to a value of 1;
As a result of executing the original branch instruction, if the branch condition of the original branch instruction is not satisfied, changing the runtime signature value to a second value different from the first value; and
A soft error detection method further comprising: detecting whether an error exists in execution of the original branch instruction based on the runtime signature value according to the execution result of the branch instruction and the original branch instruction.