KR20240027504A - Printed circuit board - Google Patents

Abstract

The present disclosure includes a first insulating layer, a through hole penetrating between the upper and lower surfaces of the first insulating layer, a first via filling at least a portion of the through hole, a first pad connected to the upper side of the first via, and It includes a second pad connected to the lower side of the first via, the diameter at the uppermost side of the through hole is larger than the width of the first pad, and at least a portion of the upper surface of the first via exposed from the first pad is the first via. 1 This relates to a printed circuit board that is recessed below the top surface of the insulating layer.

Description

Printed circuit board {PRINTED CIRCUIT BOARD}

This disclosure relates to printed circuit boards.

Recently, with the improved performance of electronic devices, the number of circuits and vias for signal transmission within the board is rapidly increasing, and accordingly, boards with high multi-layers and large areas are required. For example, as the number of signal transmission circuits rapidly increases, the design of vias and circuits increases, and as the area of the board increases, the number of layers of the board increases.

Meanwhile, in order to reduce the area of the substrate and reduce the number of layers, it is necessary to implement microcircuits and increase the degree of integration by reducing the via size, but there are still limitations in reducing the scale of the core insulating layer of the substrate.

One of the many purposes of the present disclosure is to provide a printed circuit board that can increase integration, reduce area, and reduce the number of layers.

Another object of the present disclosure is to provide a printed circuit board that can improve the reliability of a through via formed in a core insulating layer.

One of several solutions proposed through the present disclosure is to form the uppermost and/or lowermost diameter of the through hole formed in the core insulating layer to be larger than the width of the pad of the through via that fills the through hole, and also to form the uppermost and/or lowermost diameter of the through hole formed in the core insulating layer to be larger than the width of the pad of the through via that fills the through hole. A groove is formed on the side and/or bottom side to recess at least a portion of the upper and/or lower surface of the through via.

For example, a printed circuit board according to one example includes a first insulating layer; a through hole penetrating between the upper and lower surfaces of the first insulating layer; a first via filling at least a portion of the through hole; a first pad connected to the upper side of the first via; and a second pad connected to the lower side of the first via; It includes, the diameter at the uppermost side of the through hole is larger than the width of the first pad, and at least a portion of the upper surface of the first via exposed from the first pad is recessed below the upper surface of the first insulating layer. It could be.

Another of the several solutions proposed through the present disclosure is to form the uppermost and/or lowermost diameter of the through hole formed in the core insulating layer to be larger than the width of the pad of the through via that fills the through hole, and also to The width of the pad is formed to be larger than the width of the pad of the connection via that fills the via hole formed in the build-up insulating layer.

For example, a printed circuit board according to one example includes a core insulating layer; a through via that fills at least a portion of a through hole penetrating the core insulating layer; a first pad connected to an upper side of the through via; a second pad connected to the lower side of the through via; a first build-up insulating layer disposed on an upper surface of the core insulating layer and covering at least a portion of the first pad; a first connection via that fills at least a portion of the first via hole penetrating the first build-up insulating layer; and a third pad connected to the upper side of the first connection via; A diameter at the uppermost side of the through hole may be greater than the width of the first pad, and the width of the first pad may be greater than the width of the third pad.

As one of the many effects of the present disclosure, a printed circuit board can be provided that can increase integration, reduce area, and reduce the number of layers.

As another effect among the various effects of the present disclosure, a printed circuit board capable of improving the reliability of a through via formed in a core insulating layer can be provided.

1 is a block diagram schematically showing an example of an electronic device system.
Figure 2 is a perspective view schematically showing an example of an electronic device.
Figure 3 is a cross-sectional view schematically showing an example of a printed circuit board.
Figure 4 is a schematic cross-sectional view taken along line AA' of the printed circuit board of Figure 3.
5 to 10 are process diagrams schematically showing an example of manufacturing a through via and first and second pads formed in the core insulating layer of the printed circuit board of FIG. 3.
FIG. 11 is a cross-sectional image showing a comparison of the shapes of through vias and their pads according to and without the present disclosure.
Figure 12 is a cross-sectional view schematically showing another example of a printed circuit board.
Figure 13 is a schematic cross-sectional view taken along line BB' of the printed circuit board of Figure 12.

Hereinafter, the present disclosure will be described with reference to the attached drawings. The shapes and sizes of elements in the drawings may be exaggerated or reduced for clearer explanation.

Electronics

1 is a block diagram schematically showing an example of an electronic device system.

Referring to the drawing, the electronic device 1000 accommodates the main board 1010. The main board 1010 is physically and/or electrically connected to chip-related components 1020, network-related components 1030, and other components 1040. These are combined with other electronic components described later to form various signal lines 1090.

Chip-related components 1020 include memory chips such as volatile memory (eg, DRAM), non-volatile memory (eg, ROM), and flash memory; Application processor chips such as central processors (eg, CPU), graphics processors (eg, GPU), digital signal processors, cryptographic processors, microprocessors, and microcontrollers; Logic chips such as analog-digital converters and ASICs (application-specific ICs) are included, but are not limited thereto, and other types of chip-related electronic components may also be included. Additionally, it goes without saying that these chip-related components 1020 can be combined with each other. The chip-related component 1020 may be in the form of a package including the above-described chip or electronic component.

Network-related parts (1030) include Wi-Fi (IEEE 802.11 family, etc.), WiMAX (IEEE 802.16 family, etc.), IEEE 802.20, LTE (long term evolution), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM. , GPS, GPRS, CDMA, TDMA, DECT, Bluetooth, 3G, 4G, 5G and any other wireless and wired protocols designated as such, but are not limited to, and many other wireless or wired protocols. Any of the standards or protocols may be included. In addition, of course, the network-related components 1030 can be combined with the chip-related components 1020.

Other components (1040) include high-frequency inductors, ferrite inductors, power inductors, ferrite beads, LTCC (low temperature co-firing ceramics), EMI (Electro Magnetic Interference) filter, MLCC (Multi-Layer Ceramic Condenser), etc. . However, it is not limited to this, and may include passive elements in the form of chip components used for various other purposes. In addition, of course, the other components 1040 may be combined with the chip-related components 1020 and/or the network-related components 1030.

Depending on the type of electronic device 1000, the electronic device 1000 may include other electronic components that may or may not be physically and/or electrically connected to the main board 1010. Examples of other electronic components include a camera module 1050, an antenna module 1060, a display 1070, and a battery 1080. However, it is not limited to this, and may include an audio codec, a video codec, a power amplifier, a compass, an accelerometer, a gyroscope, a speaker, a mass storage device (e.g., a hard disk drive), a compact disk (CD), a digital versatile disk (DVD), etc. It may be possible. In addition to this, of course, other electronic components used for various purposes may be included depending on the type of electronic device 1000.

The electronic device 1000 includes a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a network system, and a computer ( It may be a computer, monitor, tablet, laptop, netbook, television, video game, smart watch, automotive, etc. However, it is not limited to this, and of course, it can be any other electronic device that processes data.

Figure 2 is a perspective view schematically showing an example of an electronic device.

Referring to the drawings, the electronic device may be, for example, a smartphone 1100. A motherboard 1110 is accommodated inside the smartphone 1100, and various components 1120 are physically and/or electrically connected to the motherboard 1110. Additionally, other components that may or may not be physically and/or electrically connected to the motherboard 1110, such as the camera module 1130 and/or the speaker 1140, are accommodated therein. Some of the components 1120 may be the chip-related components described above, for example, the component package 1121, but are not limited thereto. The component package 1121 may be in the form of a printed circuit board on which electronic components including active components and/or passive components are surface mounted. Alternatively, the component package 1121 may be in the form of a printed circuit board with built-in active components and/or passive components. Meanwhile, the electronic device is not necessarily limited to the smartphone 1100, and of course, it may be other electronic devices as described above.

printed circuit board

Figure 3 is a cross-sectional view schematically showing an example of a printed circuit board.

FIG. 4 is a schematic cross-sectional view taken along line A-A' of the printed circuit board of FIG. 3.

Referring to the drawing, a printed circuit board (100A) according to an example includes a first insulating layer 111, a through hole (H) penetrating between the upper and lower surfaces of the first insulating layer (111), and a through hole (H). It includes a first via 121 that fills at least a portion of the first via 121, a first pad 131 connected to the upper side of the first via 121, and a second pad 132 connected to the lower side of the first via 121. do. In addition, it may further include traces 141 disposed on the upper and/or lower surfaces of the first insulating layer 111.

The diameter W1 at the uppermost side of the through hole H may be larger than the width W2 of the first pad 131, and from this point of view, the planar area at the uppermost side of the through hole H is the planar area of the first pad 131. It can be bigger than Similarly, the diameter at the lowermost side of the through hole (H) may be larger than the width of the second pad 132, and in this respect, the planar area at the lowermost side of the through hole (H) may be larger than the planar area of the second pad 132. there is. In this case, as the size of the first pad 131 and/or the second pad 132 decreases, the density of the through holes H can be improved and the area of the substrate can be reduced. Additionally, the number of substrate layers can be reduced by placing the traces 141 in areas where the size of the first pad 131 and/or the second pad 132 is reduced.

In the present disclosure, the diameter and width can be measured using a scanning microscope or an optical microscope based on a polished or cut cross section of the printed circuit board in the vertical direction. If the diameter and width in the cross section are not constant, it may mean the values measured as the maximum diameter and maximum width. When an object such as a through hole is formed in a polygonal shape rather than a circular or oval shape on a plane, the diameter can be replaced by the width.

In the present disclosure, the planar area can be measured using a scanning microscope or an optical microscope based on a polished or cut cross section of the printed circuit board in the horizontal direction. If the planar area in the cross section is not constant, it may mean the value measured by the maximum planar area. Alternatively, it may mean the area when viewed from the top or bottom view.

In the present disclosure, the horizontal direction may be any direction on a plane, and the vertical direction may be an upper or lower direction perpendicular to the horizontal direction on a cross-section. Here, the meaning on a cross-section can mean the cross-sectional shape when the object is cut vertically, or the cross-sectional shape when the object is viewed from a side view, and the meaning on the plane can mean the shape when the object is cut horizontally, Alternatively, it may be a planar shape when the object is viewed from a top-view or bottom-view.

At least a portion of the top surface of the first via 121 exposed from the first pad 131 may be recessed below the top surface of the first insulating layer 111 . Similarly, at least a portion of the lower surface exposed from the second pad 132 of the first via 121 may be recessed above the lower surface of the first insulating layer 111 . In this case, the recessed space may be filled with a second insulating layer 112 and/or a third insulating layer 113, which will be described later, and thus the contact area of the first via 121 with the insulating material is improved, thereby improving connection. Reliability, etc. can be further improved.

A first groove portion h1 surrounding the first pad 131 may be formed in the upper area of the through hole H by the recess on the upper surface of the first via 121, and the first pad 131 At least a portion of the side surface may be recessed inward to form a second groove h2 connected to the first groove h1 on the side of the first pad 131. The first and second grooves h1 and h2 may have a round shape. Similarly, a third groove surrounding the second pad 132 may be formed in the lower area of the through hole (H) by the recess on the lower surface of the first via 121, and the second pad 132 At least a portion of the side surface may be recessed inward to form a fourth groove connected to the third groove on the side of the second pad 132. The third and fourth grooves may also have a round shape. In this case, the size of the first pad 131 and/or the second pad 132 can be further reduced. Additionally, the connection reliability of not only the first via 121 but also the first pad 131 and/or the second pad 132 can be further improved.

The first via 121 may be integrated with the first and second pads 131 and 132, respectively, without boundaries. In this case, the first via 121 and the first pad 131 may be distinguished from each other based on an extension line of the upper surface of the first insulating layer 111. The first via 121 and the second pad 132 may be distinguished from each other based on an extension line of the lower surface of the first insulating layer 111. The first via 121 and the first and second pads 131 and 132 may be formed through the same plating process. For example, the first via 121 includes a first metal layer (M1) disposed on the wall of the through hole (H) and a first via (M1) disposed on the first metal layer (M1) to fill at least a portion of the through hole (H). It may include two metal layers (M2), and the first and second pads 131 and 132 may include a second metal layer (M2). That is, the first via 121 and the first and second pads 131 and 132 may each include a second metal layer M2 in common. The first metal layer (M1) may be a seed layer such as an electroless plating layer, and the second metal layer (M2) may be an electrolytic plating layer, but are not limited thereto.

If necessary, the printed circuit board 100A according to one example includes a second insulating layer 112 disposed on the upper surface of the first insulating layer 111, and a third insulating layer 112 disposed on the lower surface of the first insulating layer 111. Insulating layer 113, third pad 133 disposed on or in the second insulating layer 112, fourth pad 134 disposed on or in the third insulating layer 113, second insulating layer A second via 122 disposed within (112) and connected to the third pad 133, and/or a third via 123 disposed within the third insulating layer 113 and connected to the fourth pad 134. It may further include.

The diameter W1 at the uppermost side of the through hole H may be larger than the width W2 of the first pad 131, and the width W2 of the first pad 131 is connected through the second via 122. It may be larger than the width (W3) of the most adjacent third pad. Similarly, the diameter at the bottom of the through hole (H) may be larger than the width of the second pad 132, and the width of the second pad 132 may be greater than the width of the fourth most adjacent pad connected through the third via 123. It can be larger than the width of (134). In this case, it is possible to prevent the size of the first pad 131 and/or the second pad 132 from becoming too small. Therefore, sufficient alignment margin can be secured during the build-up process.

Hereinafter, components of the printed circuit board 100A according to an example will be described in more detail with reference to the drawings.

The first insulating layer 111 may be a core insulating layer. The first insulating layer 111 may include an insulating material. Insulating materials include insulating resins such as thermosetting resins such as epoxy resins or thermoplastic resins such as polyimide, or materials that are a mixture of these resins with inorganic fillers such as silica, or glass fibers (Glass Fiber, Glass Cloth, A resin impregnated into a core material such as Glass Fabric, for example, an insulating layer of CCL (Copper Clad Laminate), etc. may be used, but is not limited thereto. The first insulating layer 111 includes a plurality of first build-up insulating layers 112-1, 112-2, and 112-3 and a plurality of second build-up insulating layers 113-1, 113-2, and 113, which will be described later. -3) It may be thicker than each other.

In the present disclosure, the thickness can be measured using a scanning microscope or an optical microscope based on a polished or cut cross-section of the printed circuit board in the vertical direction. If the thickness is not constant, the relationship between thicknesses can be compared with the average value of the thickness of each object measured at five arbitrary points.

The second and third insulating layers 112 and 113 may be build-up insulating layers. The second and third insulating layers 112 and 113 include a plurality of first and second build-up insulating layers 112-1, 112-2, 112-3, 113-1, 113-2, and 113-3, respectively. may include. Each of the plurality of first and second build-up insulating layers 112-1, 112-2, 112-3, 113-1, 113-2, and 113-3 may include an insulating material. Insulating materials include insulating resins such as thermosetting resins such as epoxy resins or thermoplastic resins such as polyimide, or materials in which these resins are mixed with inorganic fillers such as silica, or resins impregnated with core materials such as glass fibers along with inorganic fillers. , for example, ABF (Ajinomoto Build-up Film), prepreg, etc. may be used, but are not limited thereto. The plurality of first build-up insulating layers 112-1, 112-2, and 112-3 may be integrated with each other without boundaries or may be separated from each other, and may be stacked in a larger number or in a smaller number than shown in the drawing. You can. The plurality of second build-up insulating layers 113-1, 113-2, and 113-3 may be integrated with each other without boundaries or may be separated from each other, and may be stacked in a larger number or in a smaller number than shown in the drawing. You can.

The through hole H may penetrate between the upper and lower surfaces of the first insulating layer 111. The diameters at the uppermost and lowermost sides of the through hole (H) may be larger than the diameter at the center side between the uppermost and lowermost sides of the through hole (H), respectively. For example, the through hole H may have an hourglass shape in cross section, where the width narrows and then widens again. However, it is not limited to this, and the shape of the through hole (H) may vary in various forms. At least a portion of each of the inorganic fillers and/or glass fibers included in the first insulating layer 111 may protrude from the wall of the through hole H, but the present invention is not limited thereto.

The first and second via holes (V1, V2) each have a plurality of first and second build-up insulating layers (112-1, 112-2, 112-3, 113-1, 113-2, 113) in the thickness direction. -3) Can penetrate each. Here, penetration may mean penetration to each pad. The diameter of the first via hole V1 at the uppermost side may be larger than the diameter at the lowermost side. For example, each of the first via holes V1 may have a tapered shape in cross section. Each of the second via holes V2 may have a diameter at the bottom side that is larger than a diameter at the top side. For example, each of the second via holes V2 may have a shape tapered in a direction opposite to that of each of the first via holes V1 in its cross section. However, the shape is not limited to this, and the shapes of each of the first and second via holes V1 and V2 may vary in various ways.

The first via 121 may include a metal material. Metal materials include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and/or alloys thereof, etc. may include. The first via 121 can perform various functions depending on the design. For example, it may include a through via for a signal connection, a through via for a ground connection, a through via for a power connection, etc. The number of first vias 121 is not particularly limited and may be plural. The first via 121 may include an electroless plating layer (or chemical copper) and an electrolytic plating layer (or electrical copper).

The second and third vias 122 and 123 may include a metal material. Metal materials include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and/or alloys thereof, etc. may include. The second and third vias 122 and 123 may perform various functions depending on the design. For example, it may include a connection via for signal connection, a connection via for ground connection, a connection via for power connection, etc. The number of the second and third vias 122 and 123 is not particularly limited, and the first and second build-up insulating layers (112-1, 112-2, 112-3, 113-1, 113-2, 113) -3) Multiple units can be placed on each floor. The second and third vias 122 and 123 may include an electroless plating layer (or chemical copper) and an electrolytic plating layer (or electrolytic copper), respectively.

The first via 121 that fills at least a portion of the through hole H penetrating the first insulating layer 111 may be a through via. The second vias 122 filling at least a portion of the first via holes V1 penetrating each of the plurality of first build-up insulating layers 112-1, 112-2, and 112-3 are respectively first connection vias. It can be. The third vias 123 filling at least a portion of the second via holes V2 penetrating each of the plurality of second build-up insulating layers 113-1, 113-2, and 113-3 are respectively second connection vias. It can be. From this perspective, the first via 121 may be taller than each of the second via 122 and the third via 123.

The first and second pads 131 and 132 may each include a metal material. Metal materials include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and/or alloys thereof, etc. may include. The first and second pads 131 and 132 may perform various functions depending on the design of the corresponding layer. For example, it may include a ground pad, power pad, signal pad, etc. There may be a plurality of first and second pads 131 and 132, respectively. The first and second pads 131 and 132 may each include an electrolytic plating layer (or electrolytic copper).

The third and fourth pads 133 and 134 may each include a metal material. Metal materials include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and/or alloys thereof, etc. may include. The third and fourth pads 133 and 134 may perform various functions depending on the design of the corresponding layer. For example, it may include a ground pad, power pad, signal pad, etc. The number of the third and fourth pads 133 and 134 is not particularly limited, and the first and second build-up insulating layers 112-1, 112-2, 112-3, 113-1, 113-2, and 113 -3) Multiple units can be placed on each floor. The third and fourth pads 133 and 134 may include an electroless plating layer (or chemical copper) and an electrolytic plating layer (or electrolytic copper), respectively. If necessary, copper foil may be further included.

Trace 141 may include a metal material. Metal materials include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and/or alloys thereof, etc. may include. Trace 141 may include a signal trace. There may be multiple traces 141. The trace 141 may include an electroless plating layer (or chemical copper) and an electrolytic plating layer (or electrolytic copper). If necessary, copper foil may be further included. The trace 141 may be a microcircuit with a small line/space. For example, the line width of the trace 141 may be smaller than the width of the first pad 131 and/or the second pad 132.

In the present disclosure, the line width can be measured using a scanning microscope or an optical microscope based on a polished or cut cross section of the printed circuit board in the vertical direction. If the line width in the cross section is not constant, it may mean the value measured as the maximum line width.

In addition to the third and fourth pads 133 and 134, each of the first and second build-up insulating layers (112-1, 112-2, 112-3, 113-1, 113-2, and 113-3) Other line patterns, plane patterns, and/or pad patterns may be arranged. Each of these patterns may include a metallic material. Metal materials include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and/or alloys thereof, etc. may include. Each of these patterns can perform various functions depending on the design of the corresponding layer. For example, it may include a ground pattern, power pattern, signal pattern, etc. These patterns may include an electroless plating layer (or chemical copper) and an electrolytic plating layer (or electrolytic copper), respectively. If necessary, copper foil may be further included.

Additional resist layers may be disposed on the second and third insulating layers 112 and 113, respectively. The resist layer may be disposed on the outermost side of the printed circuit board 100A to protect internal components. The material of the resist layer is not particularly limited. For example, an insulating material may be used, and in this case, solder resist may be used as the insulating material, but is not limited thereto. A plurality of openings that open at least a portion of each pattern such as a pad may be formed in the resist layer.

5 to 10 are process diagrams schematically showing an example of manufacturing a through via and first and second pads formed in the core insulating layer of the printed circuit board of FIG. 3.

Referring to FIG. 5, the first insulating layer 111 is prepared. The first insulating layer 111 may be a copper clad laminate (CCL). Copper foil may be disposed on the upper and/or lower surface of the first insulating layer 111, but is not limited thereto.

Referring to FIG. 6, a through hole H is formed in the first insulating layer 111. The through hole (H) can be formed through laser processing. For example, processing is performed in both the upper and lower directions of the first insulating layer 111 using laser processing, for example, a CO ₂ drill, to penetrate between the upper and lower surfaces of the first insulating layer 111. An hourglass-shaped through hole (H) can be formed. If necessary, processing may be performed only in the upper or lower direction to form a tapered through hole (H).

Referring to FIG. 7, first and second metal layers (M1, M2) are formed in the first insulating layer 111 and the through hole (H). For example, the first metal layer M1 may be formed on the wall of the through hole H and the upper and lower surfaces of the first insulating layer 111 using electroless plating or the like. Next, the second metal layer (M2) can be formed on the first metal layer (M1) by using the first metal layer (M1) as a seed layer, such as electrolytic plating. The second metal layer (M2) may fill the through hole (H).

Referring to FIG. 8, first and second etching resists 210 and 220 are disposed on the second metal layer M2 above and below the through hole H, respectively. The first and second etching resists 210 and 220 may each be dry films that can be patterned through a photolithography process.

Referring to FIG. 9 , an etching process is performed on the first and second metal layers M1 and M2 using the first and second etching resists 210 and 220 as masks. For example, through an isotropic etching process using a tenting process, first and third grooves h1 and h3 may be formed in the upper and lower regions of the through hole H, respectively, and the first grooves h1 and h3 may be formed in the upper and lower regions of the through hole H, respectively. And second and fourth grooves h2 and h4 may be formed on the sides of the second pads 131 and 132, respectively. The first and second grooves h1 and h2 and the third and fourth grooves h3 and h4 may be etched to be round, respectively.

Referring to FIG. 10, the first and second etching resists 210 and 220 are removed. A resist stripping solution may be used to remove the first and second etching resists 210 and 220, but is not limited thereto, and the peeling may be performed physically. Through a series of processes, a first via 121, which is a through via, and first and second pads 131 and 132, which are pads of the through via, may be formed in the first insulating layer 111, which is a core insulating layer. Afterwards, if the build-up process is performed, the printed circuit board 100A according to the above-described example can be manufactured. Other contents are substantially the same as those described above, and redundant descriptions will be omitted.

FIG. 11 is a cross-sectional image showing a comparison of the shapes of through vias and their pads according to and without the present disclosure.

Referring to the drawing, in the case according to the present disclosure as shown in (a), the pads for through vias are formed in a relatively small size, the sides of the pads for through vias are partially etched to have a round shape, and the pads for through vias are formed in a relatively small size. It can be seen that the top and bottom surfaces are partially etched and have a round shape, and there is a recess step between the top and bottom surfaces of the core insulating layer. On the other hand, when forming through vias and their pads using a general plating process as shown in (b), the pads for through vias are formed to be relatively large in size, and it can be seen that the through vias cannot have a recess step. . Therefore, there may be differences in effectiveness from the perspective of integration or reliability. Meanwhile, the dotted lines in the drawing may be extension lines indicating the levels of the upper and lower surfaces of the core insulating layer.

Figure 12 is a cross-sectional view schematically showing another example of a printed circuit board.

FIG. 13 is a schematic cross-sectional view taken along line B-B' of the printed circuit board of FIG. 12.

Referring to the drawings, the printed circuit board 100B according to another example has a partially different shape of the through hole H compared to the printed circuit board 100A according to the above-described example. For example, the diameters at the uppermost and lowermost sides of the through hole H may be substantially equal to the diameters at the center side between the uppermost and lowermost sides of the through hole H, respectively. For example, the through hole H may have a rectangular shape with a substantially constant width in cross section. This type of through hole (H) can be formed using a mechanical drill. Other than that, other contents are substantially the same as those described above, so overlapping descriptions will be omitted.

In the present disclosure, the actual meaning can be determined including process errors, position deviations, and measurement errors that occur during the process. For example, substantially the same may include not only cases where they are completely identical, but also cases where there are subtle differences roughly caused by process errors. In addition, substantially constant may include not only cases where it is completely constant, but also cases where there are subtle differences roughly caused by process errors.

In the present disclosure, the meaning of connected is a concept that includes not only directly connected but also indirectly connected. Additionally, expressions such as first, second, etc. are used to distinguish one component from another component and do not limit the order and/or importance of the components. In some cases, the first component may be named the second component, and similarly, the second component may be named the first component without departing from the scope of rights.

The expression 'example' used in the present disclosure does not mean identical embodiments, but is provided to emphasize and explain different unique features. However, the examples presented above do not exclude being implemented in combination with features of other examples. For example, even if a matter explained in a specific example is not explained in another example, it can be understood as an explanation related to the other example, as long as there is no explanation contrary to or contradictory to the matter in the other example.

The terminology used in this disclosure is used to describe examples only and is not intended to limit the disclosure. At this time, singular expressions include plural expressions, unless the context clearly indicates otherwise.

1000: Electronic devices
1010: Motherboard
1020: Chip related parts
1030: Network related parts
1040: Other parts
1050: Camera
1060: Antenna
1070: display
1080: Battery
1090: signal line
1100: Smartphone
1110: motherboard
1120: parts
1121: Parts package
1130: Camera module
1140: Speaker
100A, 100B: printed circuit board
111: First insulating layer (core insulating layer)
112: second insulating layer
112-1, 112-2, 112-3: first build-up insulating layer
113: third insulating layer
113-1, 113-2, 113-3: second build-up insulating layer
H: Through hole
V1: first via hole
V2: Second via hole
121: 1st via (through via)
122: second via (first connection via)
123: Third via (second connection via)
131: first pad
132: second pad
133: Third pad
134: 4th pad
141: Trace
h1: first groove
h2: second groove
h3: Third groove
h4: fourth groove
M1: first metal layer
M2: second metal layer
210: first etching resist
220: second etching resist

Claims (16)

first insulating layer;
a through hole penetrating between the upper and lower surfaces of the first insulating layer;
a first via filling at least a portion of the through hole;
a first pad connected to the upper side of the first via; and
a second pad connected to the lower side of the first via; Includes,
The diameter at the uppermost side of the through hole is larger than the width of the first pad,
At least a portion of the upper surface of the first via exposed from the first pad is recessed below the upper surface of the first insulating layer,
Printed circuit board.
According to claim 1,
The planar area at the uppermost side of the through hole is larger than the planar area of the first pad,
Printed circuit board.
According to claim 1,
At least a portion of the upper surface exposed from the first pad of the first via is recessed downward to form a first groove in the upper area of the through hole,
The first groove surrounds the first pad,
Printed circuit board.
According to claim 3,
At least a portion of the side of the first pad is recessed inward to form a second groove on the side of the first pad,
The first and second grooves are connected to each other and have a round shape,
Printed circuit board.
According to claim 1,
The diameter at the lowermost side of the through hole is larger than the width of the second pad,
At least a portion of the lower surface exposed from the second pad of the first via is recessed above the lower surface of the first insulating layer,
Printed circuit board.
According to claim 5,
At least a portion of the lower surface exposed from the second pad of the first via is recessed upward to form a third groove in the lower area of the through hole,
The third groove surrounds the second pad,
Printed circuit board.
According to claim 6,
At least a portion of the side of the second pad is recessed inward to form a fourth groove on the side of the second pad,
The third and fourth grooves are connected to each other and have a round shape,
Printed circuit board.
According to claim 1,
The first via is integrated with the first and second pads, respectively, without boundaries.
Printed circuit board.
According to claim 8,
The first via includes a first metal layer disposed on a wall of the through hole and a second metal layer disposed on the first metal layer,
The first and second pads each include the second metal layer,
Printed circuit board.
According to claim 1,
The diameters at the uppermost and lowermost sides of the through hole are respectively larger than the diameter at the center side between the uppermost and lowermost sides of the through hole,
Printed circuit board.
According to claim 1,
The diameters at the uppermost and lowermost sides of the through hole are respectively substantially the same as the diameter at the center side between the uppermost and lowermost sides of the through hole,
Printed circuit board.
According to claim 1,
A trace disposed on the upper surface of the first insulating layer; It further includes,
The line width of the trace is smaller than the width of the first pad,
Printed circuit board.
According to claim 1,
a second insulating layer disposed on an upper surface of the first insulating layer;
a third pad disposed on or within the second insulating layer;
a second via disposed in the second insulating layer and connected to the third pad;
a third insulating layer disposed on the lower surface of the first insulating layer;
a fourth pad disposed on or within the third insulating layer; and
a third via disposed in the third insulating layer and connected to the fourth pad; Containing more,
Printed circuit board.
core insulation layer;
a through via that fills at least a portion of a through hole penetrating the core insulating layer;
a first pad connected to an upper side of the through via;
a second pad connected to the lower side of the through via;
a first build-up insulating layer disposed on an upper surface of the core insulating layer and covering at least a portion of the first pad;
a first connection via that fills at least a portion of the first via hole penetrating the first build-up insulating layer; and
a third pad connected to an upper side of the first connection via; Includes,
The diameter at the uppermost side of the through hole is larger than the width of the first pad,
The width of the first pad is greater than the width of the third pad,
Printed circuit board.
According to claim 14,
The core insulating layer is thicker than the first build-up insulating layer,
The through via has a greater height than the first connection via,
Printed circuit board.
According to claim 14,
a second build-up insulating layer disposed on a lower surface of the core insulating layer and covering at least a portion of the second pad;
a second connection via that fills at least a portion of the second via hole penetrating the second build-up insulating layer; and
a fourth pad connected to the lower side of the second connection via; Includes,
The diameter at the lowermost side of the through hole is larger than the width of the second pad,
The width of the second pad is greater than the width of the fourth pad,
Printed circuit board.

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