KR20240026063A - Variable resistance memory device and electronic apparatus including the same - Google Patents

Abstract

Disclosed is a variable resistance memory device and an electronic device including the same. This variable resistance memory device includes a resistance change layer composed of a metal oxide having an oxygen deficiency ratio of 9% or more, a semiconductor layer disposed on the resistance change layer, a gate insulating layer disposed on the semiconductor layer, and a gate insulating layer spaced apart from each other. It includes a plurality of electrodes disposed.

Description

Variable resistance memory element and electronic device including same {VARIABLE RESISTANCE MEMORY DEVICE AND ELECTRONIC APPARATUS INCLUDING THE SAME}

The present disclosure relates to a memory device including a variable resistance material and an electronic device including the same.

A non-volatile memory device includes a number of memory cells that retain information even when power is turned off and can use the stored information again when power is supplied. Non-volatile memory devices can be used in cell phones, digital cameras, digital assistants (PDAs), portable computer devices, stationary computer devices, and other devices.

Recently, research is underway on using 3D (or vertical) NAND (VNAND) in chips that form the next-generation Neuromorphic Computing platform or neural network.

Provided is a variable resistance memory device including a resistance change layer in which many oxygen vacancies can occur, and an electronic device including the same.

A variable resistance memory device according to an embodiment includes a resistance change layer composed of a metal oxide containing a first metal element and a second metal element and having an oxygen deficiency ratio of 9% or more; a semiconductor layer disposed on the resistance change layer; a gate insulating layer disposed on the semiconductor layer; and a plurality of electrodes spaced apart from each other on the gate insulating layer.

Additionally, the content of the first metal element relative to the total metal in the resistance change layer may be 50 at% or more.

Additionally, the content of the second metal element relative to the total metal in the resistance change layer may be 35 at% or less.

And, the first metal element may include one of tantalum (Ta), titanium (Ti), stanium (Sn), chromium (Cr), and manganese (Mn).

In addition, the second metal element is hafnium (Hf), aluminum (Al), niobium (Nb), lanthanum (La), zirconium (Zr), scandium (Sc), tungsten (W), vananium (V), Molybdenum (Mo) may be included.

And, the resistance change layer may further include silicon (Si).

Additionally, a write voltage with an absolute value of 4V or less may be applied to the semiconductor layer.

In addition, it may further include an oxide layer disposed between the semiconductor layer and the resistance change layer.

Additionally, the thickness of the oxide layer may be smaller than the thickness of the resistance change layer.

And, the resistance change layer includes a first resistance change layer and a second resistance change layer sequentially arranged in a direction away from the semiconductor layer, and the oxygen deficiency rate of the first resistance change layer is determined by the second resistance change layer. It may be greater than the oxygen deficiency rate of the layer.

Additionally, the pitch of the plurality of gate electrodes may be 20 nm or less.

and a pillar; wherein the resistance change layer, the semiconductor layer, and the gate insulating layer sequentially surround the pillar in a shell shape, and the plurality of gate electrodes and the insulating element are formed by the gate insulating layer. can be wrapped into a shell shape.

Additionally, the pillar may include an insulating material.

Additionally, the pillar may include a conductive material.

Additionally, a voltage higher than that applied to the semiconductor layer may be applied to the pillar.

A variable resistance memory device according to another embodiment includes a resistance change layer comprising silicon and a metal oxide having an oxygen deficiency ratio of 9% or more; a semiconductor layer disposed on the resistance change layer; a gate insulating layer disposed on the semiconductor layer; and a plurality of electrodes spaced apart from each other on the gate insulating layer.

Additionally, the resistance change layer may include at least one of tantalum (Ta), titanium (Ti), stanium (Sn), chromium (Cr), and manganese (Mn).

Additionally, the content of silicon relative to the sum of metal and silicon in the resistance change layer may be 35 at% or less.

A variable resistance memory device according to another embodiment includes a first metal oxide having an oxygen deficiency ratio of 9% or more and a second metal oxide having an oxygen deficiency ratio of less than 9%, and the content of the first metal oxide is a resistance change layer greater than the content of the second metal oxide; a semiconductor layer disposed on the resistance change layer; a gate insulating layer disposed on the semiconductor layer; and a plurality of gate electrodes spaced apart from each other on the gate insulation.

Additionally, the content of the metal contained in the second metal oxide relative to the total metal contained in the resistance change layer may be 35 at% or less.

A variable resistance memory device according to an embodiment can operate even when a voltage with a small absolute value is applied.

A variable resistance memory device according to an embodiment is easy to implement with low power and high integration.

1 is a diagram showing a schematic configuration of a variable resistance memory device according to an embodiment.
FIG. 2 is a diagram showing an equivalent circuit for the variable resistance memory device of FIG. 1.
FIG. 3 is a conceptual diagram illustrating the operation of the variable resistance memory device 100 of FIG. 1 by way of example.
Figure 4 is a diagram showing the relationship between the oxygen deficiency rate of metal oxide and forming voltage according to one embodiment.
Figure 5 is a diagram showing the relationship between the oxygen deficiency rate of metal oxide and forming voltage according to one embodiment.
FIG. 6 is a diagram illustrating the relationship between oxygen formation energy and oxygen deficiency rate of a metal oxide according to an embodiment.
Figure 7 is a diagram showing the difference in oxygen formation energy of various metal oxides according to an embodiment.
Figure 8a is a diagram showing the IV characteristics of a variable resistance memory device using hafnium oxide as a resistance change layer.
Figure 8b is a diagram showing the IV characteristics of a variable resistance memory device using tantanium oxide as a resistance change layer.
Figure 9 is a diagram showing the structure of a variable resistance memory device according to another embodiment.
FIG. 10 is a diagram showing an equivalent circuit for the variable resistance memory device of FIG. 9.
FIG. 11 is a diagram illustrating a portion of a variable resistance memory device including a multi-layer resistance change layer according to an embodiment.
FIG. 12 is a diagram illustrating a portion of a variable resistance memory device further including an oxide layer according to an embodiment.
FIG. 13 is a diagram illustrating a variable resistance memory device including a conductive pillar according to an embodiment.
FIG. 14 is a block diagram schematically illustrating an electronic device including a non-volatile memory device according to an embodiment.
FIG. 15 is a block diagram schematically illustrating a memory system including a non-volatile memory device according to an embodiment.

Phrases such as “in some embodiments” or “in one embodiment” that appear in various places in this specification do not necessarily all refer to the same embodiment.

Some embodiments of the present disclosure may be represented by functional block configurations and various processing steps. Some or all of these functional blocks may be implemented in various numbers of hardware and/or software configurations that perform specific functions. For example, the functional blocks of the present disclosure may be implemented by one or more microprocessors, or may be implemented by circuit configurations for certain functions. Additionally, for example, functional blocks of the present disclosure may be implemented in various programming or scripting languages. Functional blocks may be implemented as algorithms running on one or more processors. Additionally, the present disclosure may employ conventional technologies for electronic environment setup, signal processing, and/or data processing. Terms such as “mechanism,” “element,” “means,” and “configuration” may be used broadly and are not limited to mechanical and physical components.

Additionally, connection lines or connection members between components shown in the drawings merely exemplify functional connections and/or physical or circuit connections. In an actual device, connections between components may be represented by various replaceable or additional functional connections, physical connections, or circuit connections.

Terms such as “consists of” or “includes” used in the specification should not be construed as necessarily including all of the components or steps described in the specification, and only some of the components or steps may be used in the specification. may not be included, or may further include additional components or steps.

Hereinafter, the term "above" or "above" may include not only those immediately above/below/left/right in contact, but also those above/below/left/right without contact. Hereinafter, a detailed description will be given by way of example only with reference to the attached drawings.

Terms such as first, second, etc. may be used to describe various components, but the components should not be limited by the terms. Terms are used only to distinguish one component from another.

Hereinafter, the present disclosure will be described in detail with reference to the attached drawings.

FIG. 1 is a diagram showing a schematic configuration of a variable resistance memory element 100 according to an embodiment, FIG. 2 is a diagram showing an equivalent circuit for the variable resistance memory element 100 of FIG. 1, and FIG. 3 is a diagram showing the schematic configuration of the variable resistance memory element 100 of FIG. 1. This is a conceptual diagram illustrating the operation of the variable resistance memory element 100.

Referring to FIG. 1, the variable resistance memory device 100 includes a resistance change layer 122, a semiconductor layer 123 disposed on the resistance change layer 122, and a gate insulating layer ( 124), and includes a plurality of gate electrodes 131 formed on the gate insulating layer 124. An insulating element 132 that separates adjacent gate electrodes 131 may be further disposed in the space between the plurality of gate electrodes 131 . However, this is an example and the insulating element 132 may be omitted.

The resistance change layer 122 may be formed of a material whose resistance varies depending on the applied voltage. The resistance change layer 122 may change from a high resistance state to a low resistance state or from a low resistance state to a high resistance state depending on the voltage applied to the gate electrode 131.

The resistance change layer 122 can implement a desired resistance change range with a thinner thickness than a conventional charge trap-based variable resistance memory device or a variable resistance memory device using a phase change material. The thickness of the resistance change layer 122 may be 100 nm or less, or may be 5 nm or less. The thickness of the resistance change layer 122 may be 1 nm or more.

The resistance change layer 122 may be formed of a material having hysteresis characteristics. For example, the resistance change layer 122 may include metal oxide. The resistance change layer 122 is made of tantalum oxide (TaOx), titanium oxide (TiOx), stannium oxide (SnOx), chromium oxide (CrOx), manganese oxide (MnOx), hafnium oxide (HfOx), and aluminum oxide (AlOx). , silicon oxide (SiOx), niobium oxide (NbOx), lanthanum oxide (LaOx), zirconium oxide (ZrOx), scandium oxide (ScOx), tungsten oxide (WOx), vananium oxide (VOx), molybdenum oxide (MoOx) ) may include at least two of them.

The change in resistance of the resistance change layer 122 may be a phenomenon caused by oxygen vacancies. As the number of oxygen vacancies increases in the resistance change layer 122, a conductive filament can be easily formed. The conductive filament changes the resistance change layer 122 to a low resistance state, allowing current to flow through the resistance change layer 122, so that the variable resistance memory device 100 can operate. If the resistance change layer 122 is made of a material that easily generates oxygen vacancies, the variable resistance memory element 100 can ) can work well. The material of the resistance change layer 122 that easily generates oxygen vacancies will be described later.

The semiconductor layer 123 may be made of poly-Si. The material of the semiconductor layer 123 is not limited to poly-Si, and may include various semiconductor materials such as Ge, IGZO, or GaAs.

A source electrode (S) and a drain electrode (D) may be connected to both ends of the semiconductor layer 123.

The gate insulating layer 124 may be made of various types of insulating materials. For example, silicon oxide, silicon nitride, or silicon oxynitride may be used for the gate insulating layer 124.

A voltage that turns on/off the semiconductor layer 123 may be selectively applied to each of the plurality of gate electrodes 131.

The illustrated variable resistance memory element 100 has a structure in which a plurality of memory cells (MC) are arrayed, and each memory cell (MC) has a transistor and a variable resistor connected in parallel, as shown in the equivalent circuit of FIG. 2. It can be.

The operation of the variable resistance memory element 100 is as follows with reference to FIG. 3.

To select a memory cell, control logic (not shown) applies a turn-off voltage (OFF) to the gate electrode 131 of a specific memory cell (MC2) and the gate electrode (OFF) of the remaining memory cells (MC1, MC2). 131) can be controlled to apply a turn-on voltage (ON). The turn-off voltage OFF is a voltage that turns off the transistor, and is a voltage that prevents current from flowing through the semiconductor layer 123 of the transistor included in the selected memory cell MC2. The turn-on voltage (ON) is a voltage that turns on the transistor and allows current to flow through the semiconductor layer 123 of the transistor included in the unselected memory cells MC1 and MC3. Thus, the semiconductor layer 123 corresponding to the selected memory cell MC2 may have insulating properties, and the semiconductor layer 123 corresponding to the unselected memory cells MC1 and MC3 may have conductive properties.

The turn-off voltage (OFF) and turn-on voltage (ON) depend on the type and thickness of the materials constituting the resistance change layer 122, the semiconductor layer 123, the gate insulating layer 124, and the gate electrode 131. may vary depending on For example, when the turn-off voltage (OFF) is a negative voltage, the turn-off voltage (OFF) may be -10V or more and -2V or less. When the turn-on voltage (ON) is a positive voltage, the turn-on voltage (ON) may be 0V or more and 10V or less. The same value of turn-on voltage (ON) may be applied to the unselected memory cells MC1 and MC3, or different values of turn-on voltage (ON) may be applied to the unselected memory cells MC1 and MC3.

In a write operation, when a write voltage is applied between the source electrode (S) and the drain electrode (D), a current path is formed as shown by the arrow (A), thereby changing the resistance of the resistance change layer 122. Information can be stored in the resistance change layer 122 using the above-described principle. The reason why the resistance of the resistance change layer 122 changes is that when a current flows through the resistance change layer 122, oxygen vacancies (Vo) and interstitial oxygen ions are formed, and the oxygen vacancies gather to form conductivity. A filament is formed. Since the conductive filament made of oxygen vacancies has low resistance, the resistance of the resistance change layer 122 changes.

In order for the variable resistance memory device 100 to be commercialized, it is desirable that the resistance difference between the high-resistance state and the low-resistance state of the resistance change layer 122 is large. For this, oxygen vacancies in the resistance change layer 122 are easily generated. It is desirable. In particular, in order to prevent deterioration of the semiconductor layer 123 by lowering the absolute value of the operating voltage applied to the variable resistance memory device 100, for example, the write voltage or erase voltage, oxygen vacancies in the resistance change layer 122 are removed. It is desirable for it to occur well.

The resistance change layer 122 according to one embodiment may be formed of a metal oxide with a high oxygen deficiency ratio. For example, the resistance change layer 122 may be formed of a metal oxide with an oxygen deficiency rate of 9 at% or more. The oxygen deficiency rate can be defined as Equation 1 below.

[Equation 1]

Here, M1, M2, M3, M4, M5, and O are the monovalent metal element content, divalent metal element content, trivalent metal element content, tetravalent metal element content, pentavalent metal element content, and oxygen content, respectively.

A high oxygen deficiency rate means that there are fewer oxygen ions compared to the same metal cation, and a metal oxide with a large oxygen deficiency rate may have a high oxygen vacancy content. If there are many oxygen vacancies in the resistance change layer 122, the resistance state of the resistance change layer 122 can be easily changed, thereby improving the characteristics of the variable resistance memory device 100. In addition, if there are many oxygen vacancies, a conductive filament is easily formed when voltage is applied, so the forming voltage may be lowered and the operating voltage of the variable resistance memory device 100 may also be lowered.

The resistance change layer 122 according to one embodiment may include a binary metal oxide with an oxygen deficiency rate of 9% or more or a ternary metal oxide with an oxygen deficiency rate of 9% or more.

The binary metal oxide included in the resistance change layer 122 may include at least one of tantalum oxide (TaOx), titanium oxide (TiOx), stannium oxide (SnOx), chromium oxide (CrOx), and manganese oxide (MnOx). You can.

The resistance change layer 122 is a ternary metal oxide and may include different first metal elements, second metal elements, and oxygen elements. The content of the first metal element in the metal oxide may be greater than the content of the second metal element. For example, the content of the first metal element relative to the total metal in the resistance change layer may be 50 at% or more, and the content of the second metal element relative to the total metal in the resistance change layer may be 35 at% or less. The first metal element may include one of tantalum (Ta), titanium (Ti), stanium (Sn), chromium (Cr), and manganese (Mn), and the second metal element may include hafnium (Hf) or aluminum. It may include one of (Al), niobium (Nb), lanthanum (La), zirconium (Zr), scandium (Sc), tungsten (W), vananium (V), and molybdenum (Mo).

From another perspective, the resistance change layer 122 is a ternary metal oxide and may include a metal element, a silicon element, and an oxygen element. The content of metal elements in the resistance change layer 122 may be greater than the content of silicon elements. The content of the metal element relative to the sum of the metal element and silicon element in the resistance change layer 122 is 50 at% or more, and the content of the silicon element relative to the sum of the metal element and silicon element in the resistance change layer 122 is 35 at% or less. You can. The above-mentioned metal element may include one of tantalum (Ta), titanium (Ti), stanium (Sn), chromium (Cr), and manganese (Mn).

Alternatively, the resistance change layer 122 may include a first metal oxide with an oxygen deficiency rate of 9% or more and a second metal oxide with an oxygen deficiency rate of less than 9%. The content of the first metal oxide may be greater than the content of the second metal oxide. The content of the metal contained in the first metal oxide relative to the total metal included in the resistance change layer 122 is 50 at% or more, and the content of the metal contained in the second metal oxide relative to the total metal included in the resistance change layer 122 is 50 at% or more. The content of the metal may be 35 at% or less. The first metal oxide may include at least one of tantalum oxide (TaOx), titanium oxide (TiOx), stanium oxide (SnOx), chromium oxide (CrOx), and manganese oxide (MnOx). The second metal oxide is hafnium oxide (HfOx), aluminum oxide (AlOx), silicon oxide (SiOx), niobium oxide (NbOx), lanthanum oxide (LaOx), zirconium oxide (ZrOx), scandium oxide (ScOx), and tungsten oxide ( It may include at least one of WOx), vananium oxide (VOx), and molybdenum oxide (MoOx).

Figure 4 is a diagram showing the relationship between the oxygen deficiency rate of metal oxide and forming voltage according to one embodiment. Referring to FIG. 4, hafnium oxide (HfOx), a binary system, has a low oxygen deficiency rate of about 2.1% and a high forming voltage (V _forming ) of about 7.4V. Hafnium oxide is a representative variable resistance material, but has a high forming voltage, so when applied to the variable resistance memory device 100, it may deteriorate the semiconductor layer 123 of the variable resistance memory device 100.

Meanwhile, tantalum oxide (TaOx) has a high oxygen deficiency rate of about 16.5% and a low forming voltage (V _forming ) of about 1.65V. It can be expected that the variable resistance memory device 100 can be implemented with low operation by using tantalum oxide (TaOx) as a material for the resistance change layer 122 according to an embodiment.

Hafnium oxide (HfOx) has a low oxygen deficiency rate and cannot be used alone as a material for the resistance change layer. However, it can be used as a material for the resistance change layer together with tantalum, which has a high oxygen deficiency rate. As shown in FIG. 4, the oxygen deficiency rate and forming voltage may vary depending on the type of material contained in the metal oxide. For example, the oxygen deficiency rate of TaSiO with a silicon content of 12 at% is about 12.13% and the forming voltage is about 1.55 V, while the oxygen deficiency rate of TaAlO with an aluminum content of 12 at% is about 13.92% and the forming voltage is It is approximately 0.95V. It can be confirmed that if aluminum rather than silicon is included in tantalum oxide (TaO), the oxygen deficiency rate can be increased and the forming voltage can be lowered. In general, it can be seen that the higher the oxygen deficiency rate, the lower the forming voltage.

When the resistance change layer 122 is made of a metal oxide containing a plurality of different metals, the forming voltage may vary depending on the content ratio of the metals. For example, if the aluminum content relative to the total metal in TaAlO is 5 at%, the forming voltage of TaAlO is about 1.5 V, and if the aluminum content relative to the total metal in TaAlO is 12 at%, the forming voltage of TaAlO is about 0.95 V. It's V. It can be seen that the forming voltage decreases as the aluminum content is added. However, the forming voltage of TaAlO with an aluminum content of 35 at% is about 3.5V, and it can be seen that if the aluminum content is too high, the forming voltage actually increases.

The resistance change layer 122 according to one embodiment may include different first metal elements and second metal elements, and may have an oxygen deficiency rate of 9% or more. The content of the first metal element in the metal oxide may be greater than the content of the second metal element. Alternatively, the content of the first metal element relative to the total metal in the resistance change layer 122 may be 50 at% or more, and the content of the second metal element relative to the total metal in the resistance change layer 122 may be 35 at% or less. The first metal element may include one of tantalum (Ta), titanium (Ti), stanium (Sn), chromium (Cr), and manganese (Mn), and the second metal element may include hafnium (Hf) or aluminum. It may include one of (Al), niobium (Nb), lanthanum (La), zirconium (Zr), scandium (Sc), tungsten (W), vananium (V), and molybdenum (Mo).

From another perspective, the resistance change layer 122 may use a metal oxide with a large oxygen deficiency rate as a matrix and dope it with a metal or metal oxide with a small oxygen deficiency rate to lower the forming voltage. However, if the content of the doped metal or metal oxide is too high, the forming voltage may increase, and the content of the doped metal relative to the total metal of the variable resistance layer may be about 35 at% or less.

The absolute value of the operating voltage, for example, the write voltage or the erase voltage, of the variable resistance memory device 100 according to one embodiment may be about 4V or less. Alternatively, the absolute value of the write voltage or erase voltage of the variable resistance memory device 100 according to one embodiment may be about 2V or less.

Figure 5 is a diagram showing the relationship between the oxygen deficiency rate of metal oxide and forming voltage according to one embodiment. Referring to Figure 5, it can be seen that the greater the oxygen deficiency rate, the lower the forming voltage. However, the oxygen deficiency rate and forming voltage are only approximately inversely proportional and not completely inversely proportional. The forming voltage can be lowered by appropriately adjusting the type and content of the metal oxide of the resistance change layer 122.

The oxygen deficiency rate of a metal oxide is related to the oxygen formation energy between a plurality of metal oxides with different valences of the same metal.

FIG. 6 is a diagram illustrating the relationship between oxygen formation energy and oxygen deficiency rate of a metal oxide according to an embodiment. Referring to FIG. 6, the difference in oxygen formation energy between a plurality of tantalum oxides (TaOx) with different valences, for example, Ta ₂ O ₅ and TaO ₂ , is as small as 4.42 kJ/mol, while the oxygen deficiency rate is 16.5%. big. On the other hand, the difference in oxygen formation energy for aluminum oxide (AlOx) is large at about 123.79, while the oxygen deficiency rate is small at about 2.1%. It can be seen that the difference in oxygen formation energy of metal oxide is inversely proportional to the oxygen deficiency rate.

The oxygen deficiency rate of aluminum oxide (AlOx) and hafnium oxide (HfOx) is the same at about 2.1%, but the difference in oxygen formation energy for aluminum oxide (AlOx) is about 123.79 kJ/mol, which is 34.38 It is large as hafnium oxide (HfOx) in kJ/mol. In other words, even if the oxygen deficiency rate is the same, the difference in oxygen formation energy may be different. Therefore, in one embodiment, a metal oxide having a difference in oxygen formation energy of about 10 kJ/mol or more is used as the matrix of the resistance change layer 122, and a metal oxide or metal having a difference in oxygen formation energy of less than about 10 kJ/mol is used as a resist. It can be used as a dopant for the change layer 122.

Figure 7 is a diagram showing the difference in oxygen formation energy of various metal oxides according to an embodiment. Referring to FIG. 7, the difference in oxygen formation energy for manganese oxide (MnOx), titanium oxide (TiOx), stannium oxide (SnOx), and chromium oxide (CrOx) is less than 10 kJ/mol. Manganese oxide (MnOx), titanium oxide (TiOx), stanium oxide (SnOx), and chromium oxide (CrOx) may be used as dopants for the resistance change layer 122 according to an embodiment.

The difference in oxygen formation energy for molybdenum oxide (MoOx), vananium oxide (VOx), scandium oxide (ScOx), tungsten oxide (WOx), lanthanum oxide (LaOx), and zirconium oxide (ZrOx) is more than 10 kJ/mol. am. Molybdenum oxide (MoOx), vananium oxide (VOx), scandium oxide (ScOx), tungsten oxide (WOx), lanthanum oxide (LaOx), and zirconium oxide (ZrOx) are the resistance change layer 122 according to an embodiment. It can be used as a wool material.

FIG. 8A is a diagram showing the IV characteristics of a variable resistance memory device using hafnium oxide as a resistance change layer, and FIG. 8B is a diagram showing the IV characteristics of a variable resistance memory device using tantanium oxide as a resistance change layer. It can be confirmed that the absolute value of the forming voltage of the variable resistance memory device containing hafnium oxide is about 7 to 8V, as shown in FIG. 8A. As previously described, the oxygen deficiency rate of hafnium oxide is low, approximately 2.1%.

It can be confirmed that the absolute value of the forming voltage of the variable resistance memory device containing tantanium oxide is less than about 2V, as shown in FIG. 8B. As previously described, the oxygen deficiency rate of hafnium oxide is high at approximately 16.5%. This can be expected that as the oxygen deficiency rate increases, the number of oxygen vacancies within the resistance change layer 122 increases, so that a conductive filament is well formed even at a low operating voltage.

FIG. 9 is a diagram showing the structure of a variable resistance memory element 100a according to another embodiment, and FIG. 10 is a diagram showing an equivalent circuit for the variable resistance memory element 100a of FIG. 9 .

The variable resistance memory element 100a of this embodiment is a vertical NAND (vertical NAND, VNAND) memory in which a plurality of memory cells (MC) including variable resistance materials are arranged in a vertical direction.

First, referring to FIG. 9, a plurality of cell strings CS are formed on the substrate 101.

The substrate 101 may include a silicon material doped with type 1 impurities. For example, the substrate 101 may include a silicon material doped with a p-type impurity. For example, substrate 101 may be a p-type well (eg, pocket p well). Hereinafter, it is assumed that the substrate 101 is p-type silicon. However, the substrate 101 is not limited to p-type silicon.

A doped region 110, which is a source region, is provided on the substrate 101. The doped region 110 may be of a different n-type than the substrate 101. Hereinafter, the doped region 110 is assumed to be n-type. However, the doped region 110 is not limited to n-type. This doped region 110 may be connected to the common source line (CSL).

As shown in the equivalent circuit diagram of FIG. 10, the cell string (CS) may be provided in k*n pieces and arranged in a matrix form, and CSij (1≤i≤k, 1≤j≤n) according to the position of each row and column. It can be named as . Each cell string (CSij) is connected to a bit line (BL), string select line (SSL), word line (WL), and common source line (CSL).

Each cell string CSij includes memory cells MC and a string select transistor SST. The memory cells MC and string select transistor SST of each cell string CSij may be stacked in the height direction.

Rows of a plurality of cell strings (CS) are respectively connected to different string selection lines (SSL1 to SSLk). For example, the string selection transistors SSTs of the cell strings CS11 to CS1n are commonly connected to the string selection line SSL1. The string selection transistors (SST) of the cell strings (CSk1 to CSkn) are commonly connected to the string selection line (SSLk).

The columns of the plurality of cell strings CS are respectively connected to different bit lines BL1 to BLn. For example, the memory cells and string selection transistors SST of the cell strings CS11 to CSk1 may be commonly connected to the bit line BL1, and the memory cells MC of the cell strings CS1n to CSkn may be connected to the bit line BL1. and the string select transistors SST may be commonly connected to the bit line BLn.

Rows of the plurality of cell strings CS may be respectively connected to different common source lines CSL1 to CSLk. For example, the string selection transistors SST of the cell strings CS11 to CS1n may be commonly connected to the common source line CSL1, and the string selection transistors SST of the cell strings CSk1 to CSkn may be connected to the common source line CSL1. may be commonly connected to the common source line (CSLk).

The gate electrodes 131 of the memory cells (MC) located at the same height from the substrate 101 or the string select transistors (SST) are commonly connected to one word line (WL), and the memory cells located at different heights The gate electrodes 131 of (MC) may be respectively connected to different word lines (WL1 to WLm).

The circuit structure shown is exemplary. For example, the number of rows of cell strings (CS) can be increased or decreased. As the number of rows of the cell string (CS) changes, the number of string selection lines connected to the rows of the cell string (CS) and the number of cell strings (CS) connected to one bit line may also change. As the number of rows of cell strings (CS) changes, the number of common source lines connected to the rows of cell strings (CS) may also change.

The number of columns of cell strings (CS) may also be increased or decreased. As the number of columns of cell strings (CS) changes, the number of bit lines connected to the columns of cell strings (CS) and the number of cell strings (CS) connected to one string selection line may also change. .

The height of the cell string (CS) may also be increased or decreased. For example, the number of memory cells (MC) stacked in each cell string (CS) may be increased or decreased. As the number of memory cells (MC) stacked in each cell string (CS) changes, the number of word lines (WL) may also change. For example, the string select transistor provided to each of the cell strings CS may be increased. As the number of string selection transistors provided to each of the cell strings CS changes, the number of string selection lines or common source lines may also change. As the number of string selection transistors increases, the string selection transistors may be stacked in the same form as memory cells (MC).

By way of example, writing and reading may be performed in units of rows of cell strings (CS). Cell strings (CS) may be selected in units of one row by the common source line (CSL), and cell strings (CS) may be selected in units of one row by the string selection lines (SSL). Additionally, voltage may be applied to the common source lines (CSL) as a unit of at least two common source lines. Voltage may be applied to the common source lines (CSL) as a single unit.

In the selected row of cell strings (CS), writing and reading can be performed in units of pages. A page may be one row of memory cells connected to one word line (WL). In the selected row of cell strings (CSs), memory cells may be selected in units of pages by word lines (WLs).

As shown in FIG. 9, the cell string CS includes a cylindrical channel hole CH, a plurality of gate electrodes 131, and a plurality of insulating elements 132 surrounding the channel hole CH in a ring shape. The insulating element 132 is used to separate the plurality of gate electrodes 131, and the gate electrode 131 and the plurality of insulating elements 132 may be stacked while crossing each other along the vertical direction (Z direction). The cylindrical channel hole (CH) includes a cylindrical insulating pillar 121 extending in the vertical direction, a resistance change layer 122, and a semiconductor layer 123 sequentially surrounding the insulating pillar 121 in a cylindrical shell shape. ), and includes a gate insulating layer 124.

The gate electrode 131 may be made of a metal material or a highly doped silicon material. Each gate electrode 131 is connected to one of the word line (WL) and the string select line (SSL).

The insulating element 132 may be made of various insulating materials such as silicon oxide and silicon nitride.

The channel hole (CH) may be composed of multiple layers. The outermost layer of the channel hole (CH) may be the gate insulating layer 124. For example, the gate insulating layer 124 may be made of various insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride. The gate insulating layer 124 may be deposited conformally on the channel hole (CH).

The semiconductor layer 123 may be conformally deposited along the inner surface of the gate insulating layer 124. The semiconductor layer 123 may include a semiconductor material doped into the first type. The semiconductor layer 123 may include a silicon material doped to the same type as the substrate 101. For example, when the substrate 101 includes a silicon material doped to the p-type, the semiconductor layer 123 ) may also include p-type doped silicon material. Alternatively, the semiconductor layer 123 may include materials such as Ge, IGZO, and GaAs.

A resistance change layer 122 may be disposed along the inner surface of the semiconductor layer 123. The resistance change layer 122 may be disposed in contact with the semiconductor layer 123 and may be conformally deposited on the semiconductor layer 123.

The resistance change layer 122 is a layer that changes into a high-resistance state or a low-resistance state depending on the applied voltage, and may be formed of a metal oxide with a high oxygen deficiency rate.

The material and characteristics of the resistance change layer 122 are substantially the same as those of the variable resistance layer 130 described above. The variable resistance layer 122 may include a binary metal oxide with an oxygen deficiency rate of 9% or more or a ternary metal oxide with an oxygen deficiency rate of 9% or more.

The binary metal oxide included in the resistance change layer 122 may include at least one of tantalum oxide (TaOx), titanium oxide (TiOx), stannium oxide (SnOx), chromium oxide (CrOx), and manganese oxide (MnOx). You can.

The ternary metal oxide included in the resistance change layer 122 may include different first metal elements, second metal elements, and oxygen elements. The content of the first metal element in the metal oxide may be greater than the content of the second metal element. For example, the content of the first metal element relative to the total metal in the resistance change layer 122 may be 50 at% or more, and the content of the second metal element relative to the total metal in the resistance change layer 122 may be 35 at% or less. . The first metal element may include one of tantalum (Ta), titanium (Ti), stanium (Sn), chromium (Cr), and manganese (Mn), and the second metal element may include hafnium (Hf) or aluminum. It may include one of (Al), niobium (Nb), lanthanum (La), zirconium (Zr), scandium (Sc), tungsten (W), vananium (V), and molybdenum (Mo).

The content of metal elements in the resistance change layer 122 may be greater than the content of silicon elements. The content of the metal element relative to the sum of the metal element and silicon element in the resistance change layer 122 may be 50 at% or more, and the content of the silicon element relative to the sum of the metal element and silicon element in the resistance change layer 122 may be 35 at% or less. The above-mentioned metal element may include one of tantalum (Ta), titanium (Ti), stanium (Sn), chromium (Cr), and manganese (Mn).

Alternatively, the resistance change layer 122 may include a first metal oxide with an oxygen deficiency rate of 9% or more and a second metal oxide with an oxygen deficiency rate of less than 9%. The content of the first metal oxide may be greater than the content of the second metal oxide. The content of the metal contained in the first metal oxide relative to the total metal included in the resistance change layer 122 is 50 at% or more, and the content of the metal contained in the second metal oxide relative to the total metal included in the resistance change layer 122 is 50 at% or more. The content of the metal may be 35 at% or less. The first metal oxide may include at least one of tantalum oxide (TaOx), titanium oxide (TiOx), stanium oxide (SnOx), chromium oxide (CrOx), and manganese oxide (MnOx). The second metal oxide is hafnium oxide (HfOx), aluminum oxide (AlOx), silicon oxide (SiOx), niobium oxide (NbOx), lanthanum oxide (LaOx), zirconium oxide (ZrOx), scandium oxide (ScOx), and tungsten oxide ( It may include at least one of WOx), vananium oxide (VOx), and molybdenum oxide (MoOx).

The variable resistance memory element 100a has a resistance change layer 122 that facilitates the formation of oxygen vacancies, and thus can increase the difference in resistance values between the high-resistance state and the low-resistance state and have low set voltage and reset voltage characteristics. You can.

An insulating pillar 121 may be deposited along the inner surface of the resistance change layer 122. The insulating pillar 121 can fill the innermost space of the channel hole (CH).

The resistance change layer 122 and the semiconductor layer 123 may contact the doped region 110, that is, the common source region.

A drain region 140 may be provided on the channel hole (CH) of the cell string (CS). Drain region 140 may include a second type doped silicon material. For example, the drain region 140 may include an n-type doped silicon material.

On the drain region 140, a bit line 150 may be provided. The drain region 140 and the bit line 150 may be connected through contact plugs.

Each gate electrode 131 and the gate insulating layer 124, semiconductor layer 123, and resistance change layer 122 regions facing the gate electrode 131 in the horizontal direction (X direction) constitute a memory cell MC. That is, the memory cell MC has a circuit structure in which a transistor including a gate electrode 131, a gate insulating layer 124, and a semiconductor layer 123 and a variable resistance by a resistance change layer 122 are connected in parallel.

This parallel connection structure is continuously arranged in the vertical direction (Z direction) to form a cell string (CS). Additionally, both ends of the cell string CS may be connected to the common source line CSL and the bit line BL, as shown in the circuit diagram of FIG. 10 . By applying voltage to the common source line (CSL) and the bit line (BL), program, read, and erase processes can be performed on the plurality of memory cells (MC).

For example, when a memory cell (MC) to be written is selected, the gate voltage value of that cell is adjusted so that a channel is not formed in the selected cell, that is, the channel is turned off, and the unselected cells are adjusted so that the channel is turned on. The gate voltage values of the cells are adjusted. Accordingly, the current path caused by the voltage applied to the common source line (CSL) and the bit line (BL) passes through the resistance change layer 122 area of the selected memory cell (MC), and at this time, the applied voltage is set to the Vset or Vreset value. This can create a low-resistance state or a high-resistance state, and desired 1 or 0 information can be recorded in the selected memory cell (MC).

In the read operation, similarly, reading of the selected cell may be performed. That is, after the gate voltage applied to each gate electrode 131 is adjusted so that the selected memory cells (MC) are in the channel-off state and the unselected memory cells are in the channel-on state, the common source line (CSL) and the bit line (BL) are adjusted. ), the cell state (1 or 0) can be confirmed by measuring the current flowing in the corresponding cell (MC) by the applied voltage (Vread).

As described above, the variable resistance memory device 100a according to embodiments configures a memory cell (MC) using a resistance change layer 122 made of a material that can easily form a conductive filament by oxygen vacancies. By implementing a memory device by arraying them, the resistance change layer 122 can be formed thinner and have a lower operating voltage than a memory device based on an existing structure, for example, a phase change material or a charge trap. . For example, the variable resistance memory element 100a may have an operating voltage, for example, a write voltage or an erase voltage, whose absolute value is about 4V or less. Alternatively, the variable resistance memory element 100 may have an operating voltage whose absolute value is about 2V or less, for example, a write voltage or an erase voltage.

In this VNAND structure, there is a limit to increasing the number of gate electrodes 131 included in the cell string (CS) due to packaging limitations depending on the height of the cell string (CS). Moreover, in the case of charge trap-based memory devices, there is a limit to reducing the distance between adjacent gate electrodes 131 due to interference. For example, it is known that it is difficult to reduce the pitch of adjacent gate electrodes in the vertical direction (Z direction) to less than about 38 nm, so there is a limit to memory capacity.

The variable resistance memory device 100a according to the embodiment can minimize the pitch between the gate electrodes 131 by using the resistance change layer 122. In some embodiments, this length can be reduced to 20 nm or less, for example, to about 15 nm, and in this case, memory capacity can be improved by more than two times.

In this way, the variable resistance memory device 100a can solve the scaling issue between memory cells in the next generation VNAND, increase the density, and implement low power.

FIG. 11 is a diagram illustrating a portion of a variable resistance memory device 100b including a multi-layered resistance change layer 122 according to an embodiment. Referring to FIGS. 9 and 11 , the variable resistance memory device 100 of FIG. 11 may include a multi-layer resistance change layer 122a. For example, the resistance change layer 122a may include a first resistance change layer (RS1) and a second resistance change layer (RS2) sequentially arranged in a direction away from the semiconductor layer 123.

At least one of the first resistance change layer (RS1) and the second resistance change layer (RS2) may be formed of a metal oxide having an oxygen deficiency rate of 9% or more. For example, the first resistance change layer RS1 uses a first metal oxide with an oxygen deficiency ratio of 9% or more as a matrix, and a second metal oxide with an oxygen deficiency ratio of less than 9%. Can be doped. The oxygen deficiency rate of the first metal oxide included in the first resistance change layer (RS1) may be greater than the oxygen deficiency rate of the first metal oxide included in the second resistance change layer (RS2). Since oxygen vacancies are easily generated in the first resistance change layer RS1 adjacent to the semiconductor layer 123, the operating voltage of the variable resistance memory device 100 can be lowered.

FIG. 12 is a diagram illustrating a portion of a variable resistance memory device 100c further including an oxide layer 125 according to an embodiment. Referring to FIGS. 9 and 12 , the variable resistance memory device 100a of FIG. 12 may further include an oxide layer 125 between the semiconductor layer 123 and the resistance change layer 122. The oxide layer 125 may include silicon oxide, but is not limited thereto. The oxide layer 125 may include a material in contact with the oxide layer 125 in a device to which the variable resistance memory device 100c is applied, for example, an oxide of a material included in the semiconductor layer 123. The thickness of the oxide layer 125 may be smaller than the thickness of the resistance change layer 122. For example, the thickness of the oxide layer 125 may be about 5 nm or less.

FIG. 13 is a diagram illustrating a variable resistance memory device including a conductive pillar according to an embodiment. Comparing FIGS. 9 and 13 , the variable resistance memory element 100d of FIG. 13 may include a conductive pillar 126 instead of an insulating pillar.

The conductive pillar 126 may be in contact with the resistance change layer 122. The conductive pillar 126 may be conformally deposited on the resistance change layer 122. The conductive pillar 126 may be formed of a material with excellent electrical conductivity. For example, the conductive pillar 126 may include at least one of W, Ti, TiN, Ru, RuO ₂ , Ta, and TaN. The conductive pillar 126 may be formed of the same material as the gate electrode 131.

All areas of the conductive pillar 126 may be spatially spaced apart from all areas of the semiconductor layer 123 by the resistance change layer 122. Since the conductive pillar 126 and the semiconductor layer 123 are electrically insulated, voltage can be applied independently to the conductive pillar 126 and the semiconductor layer 123.

The variable resistance memory element 100d is electrically connected to the conductive pillar 126 and is electrically insulated from the first bit line (not shown) and the first bit line that provides a voltage to the conductive pillar 126 and has a semiconductor layer ( 123) and may further include a second bit line (not shown) that is electrically connected to provide a voltage to the semiconductor layer 123.

When the variable resistance memory element 100d operates, voltage may also be applied to the conductive pillar 126. The voltage applied to the conductive pillar 126 may be greater than the gate voltage of the selected memory cell, that is, the turn-off voltage, and may be greater than the voltage applied to the semiconductor layer 123. Thus, a horizontal electric field directed toward the semiconductor layer 123 may be formed in the resistance change layer 122 corresponding to the selected memory cell. Oxygen vacancies within the resistance change layer 122 corresponding to the selected memory cell are concentrated in an area of the resistance change layer 122 that is close to the semiconductor layer 123, making it easier to form a conductive filament.

FIG. 14 is a block diagram schematically illustrating an electronic device 200 including a non-volatile memory device according to an embodiment.

Referring to FIG. 14, the electronic device 200 according to one embodiment includes a PDA, a laptop computer, a portable computer, a web tablet, a wireless phone, a mobile phone, a digital music player, and a wired or wireless device. It may be one of an electronic device or a composite electronic device including at least two of them. The electronic device 200 may include a controller 220, an input/output device 230 such as a keypad, keyboard, and display, a memory 240, and a wireless interface 250 that are coupled to each other through a bus 210.

Controller 220 may include, for example, one or more microprocessors, digital signal processors, microcontrollers, or the like. Memory 240 may be used to store instructions executed by controller 220, for example.

Memory 240 may be used to store user data. The memory 240 may include at least one of non-volatile memory devices according to an embodiment.

The electronic device 200 may use the wireless interface 250 to transmit data to or receive data from a wireless communication network that communicates using RF signals. For example, the wireless interface 250 may include an antenna, a wireless transceiver, etc. The electronic device 200 may be used in communication interface protocols such as 3rd generation communication systems such as CDMA, GSM, NADC, E-TDMA, WCDAM, and CDMA2000.

FIG. 15 is a block diagram schematically illustrating a memory system 300 including a non-volatile memory device according to an embodiment.

Referring to FIG. 15, non-volatile memory devices according to one embodiment may be used to implement a memory system. The memory system 300 may include a memory 310 and a memory controller 320 for storing large amounts of data. The memory controller 320 controls the memory 310 to read or write data stored in the memory 310 in response to a read/write request from the host 330. The memory controller 320 may configure an address mapping table to map an address provided from the host 330, such as a mobile device or a computer system, to a physical address of the memory 310. The memory 310 may include at least one of semiconductor memory devices according to an embodiment of the present invention.

The non-volatile memory device according to the embodiment described so far can be implemented in chip form and used as a neuromorphic computing platform.

FIG. 16 is a diagram schematically showing a neuromorphic device including a memory device according to an embodiment. Referring to FIG. 16, the neuromorphic device 400 may include a processing circuit 410 and/or memory 420. The memory 420 of the neuromorphic device 400 may include a memory system according to an embodiment.

The processing circuit 410 may be configured to control functions for driving the neuromorphic device 400. For example, the processing circuit 410 may control the neuromorphic device 400 by executing a program stored in the memory 420 of the neuromorphic device 400.

The processing circuit 410 may include hardware such as a logic circuit, a combination of hardware and software such as a processor executing software, or a combination thereof. For example, the processor may include a central processing unit (CPU), a graphics processing unit (GPU), an application processor (AP) within the neuromorphic device 400, and an arithmetic logic unit (ALU). , arithmetic logic unit), digital processor, microcomputer, FPGA (field programmable gate array), SoC (System-on-Chip), programmable logic unit, microprocessor, application specific semiconductor (ASIC) application-specific integrated circuit), etc.

Additionally, the processing circuit 410 can read and write various data from the external device 1230 and execute the neuromorphic device 400 using the data. The external device 1230 may include a sensor array including an external memory and/or an image sensor (eg, a CMOS image sensor circuit).

The neuromorphic device 400 shown in FIG. 16 can be applied to a machine learning system. The machine learning system may optionally use, for example, a convolutional neural network (CNN), a deconvolutional neural network, a long short-term memory (LSTM), and/or a gated recurrent unit (GRU). including recurrent neural networks (RNNs), stacked neural networks (SNNs), state-space dynamic neural networks (SSDNNs), deep belief networks (DBNs), generative adversarial networks (GANs), and/or restricted neural networks (RBMs). A variety of artificial neural network organization and processing models, including Boltzmann machines, can be utilized.

These machine learning systems include, for example, linear regression and/or logistic regression, statistical clustering, Bayesian classification, decision trees, principal components, etc. It may include dimensionality reduction, such as principal component analysis, and other types of machine learning models, such as expert systems, and/or combinations of these, including ensemble techniques such as random forests. there is. These machine learning models include, for example, image classification services, user authentication services based on biometric information or biometric data, advanced driver assistance systems (ADAS), voice assistant services, and automatic voice recognition ( It can be used to provide various services such as ASR (automatic speech recognition) service, and can be installed and executed in other electronic devices.

The variable resistance memory device and the electronic device including the same have been described with reference to the embodiments shown in the drawings, but these are merely examples, and those skilled in the art will be able to make various modifications and other equivalent embodiments therefrom. You will understand that it is possible. Although many details are described in detail in the above description, they should be construed as examples of specific embodiments rather than limiting the scope of the invention. Therefore, the scope of the present invention should not be determined by the described embodiments, but rather by the technical idea stated in the patent claims.

121: Insulating pillar
122: Resistance change layer
123: semiconductor layer
124: Gate insulation layer
125: oxide layer
126: Conductive pillar
131: Gate electrode
132: insulation element

Claims (20)

A resistance change layer composed of a metal oxide containing a first metal element and a second metal element and having an oxygen deficiency ratio of 9% or more;
a semiconductor layer disposed on the resistance change layer;
a gate insulating layer disposed on the semiconductor layer; and
A variable resistance memory device comprising a plurality of electrodes spaced apart from each other on the gate insulating layer. According to clause 1,
A variable resistance memory device wherein the content of the first metal element relative to the total metal in the resistance change layer is 50 at% or more. According to clause 1,
A variable resistance memory device wherein the content of the second metal element relative to the total metal in the resistance change layer is 35 at% or less. According to clause 1,
The first metal element is,
A variable resistance memory element containing one of tantalum (Ta), titanium (Ti), stanium (Sn), chromium (Cr), and manganese (Mn). According to clause 1,
The second metal element is,
One of hafnium (Hf), aluminum (Al), niobium (Nb), lanthanum (La), zirconium (Zr), scandium (Sc), tungsten (W), vananium (V), or molybdenum (Mo). A variable resistance memory element comprising: According to clause 1,
The resistance change layer is,
A variable resistance memory device further comprising silicon (Si). According to clause 1,
A variable resistance memory device in which a write voltage with an absolute value of 4V or less is applied to the semiconductor layer. According to clause 1,
A variable resistance memory device further comprising an oxide layer disposed between the semiconductor layer and the resistance change layer. According to clause 8,
A variable resistance memory device in which the thickness of the oxide layer is smaller than the thickness of the resistance change layer. According to clause 1,
The resistance change layer is,
It includes a first resistance change layer and a second resistance change layer sequentially arranged in a direction away from the semiconductor layer,
A variable resistance memory device wherein the oxygen deficiency rate of the first resistance change layer is greater than the oxygen deficiency rate of the second resistance change layer. According to clause 1,
The pitch of the plurality of gate electrodes is,
Variable resistance memory device of 20 nm or less. According to clause 1,
It further includes pillar;
The resistance change layer, the semiconductor layer, and the gate insulating layer sequentially surround the pillar in a shell shape,
A variable resistance memory device wherein the plurality of gate electrodes and the insulating element surround the gate insulating layer in a shell shape. According to clause 12,
The pillar is,
A variable resistance memory element containing an insulating material. According to clause 12,
The pillar is,
A variable resistance memory element containing a conductive material. According to clause 14,
In the above pillar,
A variable resistance memory device to which a voltage higher than the voltage applied to the semiconductor layer is applied. A resistance change layer containing silicon and composed of a metal oxide with an oxygen deficiency ratio of 9% or more;
a semiconductor layer disposed on the resistance change layer;
a gate insulating layer disposed on the semiconductor layer; and
A variable resistance memory device comprising a plurality of electrodes spaced apart from each other on the gate insulating layer. According to clause 16,
The resistance change layer is,
A variable resistance memory element containing at least one of tantalum (Ta), titanium (Ti), stanium (Sn), chromium (Cr), and manganese (Mn). According to clause 16,
A variable resistance memory device in which the content of silicon relative to the sum of metal and silicon in the resistance change layer is 35 at% or less. A resistance comprising a first metal oxide having an oxygen deficiency ratio of 9% or more and a second metal oxide having an oxygen deficiency ratio of less than 9%, wherein the content of the first metal oxide is greater than the content of the second metal oxide. change layer;
a semiconductor layer disposed on the resistance change layer;
a gate insulating layer disposed on the semiconductor layer; and
A variable resistance memory device comprising: a plurality of gate electrodes spaced apart from each other on the gate insulation. According to clause 19,
A variable resistance memory device wherein the content of the metal contained in the second metal oxide relative to the total metal contained in the resistance change layer is 35 at% or less.

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