KR20240025438A - Image sensor, camera module including image sensor, and operating method of image sensor - Google Patents

Abstract

This description relates to image sensors. The image sensor of the present disclosure includes a plurality of pixels, and each of the plurality of pixels includes a photodiode, a transfer gate transistor between the photodiode and the floating diffusion node, and a first voltage node to which the floating diffusion node and the first voltage are supplied. A pixel array including a first transistor therebetween, connected to rows of a plurality of pixels through row lines, and when reading pixels of a selected row, for each of the pixels of the selected row, a second transistor is connected to the gate of the first transistor. a row driver configured to turn on the first transistor by applying a voltage to reset the floating diffusion node, and turn on the transfer gate transistor to dump electrons integrated in the photodiode into the floating diffusion node, and through column lines an analog-to-digital conversion circuit coupled to the plurality of columns of pixels and configured to detect pixel values from pixels in a selected row, wherein, for each of the pixels in the selected row, the row driver turns on a transfer gate transistor. It is configured to apply a clamp voltage lower than the second voltage to the gate of the first transistor.

Description

Image sensor, camera module including the image sensor, and operating method of the image sensor {IMAGE SENSOR, CAMERA MODULE INCLUDING IMAGE SENSOR, AND OPERATING METHOD OF IMAGE SENSOR}

This disclosure relates to electronic devices, and more specifically, to an image sensor that prevents band noise from occurring in image data, a camera module including an image sensor, and a method of operating the image sensor.

Image sensors are installed in various types of electronic devices. As an example, an electronic device including an image sensor may be included as a component of various types of electronic devices such as smart phones, tablet personal computers, laptop personal computers, wearable devices, etc. You can.

An image sensor acquires image information about an external object by converting light reflected from the external object into an electrical signal. An electronic device including an image sensor can display an image on a display panel using acquired image information.

An image sensor may include a plurality of pixels. Each of the plurality of pixels may include a light sensing element that generates electrons in response to light. The light sensing element may include, for example, a photodiode. A photodiode can generate an amount of electrons proportional to the intensity of incident light. An image sensor can measure the intensity of incident light by measuring the amount of electrons generated by a photodiode.

The purpose of the present disclosure is to provide an image sensor that prevents band noise from occurring due to strong incident light that disturbs the operating state of the image sensor, a camera module including the image sensor, and a method of operating the image sensor.

An image sensor according to an embodiment of the present disclosure includes a plurality of pixels, and each of the plurality of pixels includes a photodiode, a transfer gate transistor between the photodiode and the floating diffusion node, and a first voltage supplied to the floating diffusion node. A pixel array including a first transistor between first voltage nodes, connected to a plurality of rows of pixels through row lines, and when reading the pixels of the selected row, for each of the pixels of the selected row, the first transistor A row driver configured to turn on the first transistor by applying a second voltage to the gate to reset the floating diffusion node and turn on the transfer gate transistor to dump electrons integrated in the photodiode into the floating diffusion node, and an analog-to-digital conversion circuit coupled to a plurality of columns of pixels via column lines, and configured to detect pixel values from pixels in a selected row, wherein, for each of the pixels in the selected row, the row driver includes a transfer gate transistor. It is configured to apply a clamp voltage lower than the second voltage to the gate of the first transistor while turning it on.

A camera module according to an embodiment of the present disclosure includes an image sensor configured to generate image data, and a logic circuit configured to correct image data from the image sensor to generate corrected image data, and the image sensor includes a plurality of A pixel including pixels, each of the plurality of pixels including a photodiode, a transfer gate transistor between the photodiode and a floating diffusion node, and a first transistor between the floating diffusion node and a first voltage node to which a first voltage is supplied. An array, connected to a plurality of rows of pixels through row lines, and turns the first transistor by applying a second voltage to the gate of the first transistor for each of the pixels in the selected row when reading the pixels of the selected row. -A row driver configured to turn on to reset the floating diffusion node and turn on the transfer gate transistor to dump electrons integrated in the photodiode to the floating diffusion node, and connected to columns of a plurality of pixels through column lines, and an analog-to-digital conversion circuit configured to detect pixel values from pixels in a selected row, wherein, for each of the pixels in the selected row, the first transistor is turned on while the transfer gate transistor is turned on.

Includes a plurality of pixels, each of the plurality of pixels includes a photodiode, a transfer gate transistor between the photodiode and the floating diffusion node, and a first transistor between the floating diffusion node and a first voltage node to which the first voltage is supplied. A method of operating an image sensor according to an embodiment of the present disclosure includes turning on the first transistor by applying a second voltage to the gate of the first transistor for each pixel in a selected row among a plurality of pixels, thereby floating the first transistor. Resetting the diffusion node, turning on the transfer gate transistor to dump the electrons integrated in the photodiode into the floating diffusion node, and turning on the transfer gate transistor, applying a first voltage and a first voltage to the gate of the first transistor. and applying a clamp voltage that is lower than the second voltage and higher than the ground voltage.

According to the present disclosure, at least one transistor connected to each floating diffusion node of the pixels is biased by a clamp voltage. When a positive amount of electrons exceeding the bias of the clamp voltage of at least one transistor are dumped into the floating diffusion node, the electrons flow out through the at least one transistor. Accordingly, an image sensor that prevents band noise from occurring due to strong incident light, a camera module including the image sensor, and a method of operating the image sensor are provided.

Figure 1 shows an image sensor according to an embodiment of the present invention.
2 shows a pixel and a corresponding current source and analog-to-digital converter according to an embodiment of the present disclosure.
Figure 3 shows a method of operating an image sensor according to an embodiment of the present disclosure.
Figure 4 shows an example in which a clamp voltage is applied to a pixel.
Figure 5 shows an example of signals applied to a pixel by a row driver.
FIG. 6 shows an example of the potential barrier of the fifth section of FIG. 5 of some transistors inside a pixel.
Figure 7 shows another example of signals applied to a pixel by a row driver.
FIG. 8 shows an example of a potential barrier in the seventh section of FIG. 7 of some transistors inside a pixel.
Figure 9 shows another example of signals that a row driver applies to a pixel.
FIG. 10 shows an example of a potential barrier in the ninth section of FIG. 5 of some transistors inside a pixel.
Figure 11 shows another example of signals that a row driver applies to a pixel.
Figure 12 shows an example of some components of a row driver that supply voltage to the reset gate line or the dynamic conversion gain gate line.
13 shows a pixel according to another embodiment of the present disclosure.
14 shows a pixel according to another embodiment of the present disclosure.
15 is a block diagram of an electronic device including a multi-camera module.
FIG. 16 is a detailed block diagram of the camera module of FIG. 15.
FIG. 17 is a block diagram illustrating an electronic device including an image sensor or camera module according to an embodiment of the present disclosure.

Hereinafter, embodiments of the present invention will be described clearly and in detail so that a person skilled in the art can easily practice the present invention. Below, the term 'and/or' is interpreted to include any one of the items listed in connection with the term, and a combination of some or all of the items listed in connection with the term.

Figure 1 shows an image sensor 100 according to an embodiment of the present invention. Referring to FIG. 1, the image sensor 100 includes a pixel array 110, a row driver 120, a ramp signal generator 130 (RSG), an analog-to-digital conversion circuit 140, a memory circuit 150, and It may include a timing generator 160 (TG).

The pixel array 110 may include a plurality of pixels (PX) arranged in a matrix form along rows and columns. Each of the plurality of pixels PX may include photo detectors. For example, photo detectors may include photo diodes, photo transistors, photo gates, pinned photo diodes, etc. Each of the plurality of pixels PX may detect light using a photo detector and convert the amount of detected light into an electrical signal, for example, voltage or current.

A color filter array (CFA) and a lens may be stacked on the pixel array 110. The color filter array may include red (R), green (G), and blue (B) filters. Two or more different color filters may be disposed in the plurality of pixels PX. For example, at least one blue color filter, at least one red color filter, and at least two green color filters may be disposed in the plurality of pixels PX.

The row driver 120 may be connected to each row of pixels PX of the pixel array 110 through the first to mth row lines RL1 to RLm (m is a positive integer). The row driver 120 decodes the address and/or control signal generated by the timing generator 160 to sequentially select the first to mth row lines RL1 to RLm of the pixel array 110, And the selected row line can be driven with a specific voltage. For example, the row driver 120 may drive the selected row line to a voltage suitable for detecting light.

Each of the first to mth row lines RL1 to RLm connected to rows of pixels PX may include two or more lines. Two or more lines, for example, a signal to select (or activate) a pixel's photo detectors, a signal to reset a floating diffusion node, a signal to select a column line, and a signal to control the conversion gain (CG). Various signals, including signals for

The ramp signal generator 130 may generate a ramp signal RS. The ramp signal generator 130 may operate under the control of the timing generator 160. For example, the ramp signal generator 130 may operate under a control signal such as a ramp enable signal or mode signal. In response to the ramp enable signal being activated, the ramp signal generator 130 may generate a ramp signal with a slope set based on the mode signal. For example, the ramp signal generator 130 may generate a ramp signal RS that continuously decreases or increases from the initial level over time.

The analog-to-digital conversion circuit 140 may be respectively connected to columns of pixels PX of the pixel array 110 through first to nth column lines CL1 to CLn (n is a positive integer). The analog-to-digital conversion circuit 140 includes first to nth current sources (CS1 to CSn) and first to nth analog-to-digital converters respectively connected to the first to nth column lines (CL1 to CLn). It may include (AD1~ADn). The first to nth current sources CS1 to CSn may be respectively connected between a ground node to which the ground voltage VSS is applied and the first to nth column lines CL1 to CLn. The first to nth current sources CS1 to CSn may be designed to flow constant currents through the first to nth column lines CL1 to CLn, respectively. While the first to nth current sources CS1 to CSn flow constant currents, the pixels PX of a selected row line among the first to mth row lines RL1 to RLm are pixels corresponding to the intensity of incident light. Voltages may be output to the first to nth column lines CL1 to CLn.

The first to nth analog-to-digital converters AD1 to ADn may commonly receive the ramp signal RS from the ramp signal generator 130. The first to nth analog-to-digital converters AD1 to ADn may compare the voltages of the first to nth column lines CL1 to CLn with the ramp signal RS. A ramp signal is a signal that decreases (or increases) at a constant rate. The first to nth analog-to-digital converters (AD1 to ADn) count until the ramp signal RS becomes smaller (or larger) than the voltages of the first to nth column lines (CL1 to CLn). The value can be latched, and the latched count value can be converted to a digital value and output.

That is, the first to nth analog-to-digital converters AD1 to ADn are the magnitudes of voltages (or currents) output from the pixels PX to the first to nth column lines CL1 to CLn ( or quantity) can be output. Exemplarily, the first to nth analog-to-digital converters AD1 to ADn convert the digital values of the initial voltages of the first to nth column lines CL1 to CLn and the pixel voltages corresponding to the intensity of incident light. Digital values can be output.

The memory circuit 150 may include first to nth memories M1 to Mn respectively corresponding to the first to nth analog-to-digital converters AD1 to ADn. The first to nth memories (M1 to Mn) store digital values (or digital signals) received from the first to nth analog-to-digital converters (AD1 to ADn), and the stored values (or signals) ) can be output as a digital signal (DS). For example, the first to nth memories M1 to Mn may output the difference between the digital values of the initial voltages and the digital values of the pixel voltages as a digital signal DS.

The timing generator 160 (TG) may control timings at which the image sensor 100 operates. The timing generator 160 controls the timings at which the row driver 120 sequentially selects the first to mth row lines RL1 to RLm, and among the first to mth row lines RL1 to RLm. The timings at which signals are transmitted through two or more lines included in the selected row line can be controlled.

The timing generator 160 may control the timings at which the ramp signal generator 130 generates the ramp signal RS and initializes the ramp signal. The timing generator 160 generates timings at which the first to nth analog-to-digital converters (AD1 to ADn) start counting and comparing and timings to initialize the first to nth analog-to-digital converters (AD1 to ADn). You can control them.

2 shows a pixel (PX) and a corresponding current source (CS) and analog-to-digital converter (AD) according to an embodiment of the present disclosure. 1 and 2, the pixel PX includes a first photodiode PD1, a first transfer gate transistor TG1, a second photodiode PD2, a second transfer gate transistor TG2, and a source follower. Transistor (SF), selection gate transistor (SG), dynamic conversion gain transistor (DCG), first switch transistor (S1), second switch transistor (SW2), reset gate transistor (RG), and capacitor. (C) may be included.

The first photodiode PD1 may be connected between a ground node to which the ground voltage GND is applied and the first transfer gate transistor TG1. The first transmission gate transistor TG1 has a gate connected to the first transmission gate line TGL1, a first node connected to the first photodiode PD1, and a second node connected to the first floating diffusion node FD1. Can contain nodes.

The second photodiode PD2 may be connected between a ground node to which the ground voltage GND is applied and the second transfer gate transistor TG2. The second transfer gate transistor TG2 has a gate connected to the second transfer gate line TGL2, a first node connected to the second photodiode PD2, and a second node connected to the second floating diffusion node FD2. Can contain nodes.

The source follower transistor SF has a gate connected to the first floating diffusion node FD1, a first node connected to the first voltage node to which the first voltage V1 is applied, and the first node of the selection gate transistor SG. It may include a second node connected to the node.

The selection gate transistor SG includes a gate connected to a corresponding row line among the first to mth row lines RL1 to RLm, a first node connected to the second node of the source follower transistor SF, and a first node connected to the second node of the source follower transistor SF. It may include a second node connected to a corresponding column line among the to nth column lines CL1 to CLn.

The dynamic conversion gain transistor (DCG) has a gate connected to the dynamic conversion gain line (DCGL), a first node (N1) to which the second node of the first switch transistor (SW1) and the second node of the reset gate transistor (RG) are connected. ) and a second node connected to the first floating diffusion node (FD1).

The reset gate transistor (RG) has a gate connected to the reset gate line (RGL), a first voltage node to which the first voltage (V1) is applied, and a first node connected to the second node of the second switch transistor (SW2), And it may include a second node connected to the first node N1 to which the second node of the first switch transistor SW1 and the first node of the dynamic conversion gain transistor DCG are connected.

The first switch transistor (SW1) has a gate connected to the first switch line (SWL1), a first node connected to the second floating diffusion node (FD2), a second node of the reset gate transistor (RG), and a dynamic conversion gain. It may include a second node connected to the first node N1 to which the first node of the transistor DCG is connected.

The capacitor C may include a first node connected to a voltage node to which the voltage VMIM is applied, and a second node connected to the second floating diffusion node FD2. For example, the first voltage V1 may be a constant voltage. The voltage VMIM may be a voltage that transitions between a high level equal to the first voltage V1 and a low level lower than the first voltage V1 and lower than the ground voltage GND.

The second switch transistor SW2 has a gate connected to the second switch line SWL2, a first node connected to the first node of the capacitor C and a voltage node to which the voltage VMIM is applied, and a first voltage node. And it may include a second node connected to the first node of the reset gate transistor (RG).

Exemplarily, the size of the first photodiode PD1 may be larger than the size of the second photodiode PD2. Accordingly, the amount of electrons generated by the first photodiode PD1 in response to the same incident light may be greater than the amount of electrons generated by the second photodiode PD2.

The current source CS may be connected between the ground node to which the ground voltage GND is applied and the heat line CL. The current source (CS) can be implemented as a current mirror that operates as a current sink. The current source CS may include at least one transistor provided between the ground node and the heat line CL. In order to draw a constant current through the thermal line CL, at least one transistor may be designed to operate in a saturated state.

The analog-to-digital converter (AD) may include a comparator (CP) and a counter (CNT). The comparator CP may compare the ramp signal RAMP with the voltage of the column line CL, for example, the initial voltage or the pixel voltage. The counter CNT may perform counting from a predetermined timing until the output of the comparator CP changes, for example, until the ramp signal RAMP becomes greater or less than the voltage of the column line CL. The count value obtained from the initial voltage of the column line CL may be an initial value. The difference between the count value obtained from the pixel voltage of the column line CL and the initial value may be the pixel value. For example, the pixel value may be a value obtained by subtracting the count value of the pixel voltage from the initial value.

In the process where the pixel (PX) converts the intensity of incident light into a pixel voltage, first, the reset gate transistor (RG) and the dynamic conversion gain transistor (DCG) are turned on, and the first floating diffusion node (FD1) is the first It can be initialized with voltage (V1). The first transfer gate transistor TG1 may dump electrons generated by the first photodiode PD1 into the first floating diffusion node FD1. Due to the dumped electrons, the voltage of the first floating diffusion node FD1 may decrease from the first voltage V1. The source follower transistor SF may output a pixel voltage corresponding to a change in the voltage of the first floating diffusion node FD1 to the column line CL through the select gate transistor SG.

As the intensity of light incident on the pixel PX increases, the amount of electrons generated by the first photodiode PD1 may increase. As the amount of electrons dumped into the first floating diffusion node FD1 increases, the amount of change (i.e., decrease) in the voltage of the first floating diffusion node FD1 may increase.

In some cases, when the amount of electrons generated by the first photodiode PD1 increases, the transistor of the current source CS connected to the column line CL enters the triode state from the saturation state. 1 The range of change in voltage of the floating diffusion node (FD1) may increase. For example, when strong light such as sunlight or illumination light is incident on the pixel, the transistor of the current source CS may enter the triode state from the saturation state.

When the transistor of the current source CS enters the triode state from the saturation state, the amount of current sinking by the current source CS decreases, so the first voltage V1 may temporarily increase. When the first voltage V1 temporarily increases, the output voltage of the source follower transistor SF of the pixels PX sharing the row line RL increases, so that the pixel voltages of the pixels PX increase. Band noise, which reduces brightness, may occur as pixel values corresponding to pixel voltages decrease.

The present invention provides an image sensor that prevents band noise from being generated by generating enough electrons to destroy the saturation state of the current source in the first photo diode (PD1), a camera module including the image sensor, and a method of operating the image sensor. We would like to provide.

Figure 3 shows a method of operating the image sensor 100 according to an embodiment of the present disclosure. Referring to FIGS. 1, 2, and 3, in step S110, the row driver 120 may reset the floating diffusion node. For example, the row driver 120 turns on the reset gate transistor (RG) by applying a turn-on voltage to the reset gate line (RGL), and applies a turn-on voltage to the dynamic conversion gain line (DCGL). By applying it, the dynamic conversion gain transistor (DCG) can be turned on. The first floating diffusion node (FD1) may be reset to the first voltage (V1) through the reset gate transistor (RG) and the dynamic conversion gain transistor (DCG).

In step S120, the row driver 120 may transfer electrons generated in the photo diode to the floating diffusion node and apply a clamp voltage. For example, the row driver 120 resets the first floating diffusion node FD1 and then turns on the first transmission gate line TGL1 after an exposure time (determined by the design of the pixel PX) has elapsed. By applying an on voltage to turn on the first transfer gate transistor TG1, electrons generated by the first photodiode PD1 can be transmitted (or dumped) to the first floating diffusion node FD1. While turning on the first transmission gate transistor TG1, the row driver 120 operates at least one transistor connected to the first floating diffusion node FD1, for example, a dynamic conversion gain transistor (DCG), or a dynamic conversion gain transistor (DCG). A clamp voltage can be applied to the gain transistor (DCG) and reset gate transistor (RG).

The clamp voltage may be a positive voltage higher than the ground voltage (GND). The clamp voltage may be lower than the threshold voltage of the dynamic conversion gain transistor (DCG) or reset gate transistor (RG). The clamp voltage can quasi-on the dynamic conversion gain transistor (DCG) or reset gate transistor (RG). The potential barrier of the transistor in the quasi-on state may be lower than the potential barrier of the transistor in the turn-off state.

Figure 4 shows an example in which a clamp voltage is applied to the pixel PX. Referring to FIG. 4 , as indicated by the first arrow A1, electrons generated by the first photodiode PD1 may be dumped into the first floating diffusion node FD1.

Among the electrons dumped into the first floating diffusion node (FD1), electrons exceeding the potential barrier of the quasi-on dynamic conversion gain transistor (DCG) are connected to the dynamic conversion gain transistor (DCG) as indicated by the second arrow (A2). can pass. Among the electrons passing through the dynamic conversion gain transistor (DCG) and accumulated in the first node (N1), electrons exceeding the potential barrier of the quasi-on reset gate transistor (RG) may pass through the reset gate transistor (RG). there is. Accordingly, excessive electrons are prevented from accumulating in the first floating diffusion node FD1 and the voltage of the column line CL is prevented from excessively dropping. Accordingly, the transistor of the current mirror connected to the column line CL may be maintained in a saturated state.

Figure 5 shows examples of signals applied by the row driver 120 to the pixel PX. Referring to FIGS. 1, 2, and 5, the first section I1 may be an initial section. In the first section (I1), the row driver 120 applies the ground voltage (GND) to the second switch line (SWL2), applies the second voltage (V2) to the reset gate line (RGL), and performs dynamic conversion. A second voltage (V2) is applied to the gain line (DCGL), a ground voltage (GND) is applied to the first switch line (SWL1), and a third voltage (V3) is applied to the first transmission gate line (TGL1). And, the third voltage (V3) can be applied to the second transmission gate line (TGL2), and the third voltage (V3) can be applied to the row line (RL).

The second voltage (V2) may be a positive voltage higher than the first voltage (V1). The third voltage V3 may be a negative voltage lower than the ground voltage (GND).

The reset gate transistor (RG) and the dynamic conversion gain transistor (DCG) may be turned on by the second voltage (V2), and the first floating diffusion node (FD1) may be reset to the first voltage (V1).

The second section I2 may be a shutter section of the first photodiode PD1, for example, an initialization section. In the second section I2, the row driver 120 applies the ground voltage (GND) to the second switch line (SWL2), applies the second voltage (V2) to the reset gate line (RGL), and performs dynamic conversion. A second voltage (V2) is applied to the gain line (DCGL), a ground voltage (GND) is applied to the first switch line (SWL1), and a fourth voltage (V4) is applied to the first transmission gate line (TGL1). After that, the third voltage V3 can be applied, the third voltage V3 can be applied to the second transmission gate line TGL2, and the third voltage V3 can be applied to the row line RL.

The fourth voltage (V4) may be a positive voltage that is lower than the first voltage (V1) and higher than the ground voltage (GND).

The first transfer gate transistor TG1 is turned on by the fourth voltage V4, and electrons accumulated in the first photodiode PD1 can be emptied. Since the reset gate transistor (RG) and the dynamic conversion gain transistor (DCG) are turned on, electrons accumulated in the first photodiode (PD1) are discharged through the second power node to which the second voltage (V2) is applied, The voltage of the first floating diffusion node (FD) may be initialized to the second voltage (V2).

The third section I3 may be a shutter section of the second photodiode PD2, for example, an initialization section. In the third section I3, the row driver 120 applies the ground voltage (GND) to the second switch line (SWL2), applies the second voltage (V2) to the reset gate line (RGL), and performs dynamic conversion. A second voltage (V2) is applied to the gain line (DCGL), the second voltage (V2) is applied to the first switch line (SWL1), a ground voltage (GND) is applied, and the first transmission gate line (TGL1) is applied. ) is applied to the third voltage V3, the fifth voltage V5 is applied to the second transmission gate line TGL2, the third voltage V3 is applied to the row line RL, and the third voltage V3 is applied to the row line RL. Voltage (V3) can be applied.

The fifth voltage (V5) may be a positive voltage equal to or greater than the fourth voltage (V4).

The first switch transistor SW1 may be turned on by the second voltage V2, and the second transfer gate transistor TG2 may be turned on by the fifth voltage V5. Electrons accumulated in the second photodiode PD2 may be emptied, and the second floating diffusion node FD2 may be reset to the first voltage V1.

The fourth section I4 may be an optical integration section. In the fourth section I4, the row driver 120 applies the ground voltage (GND) to the second switch line (SWL2), applies the second voltage (V2) to the reset gate line (RGL), and performs dynamic conversion. A second voltage (V2) is applied to the gain line (DCGL), a ground voltage (GND) is applied to the first switch line (SWL1), and a third voltage (V3) is applied to the first transmission gate line (TGL1). And, the third voltage (V3) can be applied to the second transmission gate line (TGL2), and the third voltage (V3) can be applied to the row line (RL).

The fifth section I5 may be a high conversion gain (HCG) read section of the first photodiode PD1. In the fifth section I5, the row driver 120 applies the second voltage V2 to the second switch line SWL2 and the first clamp voltage VCLP1 to the reset gate line RGL, A second clamp voltage (VCLP2) is applied to the dynamic conversion gain line (DCGL), a ground voltage (GND) is applied to the first switch line (SWL1), and a fourth voltage (V4) is applied to the first transmission gate line (TGL1). ), then apply the third voltage (V3), apply the third voltage (V3) to the second transmission gate line (TGL2), and apply the sixth voltage (V6) to the row line (RL). You can.

The sixth voltage (V6) may be a positive voltage equal to or greater than the second voltage (V2). The first clamp voltage VCLP1 and the second clamp voltage VCLP2 may be the same or different from each other. The first clamp voltage VCLP1 and the second clamp voltage VCLP2 may be positive voltages that are lower than the first voltage V1 and higher than the ground voltage GND. The first clamp voltage VCLP1 may be lower than the threshold voltage of the reset gate transistor RG. The first clamp voltage VCLP1 may quasi-on the reset gate transistor RG. The second clamp voltage VCLP2 may be lower than the threshold voltage of the dynamic conversion gain transistor DCG. The first clamp voltage VCLP1 may quasi-on the dynamic conversion gain transistor (DCG).

The timing at which the first clamp voltage VCLP1 is applied to the reset gate line RGL and the timing at which the sixth voltage V6 is applied to the row line RL may be the same. The timing at which the second clamp voltage VCLP2 is applied to the dynamic conversion gain line DCGL may be later than the timing at which the first clamp voltage VCLP1 is applied to the reset gate line RGL.

In the fifth section I5, the phenomenon described with reference to FIG. 4 may occur in the pixel PX. The first transfer gate transistor TG1 is turned on by the fourth voltage V4 and can dump electrons of the first photodiode PD1 into the first floating diffusion node FD1. The dynamic conversion gain transistor (DCG) and reset gate transistor (RG) may be quasi-on, draining currents that exceed the potential barrier. The selection gate transistor SG is turned on by the sixth voltage V6 and can transmit the change in voltage of the first floating diffusion node FD1 to the column line CL.

The sixth section I6 may be a low conversion gain (LCG) read section of the first photodiode PD1. In the sixth section I6, the row driver 120 applies the second voltage V2 to the second switch line SWL2, applies the ground voltage GND to the reset gate line RGL, and performs dynamic conversion. A second voltage (V2) is applied to the gain line (DCGL), a ground voltage (GND) is applied to the first switch line (SWL1), and a fourth voltage (V4) is applied to the first transmission gate line (TGL1). After that, the third voltage V3 can be applied, the third voltage V3 can be applied to the second transmission gate line TGL2, and the sixth voltage V6 can be applied to the row line RL.

The dynamic conversion gain transistor (DCG) is turned on by the second voltage (V2) to increase the capacitance of the first floating diffusion node (FD1). The reset gate transistor RG is turned on by the first clamp voltage VCLP1, allowing electrons exceeding the potential barrier to leak out. The first transfer gate transistor TG1 is turned on by the fourth voltage V4 and can dump electrons of the first photodiode PD1 into the first floating diffusion node FD1. The selection gate transistor SG is turned on by the sixth voltage V6 and can transmit the change in voltage of the first floating diffusion node FD1 to the column line CL.

The seventh section I7 may be an intermediate initialization section. In the seventh section I7, the row driver 120 applies the second voltage V2 to the second switch line SWL2, applies the second voltage V2 to the reset gate line RGL, and then grounds the row driver 120. A voltage (GND) is applied, a second voltage (V2) is applied to the dynamic conversion gain line (DCGL), a ground voltage (GND) is applied to the first switch line (SWL1), and the first transmission gate line (TGL1) is applied. ), the third voltage V3 is applied to the second transmission gate line TGL2, and the third voltage V3 is applied to the row line RL. Voltage (V6) can be applied.

The dynamic conversion gain transistor (DCG) and reset gate transistor (RG) are turned on by the second voltage (V2), and the first floating diffusion node (FD1) can be initialized to the first voltage (V1).

The eighth section I8 may be a read section of the second photodiode PD2. In the eighth section I8, the row driver 120 applies the ground voltage (GND) to the second switch line (SWL2), applies the ground voltage (GND) to the reset gate line (RGL), and dynamic conversion gain A second voltage (V2) is applied to the line (DCGL), a ground voltage (GND) is applied to the first switch line (SWL1), and a third voltage (V3) is applied to the first transmission gate line (TGL1). , after applying the fifth voltage V5 to the second transmission gate line TGL2, the third voltage V3 may be applied, and the sixth voltage V6 may be applied to the row line RL.

The second transfer gate transistor TG2 is turned on by the fifth voltage V5 and can dump electrons accumulated in the second photodiode PD2 into the second floating diffusion node FD2. The first switch transistor (SW1) and the dynamic conversion gain transistor (DCG) are turned on by the second voltage (V2), and the change in voltage of the second floating diffusion node (FD2) is converted to the first floating diffusion node (FD1). It can be passed on. The selection gate transistor SG is turned on by the sixth voltage V6 and can transmit the change in voltage of the first floating diffusion node FD1 to the column line CL.

In the embodiment of FIG. 5, the image sensor 100 uses a dynamic conversion gain transistor (DCG) and a reset gate transistor (RG) in the high conversion gain read section of the first photodiode PD1, that is, the sixth section I6. The voltage of the first floating diffusion node (FD1) can be clamped using.

FIG. 6 shows an example of a potential barrier in the fifth section I5 of FIG. 5 of some transistors inside the pixel PX. In Figure 6, the horizontal axis indicates the position and the vertical axis shows the potential barrier. In Figure 6, along the horizontal axis, a first photodiode (PD1), a first transfer transistor (TG1), a first floating diffusion node (FD1), a dynamic conversion gain transistor (DCG), a first node (N1), and a reset gate transistor. (RG), and the potential barrier of the node to which the first voltage (V1) is supplied are shown.

As indicated by the fourth arrow A4, in the fifth section, the dynamic conversion gain transistor (DCG) is quasi-on by the second clamp voltage (VCLP2), so the potential barrier of the dynamic conversion gain transistor (DCG) is reduced. can do. Accordingly, electrons exceeding the potential barrier of the dynamic conversion gain transistor (DCG) may leak out to the first node (N1).

Additionally, as indicated by the fifth arrow A5, the reset gate transistor RG is quasi-on by the first clamp voltage VCLP1, so the potential barrier of the reset gate transistor RG may be reduced. Accordingly, positive electrons exceeding the potential barrier of the reset gate transistor RG may leak out to the node of the first voltage V1.

FIG. 7 shows another example of signals applied by the row driver 120 to the pixel PX. Referring to FIGS. 1, 2, and 7, the first section (I1), the second section (I2), the third section (I3), the fourth section (I4), the fifth section (I5), and the seventh section (I7), and the eighth section (I8) are the first section (I1), the second section (I2), the third section (I3), the fourth section (I4), and the fifth section described with reference to FIG. (I5), the 7th section (I7), and the 8th section (I8). Therefore, redundant descriptions are omitted. 5, the first section (I1), the second section (I2), the third section (I3), the fourth section (I4), the fifth section (I5), the seventh section (I7), and the eighth section ( The features described with reference to I8) are the first section (I1), the second section (I2), the third section (I3), the fourth section (I4), the fifth section (I5), and the seventh section in FIG. (I7), and the same can be applied to the eighth section (I8).

In the fifth section I5, as described with reference to FIG. 5, the image sensor 100 uses the dynamic conversion gain transistor (DCG) and the reset gate transistor (RG) to connect the first floating diffusion node (FD1). voltage can be clamped.

The sixth section I6 may be a low conversion gain (LCG) read section of the first photodiode PD1. In the sixth section I6, the row driver 120 applies the second voltage V2 to the second switch line SWL2 and the first clamp voltage VCLP1 to the reset gate line RGL, A second voltage (V2) is applied to the dynamic conversion gain line (DCGL), a ground voltage (GND) is applied to the first switch line (SWL1), and a fourth voltage (V4) is applied to the first transmission gate line (TGL1). After applying, the third voltage (V3) can be applied, the third voltage (V3) can be applied to the second transmission gate line (TGL2), and the sixth voltage (V6) can be applied to the row line (RL). there is.

The dynamic conversion gain transistor (DCG) is turned on by the second voltage (V2) to increase the capacitance of the first floating diffusion node (FD1). The reset gate transistor RG is turned on by the first clamp voltage VCLP1, allowing electrons exceeding the potential barrier to leak out. The first transfer gate transistor TG1 is turned on by the fourth voltage V4 and can dump electrons of the first photodiode PD1 into the first floating diffusion node FD1. The selection gate transistor SG is turned on by the sixth voltage V6 and can transmit the change in voltage of the first floating diffusion node FD1 to the column line CL.

In the embodiment of FIG. 7, the image sensor 100 uses a dynamic conversion gain transistor (DCG) and a reset gate transistor (RG) in the high conversion gain read section of the first photodiode PD1, that is, the sixth section I6. The voltage of the first floating diffusion node (FD1) can be clamped using. In addition, the image sensor 100 increases the voltage of the first floating diffusion node FD1 using the reset gate transistor RG in the low conversion gain read section of the first photodiode PD1, that is, the seventh section I7. Can be clamped.

FIG. 8 shows an example of the potential barrier of the sixth section I6 of FIG. 7 of some transistors inside the pixel PX. In Figure 8, the horizontal axis indicates the position and the vertical axis shows the potential barrier. 8, along the horizontal axis, a first photodiode (PD1), a first transfer gate transistor (TG1), a first floating diffusion node (FD1), a dynamic conversion gain transistor (DCG), a first node (N1), and a reset gate. The transistor RG and the potential barrier of the node to which the first voltage V1 is supplied are shown.

As indicated by the sixth arrow A6, in the sixth section I6, the reset gate transistor RG is quasi-on by the first clamp voltage VCLP1, so the potential barrier of the reset gate transistor RG is may decrease. Accordingly, positive electrons exceeding the potential barrier of the reset gate transistor RG may leak out to the node of the first voltage V1.

By way of example, the potential barriers of the fifth section I5 of FIG. 7 may be the same as those with reference to FIG. 6 . Therefore, redundant descriptions are omitted.

FIG. 9 shows another example of signals applied by the row driver 120 to the pixel PX. Referring to FIGS. 1, 2, and 9, the first section (I1), the second section (I2), the third section (I3), the fourth section (I4), the sixth section (I6), and the seventh section (I7), and the eighth section (I8) is the first section (I1), the second section (I2), the third section (I3), the fourth section (I4), and the sixth section described with reference to FIG. 5. (I6), the 7th section (I7), and the 8th section (I8). Therefore, redundant descriptions are omitted. 5, the first section (I1), the second section (I2), the third section (I3), the fourth section (I4), the sixth section (I6), the seventh section (I7), and the eighth section ( The features described with reference to I8) are the first section (I1), the second section (I2), the third section (I3), the fourth section (I4), the sixth section (I6), and the seventh section in FIG. (I7), and the same can be applied to the eighth section (I8).

The fifth section I5 may be a high conversion gain (HCG) read section of the first photodiode PD1. In the fifth section I5, the row driver 120 applies the second voltage V2 to the second switch line SWL2, applies the ground voltage GND to the reset gate line RGL, and performs dynamic conversion. A second clamp voltage (VCLP2) is applied to the gain line (DCGL), a ground voltage (GND) is applied to the first switch line (SWL1), and a fourth voltage (V4) is applied to the first transmission gate line (TGL1). After application, the third voltage V3 may be applied, the third voltage V3 may be applied to the second transmission gate line TGL2, and the sixth voltage V6 may be applied to the row line RL. .

The dynamic conversion gain transistor (DCG) may be quasi-on by the second clamp voltage (VCLP2). The reset gate transistor (RG) may be turned off by the ground voltage (GND). The first transfer gate transistor TG1 is turned on by the fourth voltage V4 and can dump electrons of the first photodiode PD1 into the first floating diffusion node FD1. The dynamic conversion gain transistor (DCG) can become quasi-on, draining currents that exceed the potential barrier. The selection gate transistor SG is turned on by the sixth voltage V6 and can transmit the change in voltage of the first floating diffusion node FD1 to the column line CL.

In the embodiment of FIG. 9, the image sensor 100 uses the dynamic conversion gain transistor (DCG) in the high conversion gain read section of the first photodiode PD1, that is, the fifth section I5, to detect the first floating diffusion node. The voltage of (FD1) can be clamped.

FIG. 10 shows an example of the potential barrier of the ninth section I5 of FIG. 5 of some transistors inside the pixel PX. In Figure 10, the horizontal axis indicates the position and the vertical axis shows the potential barrier. 10, along the horizontal axis, a first photodiode (PD1), a first transfer gate transistor (TG1), a first floating diffusion node (FD1), a dynamic conversion gain transistor (DCG), a first node (N1), and a reset gate. The transistor RG and the potential barrier of the node to which the first voltage V1 is supplied are shown.

As indicated by the sixth arrow A6, in the fifth section I5, the dynamic conversion gain transistor DCG is quasi-on by the second clamp voltage VCLP2, so the potential of the dynamic conversion gain transistor DCG Barriers can be reduced. Accordingly, positive electrons exceeding the potential barrier of the dynamic conversion gain transistor (DCG) may leak out to the first node (N1).

By way of example, the potential barriers of the seventh section I7 of FIG. 9 may be the same as those with reference to FIG. 8 . Therefore, redundant descriptions are omitted.

FIG. 11 shows another example of signals applied by the row driver 120 to the pixel PX. Referring to FIGS. 1, 2, and 11, the first section (I1), the second section (I2), the third section (I3), the fourth section (I4), the seventh section (I7), and the eighth section (I7). The section I8 includes the first section I1, the second section I2, the third section I3, the fourth section I4, the seventh section I7, and the eighth section I8. Same as section (I8). Therefore, redundant descriptions are omitted. Described with reference to the first section (I1), the second section (I2), the third section (I3), the fourth section (I4), the seventh section (I7), and the eighth section (I8) of FIG. The features are the same in the first section (I1), the second section (I2), the third section (I3), the fourth section (I4), the seventh section (I7), and the eighth section (I8) in FIG. It can be applied.

The fifth section I5 may be a high conversion gain (HCG) read section of the first photodiode PD1. In the fifth section I5, the row driver 120 applies the second voltage V2 to the second switch line SWL2, applies the ground voltage GND to the reset gate line RGL, and performs dynamic conversion. A second clamp voltage (VCLP2) is applied to the gain line (DCGL), a ground voltage (GND) is applied to the first switch line (SWL1), and a fourth voltage (V4) is applied to the first transmission gate line (TGL1). After application, the third voltage V3 may be applied, the third voltage V3 may be applied to the second transmission gate line TGL2, and the sixth voltage V6 may be applied to the row line RL. .

The dynamic conversion gain transistor (DCG) may be quasi-on by the second clamp voltage (VCLP2). The reset gate transistor (RG) may be turned off by the ground voltage (GND). The first transfer gate transistor TG1 is turned on by the fourth voltage V4 and can dump electrons of the first photodiode PD1 into the first floating diffusion node FD1. The dynamic conversion gain transistor (DCG) can become quasi-on, draining currents that exceed the potential barrier. The selection gate transistor SG is turned on by the sixth voltage V6 and can transmit the change in voltage of the first floating diffusion node FD1 to the column line CL.

The sixth section I6 may be a low conversion gain (LCG) read section of the first photodiode PD1. In the sixth section I6, the row driver 120 applies the second voltage V2 to the second switch line SWL2, applies the ground voltage GND to the reset gate line RGL, and performs dynamic conversion. A second voltage (V2) is applied to the gain line (DCGL), a ground voltage (GND) is applied to the first switch line (SWL1), and a fourth voltage (V4) is applied to the first transmission gate line (TGL1). After that, the third voltage V3 can be applied, the third voltage V3 can be applied to the second transmission gate line TGL2, and the sixth voltage V6 can be applied to the row line RL.

The dynamic conversion gain transistor (DCG) is turned on by the second voltage (V2) to increase the capacitance of the first floating diffusion node (FD1). The reset gate transistor RG is turned on by the first clamp voltage VCLP1, allowing electrons exceeding the potential barrier to leak out. The first transfer gate transistor TG1 is turned on by the fourth voltage V4 and can dump electrons of the first photodiode PD1 into the first floating diffusion node FD1. The selection gate transistor SG is turned on by the sixth voltage V6 and can transmit the change in voltage of the first floating diffusion node FD1 to the column line CL.

In the embodiment of FIG. 11, the image sensor 100 uses the dynamic conversion gain transistor (DCG) in the high conversion gain read section of the first photodiode PD1, that is, the fifth section I5, to detect the first floating diffusion node. The voltage of (FD1) can be clamped. In addition, the image sensor 100 increases the voltage of the first floating diffusion node FD1 using the reset gate transistor RG in the low conversion gain read section of the first photodiode PD1, that is, the sixth section I6. Can be clamped.

The potential barriers of the fifth section I5 of FIG. 11 may be the same as those described with reference to FIG. 10 . The potential barriers of the seventh section I7 of FIG. 11 may be the same as those described with reference to FIG. 8 . Therefore, redundant descriptions are omitted.

5 to 11, the first voltage (V1), the second voltage (V2), the third voltage (V3), the fourth voltage (V4), the fifth voltage (V5), and the sixth voltage (V6) The relative highness and lowness of the levels and whether they are positive or negative voltages are explained, but this is only an example. The relative high and low levels of the first voltage (V1), the second voltage (V2), the third voltage (V3), the fourth voltage (V4), the fifth voltage (V5), and the sixth voltage (V6), and Whether it is positive or negative voltage can be modified and changed in various ways.

Exemplarily, in the pixel PIX of FIG. 2, the first node of the reset gate transistor RG is connected to the node to which the first voltage V1 is applied, and the first node of the source follower transistor SF is also It was described as being connected to the node to which the first voltage (V1) is applied. However, the first node of the reset gate transistor (RG) and the first node of the source follower transistor (SF) may be respectively connected to nodes to which different voltages are applied.

Figure 12 shows an example of some components of row driver 120 that supply voltage to the reset gate line or dynamic conversion gain gate line (RGL/DCGL). Referring to FIG. 12, the row driver 120 may include a first transistor (T1), a second transistor (T2), a third transistor (T3), a fourth transistor (T4), and a level shifter (LS). there is.

The first transistor (T1), the second transistor (T2), and the third transistor (T3) are connected in series between the second voltage node to which the second voltage (V2) is supplied and the ground node to which the ground voltage (GND) is supplied. can be connected The first transistor T1 may be a PMOS transistor, and the second transistor T2 and third transistor T3 may be NMOS transistors.

The output of the level shifter LS may be connected to the gates of the first transistor T1 and the second transistor T2. The level shifter LS may convert the driving signal DRV for driving the reset gate line or the dynamic conversion gain gate line RGL/DCGL into a signal in the voltage domain of the second voltage V2.

The clamp enable signal CLP_EN may be transmitted to the gate of the third transistor T3. The first transistor (T1), the second transistor (T2), and the third transistor (T3) are activated when the clamp enable signal (CLP_EN) is at a high level and are deactivated when the clamp enable signal (CLP_EN) is at a low level. An inverter can be formed. The node between the first transistor T1 and the second transistor T2 may be connected to a reset gate line or a dynamic conversion gain gate line (RGL/DCGL) as an output of the inverter.

The fourth transistor T4 may be connected between a voltage node to which the first clamp voltage or the second clamp voltage VCLP1/VCLP2 is applied and a reset gate line or a dynamic conversion gain gate line RGL/DCGL. The clamp enable signal CLP_EN may be transmitted to the gate of the fourth transistor T4. The fourth transistor T4 may be a PMOS transistor.

When the clamp enable signal (CLP_EN) is at a low level, the fourth transistor (T4) applies the first clamp voltage or the second clamp voltage (VCLP1/VCLP2) to the reset gate line or the dynamic conversion gain gate line (RGL/DCGL). It can be approved. When the clamp enable signal CLP_EN is at a high level, the fourth transistor T4 may be turned off.

3 to 12 , a current source ( An embodiment has been described that prevents CS) from deviating from saturation and causing band noise.

According to another embodiment of the present invention, by lowering the threshold voltage of the dynamic conversion gain transistor (DCG) or the reset gate transistor (RG), a clamp voltage ( Even if the ground voltage is applied without applying VCLP1 or VCLP2), a phenomenon similar to applying the clamp voltage (VCLP1 or VCLP2) to the gate of the dynamic conversion gain transistor (DCG) or reset gate transistor (RG) may occur.

For example, by implementing the dynamic conversion gain transistor (DCG) or reset gate transistor (RG) with a native transistor or depletion mode transistor, the dynamic conversion gain transistor (DCG) or reset gate transistor (RG) The threshold voltage may be lowered.

When the threshold voltage of the dynamic conversion gain transistor (DCG) or reset gate transistor (RG) is lowered, the dynamic conversion gain transistor (DCG) or reset gate transistor (RG) is lowered, as described with reference to Figure 6, Figure 8, or Figure 10. is turned on by the ground voltage, and the potential barrier of the dynamic conversion gain transistor (DCG) or reset gate transistor (RG) can be lowered. Accordingly, positive electrons exceeding the potential barrier of the dynamic conversion gain transistor (DCG) or reset gate transistor (RG) may leak out to the first node (N1) or the node to which the first voltage (V1) is applied.

Exemplarily, the threshold voltage of the dynamic conversion gain transistor (DCG) or reset gate transistor (RG) of the pixel (PIX) is implemented to be lower than the threshold voltage of other transistors, and as described with reference to FIGS. 3 to 12 A clamp voltage may be applied to the dynamic conversion gain transistor (DCG) or reset gate transistor (RG).

That is, by lowering the threshold voltage of the dynamic conversion gain transistor (DCG) or reset gate transistor (RG), by applying a clamp voltage to the dynamic conversion gain transistor (DCG) or reset gate transistor (RG), or by applying a clamp voltage to the dynamic conversion gain transistor (DCG) or reset gate transistor (RG). By lowering the threshold voltage of the DCG) or reset gate transistor (RG) and applying a clamp voltage, the dynamic conversion gain transistor (DCG) or reset gate transistor (RG) may be quasi-on. By turning on the dynamic conversion gain transistor (DCG) or the reset gate transistor (RG), electrons accumulated in the first floating diffusion node (FD1) or the first node (N1) may leak out.

By way of example, applying a clamp voltage to a transistor and lowering the threshold voltage of the transistor may be applied to different transistors. For example, a dynamic conversion gain transistor (DCG) may be implemented to have a low threshold voltage. A dynamic conversion gain transistor (DCG) can be quasi-on in response to a ground voltage being applied to the gate.

The reset gate transistor (RG) connected to the node to which the first voltage (V1) is applied may be quasi-on using a clamp voltage. The row driver 120 may quasi-on the reset gate transistor (RG) by applying a clamp voltage to the gate of the reset gate transistor (RG) when necessary.

Figure 13 shows a pixel (PX) according to another embodiment of the present disclosure. 1 and 13, the pixel (PX) includes a photodiode (PD), a transfer gate transistor (TG), a source follower transistor (SF), a select gate transistor (SG), and a reset gate transistor (RG). can do.

The photodiode (PD) may be connected between the ground node to which the ground voltage (GND) is applied and the transmission gate transistor (TG). The transmission gate transistor (TG) may include a gate connected to the transmission gate line (TGL), a first node connected to the photodiode (PD), and a second node connected to the floating diffusion node (FD).

The source follower transistor (SF) is connected to the gate connected to the floating diffusion node (FD), the first node connected to the first voltage node to which the first voltage (V1) is applied, and the first node of the selection gate transistor (SG). It may include a connected second node.

The selection gate transistor SG includes a gate connected to a corresponding row line among the first to mth row lines RL1 to RLm, a first node connected to the second node of the source follower transistor SF, and a first node connected to the second node of the source follower transistor SF. It may include a second node connected to a corresponding column line among the to nth column lines CL1 to CLn.

The reset gate transistor (RG) has a gate connected to the reset gate line (RGL), a first node connected to the first voltage node to which the first voltage (V1) is applied, and a second connected to the floating diffusion node (FD). Can contain nodes.

Embodiments of the present disclosure may be applied to the pixel (PX) of FIG. 13. For example, while the row driver 120 turns on the transfer gate transistor TG, the row driver 120 applies a clamp voltage (e.g., the first clamp voltage VCLP1) to the reset gate line RGL. Alternatively, a second clamp voltage (VCLP2) may be applied. The reset gate transistor (RG) can be quasi-on by the clamp voltage. The reset gate transistor (RG) may clamp the voltage of the floating diffusion node (FD) by leaking electrons that exceed the potential barrier.

Figure 14 shows a pixel (PX) according to another embodiment of the present disclosure. 1 and 14, the pixel PX includes a first subpixel SP1, a second subpixel SP2, a third subpixel SP3, a fourth subpixel SP4, and a source follower transistor ( SF), a selection gate transistor (SG), a dynamic conversion gain transistor (DCG), a reset gate transistor (RG), a first capacitor (CFD1), and a second capacitor (CFD2).

The first subpixel SP1 may include a first photodiode PD1 and a first transfer gate transistor TG1. The first photodiode PD1 may be connected between a ground node to which the ground voltage GND is applied and the first transfer gate transistor TG1. The first transfer gate transistor TG1 has a gate connected to the first transfer gate line TGL1, a first node connected to the first photodiode PD1, and a second node connected to the floating diffusion node FD. It can be included.

The second subpixel SP2 may include a second photodiode PD2 and a second transfer gate transistor TG2. The second photodiode PD2 may be connected between a ground node to which the ground voltage GND is applied and the second transfer gate transistor TG2. The second transfer gate transistor TG2 has a gate connected to the second transfer gate line TGL2, a first node connected to the second photodiode PD2, and a second node connected to the floating diffusion node FD. It can be included.

The third subpixel SP3 may include a third photodiode PD3 and a third transfer gate transistor TG3. The third photodiode PD3 may be connected between the ground node to which the ground voltage GND is applied and the third transfer gate transistor TG3. The third transfer gate transistor TG3 has a gate connected to the third transfer gate line TGL3, a first node connected to the third photodiode PD3, and a second node connected to the floating diffusion node FD. It can be included.

The fourth subpixel SP4 may include a fourth photodiode PD4 and a fourth transfer gate transistor TG4. The fourth photodiode PD4 may be connected between the ground node to which the ground voltage GND is applied and the fourth transfer gate transistor TG4. The fourth transfer gate transistor TG4 has a gate connected to the fourth transfer gate line TGL4, a first node connected to the fourth photodiode PD4, and a second node connected to the floating diffusion node FD. It can be included.

The source follower transistor (SF) is connected to the gate connected to the floating diffusion node (FD), the first node connected to the first voltage node to which the first voltage (V1) is applied, and the first node of the selection gate transistor (SG). It may include a connected second node.

The selection gate transistor SG includes a gate connected to a corresponding row line among the first to mth row lines RL1 to RLm, a first node connected to the second node of the source follower transistor SF, and a first node connected to the second node of the source follower transistor SF. It may include a second node connected to a corresponding column line among the to nth column lines CL1 to CLn.

The dynamic conversion gain transistor (DCG) has a gate connected to the dynamic conversion gain line (DCGL), a first node connected to the second node of the reset gate transistor (RG), and a second node connected to the floating diffusion node (FD). may include.

The reset gate transistor (RG) has a gate connected to the reset gate line (RGL), a first node connected to the first voltage node to which the first voltage (V1) is applied, and a second connected to the floating diffusion node (FD). Can contain nodes.

The first capacitor CFD1 may be connected to the floating diffusion node FD to increase the capacitance of the floating diffusion node FD. As an example, the first capacitor CFD1 may be omitted. The second capacitor CFD2 may be connected to a node between the dynamic conversion gain transistor (DCG) and the reset gate transistor (RG) to provide capacitance. Illustratively, the second capacitor CFD2 may be omitted.

Embodiments of the present disclosure may be applied to the pixel (PX) of FIG. 14. For example, the row driver 120 turns on at least one of the first transfer gate transistor TG1, the second transfer gate transistor TG2, the third transfer gate transistor TG3, and the fourth transfer gate transistor TG4. -While on, the row driver 120 applies a clamp voltage (e.g., a first clamp voltage (VCLP1) or a second clamp voltage (VCLP2)) to the reset gate line (RGL) or the dynamic conversion gain line (DCGL). It can be approved. By way of example, the voltages applied to the dynamic conversion gain line (DCGL) and the reset gate line (RGL) refer to the fifth section (I5) and the sixth section (I6) of FIGS. 5, 7, 9, and 11. It can be adjusted as described.

15 is a block diagram of an electronic device including a multi-camera module. FIG. 16 is a detailed block diagram of the camera module of FIG. 15.

Referring to FIG. 15 , the electronic device 1000 may include a camera module group 1100, an application processor 1200, a PMIC 1300, and an external memory 1400.

The camera module group 1100 may include a plurality of camera modules 1100a, 1100b, and 1100c. Although the drawing shows an embodiment in which three camera modules 1100a, 1100b, and 1100c are arranged, the embodiments are not limited thereto. In some embodiments, the camera module group 1100 may be modified to include only two camera modules. Additionally, in some embodiments, the camera module group 1100 may be modified to include i camera modules (i is a natural number of 4 or more). By way of example, each of the plurality of camera modules 1100a, 1100b, and 1100c of the camera module group 1100 may include the image sensor 100 of FIG. 1 .

Hereinafter, the detailed configuration of the camera module 1100b will be described in more detail with reference to FIG. 16, but the following description may be equally applied to other camera modules 1100a and 1100c depending on the embodiment.

Referring to FIG. 16, the camera module 1100b includes a prism 1105, an optical path folding element (OPFE) 1110, an actuator 1130, an image sensing device 1140, and a storage device. It may include unit 1150.

The prism 1105 includes a reflective surface 1107 of a light-reflecting material and can change the path of light L incident from the outside.

In some embodiments, the prism 1105 may change the path of light L incident in the first direction X to the second direction Y perpendicular to the first direction X. In addition, the prism 1105 rotates the reflecting surface 1107 of the light reflecting material in the A direction about the central axis 1106, or rotates the central axis 1106 in the B direction in the first direction (X). The path of the incident light (L) can be changed to the vertical second direction (Y). At this time, the OPFE 1110 may also move in the third direction (Z) perpendicular to the first direction (X) and the second direction (Y).

In some embodiments, as shown, the maximum rotation angle of the prism 1105 in direction A may be less than 15 degrees in the plus (+) A direction and greater than 15 degrees in the minus (-) A direction. However, the embodiments are not limited thereto.

In some embodiments, the prism 1105 may move about 20 degrees in the plus (+) or minus (-) B direction, or between 10 degrees and 20 degrees, or between 15 degrees and 20 degrees, where the moving angle is plus. It can move at the same angle in the (+) or minus (-) B direction, or it can move to an almost similar angle within a range of about 1 degree.

In some embodiments, the prism 1105 may move the reflective surface 1107 of the light reflecting material in a third direction (eg, Z direction) parallel to the extending direction of the central axis 1106.

OPFE 1110 may include, for example, an optical lens comprised of j groups (where j is a natural number). The j lenses may change the optical zoom ratio of the camera module 1100b by moving in the second direction (Y). For example, assuming that the basic optical zoom magnification of the camera module 1100b is Z, when moving the m optical lenses included in the OPFE 1110, the optical zoom magnification of the camera module 1100b is 3Z or 5Z or The optical zoom magnification can be changed to 5Z or higher.

The actuator 1130 may move the OPFE 1110 or an optical lens (hereinafter referred to as an optical lens) to a specific position. For example, the actuator 1130 may adjust the position of the optical lens so that the image sensor 1142 is located at the focal length of the optical lens for accurate sensing.

The image sensing device 1140 may include an image sensor 1142, control logic 1144, and memory 1146. The image sensor 1142 can sense an image of a sensing object using light (L) provided through an optical lens.

The control logic 1144 may control the overall operation of the camera module 1100b. For example, the control logic 1144 may control the operation of the camera module 1100b according to a control signal provided through the control signal line CSLb.

The memory 1146 may store information necessary for the operation of the camera module 1100b, such as calibration data 1147. The calibration data 1147 may include information necessary for the camera module 1100b to generate image data using light L provided from the outside. The calibration data 1147 may include, for example, information about the degree of rotation described above, information about the focal length, and information about the optical axis. When the camera module 1100b is implemented as a multi-state camera whose focal length changes depending on the position of the optical lens, the calibration data 1147 includes the focal length value for each position (or state) of the optical lens. May include information related to auto focusing.

The storage unit 1150 may store image data sensed through the image sensor 1142. The storage unit 1150 may be placed outside the image sensing device 1140 and may be implemented in a stacked form with a sensor chip constituting the image sensing device 1140. In some embodiments, the storage unit 1150 may be implemented as an Electrically Erasable Programmable Read-Only Memory (EEPROM), but the embodiments are not limited thereto.

Referring to FIGS. 15 and 16 together, in some embodiments, each of the plurality of camera modules 1100a, 1100b, and 1100c may include an actuator 1130. Accordingly, each of the plurality of camera modules 1100a, 1100b, and 1100c may include the same or different calibration data 1147 according to the operation of the actuator 1130 included therein.

In some embodiments, one camera module (e.g., 1100b) of the plurality of camera modules 1100a, 1100b, and 1100c is a folded lens including the prism 1105 and OPFE 1110 described above. type camera module, and the remaining camera modules (e.g., 1100a, 1100b) may be vertical type camera modules that do not include the prism 1105 and OPFE 1110, but embodiments are limited to this. It doesn't work.

In some embodiments, one camera module (e.g., 1100c) among the plurality of camera modules (1100a, 1100b, 1100c) is a vertical camera module that extracts depth information using, for example, IR (Infrared Ray). It may be a type of depth camera. In this case, the application processor 1200 merges the image data provided from the depth camera and the image data provided from another camera module (e.g., 1100a or 1100b) to create a 3D depth image. can be created.

In some embodiments, at least two camera modules (eg, 1100a, 1100b) among the plurality of camera modules 1100a, 1100b, and 1100c may have different fields of view (field of view). In this case, for example, the optical lenses of at least two camera modules (eg, 1100a, 1100b) among the plurality of camera modules 1100a, 1100b, and 1100c may be different from each other, but are not limited thereto.

Additionally, in some embodiments, the viewing angles of each of the plurality of camera modules 1100a, 1100b, and 1100c may be different. In this case, optical lenses included in each of the plurality of camera modules 1100a, 1100b, and 1100c may also be different from each other, but are not limited thereto.

In some embodiments, each of the plurality of camera modules 1100a, 1100b, and 1100c may be arranged to be physically separated from each other. That is, rather than dividing the sensing area of one image sensor 1142 into multiple camera modules 1100a, 1100b, and 1100c, an independent image is generated inside each of the multiple camera modules 1100a, 1100b, and 1100c. Sensor 1142 may be placed.

Referring again to FIG. 15 , the application processor 1200 may include an image processing device 1210, a memory controller 1220, and an internal memory 1230. The application processor 1200 may be implemented separately from the plurality of camera modules 1100a, 1100b, and 1100c. For example, the application processor 1200 and the plurality of camera modules 1100a, 1100b, and 1100c may be implemented separately as separate semiconductor chips.

The image processing device 1210 may include a plurality of sub-image processors 1212a, 1212b, and 1212c, an image generator 1214, and a camera module controller 1216.

The image processing device 1210 may include a plurality of sub-image processors 1212a, 1212b, and 1212c corresponding to the number of camera modules 1100a, 1100b, and 1100c.

Image data generated from each camera module 1100a, 1100b, and 1100c may be provided to the corresponding sub-image processors 1212a, 1212b, and 1212c through separate image signal lines (ISLa, ISLb, and ISLc). For example, image data generated from the camera module 1100a is provided to the sub-image processor 1212a through the image signal line (ISLa), and image data generated from the camera module 1100b is provided to the image signal line (ISLb). The image data generated from the camera module 1100c may be provided to the sub-image processor 1212c through the image signal line (ISLc). Such image data transmission may be performed using, for example, a Camera Serial Interface (CSI) based on Mobile Industry Processor Interface (MIPI), but embodiments are not limited thereto.

Meanwhile, in some embodiments, one sub-image processor may be arranged to correspond to a plurality of camera modules. For example, the sub-image processor 1212a and the sub-image processor 1212c are not implemented separately from each other as shown, but are implemented integrated into one sub-image processor, and the camera module 1100a and the camera module 1100c Image data provided from may be selected through a selection element (eg, multiplexer) and then provided to the integrated sub-image processor.

Image data provided to each sub-image processor 1212a, 1212b, and 1212c may be provided to the image generator 1214. The image generator 1214 may generate an output image using image data provided from each sub-image processor 1212a, 1212b, and 1212c according to image generation information or mode signal.

Specifically, the image generator 1214 merges at least some of the image data generated from the camera modules 1100a, 1100b, and 1100c with different viewing angles according to the image generation information or mode signal to produce an output image. can be created. Additionally, the image generator 1214 may generate an output image by selecting one of the image data generated from the camera modules 1100a, 1100b, and 1100c having different viewing angles according to the image generation information or mode signal. .

In some embodiments, the image generation information may include a zoom signal or zoom factor. Additionally, in some embodiments, the mode signal may be, for example, a signal based on a mode selected by a user.

When the image generation information is a zoom signal (zoom factor) and each camera module (1100a, 1100b, 1100c) has a different observation field (viewing angle), the image generator 1214 performs different operations depending on the type of zoom signal. can be performed. For example, when the zoom signal is the first signal, the image data output from the camera module 1100a and the image data output from the camera module 1100c are merged, and then the merged image signal and the camera module not used for merging are merged. An output image can be generated using the image data output from 1100b. If the zoom signal is a second signal different from the first signal, the image generator 1214 does not merge the image data and uses one of the image data output from each camera module 1100a, 1100b, and 1100c. You can select to create an output image. However, the embodiments are not limited to this, and the method of processing image data may be modified and implemented as necessary.

In some embodiments, the image generator 1214 receives a plurality of image data with different exposure times from at least one of the plurality of sub-image processors 1212a, 1212b, and 1212c, and generates high dynamic range (HDR) data for the plurality of image data. ) By performing processing, merged image data with increased dynamic range can be generated.

The camera module controller 1216 may provide control signals to each camera module 1100a, 1100b, and 1100c. The control signal generated from the camera module controller 1216 may be provided to the corresponding camera modules 1100a, 1100b, and 1100c through separate control signal lines (CSLa, CSLb, and CSLc).

One of the plurality of camera modules (1100a, 1100b, 1100c) is designated as a master camera (e.g., 1100b) according to image generation information or mode signals including a zoom signal, and the remaining camera modules (e.g., For example, 1100a, 1100c) can be designated as slave cameras. This information may be included in the control signal and provided to the corresponding camera modules 1100a, 1100b, and 1100c through separate control signal lines (CSLa, CSLb, and CSLc).

Camera modules operating as master and slave can be changed depending on the zoom factor or operation mode signal. For example, when the viewing angle of the camera module 1100a is wider than that of the camera module 1100b and the zoom factor indicates a low zoom ratio, the camera module 1100b operates as a master and the camera module 1100a operates as a slave. It can operate as . Conversely, when the zoom factor indicates a high zoom magnification, the camera module 1100a may operate as a master and the camera module 1100b may operate as a slave.

In some embodiments, the control signal provided from the camera module controller 1216 to each camera module 1100a, 1100b, and 1100c may include a sync enable signal. For example, if the camera module 1100b is a master camera and the camera modules 1100a and 1100c are slave cameras, the camera module controller 1216 may transmit a sync enable signal to the camera module 1100b. The camera module 1100b that receives this sync enable signal generates a sync signal based on the sync enable signal, and transmits the generated sync signal to the camera modules (1100b) through the sync signal line (SSL). 1100a, 1100c). The camera module 1100b and the camera modules 1100a and 1100c may be synchronized to this sync signal and transmit image data to the application processor 1200.

In some embodiments, a control signal provided from the camera module controller 1216 to the plurality of camera modules 1100a, 1100b, and 1100c may include mode information according to the mode signal. Based on this mode information, the plurality of camera modules 1100a, 1100b, and 1100c may operate in a first operation mode and a second operation mode in relation to the sensing speed.

In a first operation mode, the plurality of camera modules 1100a, 1100b, and 1100c generate an image signal at a first rate (e.g., generate an image signal at a first frame rate) and transmit it to a second rate higher than the first rate. The image signal may be encoded at a higher rate (for example, an image signal of a second frame rate higher than the first frame rate), and the encoded image signal may be transmitted to the application processor 1200. At this time, the second speed may be 30 times or less than the first speed.

The application processor 1200 stores the received image signal, that is, the encoded image signal, in the internal memory 1230 provided inside or the memory 1400 outside the application processor 1200, and then stores the received image signal, that is, the encoded image signal, in the internal memory 1230 or the memory 1400 external to the application processor 1200. Alternatively, the encoded image signal may be read from the external memory 1400, decoded, and image data generated based on the decoded image signal may be displayed. For example, a corresponding subprocessor among the plurality of subprocessors 1212a, 1212b, and 1212c of the image processing device 1210 may perform decoding and may also perform image processing on the decoded image signal.

In the second operation mode, the plurality of camera modules 1100a, 1100b, and 1100c generate image signals at a third rate lower than the first rate (for example, generate image signals at a third frame rate lower than the first frame rate). generation) and transmit the image signal to the application processor 1200. The image signal provided to the application processor 1200 may be an unencoded signal. The application processor 1200 may perform image processing on a received image signal or store the image signal in the internal memory 1230 or the external memory 1400.

The PMIC 1300 may supply power, for example, a power supply voltage, to each of the plurality of camera modules 1100a, 1100b, and 1100c. For example, the PMIC 1300, under the control of the application processor 1200, supplies first power to the camera module 1100a through the power signal line (PSLa) and the camera module (1100a) through the power signal line (PSLb). Second power may be supplied to 1100b), and third power may be supplied to the camera module 1100c through the power signal line (PSLc).

The PMIC 1300 can generate power corresponding to each of the plurality of camera modules 1100a, 1100b, and 1100c in response to the power control signal (PCON) from the application processor 1200, and also adjust the power level. there is. The power control signal (PCON) may include a power adjustment signal for each operation mode of the plurality of camera modules 1100a, 1100b, and 1100c. For example, the operation mode may include a low power mode, and in this case, the power control signal (PCON) may include information about the camera module operating in the low power mode and the set power level. The levels of power provided to each of the plurality of camera modules 1100a, 1100b, and 1100c may be the same or different from each other. Additionally, the level of power may change dynamically.

By way of example, the image sensor 100 described with reference to FIGS. 1 to 14 may correspond to the image sensor 1142 of FIG. 16 . While the image sensor 1142 dumps electrons accumulated in the photodiode through the transfer gate to the floating diffusion node, at least one transistor connected to the floating diffusion node, for example, a dynamic conversion gain transistor, a reset gate transistor, or a dynamic conversion node. The voltage of the floating diffusion node can be clamped by applying a clamp voltage to the gain transistor and reset gate transistor instead of the ground voltage. Accordingly, band noise can be prevented from occurring in image data when strong light is incident.

FIG. 17 is a block diagram illustrating an electronic device 2000 including an image sensor 200 or a camera module 1100b according to an embodiment of the present disclosure. Referring to FIG. 17, the electronic device 2000 includes a main processor 2100, a touch panel 2200, a touch driver circuit 2202 (TDI) (Touch Driver IC), a display panel 2300, and a display driver circuit 2302. ) (DDI) (Display Driver IC), system memory (2400), storage device (2500), audio processor (2600), communication block (2700), image processor (2800), and user interface (2900). there is. In an exemplary embodiment, the electronic device 2000 includes a personal computer, a laptop computer, a server, a workstation, a mobile communication terminal, a personal digital assistant (PDA), a portable media player (PMP), a digital camera, a smartphone, a tablet computer, It may be one of various electronic devices such as wearable devices. The electronic device 2000 may be an electronic system (eg, an autonomous driving system or an infotainment system, etc.) mounted on a vehicle such as a car, electric vehicle, or self-driving car.

The main processor 2100 may control overall operations of the electronic device 2000. The main processor 2100 can control/manage the operations of components of the electronic device 2000. The main processor 2100 can process various operations to operate the electronic device 2000. The touch panel 2200 may be configured to detect a touch input from the user under the control of the touch driving circuit 2202. The display panel 2300 may be configured to display image information under the control of the display driving circuit 2302.

The system memory 2400 may store data used in the operation of the electronic device 2000. For example, the system memory 2400 may include volatile memory such as Static Random Access Memory (SRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), and/or Phase-change RAM (PRAM), Magneto-resistive RAM (MRAM), etc. ), Resistive RAM (ReRAM), and Ferro-electric RAM (FRAM).

The storage device 2500 can store data regardless of power supply. As an example, the storage device 2500 may include at least one of various non-volatile memories such as flash memory, PRAM, MRAM, ReRAM, FRAM, etc. As an example, the storage device 2500 may include built-in memory and/or removable memory of the electronic device 2000.

The audio processor 2600 can process an audio signal using the audio signal processor 2610. The audio processor 2600 may receive audio input through the microphone 2620 or provide audio output through the speaker 2630. The communication block 2700 may exchange signals with an external device/system through the antenna 2710. The transceiver 2720 and MODEM (Modulator/Demodulator, 2730) of the communication block 2700 are LTE (Long Term Evolution), WiMax (Worldwide Interoperability for Microwave Access), GSM (Global System for Mobile communication), and CDMA (Code Division Multiple) Signals exchanged with external devices/systems can be processed according to at least one of various wireless communication protocols such as Bluetooth, NFC (Near Field Communication), Wi-Fi (Wireless Fidelity), and RFID (Radio Frequency Identification). there is.

The image processor 2800 may receive light through the lens 2810. The image device 2820 and the image signal processor 2830 (ISP) included in the image processor 2800 may generate image information about an external object based on the received light. The user interface 2900 may include an interface for exchanging information with a user, excluding the touch panel 2200, display panel 2300, audio processor 2600, and image processor 2800. The user interface 2900 may include a keyboard, mouse, printer, projector, various sensors, human body communication devices, etc.

The electronic device 2000 may further include a power management circuit 2010 (PMIC) (Power Management IC) and a battery 2020. The power management circuit 2010 generates internal power from the power supplied from the battery 2020, and supplies internal power to the main processor 2100, the touch panel 2200, and the touch driving circuit 2202 (TDI) (Touch Driver IC). ), display panel 2300, display driving circuit 2302 (DDI) (Display Driver IC), system memory 2400, storage device 2500, audio processor 2600, communication block 2700, image processor ( 2800), and may be provided to a user interface 2900.

Each of the components of the electronic device 2000 may include a safety monitor (SM). Additionally, a safety monitor (SM) may be coupled to a channel between components of the electronic device 2000. The safety monitor (SM) detects that components and channels between components cause malfunction, and when a malfunction is detected, it can transmit a warning signal to the main processor 2100. The safety monitor (SM) can be implemented based on ISO26262 or ASIL.

The imaging device 1820 may correspond to the camera module 1100b described with reference to FIGS. 15 and 16 . The image device 1820 may include the image sensor 100 described with reference to FIGS. 1 to 14 . While the image sensor 1142 dumps electrons accumulated in the photodiode through the transfer gate to the floating diffusion node, at least one transistor connected to the floating diffusion node, for example, a dynamic conversion gain transistor, a reset gate transistor, or a dynamic conversion node. The voltage of the floating diffusion node can be clamped by applying a clamp voltage to the gain transistor and reset gate transistor instead of the ground voltage. Accordingly, band noise can be prevented from occurring in image data when strong light is incident.

In the above-described embodiments, components according to the technical idea of the present invention have been described using terms such as first, second, third, etc. However, terms such as first, second, third, etc. are used to distinguish components from each other and do not limit the present invention. For example, terms such as first, second, third, etc. do not imply order or any form of numerical meaning.

In the above-described embodiments, components according to embodiments of the present invention have been referenced using blocks. Blocks include various hardware devices such as IC (Integrated Circuit), ASIC (Application Specific IC), FPGA (Field Programmable Gate Array), CPLD (Complex Programmable Logic Device), software such as firmware and applications running on the hardware devices, Alternatively, it may be implemented as a combination of a hardware device and software. Additionally, blocks may include circuits composed of semiconductor elements in an IC or circuits registered as IP (Intellectual Property).

The above-described details are specific embodiments for carrying out the present invention. The present invention will include not only the above-described embodiments, but also embodiments that can be simply changed or easily changed in design. In addition, the present invention will also include technologies that can be easily modified and implemented using the embodiments. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be determined by the claims and equivalents of the present invention as well as the claims described later.

100: image sensor
110: pixel array
120: row driver
130: Ramp signal generator
140: Analog-digital conversion circuit
150: memory circuit
160: Timing generator

Claims (10)

Comprising a plurality of pixels, each of the plurality of pixels includes a photodiode, a transfer gate transistor between the photodiode and a floating diffusion node, and a first voltage node between the floating diffusion node and a first voltage node to which a first voltage is supplied. a pixel array including transistors;
connected to rows of the plurality of pixels through row lines, and turning the first transistor by applying a second voltage to the gate of the first transistor for each of the pixels in a selected row among the plurality of row lines. a row driver configured to turn on to reset the floating diffusion node and turn on the transfer gate transistor to dump electrons integrated in the photodiode into the floating diffusion node; and
an analog-to-digital conversion circuit coupled to the columns of the plurality of pixels through column lines and configured to detect pixel values from pixels in the selected row,
For each of the pixels in the selected row, the row driver is configured to apply a clamp voltage lower than the second voltage to the gate of the first transistor while turning on the transfer gate transistor. According to paragraph 1,
An image sensor wherein the voltage that turns on the transmission gate transistor is higher than the clamp voltage. According to paragraph 1,
The image sensor where the clamp voltage is higher than the ground voltage. According to paragraph 1,
The row driver is:
A first PMOS transistor including a gate to which a driving voltage is applied, a first node to which the second voltage is applied, and a second node connected to the gate of the first transistor of each pixel;
a first NMOS transistor including a gate to which the driving voltage is applied, a first node connected to the gate of the first transistor of each pixel, and a second node;
a second NMOS transistor including a gate to which a clamp enable signal is applied, a first node connected to a second node of the first NMOS transistor, and a second node connected to a ground node;
An image sensor comprising a second PMOS transistor including a gate to which the clamp enable signal is applied, a first node to which the clamp voltage is applied, and a second node connected to the gate of the first transistor of each pixel. According to paragraph 1,
Each of the plurality of pixels further includes a second transistor between the first transistor and the second floating diffusion node,
For each of the pixels in the selected row, the row driver is configured to reset the floating diffusion node by simultaneously applying the second voltage to the gate of the first transistor and the gate of the second transistor. According to clause 5,
For each of the pixels in the selected row, the row driver is configured to apply a second clamp voltage lower than the second voltage to the gate of the second transistor while turning on the transfer gate transistor. According to clause 6,
For each of the pixels in the selected row, the row driver is configured to apply the first clamp voltage to the gate of the first transistor and then apply the second clamp voltage to the gate of the second transistor. According to clause 6,
The row driver is:
A first PMOS transistor including a gate to which a driving voltage is applied, a first node to which the second voltage is applied, and a second node connected to the gate of the second transistor of each pixel;
a first NMOS transistor including a gate to which the driving voltage is applied, a first node connected to the gate of the second transistor of each pixel, and a second node;
a second NMOS transistor including a gate to which a clamp enable signal is applied, a first node connected to a second node of the first NMOS transistor, and a second node connected to a ground node;
An image sensor including a second PMOS transistor including a gate to which the clamp enable signal is applied, a first node to which the second clamp voltage is applied, and a second node connected to the gate of the second transistor of each pixel. . An image sensor configured to generate image data; and
A logic circuit configured to correct the image data received from the image sensor to generate corrected image data,
The image sensor is:
Comprising a plurality of pixels, each of the plurality of pixels includes a photodiode, a transmission gate transistor between the photodiode and a floating diffusion node, and a first voltage node between the floating diffusion node and a first voltage node to which a first voltage is supplied. a pixel array including transistors;
It is connected to rows of the plurality of pixels through row lines, and when reading pixels of a selected row, a second voltage is applied to the gate of the first transistor for each of the pixels in the selected row, so that the first transistor a row driver configured to turn on to reset the floating diffusion node and turn on the transfer gate transistor to dump electrons integrated in the photodiode into the floating diffusion node; and
an analog-to-digital conversion circuit coupled to the columns of the plurality of pixels through column lines and configured to detect pixel values from pixels in the selected row,
In each of the pixels of the selected row, the first transistor is turned on while the transmission gate transistor is turned on. Comprising a plurality of pixels, each of the plurality of pixels includes a photodiode, a transfer gate transistor between the photodiode and a floating diffusion node, and a first voltage node between the floating diffusion node and a first voltage node to which a first voltage is supplied. In a method of operating an image sensor including a transistor:
For each pixel in a selected row among the plurality of pixels, turning on the first transistor by applying a second voltage to the gate of the first transistor to reset the floating diffusion node; and
Turning on the transfer gate transistor to dump electrons integrated in the photodiode into the floating diffusion node, and while turning on the transfer gate transistor, the first voltage and the first voltage are applied to the gate of the first transistor. 2. A method of operation comprising applying a clamp voltage that is lower than the voltage and higher than the ground voltage.

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