KR20240023992A - Methods and systems of detecting defect of wafer - Google Patents

Abstract

A method of detecting a defect point of a wafer according to an aspect of the technical idea of the present disclosure includes obtaining a wafer level map generated by measuring a wafer for each process step, and combining a plurality of wafer level maps generated by measuring the wafer for each process step. generating a synthetic wafer map, classifying each defect point into a defect cluster based on the location of each defect point included in the synthetic wafer map, and the first process step in which a defect occurs based on step information for each defect cluster. It may include a step of detecting.

Description

Method and system for wafer defect detection {METHODS AND SYSTEMS OF DETECTING DEFECT OF WAFER}

The technical idea of the present disclosure relates to wafer defects, and in particular, to a method and system for detecting the first defect of a wafer through data related to defects occurring on the back side of the wafer.

The back side of a semiconductor wafer may be continuously contaminated by particles caused by friction and vibration generated during processing. For example, due to the force and pressure applied between the wafer and the chuck during the photo process, the local surface of the wafer may rise and a hot spot may occur. If the hotspot size is outside the DOF (depth of focus) range, the product's pattern may not be properly formed during the photo process, which may cause defocus issues. Due to defocus issues, the productivity and quality of semiconductor products may decrease and yield may decrease.

The problem that the technical idea of the present disclosure seeks to solve is to provide a method and system for early detection of defects on the back of a wafer and for quickly finding processes that cause defects.

A method for detecting wafer defects according to one aspect of the technical idea of the present disclosure includes obtaining a wafer level map generated by measuring a wafer for each process step, combining a plurality of wafer level maps generated by measuring the wafer for each process step, Creating a synthetic wafer map, classifying each defect point into a defect cluster based on the location of each defect point included in the synthetic wafer map, and determining the first process step in which the defect occurred based on step information for each defect cluster. It includes a detection step.

A system for detecting wafer defects according to one aspect of the technical idea of the present disclosure includes a memory storing a program for detecting wafer defects and a processor executing the program stored in the memory, and generates the wafer by measuring the wafer for each process step. A synthesized wafer level map is acquired, a plurality of wafer level maps generated by measuring each step are combined to generate a synthetic wafer map, and based on the location of each defect point included in the synthetic wafer map, each defect point is clustered into a defect cluster. It includes the step of classifying each defect cluster and detecting the first process step in which the defect occurred based on step information for each defect cluster.

A computer-readable non-transitory storage medium for detecting defects in a wafer according to one aspect of the technical idea of the present disclosure stores instructions that, when executed by a processor, cause the processor to detect defect points on the wafer, and process the wafer. Obtaining a wafer level map generated by measuring for each step, generating a composite wafer map by combining a plurality of wafer level maps generated by measuring for each step, based on the location of each defect point included in the composite wafer map. , classifying each defect point into defect clusters and detecting the first process step in which a defect occurred based on step information for each defect cluster.

According to the method and system according to an exemplary embodiment of the present disclosure, defects occurring on the back of the wafer can be clustered, the initial defect point can be detected for each cluster, and the process causing the defect on the back of the wafer can be tracked accordingly. there is. By early tracking of process equipment that causes defects in wafers, the productivity and quality of semiconductor products can be improved, and thus the yield of semiconductor products can be increased.

In addition, according to the method and system according to an exemplary embodiment of the present disclosure, it is possible to standardize the method of counting the number of defects for each wafer level map, and thus to conveniently and consistently cluster defects according to the user's wishes. It can be defined.

The effects that can be obtained from the exemplary embodiments of the present disclosure are not limited to the effects mentioned above, and other effects not mentioned are common knowledge in the technical field to which the exemplary embodiments of the present disclosure belong from the following description. It can be clearly derived and understood by those who have it. That is, unintended effects resulting from implementing the exemplary embodiments of the present disclosure may also be derived by those skilled in the art from the exemplary embodiments of the present disclosure.

FIG. 1 is a diagram illustrating a process for detecting defects in a target wafer according to an exemplary embodiment of the present disclosure.
FIG. 2 is a diagram illustrating a process of generating a plurality of wafer level maps for a target wafer according to an exemplary embodiment of the present disclosure.
3A to 3B are diagrams for explaining a wafer level map and a composite wafer map according to an exemplary embodiment of the present disclosure.
FIG. 4 is a diagram for explaining an initial defect point according to an exemplary embodiment of the present disclosure.
Figure 5 is a block diagram of a system according to an exemplary embodiment of the present disclosure.
Figure 6 is a flowchart showing a method for detecting an initial defect point according to an exemplary embodiment of the present disclosure.
Figure 7 is a flowchart showing a method for classifying defect points according to an exemplary embodiment of the present disclosure.
Figure 8 is a flowchart showing a method of searching for adjacent defect points according to an exemplary embodiment of the present disclosure.
Figure 9 is a flowchart showing a method for detecting an initial defect point according to an exemplary embodiment of the present disclosure.
10A to 10G are diagrams for explaining defect points forming a defect cluster according to an exemplary embodiment of the present disclosure.
Figure 11 is a table explaining the initial defect point for each defect cluster for the target wafer.
Figure 12 is a block diagram showing a system according to an exemplary embodiment of the present disclosure.

Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. When describing with reference to the drawings, identical or corresponding components are given the same reference numerals and overlapping descriptions thereof are omitted.

FIG. 1 is a diagram illustrating a process in which a defect in a target wafer (WSPi) is detected according to an exemplary embodiment of the present disclosure.

In the process of manufacturing a semiconductor wafer, a photo process may be performed on the semiconductor wafer multiple times. Semiconductor wafers may be contaminated by particles caused by friction and vibration while going through each photo process. The photo process may be referred to as photolithography or photolithography process.

Referring to FIG. 1, the target wafer (WSPi) may refer to a wafer that has undergone the photo process of the i-th step (in this case, i≥1) among several photo processes performed on a semiconductor wafer. There may be many defects due to particles on the target wafer (WSPi).

The measurement equipment 100 can measure defects in the semiconductor wafer whenever a photo process is completed on the semiconductor wafer. In an exemplary embodiment, the measurement equipment 100 measures the target wafer (WSPi) after the i-th photo process is completed, and generates a wafer level map (WLMi) corresponding to the i-th photo process to the wafer defect detection system 200. It can be delivered to . The measurement equipment 100 may be referred to as a photo level measurement equipment. In an exemplary embodiment, the measurement equipment 100 measures the target wafer at the end of each photo process, generates a wafer level map, and transmits it to the system 200, so when the ith photo process is completed, the system ( In 200), a wafer level map (not shown) corresponding to the first photo process or a wafer level map (WLMi) corresponding to the ith photo process may be stored.

A wafer level map (WLMi) may include data on defects measured in the target wafer (WSPi). Data corresponding to each defect may be referred to as a defect point. The wafer level map (WLMi) may be referred to as a wafer leveling map. The defect point may include the location and height of each defect, and step information of the photo process performed on the target wafer (WSP). As the photo process progresses, the value of step information corresponding to the photo process may increase. For example, the third photo process may be a process performed temporally later than the first photo process. Accordingly, the step information value corresponding to the third photo process may be larger than the step information value corresponding to the first photo process.

In an exemplary embodiment, the step information may be step information of a photo process performed on the target wafer (WSPi), that is, information indicating which photo process was the last photo process performed. For example, the wafer level map WLMi of FIG. 1 may include data indicating that the photo process performed on the target wafer WSPi is the i-th step. Because a semiconductor wafer goes through the photo process multiple times during the manufacturing process, multiple wafer-level maps may exist for one wafer. This will be described later with reference to Figure 2.

System 200 may be a system for executing a method for detecting wafer defects according to an embodiment of the present invention. System 200 may be referred to as a wafer defect detection system. The system 200 may store a plurality of wafer level maps corresponding to all photo process steps performed before the i th photo process, including a wafer level map (WLMi) corresponding to the i th photo process of the target wafer (WSPi). You can. System 200 can combine multiple stored wafer level maps. System 200 may generate a composite wafer map based on the plurality of wafer level maps combined. A composite wafer map may be referred to as a composite map. The composite wafer map may include multiple defect points. The system 200 may classify the defect points of the composite wafer map into several clusters and detect the first defect point of the target wafer (WSPi) based on the classified defect points. At this time, the first defect point may be referred to as a fundamental defect point. In an example embodiment, the system 200 may classify defect points in the composite wafer map into defect clusters based on the distance between each defect point. The process by which a plurality of defect points form a defect cluster will be described later with reference to FIGS. 10A to 10G.

The system 200 can extract the defect point with the smallest step information for each defect cluster. The smallest step information may mean step information corresponding to the most preceding process in time.

In an exemplary embodiment, when there is only one defect point extracted from a defect cluster, that is, a defect point with the smallest step information, the extracted defect point may be referred to as the first defect point of the defect cluster. In an exemplary embodiment, when there are multiple defect points extracted from one defect cluster, that is, defect points having the smallest step information, the defect point with the highest height among the extracted defect points is selected from the defect cluster. It can be referred to as the first defect point of .

System 200 may include a processor 210 and memory 220. For example, the system 200 may be a computing system such as a personal computer, mobile phone, server, etc., or may be a module in which a plurality of processing cores and memory are mounted on a board as independent packages, and may include a plurality of processing cores. It may be a system-on-chip (SoC) in which data and memory are built into one chip.

Processor 210 can communicate with memory 220 and execute instructions. In some embodiments, processor 210 may execute a program stored in memory 220. A program can contain a series of instructions. The processor 210 may be any hardware capable of independently executing instructions, and may be referred to as an application processor (AP), communication processor (CP), central processing unit (CPU), processor core, core, etc.

The processor 210 and memory 220 may communicate. Memory 220 may be accessed by processor 210 and may store software elements executable by processor 210 . Software elements include, but are not limited to, software components, programs, applications, computer programs, application programs, system programs, software development programs, machine programs, operating system (OS) software, middleware, firmware, software modules, and routines. , subroutines, functions, methods, procedures, software interfaces, API (application program interface), instruction sets, computing code, computer code, code segments, computer code segments, words, values, symbols, or a combination of two or more of these. You can.

Memory 220 may be any hardware capable of storing information and accessible by processor 210. For example, the memory 220 includes read only memory (ROM), random-access memory (RAM), dynamic random access memory (DRAM), double-data-rate dynamic random access memory (DDR-DRAM), and SDRAM ( synchronous dynamic random access memory (SRAM), static random access memory (SRAM), magnetoresistive random access memory (MRAM), programmable read only memory (PROM), erasable programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM), Flash memory, polymer memory, phase change memory, ferroelectric memory, SONOS (silicon-oxide-nitride-oxide-silicon) memory, magnetic card/disk, optical card/disk, or these It may include a combination of two or more of these.

A method for wafer initial defect detection according to an example embodiment of the present disclosure may be stored in a computer-readable non-transitory storage medium. The term “computer-readable media” refers to computer-readable media, such as read only memory (ROM), random access memory (RAM), hard disk drive, compact disk (CD), digital video disk (DVD), or any other type of memory. It may include any type of media that can be accessed by. “Non-transitory” computer-readable media is media that may exclude wired, wireless, optical, or other communication links that transmit electrical or other signals that are transient, and in which data can be permanently stored, and rewritable. It can include any medium on which data can be stored and later overwritten, such as an optical disk or a removable memory device.

FIG. 2 is a diagram illustrating a process of generating a plurality of wafer level maps for a target wafer (WSPm) according to an exemplary embodiment of the present disclosure. FIG. 2 may be described with reference to FIG. 1, and redundant description may be omitted.

A photo process may be performed multiple times on a semiconductor wafer (RSW). For example, referring to FIG. 2 , the first photo process (P1) to the mth photo process (Pm) may be performed on the semiconductor wafer (RSW). In other words, a photo process may be performed on the semiconductor wafer (RSW) m times (in this case, m≥1). The target wafer (WSPm) may refer to a semiconductor wafer that has undergone all of the first to m photo processes (Pm).

The measurement equipment 100 can measure the semiconductor wafer (RSW) at the end of each photo process for the semiconductor wafer (RSW) and generate a wafer level map. In an exemplary embodiment, the measurement equipment 100 may measure the semiconductor wafer (RSW) after the first photo process (P1) is completed and generate the first wafer level map (WLM21). The measurement equipment 100 may measure the semiconductor wafer (RSW) after the second photo process (P2) is completed and generate a second wafer level map (WLM22). The measurement equipment 100 may measure the semiconductor wafer (RSW) after the third photo process (P3) is completed and generate a third wafer level map (WLM23). The measurement equipment 100 may measure the semiconductor wafer (RSW) after the m-th photo process (Pm) is completed and generate the m-th wafer level map (WLM2m).

The first wafer level map WLM21 may include defect points measured after the first photo process P1. The second wafer level map WLM22 may include defect points measured after the second photo process P2. The third wafer level map (WLM23) may include defect points measured after the third photo process (P3). The mth wafer level map (WLM2m) may include defect points measured after the mth photo process (Pm). The system 200 includes the first wafer level map (WLM21) to the mth wafer level map (WLM2m). They can be combined to create a composite wafer map.

In an exemplary embodiment, defect points included in the first wafer level map (WLM21) are caused by various semiconductor processes that may exist between the first photo process (P1) and the second photo process (P2). It may or may not be included in the wafer level map (WLM22). Likewise, defect points included in the first wafer level map WLM21 may be included in the third wafer level map WLM23 even if they are not included in the second wafer level map WLM22.

According to an exemplary embodiment of the present invention, the first defect point among several defect points of the target wafer (WSPm) can be detected based on a synthesized wafer map that is cumulatively synthesized from each wafer level map. Therefore, according to an exemplary embodiment of the present invention, the first defect point occurring in the target wafer (WSPm) can be detected even if some defect points are missing from a certain wafer level map. The composite wafer map will be described later with reference to FIG. 3B.

3A to 3B are diagrams for explaining wafer level maps (WLM31, WLM32, WLM33) and composite wafer maps (CWLM3) according to an exemplary embodiment of the present disclosure. FIGS. 3A and 3B may be described with reference to FIGS. 1 and 2, and overlapping descriptions may be omitted. In FIGS. 3A and 3B, it is assumed that the photo process has been performed three times on the semiconductor wafer. Accordingly, the target wafer subject to initial defect detection may be a wafer on which the third photo process has been performed. Hereinafter, the photo process performed on the semiconductor wafer three times is an example, and of course, the photo process may be performed fewer or more times than this.

FIG. 3A is a diagram showing three wafer level maps generated while a semiconductor wafer undergoes a photo process three times. Each wafer level map (WLM31, WLM32, WLM33) may include defect points. A defect point may include location, height, and step information for the defect. The location of the defect may mean the coordinates of the defect on the wafer. The height of the defect may mean the degree of contamination caused by particles on the wafer, that is, the size of the hot spot. The height may be referred to as an abnormal value indicating whether the defect is abnormal. Step information about a defect may indicate which photo process the defect was measured in. For example, if a defect occurs in the first photo process, the step information may be the first value. As another example, when a defect occurs in the fourth photo process, the step information may be the fourth value.

The first wafer level map WLM31 may include defect points after the semiconductor wafer has gone through the first photo process. The first wafer level map WLM31 may include a first defect point d31 and a second defect point d32. The first wafer level map WLM31 may include location, height, and step information for each of the first defect point d31 and the second defect point d32. In an exemplary embodiment, step information of the first defect point d31 and the second defect point d32 may be a first value.

The second wafer level map (WLM32) may include defect points after the semiconductor wafer has gone through the second photo process. The second wafer level map WLM32 may include a third defect point d33 and a fourth defect point d34. The second wafer level map WLM32 may include location, height, and step information for each of the third defect point d33 and the fourth defect point d34. In an exemplary embodiment, the step information of the third defect point d33 and the fourth defect point d34 may be a second value.

The third wafer level map (WLM33) may include defect points after the semiconductor wafer has gone through the third photo process. The third wafer level map WLM33 may include a fifth defect point d35 and a sixth defect point d36. The third wafer level map WLM33 may include location, height, and step information for each of the fifth defect point d35 and the sixth defect point d36. In an exemplary embodiment, the step information of the fifth defect point d35 and the sixth defect point d36 may be a third value.

FIG. 3B is a diagram for explaining a composite wafer map (CWLM3) according to an exemplary embodiment of the present disclosure. System 200 may combine the first wafer level map (WLM31), the second wafer level map (WLM32), and the third wafer level map (WLM33) to generate a composite wafer map (CWLM3).

The composite wafer map (CWLM3) includes the first defect point (d31), the second defect point (d32), the third defect point (d33), the fourth defect point (d34), the fifth defect point (d35), and the sixth defect point. It may include location, height, and step information for the point d36.

System 200 may classify defect points in the composite wafer map (CWLM3) into defect clusters. System 200 may detect the initial defect point of the target wafer based on the classified defect points.

FIG. 4 is a diagram for explaining an initial defect point according to an exemplary embodiment of the present disclosure. FIG. 4 may be described with reference to FIGS. 1 to 3B, and overlapping descriptions may be omitted. In Figure 4, it is assumed that the photo process has been performed three times on the semiconductor wafer. The fact that the photo process was performed on the semiconductor wafer three times is just an example, and of course, the photo process may be performed fewer or more times than this.

The first wafer level map (WLM41) may include defect points after the semiconductor wafer has gone through the first photo process. The first wafer level map WLM41 may include a first defect point d41 and a second defect point d42. The first wafer level map WLM41 may include location, height, and step information for each of the first defect point d41 and the second defect point d42. In an exemplary embodiment, the step information of the first defect point d41 and the second defect point d42 may be a first value.

The second wafer level map (WLM42) may include defect points after the semiconductor wafer has gone through the second photo process. The second wafer level map WLM42 may include a third defect point d43, a fourth defect point d44, and a fifth defect point d45. The second wafer level map WLM42 may include location, height, and step information for each of the third defect point d43, fourth defect point d44, and fifth defect point d45. In an exemplary embodiment, step information of the third defect point d43, fourth defect point d44, and fifth defect point d45 may be a second value.

The third wafer level map (WLM43) may include defect points after the semiconductor wafer has gone through the third photo process. The third wafer level map may include a sixth defect point d46. The third wafer level map WLM43 may include location, height, and step information for the sixth defect point d36. In an exemplary embodiment, the step information of the sixth defect point d36 may be a third value.

As described above with reference to FIG. 3B, system 200 may combine the first wafer level map (WLM41), the second wafer level map (WLM42), and the third wafer level map (WLM43) to generate a composite wafer map. You can. The system 200 may detect the first defect point among the first defect points d31 to the sixth defect points d36 based on the composite wafer map. Defect points present in the composite wafer map may form defect clusters, and initial defect points may exist for each defect cluster. Accordingly, there may be more than one initial defect point in one composite wafer map.

In an exemplary embodiment, the first defect point d41 and the third defect point d43 may exist at the same location or at close locations. Accordingly, when the system 200 classifies the defect points included in the composite wafer map, the first defect point d41 and the third defect point d43 may be classified into the first cluster. The first defect point d41 may have step information corresponding to an earlier step than the third defect point d43. Therefore, the first defect point d41 may be the first defect point of the first cluster. Since the step information of the first defect point d41 has the first value, defects included in the first cluster may have occurred in the first photo process.

In an exemplary embodiment, the second defect point d42 and the fourth defect point d44 may exist at the same location or at a close location. Accordingly, when the system 200 classifies the defect points included in the composite wafer map, the second defect point d42 and the fourth defect point d44 may be classified into a second cluster. The second defect point d42 may have step information corresponding to an earlier step than the fourth defect point d44. Therefore, the second defect point d42 may be the first defect point of the second cluster. Since the step information of the second defect point d42 has the first value, defects included in the second cluster may have occurred in the first photo process.

In an exemplary embodiment, the fifth defect point d45 and the sixth defect point d46 may exist at the same location or at close locations. Accordingly, when the system 200 classifies the defect points included in the composite wafer map, the fifth defect point d45 and the sixth defect point d46 may be classified into the third cluster. The fifth defect point d45 may have step information corresponding to an earlier step than the sixth defect point d46. Therefore, the fifth defect point d45 may be the first defect point of the sixth cluster. Since the step information of the fifth defect point d46 has a second value, defects included in the third cluster may have occurred in the second photo process.

Figure 5 is a block diagram of system 200 according to an example embodiment of the present disclosure. FIG. 5 may be described with reference to FIG. 1 , and overlapping descriptions may be omitted.

System 200 may include a processor 210 and memory 220. The system 200 may receive the first wafer level map (WLM1) to the mth wafer level map (WLMm) from the outside. The system 200 may synthesize the received first wafer level map (WLM1) to mth wafer level map (WLMm) to generate a composite wafer map (not shown).

System 200 may receive a threshold reference value (CT) from an external source. The limit reference value (CT) may be a value input by the user. Therefore, according to an embodiment of the present invention, the method of clustering defects can be defined according to the user's wishes. The system 200 may determine whether each defect point corresponds to a defect point adjacent to each other by comparing the distance between each defect point and the threshold value (CT).

The system 200 can calculate the distance of each defect point existing in the composite wafer map, and the system 200 can calculate the defect point adjacent to each combination point based on the calculated distance and the threshold reference value (CT) received from the outside. The presence or absence of can be determined. In an exemplary embodiment, the distance between each defect point existing in the composite wafer map may be calculated using a vector based on the location of one defect point and the location of another defect point. For example, it is possible to determine whether each defect point is adjacent to each other using the Lp norm value of the vector. The Lp norm can be calculated by Equation 1 as follows. In Equation 1, x may mean the distance from the reference defect point to another defect point expressed as a vector. In Equation 1, k may mean an index corresponding to each element of x.

[Equation 1]

Although not shown in the drawing, the system 200 can determine the p value of the Lp norm based on the user's input received from the outside. Therefore, according to an embodiment of the present invention, a defect clustering method can be defined simply and consistently according to the user's wishes. Hereinafter, it is assumed that the p value is 1. In other words, it is assumed that the Lp norm is the L1 norm. The L1 norm may be referred to as the Manhattan norm. The fact that the Lp norm is the L1 norm is illustrative and can be calculated in various ways depending on the p value. For example, if the p value is 2, the Lp norm may be the L2 norm, and the L2 norm may be referred to as the Euclidean norm. For example, the Lp norm may be the max norm.

The system 200 may classify the plurality of defect points into defect clusters by comparing the distance and threshold value (CT) of each defect point included in the composite wafer map. There may be at least one defect cluster present on the composite wafer map.

The system 200 may classify a plurality of defect points included in the composite wafer map into clusters and detect the first defect point for each defect cluster. System 200 may generate a defect cluster set (CRD) containing each defect cluster. The defect cluster set (CRD) may include defect clusters present in the composite wafer map. Each defect cluster may include location, height, step information, and cluster ID for the defect point belonging to each defect cluster. At this time, the cluster ID may be data indicating which defect cluster each defect point is included in. In an exemplary embodiment, the system 200 may add each defect point to each defect cluster by assigning a cluster ID to each defect point.

The system 200 may detect the initial defect point for each defect cluster based on the defect cluster set (CRD).

Figure 6 is a flowchart showing a method for detecting an initial defect point according to an exemplary embodiment of the present disclosure. Specifically, the flowchart of FIG. 6 illustrates how the system 200 of FIG. 5 detects the initial defect point of a target wafer. FIG. 6 may be described with reference to FIGS. 1 and 5, and overlapping descriptions may be omitted. Hereinafter, it is assumed that the photo process has been performed m times on the target wafer for which defects are to be detected (in this case, m≥1).

In step S100, the system 200 may acquire the first wafer level map (WLM1) to the mth wafer level map (WLMm) for the target wafer from the outside. In an exemplary embodiment, the first wafer level map (WLM1) to the mth wafer level map (WLMm) may be transmitted from the measurement equipment 100 to the system 200.

In step S200, the system 200 may combine all of the first wafer level map (WLM1) to the mth wafer level map (WLMm) to generate a composite wafer map. In an exemplary embodiment, the composite wafer map may be data in which m wafer level maps are overlapped. Accordingly, the composite wafer map may include all defect points that occurred in the target wafer due to the first photo process (P1) to the mth photo process (Pm).

In step S300, the system 200 may classify a plurality of defect points included in the composite wafer map. Specifically, the system 200 may classify each defect point into a defect cluster based on the location of each defect point included in the composite wafer map. The classified defect points can form a cluster. System 200 may generate a set of fault clusters. A detailed description of step S300 will be described later with reference to FIG. 7.

In step S400, the system 200 may detect the first process step in which a defect occurred for each defect cluster and detect the first defect point of each defect cluster based on the detected first process step information. Specific details for step S400 The explanation will be provided later with reference to FIG. 9 .

Figure 7 is a flowchart showing a method for classifying defect points according to an exemplary embodiment of the present disclosure. Specifically, the flowchart of FIG. 7 is a flowchart for explaining the specific operation of step S300 of FIG. 6. FIG. 7 may be described with reference to FIGS. 1, 5, and 6, and overlapping descriptions may be omitted.

In step S310, the system 200 may randomly select one defect point from among defect points included in the composite wafer map and set it as a reference defect point. In an example embodiment, the initially selected reference defect point may be referred to as a first defect point.

In step S320, the system 200 may add the defect point selected in step S310 to the defect cluster. In an example embodiment, system 200 may add the first defect point to the first defect cluster. At this time, adding the first defect point to the first defect cluster may mean that the first defect point is a defect point included in the first defect cluster.

At step S330, the system 200 may search for a defect point adjacent to the reference defect point. Specifically, the system 200 may calculate the distance between the reference defect point and each defect point included in the composite wafer map. At this time, other defect points may be defect points that are not included in any defect cluster among defect points included in the synthetic wafer map. These defect points may be referred to as unclassified defect points, non-clustered defect points, or defect points for which a cluster ID has not been assigned.

After calculating the distance, the system 200 may extract defect points whose distance is smaller than the threshold value. At this time, the extracted defect points may be referred to as adjacent defect points or neighboring defect points. The system 200 may add the extracted adjacent defect point to the same defect cluster as the defect cluster to which the reference defect point belongs. For example, if the reference defect point belongs to the first defect cluster, the extracted adjacent defect points may also belong to the first defect cluster. The system 200 may repeat step S330 using the extracted adjacent defect points as new reference defect points. At this time, step S330 may be repeatedly performed until no new adjacent defect points are extracted. A detailed description of step S330 will be described later with reference to FIG. 8.

At step S340, system 200 may determine whether new defect clusters are needed in the composite wafer map. Specifically, the system 200 may determine whether there is an unclassified defect point that is not classified in steps S320 and S330 among the defect points included in the composite wafer map. If there is at least one unclassified defect point, the system 200 may select any one of the unclassified defect points. The system 200 may update the reference defect point so that the selected defect point becomes the reference defect point and then repeatedly perform steps S310 to S330. In one embodiment, the selected defect point may be referred to as a second defect point.

In an exemplary embodiment, assume that after step S330 is performed, a plurality of unclassified defect points still exist in the composite wafer map. System 200 may randomly select any one of a plurality of unclassified defect points. The system 200 may update the reference point so that the selected defect point becomes the reference point. System 200 may classify the updated reference points into new defect clusters. For example, if only the first defect cluster exists in the composite wafer map at the time of performing step S340, the new defect cluster may be the second defect cluster. For example, if the first to n-1th defect clusters exist in the synthesized wafer map at the time of performing step S340, the new defect cluster may be the nth defect cluster (in this case, n≥1).

The system 200 may generate a set of defect clusters when all defect points included in the composite wafer map have been classified.

Figure 8 is a flowchart showing a method of searching for adjacent defect points according to an exemplary embodiment of the present disclosure. Specifically, the flowchart of FIG. 8 is a flowchart for explaining the specific operation of step S330 of FIG. 7. FIG. 8 may be described with reference to FIGS. 1, 6, and 7, and overlapping descriptions may be omitted.

In step S331, the system 200 may calculate the distance between the reference defect point and the other defect point. At this time, other defect points may be defect points that do not belong to any defect cluster. In an exemplary embodiment, it is assumed that the first defect point corresponds to the reference defect point. The system 200 may calculate the distance between defect points that do not belong to any defect cluster among the plurality of defect points included in the composite wafer map and the first defect point. At this time, the distance can be calculated using the Lp norm in Equation 1.

At step S332, system 200 may extract adjacent defect points. Specifically, the system 200 may extract defect points whose distance calculated in step S331 is smaller than the threshold reference value (CT) among several defect points included in the synthetic wafer map.

In an exemplary embodiment, the limit reference value (CT) may be a value input from the outside or may be a value previously entered into the system 200. The user can control the system 200 to cluster defect points by changing the threshold value (CT) according to the situation.

In step S333, the system 200 may add the extracted adjacent defect point to the same defect cluster as the defect cluster to which the reference defect point belongs. For example, if the reference defect point belongs to the first defect cluster, the extracted adjacent defect points may also belong to the first defect cluster. For example, if the reference defect point belongs to the second defect cluster, the extracted adjacent defect points may also belong to the second defect cluster.

At step S334, the system 200 may update the extracted adjacent defect points with a new reference defect point. System 200 may repeatedly perform step S330 based on the updated reference defect point. At this time, the system 200 may repeat step S330 until no more new adjacent defect points are extracted.

Figure 9 is a flowchart showing a method for detecting an initial defect point according to an exemplary embodiment of the present disclosure. Specifically, the flowchart of FIG. 9 is a flowchart for explaining the specific operation of step S400 of FIG. 6. FIG. 9 may be described with reference to FIGS. 1 and 6, and overlapping descriptions may be omitted.

In step S410, the system 200 may detect the first process step in which a defect occurred for each defect cluster. Specifically, the system 200 can detect the first process step in which a defect occurred for each defect cluster using the classified defect points included in the synthetic wafer map.

In an exemplary embodiment, it is assumed that the first defect cluster includes a first defect point, a second defect point, and a third defect point. Additionally, it is assumed that the step information of the first defect point and the second defect point has a first value, and the step information of the third defect point has a second value. At this time, among the defect points belonging to the first defect cluster, the step information of the first defect point and the second defect point is the smallest. Accordingly, the first process step information corresponding to the first defect cluster may be the first value.

In step S420, the system 200 may extract defect points corresponding to the first process step for each defect cluster based on the detected first process step information.

In an exemplary embodiment, assume that the first process step information of the first defect cluster is detected as a first value in step S410. The first value may correspond to the first photo process. Therefore, the system 200 may determine that defects related to the first defect cluster are caused by the first photo process. The system 200 may extract defect points corresponding to the first photo process from among defect points included in the first defect cluster.

In step S430, the system 200 may detect the defect point with the highest height among the defect points extracted in step S420. The defect point with the highest detected height may be referred to as the first defect point of the corresponding defect cluster. Based on the process step information and location included in the first detected defect point, users can early find process equipment that has problems and take action.

In an example embodiment, assume that the first wafer level map includes a first defect point and a second defect point. It is assumed that the first defect point and the second defect point belong to the first defect cluster. Assume that the height of the first defect point is higher than the height of the second defect point. In this case, since the height of the first defect point is the highest in the first wafer level map, the first defect point may be the first defect point in the first wafer level map. Accordingly, the system 200 can detect the first defect point, which is the first defect point of the first wafer level map. Based on the step information included in the first detected defect point, the user can determine that the cause of the first defect cluster is equipment related to the first photo process. In addition, the user can take action on the part corresponding to the location of the first defect point among the first photo process equipment based on the location information of the first defect point. By early tracking of process equipment that causes defects in wafers, the productivity and quality of semiconductor products can be improved, and thus the yield of semiconductor products can be increased.

10A to 10G are diagrams for explaining defect points forming a defect cluster according to an exemplary embodiment of the present disclosure. Specifically, this is a diagram to explain how the system 200 classifies defect points on the composite wafer map 1000 into defect clusters in step S300 of FIG. 6. FIGS. 10A to 10G may be described with reference to FIGS. 1 and 6 to 8 , and overlapping descriptions may be omitted.

Hereinafter, the Lp norm used when calculating the distance between the reference defect point and other defect points is assumed to be the L1 norm. However, this is an example, and the p value can of course be changed depending on the user's needs.

Referring to FIG. 10A, a plurality of defect points may exist on the composite wafer map 1000. At this time, each defect point may not be included in any defect cluster. The system 200 may select the first defect point d1 from among the defect points on the composite wafer map 1000. The system 200 may set the first defect point d1 as a reference defect point and add the first defect point d1 to the first defect cluster C1.

The system 200 may search for adjacent defect points based on the first defect point d1. At this time, the system 200 can calculate the distance between other defect points from the first defect point (d1) using the L1 norm, and determine defect points whose distance is within the threshold reference value (CT) as adjacent defect points. there is.

In an exemplary embodiment, defect points belonging to the first area CA1 may correspond to defect points adjacent to the first defect point d1. Accordingly, defect points adjacent to the first defect point d1, which is the reference defect point in FIG. 10A, may be the second defect point d2, the third defect point d3, and the fourth defect point d4.

Referring to FIG. 10B, the system 200 determines the second defect point (d2), the third defect point (d3), and the fourth defect point (d4) as defect points adjacent to the first defect point (d1) in FIG. 10A. ) can be updated so that is the new reference defect point.

The system 200 may add the updated reference defect points, the second defect point d2, the third defect point d3, and the fourth defect point d4, to the first defect cluster C1. The system 200 may search for defect points adjacent to each of the second defect point d2, third defect point d3, and fourth defect point d4.

In an exemplary embodiment, defect points that already belong to a certain defect cluster may be excluded from the search target. For example, since the first defect point d1 already belongs to the first defect cluster C1, it may be excluded from the search target.

In an exemplary embodiment, defect points belonging to the second area CA2 may correspond to defect points adjacent to the second defect point d2. Accordingly, defect points adjacent to the second defect point d2, which is one of the reference defect points in FIG. 10B, may be the seventh defect point d7 and the eighth defect point d8.

In an exemplary embodiment, defect points belonging to the third area CA3 may correspond to defect points adjacent to the third defect point d3. Accordingly, a defect point adjacent to the third defect point d3, which is one of the reference defect points in FIG. 10B, may be the sixth defect point d6.

In an exemplary embodiment, defect points belonging to the fourth area CA4 may correspond to defect points adjacent to the fourth defect point d4. Accordingly, a defect point adjacent to the fourth defect point d4, which is one of the reference defect points in FIG. 10B, may be the fifth defect point d5.

Referring to FIG. 10C, the system 200 determines the fifth defect point d5, sixth defect point d6, seventh defect point d7, and The reference defect point can be updated so that the eighth defect point d8 becomes a new reference defect point.

The system 200 divides the updated reference defect points, the fifth defect point (d5), the sixth defect point (d6), the seventh defect point (d7), and the eighth defect point (d8) into the first defect cluster (C1). can be added to The system 200 may search for defect points adjacent to each of the fifth defect point d5, sixth defect point d6, seventh defect point d7, and eighth defect point d8.

In an exemplary embodiment, defect points that already belong to a certain defect cluster may be excluded from the search target. For example, since the second defect point d2 already belongs to the first defect cluster C1, it may be excluded from the search target.

In an exemplary embodiment, defect points belonging to the fifth area CA5 may correspond to defect points adjacent to the seventh defect point d7. Accordingly, since there are no longer defect points that are adjacent to the seventh defect point d7, which is one of the reference defect points in FIG. 10C, but do not belong to any defect cluster, the system 200 determines the seventh defect point d7. You can end the search related to .

In an exemplary embodiment, defect points belonging to the sixth area CA6 may correspond to defect points adjacent to the eighth defect point d8. Accordingly, a defect point adjacent to the eighth defect point d8, which is one of the reference defect points in FIG. 10C, may be the ninth defect point d9.

In an exemplary embodiment, defect points belonging to the seventh area CA7 may correspond to defect points adjacent to the sixth defect point d6. Accordingly, since there are no longer defect points that are adjacent to the sixth defect point d6, which is one of the reference defect points in FIG. 10C, but do not belong to any defect cluster, the system 200 determines the sixth defect point d6. You can end the search related to .

In an exemplary embodiment, defect points belonging to the eighth area CA8 may correspond to defect points adjacent to the fifth defect point d5. Accordingly, since there is no longer a defect point that is adjacent to the eighth defect point d8, which is one of the reference defect points in FIG. 10C, but does not belong to any defect cluster, the system 200 determines the fifth defect point d5. You can end the search related to .

Referring to FIG. 10D, the system 200 may update the reference defect point so that the ninth defect point d9, which is determined to be a defect point adjacent to each reference defect point in FIG. 10C, becomes a new reference defect point.

The system 200 may add the ninth defect point d9, which is an updated reference defect point, to the first defect cluster C1. The system 200 may search for the ninth defect point d9 and defect points adjacent to the defect point.

In an exemplary embodiment, defect points that already belong to a certain defect cluster may be excluded from the search target. For example, since the eighth defect point d8 already belongs to the first defect cluster C1, it may be excluded from the search target.

In an exemplary embodiment, defect points belonging to the ninth area CA9 may correspond to defect points adjacent to the ninth defect point d9. Accordingly, since there is no longer a defect point that is adjacent to the ninth defect point d9, which is one of the reference defect points in FIG. 10D, but does not belong to any defect cluster, the system 200 determines the ninth defect point d9. You can end the search related to .

Referring to FIG. 10E, there may still be defect points in the composite wafer map 1000 that do not belong to any defect cluster (may be referred to as unclassified defect points or defect points to which a cluster ID is not assigned). For example, the 10th defect point d10, the 11th defect point d11, and the 12th defect point d12 may not belong to the first defect cluster C1.

At this time, the system 200 may perform the operation of step S340 of FIG. 7. In an example embodiment, system 200 may select one of the unclassified defect points present on composite wafer map 1000 and update the selected defect point with a new reference point.

In an example embodiment, the system 200 may update the 11th defect point d11 with a new reference point. The system 200 may add the eleventh defect point d11 to the second defect cluster C2. The system 200 may search for defect points adjacent to the 11th defect point d11. Defect points belonging to the tenth area CA10 may correspond to defect points adjacent to the eleventh defect point d11. Accordingly, defect points adjacent to the 11th defect point d11, which is the reference defect point in FIG. 10E, may be the 10th defect point d10 and the 12th defect point d12.

Referring to FIG. 10F, the system 200 sets the reference point so that the 10th defect point d10 and the 12th defect point d12, which are determined to be defect points adjacent to each reference defect point in FIG. 10F, become new reference defect points. Defect points can be updated.

The system 200 may add the updated reference defect points, the 10th defect point d10 and the 12th defect point d12, to the second defect cluster C2. The system 200 may search for defect points adjacent to the tenth defect point d10 and the twelfth defect point d12.

In an exemplary embodiment, defect points belonging to the eleventh area CA11 may correspond to defect points adjacent to the tenth defect point d10. Accordingly, since there are no longer defect points that are adjacent to the tenth defect point d10, which is one of the reference defect points in FIG. 10F, but do not belong to any defect cluster, the system 200 determines the tenth defect point d10. You can end the search related to .

In an exemplary embodiment, defect points belonging to the twelfth area CA12 may correspond to defect points adjacent to the twelfth defect point d12. Accordingly, since there are no longer defect points that are adjacent to the twelfth defect point d12, which is one of the reference defect points in FIG. 10F, but do not belong to any defect cluster, the system 200 determines the twelfth defect point d12. You can end the search related to .

FIG. 10G may show that all defect points existing on the composite wafer map 1000 are classified. For example, defect points belonging to the first defect cluster C1 are included in the first defect point d1 to the th defect point d1. There may be 9 defect points (d9). Defect points belonging to the second defect cluster C2 may be the tenth defect point d10 to the twelfth defect point d12.

In the system 200, when all defect points on the composite wafer map 1000 are classified as shown in FIG. 10G, the composite wafer map 1000 may be referred to as a classified composite wafer map. System 200 may generate a set of defect clusters based on the classified composite wafer map.

Figure 11 is a table explaining the initial defect point for each defect cluster for the target wafer. Specifically, FIG. 11 illustrates the system 200 detecting the first defect point for each cluster after classifying the defect points included in the synthetic wafer map corresponding to the target wafer. FIG. 11 may be described with reference to FIGS. 1 and 9, and overlapping descriptions may be omitted.

In the following, it is assumed that the composite wafer map contains a total of four defect clusters. For example, the four defect clusters may be a first defect cluster (C1), a second defect cluster (C2), a third defect cluster (C3), and a fourth defect cluster (C4).

The first defect point may include a defect cluster to which each first defect point belongs, a first photo process step, a height, a first position, and a second position. For example, the first position may mean the x-coordinate on the composite wafer map, and the second position may mean the y-coordinate on the composite wafer map. In an exemplary embodiment, the defect cluster to which each initial defect point belongs may be distinguished by the defect cluster ID.

In an exemplary embodiment, at least one defect point may exist in the first defect cluster C1. The system 200 may detect the first defect point among the defect points included in the first defect cluster C1. The first defect point of the first defect cluster C1 may be a defect point with the smallest step information among the defect points belonging to the first defect cluster C1. At this time, the smallest step information may mean step information corresponding to the photo process that precedes it in time. In the first defect cluster C1, the most advanced photo process corresponding to the smallest step information may be the first photo process P1. If there are multiple defect points with the smallest step information, the first defect point of the first defect cluster C1 may be the defect point with the highest height among them.

In an exemplary embodiment, at least one defect point may exist in the second defect cluster C2. The system 200 may detect the first defect point among the defect points included in the second defect cluster C2. The first defect point of the second defect cluster C2 may be a defect point with the smallest step information among defect points belonging to the second defect cluster C2. In the second defect cluster C2, the most advanced photo process corresponding to the smallest step information may be the second photo process P2. If there are multiple defect points with the smallest step information, the first defect point of the second defect cluster C2 may be the defect point with the highest height among them.

In an exemplary embodiment, at least one defect point may exist in the third defect cluster C3. The system 200 may detect the first defect point among the defect points included in the third defect cluster C3. The first defect point of the third defect cluster C3 may be a defect point with the smallest step information among the defect points belonging to the third defect cluster C3. In the third defect cluster C3, the most advanced photo process corresponding to the smallest step information may be the second photo process P2. If there are multiple defect points with the smallest step information, the first defect point of the third defect cluster C3 may be the defect point with the highest height among them.

In an exemplary embodiment, at least one defect point may exist in the fourth defect cluster C4. The system 200 may detect the first defect point among the defect points included in the first defect cluster C4. The first defect point of the first defect cluster C4 may be a defect point with the smallest step information among defect points belonging to the first defect cluster C4. In the fourth defect cluster C4, the most advanced photo process corresponding to the smallest step information may be the third photo process P3. If there are multiple defect points with the smallest step information, the first defect point of the fourth defect cluster C4 may be the defect point with the highest height among them.

Figure 12 is a block diagram illustrating a system 1200 according to an example embodiment of the present disclosure. Specifically, system 1200 of FIG. 12 may correspond to system 200 of FIG. 1 . FIG. 12 may be described with reference to FIG. 1, and overlapping description may be omitted.

As shown in FIG. 12 , system 1200 may include a processor 1201, an accelerator 1202, an input/output interface 1203, a memory subsystem 1204, storage 1205, and a bus 1206. . Processor 1201, accelerator 1202, input/output interface 1203, memory subsystem 1204, and storage 1205 may communicate with each other via bus 1206. In some embodiments, system 1200 may be a system-on-chip (SoC) with components implemented on a single chip, and storage 1205 may be external to the system-on-chip. In some embodiments, at least one of the components shown in FIG. 12 may be omitted from system 1200.

The processor 1201 can control the operation of the system 1200 at the top layer and control other components of the system 1200.

In some embodiments, processor 1201 may include two or more processing cores. As described above with reference to the figures, processor 1201 may process various steps necessary for operation of system 1200 to detect the initial defect point on the wafer.

Accelerator 1202 may be designed to perform designated functions at high speed. For example, accelerator 1202 may provide data generated by processing data received from memory subsystem 1204 to memory subsystem 1204.

The input/output interface 1203 may provide an interface for receiving input from outside the system 1200 and providing output to the outside of the system 1200. For example, the system 1200 may receive the first to mth wafer level maps from the outside through the input/output interface 1203. For example, the system 1200 may receive the p value and limit reference value for the Lp norm from the outside through the input/output interface 1203.

Memory subsystem 1204 may be accessed by other components coupled to bus 1206. In some embodiments, memory subsystem 1204 may include volatile memory, such as DRAM, SRAM, or non-volatile memory, such as flash memory or resistive random access memory (RRAM). Additionally, in some embodiments, memory subsystem 1204 may provide an interface to storage 1205. The storage 1205 may be a storage medium that does not lose data even when power is turned off. For example, storage 1205 may include a semiconductor memory device, such as non-volatile memory, or may include any storage medium, such as a magnetic card/disk or an optical card/disk. In an example embodiment, the first to mth wafer level maps corresponding to the target wafer may be stored in the memory subsystem 1204 or the storage 1205. In an example embodiment, the composite wafer map, defect cluster set, and original defect point set corresponding to the target wafer may be stored in memory subsystem 1204 or storage 1205.

Bus 1206 may operate based on one of a variety of bus protocols. The various bus protocols include Advanced Microcontroller Bus Architecture (AMBA) protocol, Universal Serial Bus (USB) protocol, MultiMedia Card (MMC) protocol, Peripheral Component Interconnection (PCI) protocol, PCI-Express (PCI-E) protocol, and Advanced Microcontroller Bus (ATA) protocol. Technology Attachment) protocol, Serial-ATA protocol, Parallel-ATA protocol, SCSI (Small Computer Small Interface) protocol, ESDI (Enhanced Small Disk Interface) protocol, IDE (Integrated Drive Electronics) protocol, MIPI (Mobile Industry Processor Interface) protocol, It may include at least one of the UFS (Universal Flash Storage) protocol.

As described above, exemplary embodiments have been disclosed in the drawings and specification. In this specification, embodiments have been described using specific terms, but this is only used for the purpose of explaining the technical idea of the present disclosure and is not used to limit the meaning or scope of the present disclosure as set forth in the patent claims. . Therefore, those skilled in the art will understand that various modifications and other equivalent embodiments are possible. Therefore, the true technical protection scope of the present disclosure should be determined by the technical spirit of the attached patent claims.

Claims (10)

As a method for detecting defect points on a wafer,
Obtaining a wafer level map generated by measuring the wafer for each process step;
Generating a composite wafer map by combining a plurality of wafer level maps generated by measuring each step;
Classifying each defect point into a defect cluster based on the location of each defect point included in the composite wafer map; and
A method comprising the step of detecting the first process step in which a defect occurs based on step information for each defect cluster. According to paragraph 1,
The step of classifying each defect point into defect clusters is:
setting a first defect point selected from defect points included in the composite wafer map as a reference defect point;
adding the reference defect point to a first defect cluster;
searching for defect points adjacent to the reference defect point; and
A method comprising adding the adjacent defect points to the first defect cluster. According to paragraph 2,
The step of searching for defect points adjacent to the reference defect point is:
calculating a distance between the reference defect point and each defect point included in the composite wafer map; and
A method comprising extracting defect points whose distance is less than or equal to a threshold value. According to paragraph 3,
Further comprising updating the extracted defect point with the reference defect point,
The method of searching for a defect point adjacent to the reference defect point is performed again based on the updated reference point. According to paragraph 2,
The method further includes determining whether an unclassified defect point that does not belong to any defect cluster exists among defect points included in the composite wafer map. According to clause 5,
If the unclassified defect point exists, updating a second defect point selected from among the unclassified defect points as a reference defect point and adding the updated reference point to a second defect cluster,
The method of searching for a defect point adjacent to the reference defect point is performed again based on the updated reference point. According to paragraph 1,
The method further includes extracting, for each defect cluster, a defect point with the highest height based on the detected first process step. In the wafer defect detection system,
a memory storing a program for detecting defects in the wafer; and
Includes a processor that executes a program stored in the memory,
Obtaining a wafer level map generated by measuring the wafer for each process step,
Generate a composite wafer map by combining a plurality of wafer level maps generated by measuring each step,
Based on the location of each defect point included in the composite wafer map, each defect point is classified into defect clusters,
A wafer defect detection system comprising the step of detecting the first process step in which a defect occurred based on step information for each defect cluster. According to clause 8,
The processor,
Setting a first defect point selected from defect points included in the composite wafer map as a reference defect point,
Adding the reference defect point to a first defect cluster,
Search for defect points adjacent to the reference defect point,
A wafer defect detection system, characterized in that adding the adjacent defect points to the first defect cluster. A computer-readable non-transitory storage medium storing instructions that, when executed by a processor, cause the processor to perform defect point detection on a wafer, comprising:
The defect point detection is,
Obtaining a wafer level map generated by measuring the wafer for each process step;
Generating a composite wafer map by combining a plurality of wafer level maps generated by measuring each step;
Classifying each defect point into a defect cluster based on the location of each defect point included in the composite wafer map; and
A computer-readable non-transitory storage medium comprising the step of detecting the first process step in which a defect occurred based on step information for each defect cluster.

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