KR20240023541A - Apparatus of inverse parity puncturing for fixed-length signaling information and method using the same - Google Patents

Abstract

A parity puncturing device and method for fixed-length signaling information are disclosed. A parity puncturing device according to an embodiment of the present invention includes a memory that provides a parity bit string for parity puncturing of parity bits of an LDPC codeword with a length of 16200 and a code rate of 3/15; and a processor that punctures a number of bits corresponding to the final puncturing size at the rear of the parity bit string.

Description

Inverse parity puncturing device for fixed-length signaling information and inverse parity puncturing method using the same {APPARATUS OF INVERSE PARITY PUNCTURING FOR FIXED-LENGTH SIGNALING INFORMATION AND METHOD USING THE SAME}

The present invention relates to channel coding and modulation techniques for transmitting signaling information, and particularly to encoding and decoding devices for effectively transmitting signaling information in a next-generation digital broadcasting system.

BICM (Bit-Interleaved Coded Modulation) is a bandwidth-efficient transmission technology that includes an error-correction coder, bit-by-bit interleaver, and high-order modulator. It is a combined form.

BICM can provide excellent performance with a simple structure by using an LDPC (Low-Density Parity Check) encoder or a turbo encoder as an error correction encoder. In addition, BICM provides a high level of flexibility because the modulation order, length of error correction code, and code rate can be selected in various ways. Because of these advantages, BICM is not only used in broadcasting standards such as DVB-T2 and DVB-NGH, but is also likely to be used in other next-generation broadcasting systems.

Such BICM can be used not only for data transmission but also for signaling information transmission. In particular, channel coding and modulation techniques for transmitting signaling information need to be more robust than channel coding and modulation techniques for data transmission.

Therefore, there is an urgent need for new channel coding and modulation techniques, especially for transmitting signaling information.

The purpose of the present invention is to provide a channel coding and modulation technique suitable for transmitting signaling information in a broadcasting system channel.

Additionally, the purpose of the present invention is to provide a new parity puncturing technique optimized for signaling information transmission.

The parity puncturing device according to the present invention for achieving the above object is a memory that provides a parity bit string for parity puncturing the parity bits of an LDPC codeword with a length of 16200 and a code rate of 3/15. ; and a processor that punctures a number of bits corresponding to the final puncturing size at the rear of the parity bit string.

At this time, the LDPC codeword may include zero-padded fixed-length signaling information as information bits.

At this time, the final puncturing size is calculated using the temporary puncturing size, the number of transmission bits, and the number of temporary transmission bits, and the number of transmission bits is the number of temporary transmission bits and the modulation order. is calculated using, and the number of temporary transmission bits is calculated using the difference between the sum of the length of the BCH encoded bit string and 12960 and the temporary puncturing size, and the temporary puncturing size is the length of the LDPC information bit string and It can be calculated regardless of the difference in length of the BCH encoded bit string.

At this time, the temporary puncturing size can be calculated using a first integer multiplied by the difference between the length of the LDPC information bit stream and the length of the BCH encoded bit stream and a second integer different from the first integer.

At this time, the first integer may be 0 and the second integer may be 9360. At this time, the modulation order may be 2, corresponding to QPSK.

At this time, the parity bit string can be generated by dividing the parity bits of the LDPC codeword into a plurality of groups and group-wise interleaving the groups using group-wise interleaving order.

At this time, the group-wise interleaving order is in the sequence [20 23 25 32 38 41 18 9 10 11 31 24 14 15 26 40 33 19 28 34 16 39 27 30 21 44 43 35 42 36 12 13 29 22 37 17] corresponding It may be.

Additionally, the parity puncturing method according to an embodiment of the present invention includes calculating a final puncturing size; And for parity puncturing the parity bits of an LDPC codeword with a length of 16200 and a code rate of 3/15, including the step of puncturing a number of bits corresponding to the final puncturing size at the rear of the parity bit string. do.

At this time, the LDPC codeword may include zero-padded fixed-length signaling information as information bits.

At this time, the parity puncturing method includes calculating a temporary puncturing size; Calculating the number of temporary transmission bits using the difference between the length of the BCH encoded bit string and the sum of 12960 and the temporary puncturing size; and calculating the number of transmission bits using the temporary number of transmission bits and the modulation order. At this time, in the step of calculating the final puncturing size, the final puncturing size may be calculated using the number of temporary transmission bits, the number of transmission bits, and the number of temporary transmission bits.

At this time, the temporary puncturing size can be calculated regardless of the difference between the length of the LDPC information bit string and the length of the BCH encoded bit string.

At this time, the temporary puncturing size can be calculated using a first integer multiplied by the difference between the length of the LDPC information bit stream and the length of the BCH encoded bit stream and a second integer different from the first integer.

At this time, the first integer may be 0 and the second integer may be 9360. At this time, the modulation order may be 2, corresponding to QPSK.

At this time, the parity bit string may be generated by dividing the parity bits of the LDPC codeword into a plurality of groups and group-wise interleaving the groups using group-wise interleaving order.

At this time, the group-wise interleaving order is in the sequence [20 23 25 32 38 41 18 9 10 11 31 24 14 15 26 40 33 19 28 34 16 39 27 30 21 44 43 35 42 36 12 13 29 22 37 17] corresponding It may be.

In addition, the reverse parity puncturing device according to an embodiment of the present invention calculates the final puncturing size and performs reverse parity puncturing corresponding to the final puncturing size to obtain a length of 16200 and a code rate of 3/15. a processor that generates a parity bit string of an LDPC codeword; and a memory that stores the parity bit string.

At this time, the LDPC codeword may include zero-padded fixed-length signaling information as information bits.

At this time, the final puncturing size is calculated using the temporary puncturing size, the number of transmission bits, and the number of temporary transmission bits, and the number of transmission bits is calculated based on the number of temporary transmission bits and the modulation order. The number of temporary transmission bits is calculated using the difference between the sum of the length of the BCH encoded bit string and 12960 and the temporary puncturing size, and the temporary puncturing size is the length of the LDPC information bit string and the BCH It can be calculated regardless of the difference in length of the encoded bit string.

At this time, the temporary puncturing size can be calculated using a first integer multiplied by the difference between the length of the LDPC information bit stream and the length of the BCH encoded bit stream and a second integer different from the first integer.

At this time, the first integer may be 0 and the second integer may be 9360. At this time, the modulation order may be 2, corresponding to QPSK.

According to the present invention, a channel coding and modulation technique suitable for transmitting signaling information in a broadcast system channel is provided.

Additionally, in configuring BICM for transmitting signaling information, the present invention can efficiently transmit/receive signaling information by optimizing shortening and puncturing according to the amount of signaling information.

1 is a block diagram showing a signaling information encoding/decoding system according to an embodiment of the present invention.
Figure 2 is an operation flowchart showing a method of encoding signaling information according to an embodiment of the present invention.
Figure 3 is an operation flowchart showing a method of decoding signaling information according to an embodiment of the present invention.
Figure 4 is a diagram showing a broadcast signal frame according to an embodiment of the present invention.
Figure 5 is a diagram showing the structure of a parity check matrix corresponding to an LDPC code according to an embodiment of the present invention.
FIG. 6 is a diagram illustrating an example of the operation of the zero padding unit shown in FIG. 1.
FIG. 7 is a diagram illustrating an example of the operation of the parity permutation unit shown in FIG. 1.
FIG. 8 is a diagram showing an example of the operation of the zero removing unit shown in FIG. 1.
Figure 9 is a block diagram showing a parity puncturing device according to an embodiment of the present invention.
Figure 10 is an operational flowchart showing a parity puncturing method according to an embodiment of the present invention.

The present invention will be described in detail with reference to the attached drawings as follows. Here, repeated descriptions, known functions that may unnecessarily obscure the gist of the present invention, and detailed descriptions of configurations are omitted. Embodiments of the present invention are provided to more completely explain the present invention to those skilled in the art. Accordingly, the shapes and sizes of elements in the drawings may be exaggerated for clearer explanation.

Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the attached drawings.

1 is a block diagram showing a signaling information encoding/decoding system according to an embodiment of the present invention.

Referring to FIG. 1, the signaling information encoding/decoding system includes a signaling information encoding device 100 and a signaling information decoding device 300.

The signaling information encoding device 100 and the signaling information decoding device 300 communicate via the wireless channel 200.

The signaling information encoding device 100 channels encodes and modulates signaling information such as L1-Basic or L1-Detail.

The signaling information encoding device 100 includes a segmentation unit 110, a scrambling unit 120, a BCH encoder 130, a zero padding unit 140, an LDPC encoder 150, a parity permutation unit 160, and a parity puncturing unit. 170, a zero removing unit 180, a bit interleaving unit 190, and a constellation mapping unit 195.

The signaling information encoding device 100 shown in FIG. 1 can be viewed as corresponding to a BICM (Bit-Interleaved Coded Modulation) device, and in this case, the error correction encoder of the BICM device is the segmentation unit 110 shown in FIG. 1. , corresponding to the scrambling unit 120, BCH encoder 130, zero padding unit 140, LDPC encoder 150, parity permutation unit 160, parity puncturing unit 170, and zero removing unit 180. It can be seen as

When the length of the signaling information is longer than a preset length, the segmentation unit 110 divides the signaling information into several groups to transmit the signaling information by dividing it into several LDPC codewords. That is, when signaling information cannot be contained in one LDPC codeword, the segmentation unit can determine how many codewords to contain the signaling information and divide the signaling information according to the determined number.

For example, when the length of signaling information is fixed, such as L1-Basic, the signaling information encoding device 100 may not include the segmentation unit 110.

For example, when the length of signaling information is variable such as L1-Detail, the signaling information encoding device 100 may include a segmentation unit 110.

The scrambling unit 120 performs scrambling to protect signaling information. At this time, scrambling can be performed in various ways known in the art.

The BCH encoder 130 performs BCH encoding using BCH parity with a parity length of N _{bch_parity} = 168 bits.

At this time, the BCH encoding may be the same as the BCH encoding for the LDPC code whose data BICM length is 16200.

At this time, the BCH polynomial used in BCH encoding can be expressed as in Table 1 below, and the BCH encoding expressed in Table 1 can have an error correction capability of 12 bits.

[Table 1]

After performing BCH encoding, the zero padding unit 140 performs zero padding or shortening.

At this time, zero padding means filling part of the bit string with bit '0'.

The length of the bit string as a result of BCH encoding can be expressed as N _bch = K _sig + N _{bch_Parity} . At this time, K _sig may be the number of information bits of BCH encoding. For example, if K _sig is fixed to 200 bits, N _bch may be 368 bits.

When the LDPC encoder 150 uses an LDPC code with a code rate of 3/15 and a length of 16200, the information length K _ldpc of LDPC is 3240 bits. At this time, since the information to be actually transmitted is N _bch bits and the length of the LDPC information part is K _ldpc bits, zero padding, which is the process of filling K _ldpc - N _bch bits with bit '0', is performed. For L1-Basic information, K _ldpc - N _bch may be 2872.

At this time, the order of zero padding plays a very important role in determining the performance of the encoder, and the order of zero padding can be expressed as a shortening pattern order.

At this time, zero-padded bits are used only during LDPC encoding and are not actually transmitted.

The LDPC information bits of the K _ldpc bits are divided into N _{info_group} groups as shown in Equation 1 below. For example, when K _ldpc is 3240, N _{info_group} is 9, so LDPC information bits can be grouped into 9 groups.

[Equation 1]

At this time, Z _j represents a group of 360 bits.

Which part of the K _ldpc bits will be zero-padded is determined by the process below.

(Step 1) First, calculate the number of groups in which all the bits shall be padded with '0' using Equation 2 below.

[Equation 2]

For example, if K _ldpc is 3240 and N _bch is 368, N _pad may be 7. N _pad of 7 indicates that the number of groups to fill all bits with 0 is 7.

(Step 2) When N _pad is not 0, for N _pad groups according to the shortening pattern order π _S (j) in Table 2 below. Zero padding in order. At this time, π _S (j) may represent the shortening pattern order of the jth bit group.

If N _pad is 0, the above procedure is omitted.

[Table 2]

The shortening pattern order in Table 2 is the 5th group indexed by 4, the 2nd group indexed by 1, the 6th group indexed by 5, the 3rd group indexed by 2, the 9th group indexed by 8, and the 6th group. This means that the 7th group indexed, the 1st group indexed with 0, the 8th group indexed with 7, and the 4th group indexed with 3 are subject to zero padding in that order. That is, in the example of Table 2, if only 7 groups are selected as targets of zero padding, the 5th group indexed by 4, the 2nd group indexed by 1, the 6th group indexed by 5, and the 3rd group indexed by 2. A total of 7 groups are selected for zero padding: the 9th group, the 9th group indexed by 8, the 7th group indexed by 6, and the first group indexed by 0.

In particular, the shortening pattern order in Table 2 may be optimized for fixed-length signaling information.

Once the number of groups to fill all bits with 0 and the corresponding groups are determined, all bits of the determined groups are filled with '0'.

(Step 3) Additionally, for the group corresponding to Zπ _s ( N _pad ), ( K _ldpc - N _bch - 360 x N _pad ) bits are additionally zero-padded from the front of the group. At this time, zero padding from the front of the group may mean zero padding starting from the bit corresponding to the small index.

(Step 4) When all zero padding is completed, the BCH encoded N _bch bits are sequentially mapped to the remaining portion that is not zero padded to generate an LDPC information bit string.

The LDPC encoder 150 performs LDPC encoding using K _ldpc to which zero padding and signaling information are mapped.

At this time, the LDPC encoder 150 may correspond to an LDPC codeword with a code rate of 3/15 and a length of 16200. The LDPC codeword is a systematic code, and the LDPC encoder 150 generates an output vector as shown in Equation 3 below.

[Equation 3]

For example, if K _ldpc is 3240, the parity bits may be 12960 bits.

The parity permutation unit 160 performs group-wise parity interleaving on the parity part, not the information part, as a preliminary task for parity puncturing.

At this time, the parity permutation unit 160 may perform parity interleaving using Equation 4 below.

[Equation 4]

At this time, Y _j represents the jth group-wise interleaved bit group, and π(j) represents the order of group-wise interleaving, as shown in Table 3 below. It can be defined as follows.

[Table 3]

That is, the parity permutation unit 160 outputs 3240 bits (9 bit groups) corresponding to information bits among the 16200 bits (45 bit groups) of the LDPC codeword as is, and 12960 parity bits. After grouping them into 36 bit groups each containing 360 bits, the order of the 36 bit groups is interleaved in the order of group-wise interleaving corresponding to Table 3 above.

The group-wise interleaving order in Table 3 places the 21st group, indexed as 20, at the 10th group indexed as 9, and places the 24th group, indexed as 23, at the 11th group indexed as 10, This indicates that the 26th group, indexed by 25, is placed in the 12th group, indexed by 11, and the 18th bit group, indexed by 17, is placed in the 45th group, indexed by 44.

At this time, the bit group in the front position (bit group indexed by 20) may correspond to an important parity bit, and the bit group in the back position (bit group indexed by 17) may correspond to an unimportant parity bit.

In particular, the group-wise interleaving order in Table 3 may be optimized for fixed-length signaling information.

After parity interleaving (parity permutation) is completed, the parity puncturing unit 170 may puncture some parities of the LDPC codeword. Punctured bits are not transmitted. At this time, after parity interleaving is completed and before parity puncturing is performed, parity repetition may be performed in which a portion of the parity interleaved LDPC parity bits are repeated.

The parity puncturing unit 170 calculates the final puncturing size and punctures bits corresponding to the calculated final puncturing size. The final puncturing size corresponding to the number of bits to be punctured can be calculated according to the length ( N _bch ) of the BCH encoded bit string as follows.

(Step 1) The temporary puncturing size ( N _{punc_temp} ) is calculated using Equation 5 below.

[Equation 5]

At this time, K _ldpc represents the length of the LDPC information bit string, N _bch represents the length of the BCH encoded bit string, A represents the first integer, and B represents the second integer.

At this time, the difference ( K _ldpc - N _bch ) between the length of the LDPC information bit string and the length of the BCH encoded bit string may correspond to the zero padding length or shortening length.

The parameters for puncturing required for calculating Equation 5 can be defined as shown in Table 4 below.

[Table 4]

At this time, N _{ldpc_parity} represents the number of parity bits of the LDPC codeword, and η _MOD represents the modulation order. At this time, the modulation order may be 2, which may indicate QPSK.

In particular, the puncturing parameters in Table 4 may be optimized for fixed-length signaling information.

(Step 2) Using the calculated temporary puncturing size ( N _{punc_temp} ) and N _{ldpc_parity} in Table 4 above, calculate the number of temporary transmission bits ( N _{FEC_temp} ) as shown in Equation 6 below.

[Equation 6]

(Step 3) Using the calculated number of temporary transmission bits ( N _{FEC_temp} ), calculate the number of transmission bits ( N _FEC ) as shown in Equation 7 below.

[Equation 7]

The number of transmitted bits ( N _FEC ) means the total length of the information part and parity part after puncturing is completed.

(Step 4) Using the calculated number of transmission bits ( N _FEC ), calculate the final puncturing size ( N _punc ) as shown in Equation 8 below.

[Equation 8]

The final puncturing size ( N _punc ) refers to the size of the parity that needs to be punctured.

That is, the parity puncturing unit 170 punctures the last N _punc bits of the whole LDPC codeword with parity _permutation and repetition. You can.

The zero removing unit 180 removes zero-padded bits from the information portion of the LDPC codeword.

The bit interleaving unit 190 performs bit interleaving on the zero removed LDPC codeword. At this time, bit interleaving can be performed by differentiating the recording and reading directions of the LDPC codeword in a memory of a preset size.

The constellation mapping unit 195 performs symbol mapping. For example, the constellation mapping unit 195 may be implemented in QPSK.

The signaling information decoding device 300 demodulates and channel decodes signaling information such as L1-Basic or L1-Detail.

The signaling information decoding device 300 includes a constellation demapping unit 395, a bit deinterleaving unit 390, an inverse zero removing unit 380, an inverse parity puncturing unit 370, and an inverse parity permutation unit 360. , LDPC decoder 360, inverse zero padding unit 340, BCH decoder 330, inverse scrambling unit 320, and inverse segmentation unit 310.

The signaling information decoding device 300 shown in FIG. 1 can be viewed as corresponding to a BICM (Bit-Interleaved Coded Modulation) decoding device, and in this case, the error correction decoder of the BICM decoding device is the inverse zero limit shown in FIG. 1. Ice unit 380, reverse parity puncturing unit 370, reverse parity permutation unit 360, LDPC decoder 360, reverse zero padding unit 340, BCH decoder 330, reverse scrambling unit 320, and reverse It can be viewed as corresponding to the segmentation unit 310.

The reverse segmentation unit 310 performs the reverse process of the segmentation unit 110.

The reverse scrambling unit 320 performs the reverse process of the scrambling unit 120.

The BCH decoder 330 performs the reverse process of the BCH encoder 130.

The reverse zero padding unit 340 performs the reverse process of the zero padding unit 140.

In particular, the inverse zero padding unit 340 receives the LDPC information bit string from the LDPC decoder 350, selects groups in which all bits are filled with 0 using a shortening pattern order, and uses the groups excluding the groups. A BCH encoded bit string can be generated from the LDPC information bit string.

The LDPC decoder 350 performs the reverse process of the LDPC encoder 150.

The reverse parity permutation unit 360 performs the reverse process of the parity permutation unit 160.

In particular, the inverse parity permutation unit 360 divides the parity bits of the LDPC codeword into a plurality of groups and group-wise deinterleaves the groups using group-wise interleaving order to generate the LDPC codeword to be LDPC decoded. can be created.

The reverse parity puncturing unit 370 performs the reverse process of the parity puncturing unit 170.

At this time, the inverse parity puncturing unit 370 uses a first integer multiplied by the difference between the length of the LDPC information bit string and the length of the BCH encoded bit string and a second integer different from the first integer to create a temporary puncturing size (temporary puncturing size), calculate the number of temporary transmission bits using the difference between the length of the BCH encoded bit string and the sum of 12960, and the temporary puncturing size, and calculate the number of temporary transmission bits using the number of temporary transmission bits and the modulation order. Calculate the number, calculate the final puncturing size using the number of temporary transmission bits, the number of transmission bits, and the number of temporary transmission bits, and consider the final puncturing size to the inverse parity permutation unit 360. The provided LDPC codeword can be generated.

The reverse zero removing unit 380 performs the reverse process of the zero removing unit 180.

The bit deinterleaving unit 390 performs the reverse process of the bit interleaving unit 190.

The constellation demapping unit 395 performs the reverse process of the constellation mapping unit 195.

Figure 2 is an operation flowchart showing a method of encoding signaling information according to an embodiment of the present invention.

Referring to FIG. 2, the signaling information encoding method according to an embodiment of the present invention first divides signaling information into several groups (S210).

That is, in step S210, when the length of the signaling information is longer than the preset length, the signaling information is divided into several groups to transmit the signaling information by dividing it into several LDPC codewords. That is, when signaling information cannot be contained in one LDPC codeword, step S210 determines how many codewords to contain the signaling information, and divides the signaling information according to the determined number.

For example, when the length of signaling information is variable such as L1-Detail, the signaling information encoding method may include step S210.

For example, if the length of signaling information is fixed, such as L1-Basic, the signaling information encoding method may not include step S210.

Additionally, the signaling information encoding method according to an embodiment of the present invention performs scrambling to protect signaling information (S220).

At this time, scrambling can be performed in various ways known in the art.

Additionally, the signaling information encoding method according to an embodiment of the present invention performs BCH encoding using BCH parity with a parity length of N _{bch_parity} = 168 bits (S230).

Step S230 may be performed by the BCH encoder 130 shown in FIG. 1.

Additionally, the signaling information encoding method according to an embodiment of the present invention performs zero padding or shortening after performing BCH encoding (S240).

At this time, zero padding may be performed by the zero padding unit 140 shown in FIG. 1.

Since the information to be actually transmitted is N _bch bits, and the length of the LDPC information part is K _ldpc bits, zero padding, which is the process of filling K _ldpc - N _bch bits with bit '0', is performed in step S240. .

Zero padding in step S240 can be performed according to the shortening pattern order in Table 2 above.

Additionally, the signaling information encoding method according to an embodiment of the present invention performs LDPC encoding using K _ldpc to which zero padding and signaling information is mapped (S250).

At this time, step S250 can be performed by an LDPC encoder corresponding to an LDPC codeword with a code rate of 3/15 and a length of 16200.

In addition, the signaling information encoding method according to an embodiment of the present invention is a preliminary work for parity puncturing, and involves group-wise parity interleaving for the parity part, not the information part. Perform (S260).

At this time, step S260 may perform group-wise parity interleaving according to the group-wise interleaving order of Equation 4 and Table 3 above.

Additionally, the signaling information encoding method according to an embodiment of the present invention punctures some parity of the LDPC codeword after parity interleaving (parity permutation) is completed (S270).

The punctured bits in step S270 are not transmitted.

At this time, after parity interleaving is completed and before parity puncturing is performed, parity repetition may be performed in which a portion of the parity interleaved LDPC parity bits are repeated.

Parity puncturing in step S270 may be performed by the parity puncturing unit 170 shown in FIG. 1.

Additionally, the signaling information encoding method according to an embodiment of the present invention performs zero removal to remove zero-padded bits from the information portion of the LDPC codeword (S280).

Additionally, the signaling information encoding method according to an embodiment of the present invention performs bit interleaving on the zero removed LDPC codeword (S290). At this time, step S290 may be performed by changing the direction of writing and reading the LDPC codeword in a memory of a preset size.

Additionally, the signaling information encoding method according to an embodiment of the present invention performs symbol mapping (S295).

Figure 3 is an operation flowchart showing a method of decoding signaling information according to an embodiment of the present invention.

Referring to FIG. 3, the signaling information decoding method according to an embodiment of the present invention performs constellation demapping on a signal received through an antenna (S310).

At this time, step S310 may correspond to the reverse process of step S295 shown in FIG. 2 and may be performed by the constellation demapping unit 395 shown in FIG. 1.

Additionally, the signaling information decoding method according to an embodiment of the present invention performs bit deinterleaving (S320).

At this time, step S320 may correspond to the reverse process of step S290 shown in FIG. 2 and may be performed by the bit deinterleaving unit 390 shown in FIG. 1.

Additionally, the signaling information decoding method according to an embodiment of the present invention performs inverse zero removal (S330).

At this time, step S330 may correspond to the reverse process of step S280 shown in FIG. 2 and may be performed by the reverse zero removing unit 380 shown in FIG. 1.

Additionally, the signaling information decoding method according to an embodiment of the present invention performs inverse parity puncturing (S340).

At this time, step S340 may correspond to the reverse process of step S270 shown in FIG. 2 and may be performed by the reverse parity puncturing unit 370 shown in FIG. 1.

Additionally, the signaling information decoding method according to an embodiment of the present invention performs reverse parity permutation (S350).

At this time, step S350 may correspond to the reverse process of step S260 shown in FIG. 2 and may be performed by the reverse parity permutation unit 360 shown in FIG. 1.

Additionally, the signaling information decoding method according to an embodiment of the present invention performs LDPC decoding (S360).

At this time, step S360 may correspond to the reverse process of step S250 shown in FIG. 2 and may be performed by the LDPC decoder 350 shown in FIG. 1.

Additionally, the signaling information decoding method according to an embodiment of the present invention performs inverse zero padding (S370).

At this time, step S370 may correspond to the reverse process of step S240 shown in FIG. 2 and may be performed by the reverse zero padding unit 340 shown in FIG. 1.

Additionally, the signaling information decoding method according to an embodiment of the present invention performs BCH decoding (S380).

At this time, step S380 may correspond to the reverse process of step S230 shown in FIG. 2 and may be performed by the BCH decoder 330 shown in FIG. 1.

Additionally, the signaling information decoding method according to an embodiment of the present invention performs inverse scrambling (S390).

At this time, step S390 may correspond to the reverse process of step S220 shown in FIG. 2 and may be performed by the reverse scrambling unit 320 shown in FIG. 1.

Additionally, the signaling information decoding method according to an embodiment of the present invention performs reverse segmentation (S395).

At this time, step S395 may correspond to the reverse process of step S210 shown in FIG. 2 and may be performed by the reverse segmentation unit 310 shown in FIG. 1.

Figure 4 is a diagram showing a broadcast signal frame according to an embodiment of the present invention.

Referring to FIG. 4, a broadcast signal frame according to an embodiment of the present invention may be composed of a bootstrap 421, a preamble 423, and data symbols 425.

The preamble 423 includes signaling information.

In the example shown in FIG. 4, the preamble 423 may include L1-Basic information 431 and L1-Detail information 433.

At this time, L1-Basic information 431 may be fixed-length signaling information.

For example, L1-Basic information 431 may correspond to 200 bits.

At this time, L1-Detail information 433 may be variable length signaling information.

For example, L1-Detail information 433 may correspond to bits 200 to 2352.

The LDPC (Low Density Parity Check) code is known as a code that approaches the Shannon limit in the AWGN (Additive White Gaussian Noise) channel, and has asymptotically better performance than the turbo code, parallelelizable decoding, etc. There is an advantage.

Generally, LDPC codes are defined by a randomly generated low density PCM (Parity Check Matrix). However, randomly generated LDPC codes not only require a lot of memory to store the PCM, but also take a lot of time to access the memory. To solve this problem, a quasi-cyclic LDPC (QC-LDPC) code was proposed, and the QC-LDPC code composed of a zero matrix or CPM (Circulant Permutation Matrix) has the following equation: It is defined by the PCM expressed by 9.

[Equation 9]

Here, J is a CPM of size L x L and is given as Equation 10 below. Hereinafter, L may be 360.

[Equation 10]

In addition, J ⁱ is the L x L identity matrix I (=J ⁰ ) shifted to the right i (0≤i<L) times, and J ^∞ is the L x L zero matrix. Therefore, in the QC-LDPC code, only the exponent i needs to be stored to store J ⁱ , so the memory required to store the PCM is greatly reduced.

Figure 5 is a diagram showing the structure of a parity check matrix corresponding to an LDPC code according to an embodiment of the present invention.

Referring to Figure 5, the sizes of matrices A and C are g x K and (N-K-g) x (K+g), respectively, and are composed of a zero matrix and CPM of size L x L. Additionally, matrix z is a zero matrix of size g x (N-K-g), matrix D is an identity matrix of size (N-K-g) x (N-K-g), and matrix B is a dual diagonal matrix of size g x g. matrix). At this time, matrix B may be a matrix in which all elements other than the diagonal elements and neighboring elements below the diagonal are all 0, or may be defined as in Equation 11 below.

[Equation 11]

Here, I _LxL is an identity matrix of size L x L.

That is, matrix B may be a general (bit-wise) double diagonal matrix, or it may be a block-wise double diagonal matrix with the identity matrix as a block, as expressed in Equation 11 above. The general (bit-wise) double diagonal matrix is disclosed in detail in Korean Patent Publication No. 2007-0058438, etc.

In particular, when matrix B is a general (bit-wise) double diagonal matrix, row permutation or column permutation is applied to the PCM of the structure shown in Figure 5 including this matrix B. It is obvious to those skilled in the art that it can be converted to quasi-cyclic.

At this time, N is the length of the codeword, and K represents the length of the information.

The present invention proposes a newly designed QC-LDPC code with a code rate of 3/15 and a code word length of 16200, as shown in Table 5 below. In other words, we propose an LDPC code that receives information with a length of 3240 and generates an LDPC codeword with a length of 16200.

Table 5 shows the sizes of the A, B, C, D, and Z matrices of the QC-LDPC code of the present invention.

[Table 5]

The newly designed LDPC code can be displayed in the form of a sequence, an equivalent relationship is established between the sequence and the matrix (parity bit check matrix), and the sequence can be expressed as in the table below.

[table]

Line 1: 8 372 841 4522 5253 7430 8542 9822 10550 11896 11988

Line 2: 80 255 667 1511 3549 5239 5422 5497 7157 7854 11267

Line 3: 257 406 792 2916 3072 3214 3638 4090 8175 8892 9003

Line 4: 80 150 346 1883 6838 7818 9482 10366 10514 11468 12341

Line 5: 32 100 978 3493 6751 7787 8496 10170 10318 10451 12561

Line 6: 504 803 856 2048 6775 7631 8110 8221 8371 9443 10990

Line 7: 152 283 696 1164 4514 4649 7260 7370 11925 11986 12092

Line 8: 127 1034 1044 1842 3184 3397 5931 7577 11898 12339 12689

Line 9: 107 513 979 3934 4374 4658 7286 7809 8830 10804 10893

Line 10: 2045 2499 7197 8887 9420 9922 10132 10540 10816 11876

Line 11: 2932 6241 7136 7835 8541 9403 9817 11679 12377 12810

Line 12: 2211 2288 3937 4310 5952 6597 9692 10445 11064 11272

LDPC codes, written in sequence form, are widely used in the DVB standard.

According to one embodiment of the present invention, the LDPC code written in sequence form is encoded as follows. Assume an information block S=(s ₀ , s ₁ , ..., s _K-1 ) with information size K. The LDPC encoder uses an information block S of size K to generate a codeword of size N=K+M ₁ +M ₂ creates . Here, M ₁ =g, M ₂ =NKg. Additionally, M ₁ is the size of the parity corresponding to the dual diagonal matrix B, and M ₂ is the size of the parity corresponding to the identity matrix D. The encoding process is as follows.

-Initialization:

[Equation 12]

-first Accumulate at the parity bit addresses specified in the first row of the sequence of the table. For example, the accumulation process in an LDPC code with a length of 16200 and a code rate of 3/15 is as follows.

Here addition ( ) occurs in GF(2).

-Next L-1 information bits, i.e. , they are accumulated from the parity bit addresses calculated in Equation 13 below.

[Equation 13]

where x is the first bit Indicates the parity bit addresses corresponding to, that is, the parity bit addresses written in the first row of the sequence of the table, where Q ₁ = M ₁ /L, Q ₂ = M ₂ /L, L = 360. Additionally, Q ₁ and Q ₂ are defined in Table 6 below. For example, an LDPC code with a length of 16200 and a code rate of 3/15 has M ₁ = 1080, Q ₁ = 3, M ₂ = 11880, Q ₂ = 33, L = 360, so the second bit Using Equation 13 above, the following calculation is performed.

Table 6 shows the sizes of M ₁ , M ₂ , Q ₁ , and Q ₂ of the designed QC-LDPC code.

[Table 6]

-the next from The new 360 information bits are calculated and accumulated by using the second row of the sequence to calculate the addresses of the parity bit accumulators from Equation 13.

- In a similar way, for all groups consisting of new L information bits, the addresses of the parity bit accumulators are calculated from Equation 13 using the new rows of the sequences, and accumulated.

- at After all information bits up to are used, the calculation of Equation 14 below is sequentially performed, starting from i = 1.

[Equation 14]

-Next, by performing parity interleaving as shown in Equation 15 below, parity generation corresponding to the double diagonal matrix B is completed.

[Equation 15]

K information bits ( ), when the parity generation corresponding to the double diagonal matrix B is completed, M ₁ generated parity ( ) is used to generate parity corresponding to the identity matrix D.

- at For all groups consisting of L bits up to L, a new row of the sequences (starting from the row immediately following the last row used when generating the parity corresponding to the double diagonal matrix B) and Equation 13 Use to calculate the addresses of parity bit accumulators and perform related operations.

- at After all bits up to are used, parity interleaving as shown in Equation 16 below is performed, and parity generation corresponding to the identity matrix D is completed.

[Equation 16]

FIG. 6 is a diagram illustrating an example of the operation of the zero padding unit shown in FIG. 1.

Referring to FIG. 6, the zero padding operation when the shortening pattern order is [4 1 5 2 8 6 0 7 3] can be seen.

In the example shown in FIG. 6, the length of the LDPC information bit string is 3240, so the LDPC information bits are composed of nine groups of 360 bits.

First, if the number of groups to fill all bits with 0 is determined using Equation 2 above, (3240-368)/360 = 7.9, so 7 groups are determined to be filled with 0.

Additionally, since the shortening pattern order is [4 1 5 2 8 6 0 7 3], the 5th group 610 indexed by 4, the 2nd group 620 indexed by 1, and the 6th group indexed by 5 Group 630, third group 640 indexed by 2, 9th group 650 indexed by 8, 7th group 660 indexed by 6, first group indexed by 0 ( A total of 7 groups (670) are selected and all bits in the groups are filled with 0.

In addition, the next order of the first group 670 indexed by 0 is the 8th group 680 indexed by 7, so from the front of the 8th group 680 indexed by 7 (3240 - 368 - (360 x 7) )) = 352 bits are filled with 0.

After zero padding is completed, BCH encoded N _bch (=368) bits for a total of 368 bits of the 360 bits of the 4th group 690 indexed by 3 and the remaining 8 bits of the 8th group 680 indexed by 7. Bit strings are mapped sequentially.

FIG. 7 is a diagram illustrating an example of the operation of the parity permutation unit shown in FIG. 1.

Referring to Figure 7, the group-wise interleaving order is the sequence [20 23 25 32 38 41 18 9 10 11 31 24 14 15 26 40 33 19 28 34 16 39 27 30 21 44 43 35 42 36 12 13 29 22 37 17 ] The parity permutation operation in the corresponding case can be known.

K _ldpc (=3240) information bits are not interleaved, and 36 groups of 360 bits (a total of 12960 bits) are subject to interleaving.

Since the group-wise interleaving order corresponds to the sequence [20 23 25 32 38 41 18 9 10 11 31 24 14 15 26 40 33 19 28 34 16 39 27 30 21 44 43 35 42 36 12 13 29 22 37 17], parity The permutation unit places the 21st group, indexed as 20, at the 10th group position (710) indexed as 9, and places the 24th group, indexed as 23, at the 11th group position (720) indexed as 10. .., the 38th group indexed by 37 is placed at the 44th group position 730 indexed by 43, and the 18th bit group indexed by 17 is placed at the 45th group position 740 indexed by 44.

Parity puncturing can be performed behind the parity interleaved parity bits (toward the 18th bit group indexed by 17).

FIG. 8 is a diagram showing an example of the operation of the zero removing unit shown in FIG. 1.

Referring to FIG. 8, it can be seen that the zero removing unit removes zero-padded parts from the information part of the LDPC codeword and generates signaling information for transmission.

Figure 9 is a block diagram showing a parity puncturing device according to an embodiment of the present invention.

Referring to FIG. 9, the parity puncturing device according to an embodiment of the present invention includes a processor 920 and a memory 910.

The processor 920 punctures a number of bits corresponding to the final puncturing size at the back of the parity bit string for parity puncturing of the parity bits of an LDPC codeword with a length of 16200 and a code rate of 3/15. .

At this time, the LDPC codeword may include zero-padded fixed-length signaling information as information bits.

At this time, the final puncturing size is calculated using the temporary puncturing size, number of transmission bits, and number of temporary transmission bits as in Equation 8, and the number of transmission bits is as in Equation 7. It is calculated using the number of temporary transmission bits and the modulation order, and the number of temporary transmission bits is the difference between the sum of the length of the BCH encoded bit string and 12960 and the temporary puncturing size as shown in Equation 6. The temporary puncturing size can be calculated (A=0) regardless of the difference between the length of the LDPC information bit stream and the length of the BCH encoded bit stream, as shown in Equation 5 and Table 4.

At this time, the temporary puncturing size is a first integer (A) multiplied by the difference between the length of the LDPC information bit string and the length of the BCH encoded bit string, and a second integer (A) different from the first integer, as shown in Equation 5 above. B) can be calculated using

At this time, as shown in Table 4, the first integer is 0, the second integer is 9360, and the modulation order may be 2, corresponding to QPSK.

The memory 910 provides a parity bit string for parity puncturing of parity bits of an LDPC codeword with a length of 16200 and a code rate of 3/15.

At this time, the parity bit string can be generated by dividing the parity bits of the LDPC codeword into a plurality of groups and group-wise interleaving the groups using group-wise interleaving order.

At this time, the group-wise interleaving order is in the sequence [20 23 25 32 38 41 18 9 10 11 31 24 14 15 26 40 33 19 28 34 16 39 27 30 21 44 43 35 42 36 12 13 29 22 37 17] corresponding It may be.

The parity puncturing device shown in FIG. 9 may correspond to the parity puncturing unit 170 shown in FIG. 1.

Additionally, the structure shown in FIG. 9 may correspond to a reverse parity puncturing device. At this time, the reverse parity puncturing device may correspond to the reverse parity puncturing unit 370 shown in FIG. 1.

If the structure shown in FIG. 9 corresponds to an inverse parity puncturing device, the processor 920 calculates a temporary puncturing size, the sum of the length of the BCH encoded bit string and 12960, and the temporary puncturing Calculate the number of temporary transmission bits using the difference in the processing size, calculate the number of transmission bits using the number of temporary transmission bits and the modulation order, and calculate the number of temporary transmission bits, the number of transmission bits, and the number of temporary transmission bits. The final puncturing size is calculated, and reverse parity puncturing corresponding to the final puncturing size is performed to generate a parity bit string of the LDPC codeword with a length of 16200 and a code rate of 3/15.

At this time, the LDPC codeword may include zero-padded fixed-length signaling information as information bits.

At this time, the temporary puncturing size can be calculated (A=0) regardless of the difference between the length of the LDPC information bit string and the length of the BCH encoded bit string, as shown in Equation 5 and Table 4.

At this time, the temporary puncturing size is a first integer (A) multiplied by the difference between the length of the LDPC information bit string and the length of the BCH encoded bit string as shown in Equation 5 above, and a second integer (B) different from the first integer. ) can be calculated using .

At this time, as shown in Table 4, the first integer is 0, the second integer is 9360, and the modulation order may be 2, corresponding to QPSK.

The memory 910 stores a parity bit string.

Figure 10 is an operational flowchart showing a parity puncturing method according to an embodiment of the present invention.

Referring to FIG. 10, the parity puncturing method according to an embodiment of the present invention calculates the final puncturing size (S1010).

Although not explicitly depicted in FIG. 10, the parity puncturing method according to an embodiment of the present invention includes calculating a temporary puncturing size; Calculating the number of temporary transmission bits using the difference between the length of the BCH encoded bit string and the sum of 12960 and the temporary puncturing size; and calculating the number of transmission bits using the temporary number of transmission bits and the modulation order.

At this time, step S1010 may calculate the final puncturing size using the number of temporary transmission bits, the number of transmission bits, and the number of temporary transmission bits.

At this time, the temporary puncturing size can be calculated regardless of the difference between the length of the LDPC information bit string and the length of the BCH encoded bit string (A is 0), as shown in Equation 5 and Table 4.

At this time, the temporary puncturing size is a first integer (A) multiplied by the difference between the length of the LDPC information bit string and the length of the BCH encoded bit string as shown in Equation 5 above, and a second integer (B) different from the first integer. ) can be calculated using .

At this time, as shown in Table 4, the first integer may be 0, the second integer may be 9360, and the modulation order may be 2, corresponding to QPSK.

In addition, the parity puncturing method according to an embodiment of the present invention includes the final puncturing at the back of the parity bit string for parity puncturing of the parity bits of an LDPC codeword with a length of 16200 and a code rate of 3/15. A number of bits corresponding to the piercing size are punctured (S1020).

At this time, the LDPC codeword may include zero-padded fixed-length signaling information as information bits.

At this time, the parity bit string may be generated by dividing the parity bits of the LDPC codeword into a plurality of groups and group-wise interleaving the groups using group-wise interleaving order.

At this time, the group-wise interleaving order is in the sequence [20 23 25 32 38 41 18 9 10 11 31 24 14 15 26 40 33 19 28 34 16 39 27 30 21 44 43 35 42 36 12 13 29 22 37 17] corresponding It may be.

As described above, the parity puncturing device, parity puncturing method, and reverse parity puncturing device according to the present invention are not limited to the configuration and method of the embodiments described above, and the embodiments can be applied in various ways. All or part of each embodiment may be selectively combined so that modifications can be made.

910: memory
920: Processor

Claims (6)

A processor that performs de-puncturing corresponding to the final puncturing size and generates parity values corresponding to parity bits of an LDPC codeword with a length of 16200 and a code rate of 3/15; and
Memory for storing the parity values
A reverse parity puncturing device comprising: In claim 1,
The LDPC codeword is
An inverse parity puncturing device comprising zero-padded fixed-length signaling information as information bits. In claim 1,
The final puncturing size is
Calculated using the temporary puncturing size, number of transmitted bits, and number of temporary transmitted bits,
The number of transmission bits is calculated using the temporary number of transmission bits and a modulation order,
The number of temporary transmission bits is calculated using the difference between the sum of the length of the BCH encoded bit string and 12960 and the temporary puncturing size,
Inverse parity puncturing device, wherein the temporary puncturing size is calculated regardless of the difference between the length of the LDPC information bit stream and the length of the BCH encoded bit stream. In claim 3,
Inverse parity puncturing, wherein the temporary puncturing size is calculated using a first integer multiplied by the difference between the length of the LDPC information bit stream and the length of the BCH encoded bit stream and a second integer different from the first integer. Device. In claim 4,
The first integer is 0, the second integer is 9360,
Inverse parity puncturing device, characterized in that the modulation order is 2 corresponding to QPSK. determining a final puncturing size using a temporary puncturing size, the number of transmission bits, and the number of temporary transmission bits; and
Performing de-puncturing corresponding to the final puncturing size to generate parity values corresponding to parity bits of an LDPC codeword with a length of 16200 and a code rate of 3/15.
A reverse parity puncturing method comprising: