KR20240020780A - How to layout the signal lines on the upper layer of the conductor - Google Patents

Abstract

The present invention is to change the width of the signal line from wide to narrow it to be the same as the width of the short-distance signal line in order to lower the resistance of the long-distance CDA signal line for the CDA that constitutes the capacitance detection device of the present invention installed on the upper surface of a conductor. As a result, the detection speed is improved by making the time constant in the long-distance CDA smaller, and the width of the dead zone caused by the signal line is minimized to minimize object detection errors or touch coordinate calculation errors.

Description

{How to layout the signal lines on the upper layer of the conductor}

The present invention is installed on the upper surface of a conductor and the CDA signal line width connected to the CDA (Capacitor Detection Area) constituting the capacitance detection device is widened, thereby reducing touch sensitivity due to an increase in the capacitance of the common electrode and detection errors due to an increase in the time constant. And, compared to the existing embodiment in which object detection errors and touch coordinate determination errors occur due to dead zones, the CDA signal line width is reduced by changing the layout, thereby solving the problems of lowered touch detection sensitivity and detection errors. This relates to a method to prevent object detection errors and calculation errors in touch detection coordinates by narrowing the width of the dead zone.

In the past, mechanical buttons were used to press phone numbers on mobile phones, but recently, input devices are changing from mechanical to electronic, with phone numbers being entered just by lightly touching the display of the mobile phone with a finger. As an example of an electronic input device, a capacitive type touch input device is mainly used. A capacitive touch input device is the size of capacitance generated when an object such as a finger or pen approaches or touches the capacitance detection area (CDA) installed on the top of the display device. By detecting changes in capacitance, it is determined that the input at that location is valid, as if a mechanical button was pressed.

Figure 1 is an embodiment of the present invention regarding modeling of a capacitive touch input device. Referring to Figure 1, Cd is the "line-to-line capacitance", which is the capacitance formed between the sensing signal line and the driving signal line, which will be described later, and Cprs is the capacitance formed between the sensing signal line and the semiconductor substrate or other signal lines inside the semiconductor IC. This is the “internal parasitic capacitance” formed, and Ccm is the “common electrode capacitance” formed by opposing the CDA and CDA signal lines and conductors such as the common electrode or cathode of the display device. One side of each of these three capacitances is connected to a sensing signal line, and in Figure 1, the sensing signal line is indicated as point P in an equivalent circuit. Vprs, the voltage supplied to the other side of the "internal parasitic capacitance", is the DC power potential of the semiconductor substrate or the AC potential due to noise of other coupled signal lines, and is the potential of the "common electrode capacitance". The common electrode voltage Vcm, which is the voltage supplied to the other side, is the pixel voltage, which is a DC voltage of a certain size supplied to the common electrode of LCD or the cathode of OLED, or the ground or predetermined voltage supplied to a separate conductor. is the DC voltage of Vd, the voltage supplied to Cd, the line-to-line capacitance, is a driving voltage that changes in size from Vd1 to Vd2 or from Vd2 to Vd1. The driving voltage supplies charge to the line-to-line capacitance (Cd), and the charge supplied through the line-to-line capacitance (Cd) causes a charge sharing phenomenon based on the size of the capacitances commonly connected to the P point, which is the sensing signal line. The potential of point P, the sensing signal line, is determined.

The common electrode voltage is a voltage that has a predetermined size for display on the screen of the display device and cannot be changed, and Vprs, the voltage supplied to the internal parasitic capacitance, cannot be changed because it is a power source coupled to a semiconductor substrate or other signal line. , it is possible to apply the driving voltage only to the line-to-line capacitance. In the present invention, when a driving voltage is applied to the line-to-line capacitance and charge is supplied to the sensing signal line through the line-to-line capacitance, the sensing CDA detects the amount of change in voltage based on the size of the object capacitance detected by the sensing CDA to determine whether or not to touch. Determine.

In Figure 1, when there is no object capacitance (Cobj), that is, in a non-touch (Not Touch) state, the voltage when the potential at point P is stabilized by the voltage supplied for each of the three capacitances is referred to as Vp. The current flowing through the line-to-line capacitance Cd due to the voltage Vd supplied to the line-to-line capacitance (Cd) is defined as id, and the current flowing through Cprs due to the voltage Vprs supplied to the internal parasitic capacitance (Cprs) is defined as iprs. Assuming that icm is the current flowing through Ccm due to the voltage Vcm supplied to the common electrode capacitance (Ccm), id = iprs + icm according to Kirchhoff's current law.

Because of,

am. If we summarize this equation for Vp, we get am.

In the above equation, if the voltage Vd supplied to the line-to-line capacitance (Cd) is replaced with Vd1, the voltage at point P when Vd1 is applied is am. Also, when supplying Vd2, a voltage greater than Vd1, to the line-to-line capacitance (Cd), Vp2, the voltage at point P, is am. Therefore, when voltages Vd1 and Vd2 of different magnitudes are applied to the line-to-line capacitance (Cd), Vp2-Vp1 detected at the connection point P is equal to the following <Equation 1>.

<Equation 1>

Line-to-line capacitance (Cd) is the capacitance formed between the sensing signal line and the driving signal line, and is the mutual capacitance (described later) and the (parallel) capacitance of the common electrode formed by the sensing signal line and the driving signal line but connected in series. determined by the sum (by connection).

Figure 2 is an embodiment of the present invention related to a display module equipped with a capacitance detection device. Referring to FIG. 2, the capacitance detection device is composed of a plurality of CDAs consisting of three rows and four columns. For the convenience of drawing, the capacitance detection device is composed of 12 CDAs (100), but in reality, it has 25 rows and 25 columns, or 20 (R) x 30 (C). It consists of a large number of rows and columns. If a row is composed of 25 CDAs (100), each column contains 25 CDAs (100) from Row 1 at a distance to Row 25 at a near distance. At this time, the length of the CDA signal line 201 connected to the CDA located in Row 1, which is the furthest from the semiconductor IC 400, which controls all operations to detect the touch signal, is the longest, and the length of the CDA signal line connected to the CDA located in Row 25 is the longest. is the shortest.

In the capacitance detection device of the present invention installed on the top of the display device, the line resistance (R) of the CDA signal line made of transparent conductive material such as ITO or IZO is determined by the resistivity (ρ) of the constituent material, the signal line width (d_sig), and the signal line. It is determined by the length (l) as shown in Equation 2 below.

<Equation 2>

R=

Referring to <Equation 2>, it can be seen that the size of the CDA signal line resistance is proportional to the length of the CDA signal line and inversely proportional to the width of the CDA signal line.

Paragraph number [0027] of Korean Patent No. 10-1637422 (Application No. 10-2014-0177766, hereinafter referred to as Cited Patent 1), which the applicant previously applied for and registered, is as follows.

" Meanwhile, in the wiring method of the sensor signal line 22 as shown in FIG. 6, the signal line connected to the sensor pattern 10(1,1) located at the top and the sensor pattern 10(1,5) located at the bottom Since the length of the signal line connected to is different, the wiring resistance of the signal line varies for each sensor pattern 10. As the resistance value increases, a delay occurs in detecting the touch signal, so the width of the sensor signal line 22, which is wired at the top, is wired at the bottom. If the resistance value of the sensor signal line 22 wired to the top is lowered by making it wider than the width of the sensor signal line 22 and the resistance value is increased by narrowing the wiring width of the sensor signal line 22 wired to the bottom, all sensor patterns (10 ), it is possible to match the wiring resistance of the signal lines. Therefore, detection of the touch signal in the signal processing unit 35 becomes easier - omitted below."

Additionally, referring to paragraph numbers [0102] to [0104] of Cited Invention 1, it is as follows.

"As shown in FIG. 9, the size of the sensor pattern 10a at a distance from the touch drive IC 30 and the width of the sensor signal line 22a connected thereto are determined by the size of the sensor pattern 10e at a short distance and the width connected thereto. Each is larger than the width of the sensor signal line 22e.

In FIG. 9 , the size of the sensor pattern is in the order of 10a > 10b > 10c > 10d > 10e depending on the distance from the touch drive IC 30.

At the same time, the width of the sensor signal line connected to each sensor pattern is in the following order: 22a > 22b > 22c > 22d > 22e ."

In the embodiment of Cited Invention 1, if the line width of the CDA signal line laid out at a greater distance becomes wider, the dead zone caused by the CDA signal line gradually widens as it moves closer to the semiconductor IC, so the Pen is composed of a width narrower than the width of the dead zone. There is a problem of not detecting a touch by . In addition, when a finger touches two neighboring CDAs, a CDA with a dead zone and a CDA without a dead zone, the touch signal detected in the CDA with a dead zone becomes smaller than the touch signal detected in the CDA without a dead zone, thereby reducing the touch signal. When determining the touch coordinates based on the touch coordinate determination error, a touch coordinate determination error occurs. In addition, the time constant increases due to the increase in common electrode capacitance in long-distance CDA, so if the detection time is not sufficient in a system that detects signals within a limited time, signal detection errors occur, and the increased common electrode capacitance causes short-distance and There are problems such as a difference in detection voltage at a long distance and a decrease in detection sensitivity.

Korean registered patent: No. 10-1637422 (hereinafter: Cited Patent 1)

The present invention was proposed to solve the problems of the prior art as described above. By using a CDA signal line layout method different from the embodiment of Cited Invention 1, object detection errors and touch coordinate determination errors due to dead zones are minimized. The goal is to provide a signal line layout method that minimizes touch detection errors.

In order to achieve the above object, an embodiment of the present invention includes a capacitance detection area (Capacitor Detection Area, CDA) installed on the upper surface of the display device and composed of a conductor and an independent area; CDA signal line connected to CDA; When CDA signal lines are installed on the upper surface of the pixel of a display device and face each other, the line width of the CDA signal lines or the pitch of the CDA signal lines, including the space between CDA signal lines and the line width of the CDA signal lines, is narrower than the width of the pixel. do.

Additionally, a CDA column composed of a plurality of CDAs; and in the CDA column, a CDA group consisting of a plurality of neighboring CDA signal lines; And the line width of the CDA signal line constituting the CDA group is the same as the line width of the CDA signal line neighboring in the short distance.

Additionally, all CDA signal lines that make up the CDA column have the same line width.

Additionally, within the same CDA group, the line width of the CDA signal line is the same, and in different CDA groups, CDA signal line line widths of different sizes are laid out.

Additionally, in the CDA column, the line width of the CDA signal line located at a distance based on the position of the semiconductor IC is the same as the line width of the CDA signal line adjacent at a short distance based on the position of the semiconductor IC.

In addition, the line width of the CDA signal line or the pitch of the CDA signal line is determined as m x SPP based on the Sub Pixel Pitch (hereinafter, SPP) constituting the pixel. However, m is a positive integer or a positive real number.

In addition, the line width of the CDA signal line or the pitch of the CDA signal line is determined as n x PP based on the pixel pitch (hereinafter referred to as PP). However, n is a positive integer or a positive real number.

Additionally, the line width of the CDA signal lines and the width of the space between CDA signal lines are the same.

Additionally, at a short distance, the width of the space between the CDA signal lines is laid out to be narrower than the line width of the CDA signal lines.

According to one embodiment of the present invention, the size of the common electrode capacitance of the far-distance CDA signal line is reduced, thereby improving touch sensitivity and minimizing the difference in voltage detected by the object capacitance of the same area in the far-distance and near-distance CDA. there is. In addition, the time constant of the long-distance CDA signal line is shortened, which has the effect of improving touch detection speed and reducing current consumption. In addition, since the width of the dead zone is narrowed, it is possible to detect objects with a small touch area such as a pen or fine finger touches. In addition, there is an effect of improving touch coordinate errors.

The effects of the present invention are not limited to the effects described above, and should be understood to include all effects that can be inferred from the configuration of the invention described in the detailed description or claims of the present invention.

Figure 1 is an embodiment of the present invention regarding modeling of a capacitive touch input device.
Figure 2 is an embodiment of the present invention related to a display module equipped with a capacitance detection device.
Figure 3 is an embodiment of the present invention regarding formation of common electrode capacitance (Ccm).
Figure 4 is an embodiment of the present invention relating to a capacitance detection device consisting of one CDA column and a semiconductor IC connection.
Figure 5a shows an embodiment of the present invention regarding the formation of capacitance between a sensing signal line and two driving signal lines adjacent to the sensing signal line.
Figure 5b is an embodiment of the present invention related to the equivalent circuit of Figure 5a.
Figure 6 is an embodiment of the present invention regarding the layer configuration of a semiconductor IC.
Figure 7 is an embodiment of the present invention related to modeling of a capacitive touch input device when an object capacitor is added.
Figure 8 shows an embodiment of the present invention regarding the layout of CDA signal lines installed on the upper surface of a pixel of a display device.

The terms used in the present invention are general terms that are currently widely used as much as possible while considering the functions in the present invention, but this may vary depending on the intention of a person skilled in the art, precedents, or the emergence of new technologies. In addition, in certain cases, terms arbitrarily selected by the applicant were used, and in this case, the meaning will be described in detail in the description of the relevant invention. Therefore, the terms used in the present invention should be defined based on the meaning of the term and the overall content of the present invention, rather than simply the name of the term.

In addition, the size and thickness of each component shown in the drawings are arbitrarily shown for convenience of explanation, and the present invention is not necessarily limited to what is shown.

In order to clearly express various layers and areas in the drawing, the thickness and width are exaggerated through drawings such as relative enlargement and relative reduction. When a part of a layer, area, etc. is said to be "on" or "on" or "on top" or "on top" another part, it means not only being "directly above" another part, but also if there is another part in between. Also includes. “Below” or “lower side” or “underside” also has the same meaning.

When it is said that a part "includes" a certain element throughout the specification, this means that, unless specifically stated to the contrary, it does not exclude other elements but may further include other elements. In addition, terms such as "... unit" and "module" used in the specification refer to a unit that processes at least one function or operation, which may be implemented as hardware or software, or as a combination of hardware and software. .

<Definition of terms>

In this specification, “capacitance” and “capacitor” are used with the same meaning.

Additionally, the capacitance symbol is used in two senses: the reference symbol for the capacitance and the size (Capacitance) of the capacitance. For example, Cprs is a capacitor as a symbol indicating the capacitance formed by the sensing signal line and the bulk (substrate) of the semiconductor inside the semiconductor IC, and may also be the size (Capacitance) of a certain capacitance. In cases where the meaning is confusing, it is written separately as “capacitance” or “size of capacitance.”

In addition, a finger or a pen forming an object capacitance facing the CDA 100 is designated as an object 20 or Object.

In addition, among several CDA signal lines 200, the signal line that detects voltage (or detects a signal) based on the mathematical equation provided by the present invention is denoted as a sensing signal line, and the CDA ( 100) is denoted as sensing CDA. It is adjacent to the sensing signal line, forming a line-to-line capacitance, and the signal line to which the driving voltage is applied is marked as a driving signal line.

In addition, other signal lines required for operation inside the semiconductor IC 400 other than the CDA signal line 200 connected to the CDA 100, such as the Logic Signal Line, Oscillator Signal Line, and Power Line, are referred to as "other signal lines." (Different Signal Line) to distinguish it from the CDA signal line 200 of the present invention.

In addition, the CDA 100 and the CDA signal line 200 connected thereto are geometrically distinct, but electrically have the same meaning. Therefore, the meaning of “detecting voltage from the sensing CDA” is the same as “detecting the voltage from the sensing signal line connected to the sensing CDA.”

Additionally, under the control of the semiconductor IC, the CDA sequentially becomes a sensing CDA, a driving CDA, or operates as a CDA that does not play any role. In this specification, “voltage detected in the CDA” has the same meaning as “voltage detected when the CDA operates as a sensing CDA.”

In addition, the distance and direction (far/near) are based on the semiconductor IC (400). Far distance means far away from the semiconductor IC, and near distance means close to the semiconductor IC (400).

Additionally, one column formed from multiple CDAs is called a CDA Column, and multiple CDA columns are gathered together to form a column group.

Additionally, the pixels of the display device are composed of sub-pixels such as Red/Green/Blue or White. In this specification, a pixel is composed of the three primary colors of R/G/B, and the length of the short side of the sub pixel constituting the pixel is defined as the pitch of the sub pixel. Sub Pixel Pitch also includes BM (Black Matrix). Triple the pitch of the sub pixel becomes the pitch of the pixel.

In addition, the capacitance detection device of the present invention is a "system" that detects the voltage on the sensing signal line after applying the driving voltage to the driving signal line adjacent to the sensing signal line and the potential of the sensing signal line is stabilized. The mathematical equation representing the voltage detected from the sensing signal line after applying the driving voltage to the line-to-line capacitance was expressed as the “transfer function” of the system.

Below, with reference to the attached drawings, embodiments of the present invention will be described in detail so that those skilled in the art can easily practice the embodiments of the present invention. However, the present invention may be implemented in various different forms and is not limited to the embodiments described herein. In order to clearly explain the present invention in the drawings, parts unrelated to the description are omitted, and similar reference numerals are used for similar parts throughout the specification.

Figure 2 is an embodiment of the present invention related to a display module equipped with a capacitance detection device. The capacitance detection area 100 of the capacitance detection device is made of a transparent conductor and is installed inside the display device 10 or on the top surface of the display device 10 or in home appliances or industrial equipment and has an independent area. The CDA signal line 200 connected to the CDA on one side of the CDA 100 electrically connects the CDA 100 to the semiconductor IC 400 located on one side of the display device 10 or outside the display device 10. It is connected to the signal processing unit 410 of the semiconductor IC 400 through a member 300 (Material for connection).

The CDA 100 used in the display device 10 or industrial equipment is covered with tempered glass, plastic, or film to be protected from the object 20 or external foreign substances. CDA 100 is a geometric shape such as a circle, square, or triangle with a predetermined area, and is mostly made of the same or similar geometric shape. When an object such as a human finger or a pen appears on the upper surface of the CDA (100) and touches or approaches the CDA, object capacitance (Cobj) is formed according to the mutual clearance distance and opposing area between the object and the CDA. do.

When a touch occurs by an object, an object capacitance (Cobj) is formed by the distance "d1" and the opposing area "s1" between the CDA 100 and the object 20, and the size of the formed object capacitance Cobj ( Capacitance) It is (F). ε is the permittivity of the material existing between the CDA 100 and the object 20, and a complex permittivity due to the protective layer 7 such as glass or film and air (if the object is floating in the air) is applied. .

The location of CDA 100 in the display device is as follows.

1) In the case of LCD: It is formed on the top of the Color Filter Glass, that is, on the Color Filter Glass where the Color Filter Glass and the polarizing plate are joined, or is formed on the lower or upper side of the polarizing plate, or is installed on the lower side of the protective layer (7).

2) In case of OLED 1: Passivation is formed on the upper surface of the cathode after applying it.

3) In case of OLED 2: It is formed on the top or bottom of the PI (Polyimide) series thin film, which is the encapsulation substrate of OLED, or on the top or bottom of the encapsulation glass.

In the case of the above LCD, the CDA is located on the upper surface of the common electrode of the LCD made of ITO or IZO, which is a conductor, and in the case of OLED, the CDA is installed on the upper surface of the cathode made of ITO or IZO, which is a conductive material. When the capacitance detection device of the present invention is used in places other than display devices such as aircraft control boards or vehicle operation switches, a conductor is present on the bottom of the CDA.

It must be installed, and this is to ensure that the CDA signal line width is not included in the time constant (according to the mathematical equation described later). Transmittance is important for the conductor of the display device, so the conductor is made of transparent materials such as ITO or IZO. However, if it is not installed on the top of the display device, such as the touch used for elevator buttons, the conductor facing the CDA is non-transparent. Conductive materials such as iron, copper, silver, or gold may be used.

In this specification, the direction in which the number of CDA signal lines 200 increases or decreases based on the position of the semiconductor IC 400 is defined as a column. In Figure 2, the number of signal lines decreases from 3 to 1 from the bottom where the semiconductor IC is located to the top, so the up-down direction can be defined as a row. Additionally, the column direction and the orthogonal direction are defined as rows. In the present invention, a set of multiple CDAs included in the same column and forming the same signal line harness (SLH) is called a “CDA column.” In Figure 2, CDA101 to CDA103 are included in the same column, and signal lines 201 to 203 connected to them constitute the SLH and are therefore CDA columns. There are four CDA columns from Col1 to Col4, and one CDA column consists of three CDAs (100). As described above, the capacitance detection device of the present invention, which consists of a CDA of 20 (Row) x 15 (Column), is composed of 15 CDA columns, and each CDA column includes 20 CDAs (100). Therefore, Figure 2 is only a simple embodiment used in this specification, and in reality, the capacitance detection device of the present invention is composed of a plurality of CDAs close to hundreds to thousands.

The connecting member 300 is manufactured from Flexible Printed Circuit (FPC), Chip On Film (COF), or Tape Carrier Package (TCP), and a semiconductor IC 400 is located on one side of the connecting member 300. The joint portion 301, which is one side of the connecting member 300, is connected to the display device 10 through a bonding process using heat compression or is connected to the display device using a connector. The CDA signal line 200 originating from the semiconductor IC 400 is connected to the CDA signal line constituting each CDA column installed in the display device 10 through the junction part 301.

Line-to-line capacitance (Cd) and common electrode capacitance (Ccm) are formed in the sensing signal line and the driving signal line according to physical laws, and object capacitance (Cobj) is formed by a touch by an object in the sensing CDA 100. The semiconductor IC 400 sequentially divides the same CDA signal line 200 into a sensing signal line and a driving signal line or a non-operating CDA signal line using a time sharing method, and applies a driving voltage to the driving signal line adjacent to the sensing signal line. Afterwards, comprehensive processing is performed, such as detecting the voltage formed in the sensing signal line and calculating touch coordinates based on the charge sharing phenomenon. The connection part 302 formed on the other side of the connection member 300 is connected to a PCB (not shown), etc., and the control signal or power required by the semiconductor IC 400 is supplied through the connection part 302, and the object's Information output by the semiconductor IC 400, such as coordinates or information received from the pen, is output and transmitted to the external host CPU.

The following is an example of the present invention regarding formation of common electrode capacitance. The CDA (100) installed on the upper surface of the display device or conductor is installed face to face with the common electrode layer (Vcom Layer) of LCD or the cathode layer or conductive layer of OLED at a certain distance and a certain area. At this time, CDA Between (100) and CDA signal line and display device A common electrode capacitance with a size (Capacitance) is formed (d2 is the distance between the CDA and CDA signal lines and the common electrode layer, and s2 is the combined area of the CDA and CDA signal lines facing the common electrode layer).

Figure 3 is an example of the present invention regarding the formation of common electrode capacitance (Ccm), and the display device used was an LCD. Referring to Figure 3, CDA (100) is located on the upper surface of Color Filter Glass (5). A red/green/blue color layer (4) is located at the bottom of the color filter glass (5), and a common electrode (3), which is a conductor, is located at the bottom of the color layer (4). Since the dielectric constant of Color Filter Glass (5) and the dielectric constant of Color Layer (4) are different from each other, between CDA (100) and Color Layer (4), there is a capacitance Ccm1 based on the dielectric constant of Color Filter Glass (5), Capacitance Ccm2 based on the dielectric constant of the color layer (4) is formed in series. Therefore, the common electrode capacitance (Ccm) formed between the CDA (100) and the common electrode (3) is a composite capacitance formed by the series connection of Ccm1 and Ccm2.

Meanwhile, although not shown in Figure 3, the CDA signal line 200 connected to the CDA 100 is also a part of the CDA 100, so a common electrode capacitance is also formed between the CDA signal line 200 and the common electrode 3, The size of the common electrode capacitance (Ccm) by the CDA 100 is composed of the sum of the common electrode capacitance formed by the CDA 100 and the common electrode capacitance formed by the CDA signal line 200.

If Fig. 3 is assumed to be the case of OLED rather than LCD, symbol 5 is the encapsulation substrate, symbol 3 is the cathode, and symbol 4 is replaced by the passivation on the top of the cathode, so that Ccm1 and Ccm2 are formed the same as in the LCD embodiment. It is possible to calculate the size of Ccm using

A common electrode voltage or cathode voltage having a predetermined size is supplied to the common electrode of an LCD (or cathode of an OLED) made of a conductor, and no variation in voltage is allowed to display a normal screen. <Equation 1> and <Equation 3> (described later) of the present invention state that when a driving voltage is applied to a driving signal line, a charge according to the application of the driving voltage is supplied to the inter-line capacitance formed between the driving signal line and the sensing signal line. It expresses the transfer function of the system that detects the voltage difference due to the charge sharing phenomenon in the line capacitance, the interconnected common electrode capacitance, and the internal parasitic capacitance. Referring to <Equation 1>, the capacitance that supplies charge according to the application of the driving voltage has the characteristic that the denominator and numerator of the equation are commonly located. Therefore, the pixel common electrode voltage (Vcm) connected to the common electrode capacitance (Ccm) cannot be a driving voltage as a DC voltage, and therefore cannot be located in the numerator of <Equation 1>, which is an embodiment of the present invention, and <Equation 1> It is located only in the denominator. As a result, as the size of the common electrode capacitance increases, the level of voltage detected in the sensing signal line decreases, that is, the detection sensitivity decreases.

Figure 4 is an embodiment of the present invention relating to a capacitance detection device consisting of one CDA column and a semiconductor IC connection. Referring to Figure 4, one CDA column consists of seven CDAs, and each CDA included in the CDA column is connected to two multiplexers (430, 440) through a CDA signal line (200). The sensing signal line selection multiplexer (430, hereinafter MUX_S) is installed one at each CDA column, and is a multiplexer that selects one sensing signal line (210) among all CDA signal lines (200) in the CDA column. The sensing signal line 210 selected in the MUX_S 430 is connected to the signal processing unit 410 of the semiconductor IC 400.

Meanwhile, all CDA signal lines 200 of the CDA column are also input to the driving signal line selection multiplexer 440 (hereinafter MUX_D). MUX_D (440) is a multiplexer that selects one or more driving signal lines adjacent to the sensing signal line. If the CDA signal line connected to CDA4 in Figure 4 is selected as the sensing signal line 210 in MUX_S (430), MUX_D (440) selects one driving signal line from CDA3 or CDA5 adjacent to the sensing signal line connected to CDA4, or CDA3 A pair of driving signal lines consisting of and CDA5 may be selected, or a plurality of driving signal line pairs may be selected, such as two pairs of driving signal lines consisting of (CDA3, CDA5) and (CDA2, CDA6). One or more driving signal lines 220 selected from the MUX_D 440 are connected to the driver 420 of the semiconductor IC 400, and the driving voltage provided by the driver 420 is applied. (The fact that the number of driving signal lines 220 output from MUX_D 440 is displayed indicates that one or multiple driving signal lines can be selected.)

The following is an embodiment of the present invention regarding the configuration of the signal processing unit 410 among the components of the semiconductor IC 400. The signal processing unit 410 of the semiconductor IC 400 detects the voltage due to the charge sharing phenomenon between capacitances connected to the sensing CDA based on Equation 1. Accordingly, when the object capacitance (Cobj) is added, a change in voltage according to a change in the system configuration factor is detected and a function is performed to extract whether or not the object is touched or the coordinates of the object according to the touch.

From the plurality of CDA columns constituting one column group, one sensing signal line 210 is selected to form the same row in which processing is performed, and processing is started and completed at the same point. After processing is completed, the voltage detected by each sensing CDA is individually stored in an analog storage device such as Sample & Holder. A plurality of sensing CDA voltages stored in an analog storage device are digitized by a time sharing method using an ADC, stored in memory, and then used to determine the size of the object capacitance based on the mathematical equation of the present invention. At this time, a multiplexer is needed to sequentially select one of a plurality of Samples & Holders, and for this purpose, a multiplexer (MUX) is installed inside the signal processing unit 410.

One embodiment of the present invention is a voltage detected based on <Equation 1>, which is an initial and fixed value that is the value when there is no touch, that is, a value when not touched, and < (described later) detected in real time. Based on Equation 3, the touch is determined based on the difference in detected voltage. Therefore, the value of <Equation 1>, which is the initial value, must be recorded in memory, and is called and used for comparison with <Equation 3>, which is a real-time detection value. For this process, in the present invention, an ADC, a digital to analog converter (DAC), and a memory for recording the value of <Equation 1> are installed in the signal processing unit 410 of the semiconductor IC 400. In addition, the analog operation to extract the difference between the called voltage value based on <Equation 1>, which is a fixed value, and the real-time measured voltage value based on <Equation 3> is generally performed in a differential amplifier (Operational Amplifier), so the signal processing unit A differential amplifier (OPAMP) is installed at (410). Additionally, for analog signal processing, ADC or DAC requires a precise power source, so a reference voltage (Voltage Reference, or Voltage Ref) is required. In addition, a number of circuit components such as Sample & Holder and Decoder are required, but they are omitted for convenience.

The following is an example of the driver 420 and other functional elements of the semiconductor IC 400. The driving unit is a block responsible for applying a driving voltage to the driving signal line 220. The driving unit 420 applies a driving voltage to the driving signal line 220 using a voltage such as Vd1 or Vd2, which is a driving voltage generated by the power supply unit, or ground. Controlling the switch that supplies power and determining the turn-on time and turn-off time of the switch is performed by the CPU or logic unit of the semiconductor IC 400.

The power supply unit generates the voltage required by the driving unit 420 and generates all power supplies required by the semiconductor IC 400, such as the voltage required by Voltage Ref or the power of the CPU. The voltage generated in the power supply can be transmitted to the display device and used by the multiplexer or driver installed in the display device.

After calculating the voltage detected in the CDA, the CPU performs the function of calculating the position of the object, that is, the coordinates of the object, in the capacitance detection device of the present invention and performs timing control of the circuit elements included in the signal processing unit 410. Sometimes it happens. The Logic unit controls the CDAs included in the CDA column and column group to determine the order of the sensing signal line and driving signal line and controls the operation sequence and operation process of the ADC or DAC. This process may be performed by the CPU.

The present invention uses ADC and DAC to detect the voltage formed in the sensing CDA. Multiple ADCs or DACs may be used, but in order to reduce the area of the semiconductor IC, preferably one DAC and one ADC are used. When using one DAC and one ADC, processing is performed in a time-sharing manner for multiple column groups, and the CDA included in the CDA column in the column group selected for processing is also processed using a time-sharing method. Perform. In one embodiment, in a capacitance detection device divided into an odd column group and an excellent column group, processing of the odd column group is performed first, and then processing of the superior column group is performed alternately and repeated. Additionally, each column group is composed of multiple CDA columns, and each CDA column is composed of multiple CDAs. In one embodiment of the present invention, which detects a touch, that is, detecting object capacitance, processing is performed in all CDAs belonging to the same row of each CDA column included in the same column group, and then processing is performed in the CDA of the next row. Use the time sharing method that works. In this way, processing proceeds sequentially from the CDA of the first row to the CDA of the last row in the plurality of CDA columns included in the odd column group, and when the processing of the odd column group is completed, the first column of all CDA columns belonging to the superior column group is processed sequentially. Processing is carried out from the row to the CDA of the last row, and processing is carried out alternately and repeatedly, such as processing in odd column groups. At each stage of this processing, the ADC and DAC intervene in the processing in a time-sharing manner.

As the number of CDA columns undergoing processing increases, the number of sensing CDAs from which the ADC and DAC must extract signals increases, so the operating time of the ADC and DAC increases, causing discharge to occur in the sensing signal line of the column that is processed late, which causes the detected There is a problem that signal distortion occurs. To solve this problem, a column group, which is a collection of multiple CDA columns, is used. In one embodiment, the 20 CDA columns can be divided into two column groups, 10 columns on the left and 10 columns on the right, and are divided into an odd column group composed of odd CDA columns and an excellent column group composed of excellent CDA columns. It could be.

The following is an embodiment of the present invention regarding a method of forming line-to-line capacitance and applying a driving voltage to a driving signal line. When processing to detect object capacitance (Cobj) is performed in the CDA (102) indicated by A1 in Figure 2, the CDA signal line (202) connected to the A1 CDA (102) is the sensing signal line (210) and is connected to the MUX_S (430). After being selected, it is connected to the signal processing unit 410. The A1 CDA signal line 202 and the two neighboring CDA signal lines 201 and 203 are the driving signal lines 220, and are selected by the MUX_D 440 and then connected to the driving unit 420 of FIG. 4. At this time, capacitance between lines is formed between the sensing signal line 202 and the driving signal line 201 and the driving signal line 203.

Figure 5a is an embodiment of the present invention regarding the formation of capacitance between a sensing signal line and two driving signal lines adjacent to the sensing signal line, and is a diagram illustrating a cut section of A and A' in Figure 2, and Figure 5b is a diagram illustrating Figure 5a. This is an embodiment of the present invention regarding the equivalent circuit of. Referring to FIGS. 5A and 5B, the sensing signal line 202 and the driving signal line 201 adjacent to the right of the sensing signal line 202 are composed of two plates spaced apart at a predetermined distance (d_line). When a driving voltage is applied to the driving signal line 201, it is proportional to the opposing distance (i.e., the length of the CDA signal line) between the driving signal line 201 (not shown) and the sensing signal line 202, and the signal line width (d_sig) and signal line Mutual capacitance Cd201 is formed, which is influenced by the separation distance (d_line). Since the driving voltage is equally applied to the driving signal line 203, a mutual capacitance Cd203 is formed between the driving signal line 203 and the sensing signal line 202.

The mutual capacitance formed between the driving signal line and the sensing signal line is a physical quantity whose size changes depending on the width (d_sig) of the CDA signal line. As the width (d_sig) of the driving signal line and the sensing signal line becomes wider, the mutual capacitance Cd201 and Cd203 also increase. It has characteristics. Therefore, as in the embodiment of Cited Invention 1, if the width of the CDA signal line becomes wider as the distance increases, the expanded signal line width affects the size of the mutual capacitance.

As in the embodiment of Cited Invention 1, if the width of the CDA signal line becomes wider as the distance increases, the size of mutual capacitance, which is one of the elements constituting the line-to-line capacitance (Cd), increases as the distance increases, The size of line-to-line capacitance also increases as the distance increases. Therefore, the further away the CDA is, the larger the size of the line-to-line capacitance (Cd) located in the denominator of <Equation 1>, and the detection sensitivity of the object capacitance in the distant CDA decreases (i.e., the size of the detection voltage becomes smaller) ). In addition, a detection error occurs in which different voltages are detected for the same size of object capacitance at each CDA location, such as a difference between the voltage detected at a short-distance CDA and a far-distance CDA for the same object capacitance. there is a problem.

Meanwhile, the line-to-line capacitance (Cd) is determined by the sum of the mutual capacitance and the capacitance of the common electrodes connected in series (described later). The sensing signal line 202 faces the common electrode 3, which is a conductor, with a width of d_sig, and faces the distance equal to the thickness of the Color Filter Glass 5 and the Color Layer 4, so in Figure 3 In the same manner as the principle by which the common electrode capacitance Ccm is formed, the common electrode capacitance Ccm202 is formed between the sensing signal line 202 and the common electrode 3 or the conductor. According to the same principle, a common electrode capacitance Ccm201 is formed between the driving signal line 201 and the common electrode 3, and a common electrode capacitance Ccm203 is formed between the driving signal line 203 and the common electrode 3.

When a driving voltage is applied to the driving signal line 203 and the sensing signal line 202 is in a floating or high impedance (Hi-z) state, the charge supplied to the driving signal line 203 is Ccm203 and Ccm202 connected by the conductor 3. Since it is transmitted to the sensing signal line 202, Ccm203 and Ccm202 are equivalent to one capacitance connected in series, and this can be interpreted as one capacitance connected in parallel with the mutual capacitance Cd203. In this way, Cd2, which is an equivalent line-to-line capacitance, is formed between the sensing signal line 202 and the driving signal line 203. In the same way, a line-to-line capacitance Cd1, which is an equivalent capacitance, is formed between the sensing signal line 202 and the driving signal line 201.

if, When the same driving voltage is applied to the right driving signal line 201 and the left driving signal line 203 of the sensing signal line 202, Cd1 and Cd2 can be expressed as an equivalent circuit representing one capacitance connected in parallel, that is, the line-to-line capacitance represented by Cd in Figure 1. there is. In this way, when the driving voltage is applied to one driving signal line adjacent to the sensing signal line, or when the driving voltage is applied to a pair of driving signal lines adjacent to the sensing signal line in both directions, it is composed of multiple pairs such as two or three pairs. When applying a driving voltage to a driving signal line, it is equivalent to the fact that there is one line-to-line capacitance between the sensing signal line and the driving signal line, one side of the equalized line-to-line capacitance is connected to the sensing signal line, and the other side of the line-to-line capacitance is connected to the line-to-line capacitance. It is possible to model it by applying a driving voltage.

The line-to-line capacitance Cd1 is determined by the sum of the above-mentioned mutual capacitance and the common electrode capacitance of Ccm201 and Ccm202 connected in series. The same principle is applied to Cd2, and the mutual capacitance and the common electrode capacitance of Ccm203 and Ccm202 connected in series are determined. It is decided by the sum. Since Cd1 and Cd2 are equivalent to one line-to-line capacitance Cd connected in parallel, the mutual capacitances Cd201 and Cd202 are also equivalent to one mutual capacitance connected in parallel, and the capacitances of the two common electrodes connected in series (Ccm202/Ccm201, Ccm202/Ccm203) ) can also be equivalent to the capacitance of one common electrode connected in parallel.

Next is an embodiment of the present invention regarding the “internal parasitic capacitance (Cprs)” formed when the sensing signal line is laid out inside the semiconductor IC 400. The semiconductor IC 400 includes multiple insulating layers and multiple conductive layers stacked in a specific pattern on a substrate, and includes multiple elements with electrical characteristics and multiple wiring lines. For example, the Source Metal Layer or Gate Metal Layer, a power layer including the ground, a clock, or an analog/digital signal constitute the conductive layer (Signal Layer). These signal layers are patterned with conductive metal and separated by an insulator to avoid shorting with adjacent signal layers.

Figure 6 shows an embodiment of the present invention regarding the layer configuration of the semiconductor IC 400. Referring to Figure 6, an insulating layer 462 is disposed on the upper surface of the silicon substrate 461, and a first signal layer 463, a second signal layer 464, and a third signal layer 465 are disposed on the upper surface of the insulating layer. do. Each signal layer is patterned with a line made of metal, and the patterned line transmits signals, supplies power, or serves as a ground. In this embodiment, three signal layers are used as an example, but three or more signal layers may be used.

All elements that make up the semiconductor IC 400, such as the sensing signal line 210 and the driving signal line 220, and the signal processing unit 410 or driving unit 420, are located inside the semiconductor IC 400. It is laid out and placed at a random location among the first signal layer 463 to the third signal layer 465. At this time, the sensing signal line 210 has an opposing distance (d3) and opposing area (s3) with the semiconductor substrate 461 or “other signal lines” in the lower layer, or an opposing distance (d4) with “other signal lines” in the upper layer, and Depending on the opposing area (s4) and Two capacitances with sizes of are formed ( is the dielectric constant of each insulating layer). Since the two capacitances are connected in parallel to the sensing signal line 210, the sum of the two capacitances is equivalent to one capacitance, and the equivalent capacitance is called the IC internal parasitic capacitance (Cprs, hereinafter referred to as the internal parasitic capacitance). ). In addition, since the sensing signal line 210 forms parasitic capacitance between the “other signal lines” facing left and right, the internal parasitic capacitance is formed when the sensing signal line 210 is laid out inside the semiconductor IC 400. Includes all parasitic capacitances. The internal parasitic capacitance (Cprs) is modeled as a capacitance in which one side is connected to the sensing signal line and the voltage of "other signal lines" opposing the sensing signal line is applied to the other side. As shown in Figure 1, one side is P, which is the sensing signal line. It can be shown that a voltage Vprs is applied to one point and a predetermined voltage Vprs is applied to the other side.

The following is an embodiment of the present invention regarding a method for detecting object capacitance when adding object capacitance according to a touch. Until now, when no object capacitance was added, that is, when no touch was made, the line-to-line capacitance (Cd), common electrode capacitance (Ccm), and internal parasitic capacitance (Cprs) that make up the capacitance detection device were formed and interline. A method of applying a driving voltage to the capacitance was described, and the transfer function of the system, <Equation 1>, was derived using the modeling in Figure 1.

Referring to Figure 3, when an object 20 is located on the upper surface of the CDA 100 with an opposing area s1 and an opposing distance d1, an object capacitance Cobj is formed between the CDA 100 and the object 20, The size of object capacitance is am. The element that determines the facing distance "d1" is the protective layer 7 composed of protective glass or protective film between the CDA 100 and the object 20 (Object), and the bonding of the CDA 100 and the protective layer 7. When the transparent adhesive such as adhesive (not shown) and the object 20 do not contact the upper surface of the protective layer 7, it is an air layer. The size of the object capacitance (Cobj) is based on the opposing area of the object 20 and the CDA 100, the thickness of the air layer and the dielectric constant of the air ( ) and the thickness of the protective layer and dielectric constant of the protective layer element ( ) and the thickness of the transparent adhesive and the dielectric constant of the transparent adhesive element (Cgls) formed by It is determined by the series complex capacitance of capacitances formed from materials existing between the object and the CDA, such as the capacitance (Cadh) formed based on ).

In one embodiment, when the CDA is composed of a square shape of 4mm x 4mm and the CDA is touched with a test bar with a diameter of 3mm, the thickness of the glass as the protective layer 7 is assumed to be 0.5mm At this time, an object capacitance of between 0.5 pF and 1 pF is formed between the CAD 100 and the object 20. Since one side of the object capacitance Cobj formed on the upper surface of the CDA 100 is connected to the sensing CDA as in the embodiment of FIG. 1, one side of the object capacitance Cobj is connected to the sensing signal line 210 connected to the sensing CDA. It can be equivalent to being connected to point P, which is the equivalent circuit, and the other side is connected to Vobj, which is the potential (Voltage Level) of the object. If the object 20 is a human finger, the potential (Vobj) of the object 20 is 0V, which is the ground, and in the case of a pen, it is the voltage output from the pen.

Figure 7 is an embodiment of the present invention related to modeling of a capacitive touch input device when an object capacitor is added, and an object capacitance (Cobj) is added to the embodiment of Figure 1. <Equation 3>, the transfer function of the system to which the object capacitance (Cobj) is added, is determined as follows using the same method as the method in which <Equation 1> was derived.

<Equation 3>

(However, the voltage when the potential of point P is stabilized by application of the driving voltage of Vd1 is Vpo1, and the voltage when the potential of point P is stabilized by application of Vd2 is Vpo2)

The difference between <Equation 1>, which is the voltage at point P, which is the sensing CDA when not touched, and <Equation 3>, which is the voltage at point P, which is the sensing CDA when a touch occurs, is the object capacitance included in the denominator of <Equation 3>. (Cobj). Since the difference between <Equation 1> and <Equation 3> occurs only due to the presence and size of the object capacitance (Cobj), detecting the difference between <Equation 1> and <Equation 3> determines whether or not there is a touch caused by the object. can be confirmed, and it is possible to extract touch coordinates by an object based on the size of each object's capacitance detected in a plurality of successively neighboring CDAs.

<Equation 4> below is an equation for detecting the size of object capacitance (Cobj) and is defined as <Equation 1> - <Equation 3>.

<Equation 4>

<Equation 1> - <Equation 3> =

<Equation 1> is the voltage when there is no object, and processing is performed on the premise that there is no object when a product such as a mobile phone or laptop is powered on, and is the voltage detected for each CDA and is the reference voltage stored in memory. <Equation 3> is the voltage detected by processing the CDA according to a predetermined sequence (for example, once every 10 ms at 100 Hz), and when a touch occurs, a difference from <Equation 1> occurs. . When the voltage for each CDA detected in real time is transmitted to the CPU or Logic, the CPU or Logic analyzes the difference with <Equation 3> based on <Equation 1> and extracts whether or not the object is touched and the object coordinates.

The size of the mutual capacitance or common electrode capacitance that constitutes the inter-line capacitance is directly proportional to the length of the CDA signal line. Since the length of the CDA signal line cannot be changed, the length of the CDA signal line is not a consideration in the present invention. The variable of the present invention is the line width of the CDA signal line. It will be explained below that even if the line width is reduced, there is no factor that deteriorates compared to Cited Invention 1. In addition, the line width of the sensing signal line and the driving signal line is reduced, that is, the CDA signal line. The areas that are improved due to line width reduction are described below.

In an RC circuit, the time constant is the product of resistance and capacitance, and is the time during which the driving voltage applied to the RC circuit shows 63.2% saturation in the resistance. After about 5 times the time constant, the applied initial voltage is mostly saturated, so it is ideal to detect the signal (through resistance) at this time, but sensing is sequentially selected from multiple column groups and CDA columns included in each column group. Since it takes a lot of sensing time considering CDA, the present invention detects a signal at about 3 times the time constant, which shows a saturation rate of about 98% of the applied voltage. In other words, the time constant is determined by considering the line resistance of the sensing signal line and the size of the complex capacitance due to the line-to-line capacitance/common electrode capacitance/internal parasitic capacitance connected to the sensing signal line, and the time constant is determined by applying the driving voltage to the driving signal line. After a time multiple of 3 has elapsed, the voltage is detected in the sensing signal line 210 based on <Equation 1> or <Equation 3>. In one embodiment, when the line resistance of the sensing signal line 210 is 100㏀ and the capacitance between lines is 30pF, the time constant is 3ms, so the voltage detected in the sensing signal line 210 9ms after applying the driving voltage to the driving signal line is the size at which 98% of the driving voltage applied to the driving signal line 220 is saturated.

When the length of the CDA signal line is "l" and the line width is "d_sig", the area "s2" of the CDA signal line is determined as s2=d_sig*l. The line resistance of the CDA signal line is R = And the size of the common electrode capacitance is, (F) (d2 is the opposing distance between the CDA signal line and the common electrode or conductor). Assuming that the line width (d_sig) and opposing length (l) of the sensing signal line 202 and the driving signal lines 201 and 203 in FIG. 5A are the same, the size of the common electrode capacitance due to the series connection of Ccm201 and Ccm202 is and by serial connection of Ccm203 and Ccm202.

The size of the common electrode capacitance is also the same. am. As mentioned above, in the line-to-line capacitance, the size of the common electrode capacitance is the size of the common electrode capacitance by the series connection of Ccm201 and Ccm202, and the parallel connection of the common electrode capacitance by the series connection of Ccm203 and Ccm202. , the size of the line-to-line capacitance by the common electrode capacitance is, + = am. Accordingly, RC1, the first time constant of the sensing signal line due to the capacitance of the common electrodes connected in series among the inter-line capacitances, is determined as shown in Equation 5 below.

<Equation 5>

RC1=

Looking at <Equation 5>, which is the calculation result of RC1, the first time constant of the sensing signal line, since the signal line width (d_sig) is not included in the formula, the first time constant does not change due to the size change of the signal line width. Therefore, it can be seen that there is an error in the embodiment of cited invention 1, which attempts to reduce the size of the line resistance by widening the signal line width and thereby reduce the size of the time constant. In other words, there is no need to widen the line width of the signal line to improve detection speed.

The inter-line capacitance formed in the sensing signal line is the common electrode capacitance obtained by connecting the common electrode capacitance of both the driving signal line and the sensing signal line in series, and the mutual capacitance (Cd201, Cd203) formed between the driving signal line and the sensing signal line. It is obtained as a sum.

In the equation that determines RC2, the second time constant due to the mutual capacitance among the line-to-line capacitances, the signal line width "d_sig" and the separation distance "d_line" act as variables (the effect on the separation distance will be explained later). Referring to the equation regarding the size of the mutual capacitance of two parallel plate conductors, it is known that the change in the time constant RC2 occurs by about 20 to 40% with respect to the change in the line width “d_sig” of the CDA signal line. In one embodiment, when the line width "d_sig" of the driving signal line and the sensing signal line is expanded to "2d_sig" and a 100% change occurs, the mutual capacitance RC2 increases by 20 to 40%. These results indicate that the embodiment of Cited Invention 1, which attempts to reduce the time constant by widening the signal line width, actually further increases the time constant, resulting in a further delay in signal detection.

Next is another problem caused by the increase in signal line width, which is an embodiment of cited invention 1. Referring to <Equation 1> or <Equation 3>, the common electrode capacitance is located in the denominator of the equation. As in Cited Invention 1, if the signal line width increases as the distance increases, the size of the common electrode capacitance increases as the distance increases, and this causes the problem that detection sensitivity decreases as the distance increases due to the size of the same object capacitance. (For reference, Cited Invention 1 uses different object sizes for near and far CDA, making an error in that the objects are not the same size.)

In the CDA column of the present invention, since the time constants of rows located near and far are different from each other, the time at which the driving voltage saturates the sensing signal line is different for each row. In order to reduce processing time, the processing time may be different for each row, but considering the time for discharging after storing the signals captured from the sensing signal line in the sample end hold (Sample & Holder), the same processing time is allocated to all rows. (When processing one row, the voltage detected in the previous row is processed using S&H and ADC, so if the time stored in S&H changes, the discharge time may change, causing an error in the processed signal.) . At this time, if you set the processing time for each row based on the time constant of the CDA located at the farthest distance, there is a problem that the closer the distance, the more processing time is lost and the total processing time increases, which slows down the touch response speed and increases current consumption. Conversely, if the processing time is set based on the time constant of the short-distance CDA, there is a problem in the long-distance CDA that detection errors occur due to detection of incomplete signals due to signal delay. Considering this, an appropriate row position is selected and the processing time is set based on the time constant there. At this time, in the long-distance CDA, signal delay due to the time constant still exists, so to improve the performance of the system, the long-distance CDA signal line is set. The time constant should be reduced as much as possible.

As discussed above, the following five problems were created due to the configuration of the embodiment of Cited Invention 1, which widens the signal line width as the distance increases.

1) Missing object detection due to dead zone

2) Touch coordinate calculation error due to dead zone

3) Inconsistency in signal detection between far and near CDAs due to increase in common electrode capacitance of long distance sensing signal line and increase in mutual capacitance.

4) Decreased sensitivity in long-distance CDA due to increase in common electrode capacitance and mutual capacitance of the long-distance sensing signal line.

5) Increased processing time due to increase in second time constant

In order to improve this problem, the present invention reduces the CDA signal width and layouts it in various ways, which will be described later.

According to Equation 5, which represents the first time constant, the signal detection speed in the long-distance CDA is not affected even if the signal line width is narrowed. One embodiment of the present invention layouts the line width of the long-distance signal line as narrow as possible based on Equation 5. Reducing the long-distance CDA signal line width reduces the size of the common electrode capacitance, thereby improving problems 3) and 4 above. In addition, when the CDA signal line width is narrowed, the size of mutual capacitance decreases and the second time constant becomes faster, thereby improving problems 3) to 5). Additionally, as the CDA signal line width narrows, the SLH width also narrows compared to the embodiment of Cited Invention 1, which means that the dead zone narrows, thereby improving problems 1) and 2) above.

According to the analysis of the first and second time constants of the line-to-line capacitance, it is desirable to narrow the signal line width as much as possible, and for this purpose, the following method can be applied.

* Layout method of CDA signal lines

1-1) In any CDA column, the CDA signal linewidth located far away is the same as the nearby CDA linewidth.

1-2) In the CDA column, for a CDA group that bundles a plurality of neighboring CDA signal lines, the width of the CDA signal lines constituting the CDA group is the same, and the width of the short-distance CDA signal lines not included in the CDA group is the same.

1-3) All CDA signal lines in the CDA column have the same line width.

2) In the CDA column, for a CDA group that bundles a plurality of neighboring CDA signal lines, the CDA signal line width within the same CDA group is the same, but is laid out with different CDA line widths in different CDA groups.

3) When the capacitance detection device of the present invention is installed on the upper surface of the display device, the CDA signal line width facing the pixel is formed to be narrower than the width of the sub pixel constituting the pixel.

4) When the capacitance detection device of the present invention is installed on the upper surface of the display device, the CDA signal line width facing the pixel is formed to be narrower than the width of the pixel.

5) When the capacitance detection device of the present invention is installed on the upper surface of the display device, the CDA signal line width facing the pixel is set based on the sub pixel pitch (hereinafter SPP) of the pixel. In one embodiment, the CDA signal line width is installed as a positive integer multiple of SPP, such as 1SPP, 2SPP, or 3SPP, or as a positive real multiple of SPP, such as 0.5SPP, or 1.5SPP, 2SPP, 2.5SPP.

6) When the capacitance detection device of the present invention is installed on the upper surface of the display device, the CDA signal line width facing the pixel is set based on the Pixel Pitch (hereinafter referred to as PP) of the pixel. In one embodiment, the CDA signal line width is installed as a positive integer multiple of SPP, such as 1PP, 2PP, or 3PP, or as a positive real multiple of PP, such as 0.5PP, or 1.5PP, 2PP, 2. 5PP.

In the above layout method 1-1), under the condition that the CDA signal line width located at a distance from any CDA column is the same as the CDA line width adjacent at a short distance, the signal line width becomes wider as the distance increases, as in the embodiment of cited invention 1. The condition is lifted, and it becomes a condition where the far-distance signal line width can be the same as the near-distance signal line width.

In this context, remoteness should be understood as the most distant or distant part. Additionally, long distance is a concept of relative distance from other signal lines being compared. In one embodiment, with respect to the CDA located in Row9 and the CDA located in Row10, the CDA located in Row9 is located farther away than the CDA located in Row10.

While the layout method 1-1) specifies layout conditions for two adjacent signal lines, layout method 1-2) specifies layout conditions for one signal line and one CDA group. In one embodiment, when one CDA group is set to Row1 to Row10, this means that the CDA line width of Row1 to Row10 of the CDA group is the same as the CDA signal linewidth of Row11 or Row 15 in the short distance. In one embodiment, when the line width of Row11 is the same as the line width of the CDA group constituting Row1 to Row10, it may be unclear whether Row11 is included in the CDA group constituting Row1 to Row10. Therefore, for one CDA group composed of a plurality of CDA signal lines, if the width of the CDA signal lines is the same, it can be considered to correspond to layout method 1-2).

The above layout method 1-3) means that all CDA signal lines included in the CDA column are laid out with the same line width. As discussed in the first and second time constants, it is desirable to lay out the signal line width under the narrowest signal line width conditions among process conditions and conditions to avoid the moiré phenomenon. By a layout method based on 1-3), all CDA signal lines of the capacitance detection device of the present invention formed of a plurality of column groups are configured with the same line width.

The layout method 2) is a case where the CDA is divided into a plurality of CDA groups within the CDA column, and the same signal line width is used within the CDA group, but is different from the CDA line width used in other CDA groups. In one embodiment, in a CDA column composed of 25 CDAs, Row1 to Row5 becomes CDA Group 1, Row6 to Row10 become CDA Group 2, and CDA Group 3 and CDA Group 4 are formed in the same manner, with the last Row21 to Row25. constitutes CDA Group 5. At this time, since CDA group 1 is located at the farthest distance, the Row1 CDA signal line completely connects the longitudinal start and end points of the capacitance detection device of the present invention with a signal line. When the capacitance detection device of the present invention transmits and receives necessary information with a pen, CDA group 1 can be used as a transmission antenna. At this time, the CDA signal lines of Row1 to Row5 of CDA Group 1 must be configured with a predetermined line width to provide an appropriate area required by the opposing pen.

In addition, the CDA signal lines of Row6 to Row10 belonging to CDA Group 2 serve as antennas that receive signals from the pen and are composed of a predetermined CDA signal line width suitable for antenna engineering, but the CDA signal line width of CDA Group 1 or the CDA signal line width belonging to another CDA group It may have a different signal line width. CDA Group 3 to CDA Group 5 may also be laid out with different signal line widths or all configured with the same line width depending on the characteristics of the product.

Next, the layout method 3) will be described using Figure 8 as an example. Figure 8 shows an embodiment of the present invention regarding the layout of CDA signal lines installed on the upper surface of a pixel of a display device. The display device is based on LCD, but the same applies to OLED display devices.

The display device 10 is an LCD with an RGB stripe structure, and a portion of the SLH constituting an arbitrary CDA column among the capacitance detection devices of the present invention installed on the upper surface of the display device is shown. The display device is composed of a set of pixels consisting of three sub-pixels, including Red, Green, and Blue. The BM (Black Matrix) by the gate signal line in the horizontal direction between the sub pixels and the BM by the source signal line in the vertical direction are installed on the opposing color filters, and are shown as thick lines between the sub pixels in Figure 8. The six CDA signal lines 200, which are part of the many CDA signal lines that make up the SHL, are laid out from the far top to the near bottom (based on a semiconductor IC installed on the bottom, not shown).

The CDA signal line 200 is arranged diagonally in a zigzag shape to avoid moiré phenomenon with sub pixels, and maintains a constant opposing area occupancy between the CDA signal line and sub pixel, but each R/G/B sub pixel has an opposing area. It has a unique opposing area share with the CDA signal line. In one embodiment, the area facing the CDA signal line disposed on the upper surface of the Red Sub Pixel and the Red Sub Pixel is both 55%. Also, it is 45% for Green Sub Pixel and 65% for Blue Sub Pixel. Therefore, in the embodiment of Figure 8, the opposing areas of the Red/Green/Blue Sub Pixel and the CDA signal line are displayed as the same, but in reality, they may differ for each sub pixel.

If the sub-pixel pitch is large due to the low resolution of the display device, such as XGA or HD, one or more CDA signal lines may be placed inside the sub-pixel. In one embodiment, when the pitch of the pixel is 210um(H) Since 25 Sub Pixels are required to lay out 25 CDA signal lines (which make up a column), the width of the area where the SLH width is widest is 1.75mm. Assuming that the CDA is composed of a square and has an area of 4mm In order to solve this problem, the present invention arranges a plurality of CDA signal lines, such as two or three, facing one sub pixel. If two CDA signal lines are placed in one sub-pixel, 12.5 sub-pixels are required to place 25 CDA signal lines. At this time, the width of the widest part of the SLH is 0.875mm, which is reduced by half compared to 1.75mm.

As such, in the present invention, when the display device is low resolution, one or more CDA signal lines must be placed opposite the sub pixel, so the CDA signal line width must be smaller than the pitch of the sub pixel.

Next is a description of the layout method 4). In high-resolution, high-end products such as 400PPI or 500PPI display devices, the pitch of the sub pixel may be less than 20um. If the process capability for manufacturing a CDA signal line exceeds 20um (considering the yield), it is impossible to install one CDA signal line opposite to one sub pixel as in the case of layout example 3) above. In this case, one CDA signal line must be laid out facing each of two sub-pixels, or one CDA signal line must be laid out facing a pixel consisting of three sub-pixels. Layout method 4) applies when the CDA signal line width is not larger than one pixel when the display device is high resolution.

Next is an explanation of layout method 5).

Some display devices have different sub-pixel pitches, such as red, green, and blue. In particular, the pitch of the blue sub-pixel is often small. To avoid moiré, the CDA signal line width or signal line pitch placed for each sub-pixel may be laid out differently for each sub-pixel. As an example, in the case of a low-resolution display device, methods such as 0.6 SPP (Sub Pixel Pitch) for Red Sub Pixel, 0.7 SPP for Green Sub Pixel, and 0.8 SPP for Blue may be used. Additionally, in the case of high resolution, methods such as 1.2SPP for Red Sub Pixel, 1.3 SPP for Green Sub Pixel, and 1.45SPP for Blue can be used. The multiplier varies from sub-pixel to sub-pixel, but may be the same for any two sub-pixels or for all sub-pixels. A multiple is a positive integer or a positive real number. As in layout method 2), multiples may be determined differently for different CDA groups. In one embodiment, the multiplier is set to 1 in some CDA groups. Additionally, in another CDA group adjacent to a CDA group whose multiplier is set to 1, the multiplier may be set to 2 or 1.2.

Next is a description of the layout method 6). In a high-resolution display device, if the sub-pixel pitch is small and the processing capability for the CDA signal line does not reach the pixel pitch, which is the sum of the sub-pixels, the line width of the CDA signal line must be determined as a multiple of the pixel. Pixel pitch (hereinafter referred to as PP) is the width including the visible area and BM of the pixel. In one embodiment, 2PP means that the CDA signal line width is twice the width of the pixel pitch. As in layout method 2), multiples may be determined differently for different CDA groups. In one embodiment, the multiplier is set to 1 in some CDA groups. Additionally, in another CDA group adjacent to a CDA group whose multiplier is set to 1, the multiplier may be set to 2 or 1.2.

The above layout methods 1-1) to 6) may be used singly or may be used in combination. As an example. Method 2) and method 3) may be used simultaneously, or methods 1-2), 2), and 3) may be used simultaneously. In another embodiment, for 25 CDAs constituting one CDA column, method 1-1) is applied to the near part and method 1-2) is applied to the far part for 12 CDAs in the near part and 13 CDAs in the far part. It is possible to lay out the line width narrowly for all or part of the CDA signal line by applying various combinations.

Next is an explanation of the space between CDA signal lines. As described above, mutual capacitance is formed when the sensing signal line and the driving signal line are spaced apart and face each other, and at this time, the distance (d_line) between the two signal lines affects the size of the mutual capacitance. Whenever the separation distance between two signal lines is reduced by 100%, the mutual capacitance increases by about 20% to 30% (under certain conditions).

The CDA signal line width (d_sig) and separation distance (d_line) combined are called the pitch of the CDA signal line and are shown in Figures 5a and 8. Since SLH is determined by the sum of multiple signal line widths and separation distances, the width of the dead zone decreases as the separation distance becomes narrower. Since narrowing the separation distance does not have a significant impact on the size of mutual capacitance, in order to minimize the area of the dead zone, the separation distance is also minimized, but set as follows according to the relationship with the CDA signal line width.

The most desirable method is to keep the CDA signal line width and separation distance the same. When the separation distance between CDA signal lines is the same as the width of the CDA signal line installed on the upper surface of the sub pixel and has the same shape as the CDA signal line (as in the embodiment of Figure 8), moiré due to refraction or interference of light occurs regularly in the CDA signal line and the separation space. Occurs. At this time, by adjusting the diagonal angle of the CDA signal line or the opposing area between the CDA signal line and the sub pixel, it is possible to remove moire from the entire display device with one recipe. If the width of the CDA signal line and the width of the separation distance are different, moiré caused by the CDA signal line and moiré caused by the separation space may occur separately, so moiré cannot be removed with one recipe to avoid moiré. Multiple recipes are required. There is a difficulty in avoiding moiré.

In order to minimize the width of the dead zone due to SLH, the separation distance can be made narrower than the CDA signal line width, and this method can be applied to CDA signal lines located nearby. Because the length of the CDA signal line located at a short distance is short, the size of the inter-line capacitance and the size of the common electrode capacitance are smaller than those of the CDA signal line located at a long distance. Therefore, even if the time constant increases as the separation distance decreases, it is lower than the time constant of the CDA located at a distance, so it does not affect the stability of the detected signal or the operation of the system.

In this way, the present invention makes it possible to minimize the area of the dead zone by making the separation distance of CDA signal lines located in close proximity narrower than the CDA signal line width.

The above-described CDA signal line layout methods 1-1) to 6) were explained based on the CDA signal line width, but “CDA signal line width” can be replaced with “CDA signal line pitch.” In other words, the CDA signal line width can be replaced by the CDA signal line width and the separation distance. Accordingly, in this specification, it is possible to clearly understand the configuration of the SLH consisting of the CDA signal line and the CDA signal line pitch, which is the separation distance. As an example, in the embodiment of layout method 3), “CDA signal line width is smaller than Sub Pixel” can be replaced with “CDA signal line Pitch” is smaller than Sub Pixel.

The foregoing description of the present invention is for illustrative purposes, and those skilled in the art will understand that the present invention can be easily modified into other specific forms without changing the technical idea or essential features of the present invention. will be.

Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. For example, individual elements that are described as a single type may be implemented as a comprehensive device by combining them, and similarly, a comprehensive device may be implemented as a combination of individual elements that are not described. The scope of the present invention is indicated by the patent claims described later, and all changes or modified forms derived from the meaning and scope of the claims and their equivalent concepts should be construed as being included in the scope of the present invention.

3: Common electrode or conductor
4: Color Layer
5: Color Filter Glass
7: protective layer
10: display device
20: Object
100: CDA (Capacitor Detection Area)
200: CDA signal line
201: Long-distance CDA signal line
202: Medium distance CDA signal line
203: Short-distance CDA signal line
210: Sensing signal line
220: Driving signal line
300: Connecting member
301: joint
302: connection part
400: Semiconductor IC
410: signal processing unit
420: driving unit
430: Sensing signal line selection multiplexer
440: Driving signal line selection multiplexer
461: Substrate
462: Insulator
463: First signal layer
464: Second signal layer
465: Third signal layer
466: Passivation

Claims (9)

A capacitance detection area (CDA) installed on the top of the display device and composed of a conductor and an independent area;
CDA signal line connected to the CDA;
When the CDA signal line is installed on the upper surface of the pixel constituting the display device and faces the pixel, the line width of the CDA signal line or the pitch (Ptich) of the CDA signal line including the space between CDA signal lines and the line width of the CDA signal line is the pixel (Pixel). A capacitance detection device characterized in that it is formed narrower than the width of
According to paragraph 1,
CDA column composed of a plurality of the above CDAs; and
In the CDA column, a CDA group consisting of a plurality of neighboring CDA signal lines; and
A capacitance detection device characterized in that the line width of the CDA signal line constituting the CDA group is the same as the line width of the CDA signal line neighboring in a short distance.
According to paragraph 1,
A capacitance detection device characterized in that all CDA signal lines constituting the CDA column have the same line width.
According to paragraph 2,
A capacitance detection device characterized in that the line width of the CDA signal line within the same CDA group is the same, and in other CDA groups, the line width of the CDA signal line is laid out with different sizes.
According to paragraph 2,
In the CDA column, the line width of the CDA signal line located at a distance based on the position of the semiconductor IC is the same as the line width of the CDA signal line located at a short distance based on the position of the semiconductor IC.
According to paragraph 1,
A capacitance detection device characterized in that the line width of the CDA signal line or the pitch (Ptich) of the CDA signal line is determined as mx SPP based on the Sub Pixel Pitch (hereinafter, SPP) constituting the pixel (where m is a positive is an integer or positive real number)
According to paragraph 1,
The line width of the CDA signal line or the pitch (Ptich) of the CDA signal line is a capacitance detection device characterized in that nxPP is determined based on the pitch (Pixel Pitch, hereinafter PP) of the pixel (where n is a positive integer or It is a positive mistake)
According to paragraph 1,
A capacitance detection device characterized in that the line width of the CDA signal line and the width of the space between the CDA signal lines are the same.
According to paragraph 1,
At the short distance, the width of the space between the CDA signal lines is narrower than the line width of the CDA signal line.