KR20240017733A - Semiconductor package including memory die stacks having clock signal shared by lower and upper bytes - Google Patents

Abstract

A semiconductor package including a memory die stack with a clock signal shared for lower and upper bytes is disclosed. Each of the plurality of memory dies constituting the memory die stack of the semiconductor package is a memory system including a first clock circuit and a memory die that generate a read clock signal for the lower byte and upper byte constituting the data width of the memory die. It includes a plurality of first die bond pads corresponding to the number of ranks, and each of the plurality of first die bond pads is set for each rank. The first clock circuit is connected to a die bond pad corresponding to the rank to which the memory die belongs among the plurality of first die bond pads.

Description

Semiconductor package including memory die stacks having clock signal shared by lower and upper bytes}

The present invention relates to a semiconductor device, and more particularly, to a semiconductor package in which memory chips having a clock signal shared between lower and upper bytes are stacked.

As electronic devices include a plurality of semiconductor integrated circuits (or semiconductor chips), their hardware configuration is becoming more complex. Electronic devices widely use DRAM (Dynamic Random Access Memory) as operating memory or main memory to store data or instructions used by the host and/or perform computational operations, and as a storage medium. Use a storage device. The storage device includes a plurality of non-volatile memories (NVMs).

The power consumption of electronic devices is critical. Memory system power is an important element of the power budget of electronic devices and accounts for a significant portion of overall system power. Memory systems include memory having large amounts of dynamic random access memory (DRAM) implemented on multiple individual dynamic random access memory (DRAM) chips. Some electronic devices may include multiple DRAM chips and memory controllers. The memory controller may partition individual DRAM chips among multiple DRAM chips into logical and/or physical groups in terms of power control, addressing/memory access, etc. For example, multiple DRAM chips may be included in one of multiple ranks, which may be divided into a target rank and a non-target rank. The target rank may include a DRAM chip that performs memory access according to a memory request, and the non-target rank may include a DRAM chip on which no memory access is performed.

Low Power Double Data Rate Synchronous DRAM (LPDDR SDRAM) is mainly used in mobile electronic devices such as smart phones, tablet PCs, and ultra books. As the capacity of mobile operating systems (OS) increases to support multi-tasking operations performed in mobile electronic devices, mobile electronic devices with lower power consumption characteristics, high-speed operation performance, and high capacity are desired. Accordingly, in order to provide highly integrated and high-capacity LPDDR SDRAM, a multi-chip package (MCP) that stacks a plurality of memory dies in one package is used.

In an MCP where a plurality of memory dies are stacked, the memory dies are connected to each other through a wire bond scheme and to the package substrate, thereby implementing an electrical connection structure. It would be beneficial to improve the signal characteristics and/or performance of MCP semiconductor devices if the wire bond connections of the memory die stack could be optimized while maintaining the functionality of the shared clock signal for the lower and upper bytes specified in the LPDDR SDRAM. .

An object of the present invention is to provide a semiconductor package including memory die stacks with a clock signal shared for lower and upper bytes.

A memory die according to embodiments of the present invention includes a first clock circuit that generates a read clock signal for the lower byte and the upper byte constituting the data width of the memory die; and a plurality of first pads corresponding to the number of ranks of a memory system in which the memory die is included, wherein each of the plurality of first die bond pads is configured to be connected to a rank to which the memory die belongs, and the first A clock circuit is connected to a corresponding rank die bond pad among the plurality of first die bond pads.

A semiconductor package according to embodiments of the present invention includes a package substrate; a memory die stack mounted on the package substrate and stacking a plurality of memory dies, the plurality of memory dies being composed of first rank memory dies and second rank memory dies; first wire bonds connecting the memory dies of the first rank; and second wire bonds connecting the memory dies of the second rank. Each of the plurality of memory dies includes: a first clock circuit that generates a read clock signal for the lower byte and upper byte constituting the data width; a first die bond pad transmitting the first rank read clock signal; and a second die bond pad transmitting a read clock signal of the second rank, wherein the first clock circuit transmits the read clock signal of the rank to which the memory die belongs among the first and second die bond pads. It is connected to the die bond pad that delivers.

A semiconductor package according to embodiments of the present invention includes a package substrate; and a memory die stack mounted on the package substrate and stacking a plurality of memory dies, wherein the plurality of memory dies are comprised of a plurality of ranks; Each of the plurality of memory dies includes a clock circuit that generates a read clock signal for the lower byte and the upper byte constituting the data width; and a plurality of first die bond pads corresponding to the number of the plurality of ranks, wherein each of the plurality of first die bond pads is configured to be connected to a rank to which the corresponding memory die belongs, and the first clock circuit is It is connected to a corresponding rank die bond pad among the plurality of first die bond pads.

According to the semiconductor package of the present invention, the memory die includes die bond pads on which a read clock signal for each rank is loaded, and a read clock circuit shared by the lower and upper bytes of each memory die stack is used to read the rank to which the memory die belongs. By connecting to the die bond pad where the clock signal is carried and connecting the corresponding ranks between the memory die stacks with wire bonds, the signal characteristics and/or performance of the semiconductor package can be improved. Additionally, by connecting die bond pads carrying read clock signals for each rank to the read clock circuit through a redistribution layer, it is possible to easily configure the memory die without performing a separate process.

1 is a block diagram illustrating an electronic device according to embodiments of the present invention.
FIG. 2 is a diagram for explaining a semiconductor package according to exemplary embodiments of the present invention.
3 and 4 are diagrams illustrating a memory die and a semiconductor package described as comparative examples of the present invention.
5 to 6B are diagrams explaining semiconductor packages according to embodiments of the present invention.
7 is a diagram illustrating a semiconductor package according to embodiments of the present invention.
8 is a diagram illustrating a semiconductor package according to embodiments of the present invention.
Figure 9 is a diagram explaining a memory system according to embodiments of the present invention.
FIGS. 10A to 10D are diagrams explaining the memory chip configuration for each rank in FIG. 9 .
11 is a block diagram of a system for explaining an electronic device including a semiconductor package according to embodiments of the present invention.

1 is a block diagram illustrating an electronic device 100 according to embodiments of the present invention.

Referring to FIG. 1 , the electronic device 100 may include a processor 110 and a memory system 120. The electronic device 100 may be implemented to be included in a personal computer (PC) or a mobile electronic device. Mobile electronic devices include laptop computers, mobile phones, smartphones, tablet PCs, personal digital assistants (PDAs), enterprise digital assistants (EDAs), digital still cameras, digital video cameras, and PMPs. Portable Multimedia Player, PND (Personal Navigation Device or Portable Navigation Device), handheld game console, Mobile Internet Device (MID), wearable computer, Internet of Things (IoT) It can be implemented as a device, an Internet of Everything (IoE) device, or a drone.

The processor 110 is a primary component of the electronic device 100 that processes and manages instructions, and is mainly responsible for executing an operating system and applications. Additionally, processor 110 allows the workload to be distributed across multiple computing entities for parallel processing to solve complex tasks or tasks. Processor 110 is a functional block configured to execute one or more machine-executable instructions or pieces of software, firmware, or a combination thereof. The processor 110 may be implemented using hardware that performs calculations and other operations (eg, control operations, configuration operations, etc.) in the electronic device 100, that is, various circuit elements and devices.

The processor 110 may be implemented as an integrated circuit (IC), system on chip (SoC), application processor (AP), mobile AP, chipset, or a set of chips. As an example, the processor 110 may be a semiconductor device that performs a memory control function and may include a memory controller 112. The processor 110 may further include RAM, a central processing unit (CPU), a graphics processing unit (GPU), and/or a modem.

The memory system 120 is composed of functional blocks that perform operations as a memory (e.g., “main memory”) for the electronic device 100, and may be implemented with, for example, 6th generation LPDDR SDRAM (LPDDR6 SDRAM). . LPDDR6 SDRAM includes memory circuitry and can handle access to data and instructions stored in the memory circuitry and perform other control or configuration operations. LPDDR6 SDRAM is a “dynamic” memory circuit. Dynamic memory circuits store information (e.g., bits of information such as data, instructions, etc.) using circuit elements such as capacitors that lose charge over time due to leakage and/or other charge loss mechanisms. A DRAM cell consisting of one transistor and one storage capacitor exhibits variable data retention characteristics, and periodically performs a refresh operation to restore DRAM cell data to prevent loss of stored information.

Memory system 120 may include multiple memory dies 241 to 244. For example, each of the memory dies 241 to 244 includes a memory cell array (MCA), and the memory cell array (MCA) includes a number of bank groups (BG0 to BG3) including a number of banks (BANK0 to BANK3). It includes, and each bank (BANK0 to BANK3) may be composed of a plurality of memory cell rows (or pages). The example memory cell array (MCA) configuration shown in FIG. 1 does not represent or imply any limitations to the present disclosure. For example, the memory cell array (MCA) includes 4 bank groups and includes 4 banks per bank group, or 8, depending on the 16, 12, 8, 6, 4 data (DQ) signal configuration implemented in the single channel 130. It may contain 10 banks or 16 banks.

The plurality of memory dies 240 - 244 may include, for example, LPDDR6 SDRAM, and may be logically and/or physically divided into at least two ranks. In this embodiment, the memory system 120 is shown as having a two-rank structure, but it is not limited to this and may have various rank structures. In the following embodiments, for convenience of explanation, the memory dies 242 and 244 may be referred to as the first rank 121 and the memory dies 241 and 243 may be referred to as the second rank 122. . Additionally, the terms first and second ranks 121 and 122 and RANK0 and RANK1 may be used interchangeably.

Memory controller 112 of FIG. 1 is a functional block that manages, controls, and otherwise handles interactions between processor 110 and memory system 120. For example, memory controller 112 may perform memory accesses (i.e., reads, writes, etc.) on behalf of processor 110, configuration and control operations, and/or other operations with respect to memory system 120. You can. The memory controller 112 may communicate with the memory system 120 through a channel 130. Channel 130 is a command/address signal line that transmits a command/address (CMD/ADDR, hereinafter referred to as “CA”), and data that transmits data (DQ[12:0], hereinafter referred to as “DQ”). It may be implemented as a bus including clock signal lines that transmit data clock signals (WCK, WCKB, hereinafter referred to as “WCK”) and read clock signals (RDQS, RDQSB, hereinafter referred to as “RDQS”). The channel 130 transmits clock signal lines transmitting clock signals CK and CKB and chip selection signals CS0 and CS1 for distinguishing the first and second ranks 121 and 122, respectively. It may further include signal lines. The WCK and WCKB clock signals are complementary, the RDQS and RDQSB clock signals are complementary, and the CK and CKB clock signals are complementary. Clock signals are complementary if the rising edge of the first clock signal occurs simultaneously with the falling edge of the second clock signal and the rising edge of the second clock signal occurs simultaneously with the falling edge of the first clock signal. The first and second ranks 121 and 122 may share clock signal lines, command/address signal lines, and data lines of the channel 130.

2 is a diagram for explaining a semiconductor package according to exemplary embodiments of the present invention. FIG. 2 is an edge view of a semiconductor package 200 implementing the memory system 120 of FIG. 1 .

Referring to FIG. 2, the semiconductor package 200 shows a memory die stack 240 mounted on a package substrate 220. In the memory die stack 240, memory dies 241, 242, 243, and 244 are stacked in a continuous offset stepped configuration. In the following embodiments, for convenience of description, the semiconductor package 200 may be referred to as a multi-chip package. The terms semiconductor package and multi-chip package may be used interchangeably.

The memory dies 241, 242, 243, and 244 may include die bond pads 250 aligned along the edges of each of the memory dies 241, 242, 243, and 244. The die bond pads 250 of each of the memory dies 241, 242, 243, and 244 may be electrically connected to the contact pad 230 of the package substrate 220 through wire bonds 252. The numbers of die bond pads 250 and wire bonds 252 are shown for simplicity, and it can be appreciated that more die bond pads 250 and wire bonds 252 than shown may be included. will be. Wire bonds 252 may connect corresponding die bond pads 250 to establish an interface connection between each memory die 241, 242, 243, and 244. The term “pad” refers broadly to an electrical interconnection to an integrated circuit and may include, for example, pins or other electrical contact points on the integrated circuit.

The package substrate 220 may include a plurality of conductive layers separated by an insulating layer and through-silicon vias (TSVs) therein. The conductive layers and through electrodes of the package substrate 220 may be connected to the external terminals 210 of the semiconductor package 200. In exemplary embodiments, the external terminals 210 of the semiconductor package 200 may be implemented as package balls or leads. The semiconductor package 200 includes, for example, Package On Package (PoP), Ball Grid Arrays (BGA), Chip Scale Package (CSP), Plastic Leaded Chip Carrier (PLCC), Plastic Dual In-line Package (PDIP), Die in Waffle Pack, Die in Wafer Form, COB (Chip On Board), CERDIP (CERamic Dual In-line Package), MQFP (Metric Quad Flat Package), TQFP (Thin Quad FlatPack), Small Outline (SOIC), SSOP ( Implemented in packages such as Shrink Small Outline Package), TSOP (Thin Small Outline), SIP (System In Package), MCP (Multi Chip Package), WFP (Wafer-level Fabricated Package), WSP (Wafer-level processed Stack Package), etc. It can be.

3 and 4 are diagrams illustrating a memory die and a semiconductor package described as comparative examples of the present invention. FIG. 3 illustrates a portion of one memory die (e.g., 241) constituting the memory die stack 240 of FIG. 2, and the semiconductor package 200 of FIG. 4 has the same memory configuration as the memory die 241 of FIG. 3. Shows wire bond connections between dies 242, 243, 244 and memory die 241.

Referring to FIG. 3, the memory die 241 includes a first set of die bond pads 310, and the first set of die bond pads 310 include a plurality of CA pads (CA0 to CA3). It can be included. A plurality of CA pads (CA0 to CA3) may receive commands or addresses transmitted from the memory controller 112.

Memory die 241 may include a second set of die bond pads 320 and a third set of die bond pads 330. The second set of die bond pads 320 includes a plurality of lower DQ pads (DQ0 to DQ5), and the third set of die bond pads 330 includes a plurality of upper DQ pads (DQ6 to DQ11). may include. A plurality of lower and upper DQ pads (DQ0 to DQ5, DQ6 to DQ11) transmit data (DQ) read from the memory cell array (MCA) to the memory controller 112 or write data provided from the memory controller 112. (DQ) can be received.

Memory die 241 includes a fourth set of die bond pads 340 and a fifth set of die bond pads 350, where the fourth set of die bond pads 340 are RDQS pads (RDQS). , RDQSB), and the fifth set of die bond pads 350 may include WCK pads (WCK, WCKB). The RDQS pads (RDQS, RDQSB) provide timing of the read data (DQ) when the read data (DQ) is transmitted through a plurality of lower and upper DQ pads (DQ0 to DQ5, DQ6 to DQ11). A clock signal can be transmitted to the memory controller 112. WCK pads (WCK, WCKB) provide timing of write data (DQ) when write data (DQ) is received through a plurality of lower and upper DQ pads (DQ0 to DQ5, DQ6 to DQ11). A clock signal may be received from the memory controller 112. Additionally, the WCK pads (WCK, WCKB) may receive the WCK and WCKB clock signals provided from the memory controller 112 in a preparation operation for providing read data (DQ) to the memory controller 112.

Referring to FIG. 4, each of the memory dies 241 to 244 stacked in the semiconductor package 200 may include die bond pad sets 310, 320, 330, 340, and 350 described with reference to FIG. 3. You can. The package substrate 220 includes a first set of contact pads 410 - 413, where the first set of contact pads 410 - 413 are positioned at CA0 of the first rank 121 and the second rank 122. ~CA3 signals can be transmitted. The first set of contact pads 410 - 413 are connected to wire bonds 41a, 41b, 41c, 41d connected to the memory dies 241 - 244 of the first rank 121 and the second rank 122. are connected and may transmit CA0 to CA3 signals to the die bond pads 310 of the first set of memory dies 241 to 244.

The package substrate 220 includes a second set of contact pads 420 - 425, where the second set of contact pads 420 - 425 stores subgroup data (e.g., DQ[) of the first rank 121. 5:0]) can be transmitted. The second set of contact pads 420-425 are connected to wire bonds 42a and 42b connected to the memory dies 242 and 244 of the first rank 121 and are connected to the wire bonds 42a and 42b of the corresponding memory dies 242 and 244. DQ[5:0] data may be transmitted to and from the second set of die bond pads 320.

The package substrate 220 includes a third set of contact pads 430 to 435, and the third set of contact pads 430 to 435 contain upper group data (e.g., DQ[) of the second rank 122. 11:6]) can be transmitted. The third set of contact pads 430 to 435 are connected to wire bonds 43a and 43b connected to the memory dies 241 and 243 of the second rank 122 and are connected to the wire bonds 43a and 43b of the corresponding memory dies 241 and 243. DQ[11:6] data may be transmitted to and from the third set of die bond pads 330. Hereinafter, with respect to the lower byte and upper byte terms specified in the LPDDR specification, lower group data (e.g., DQ[5:0]) is referred to as lower byte data, and upper group data (e.g., DQ[11:6] ) may be referred to as upper byte data.

The package substrate 220 includes a fifth set of contact pads 450, 451, wherein the fifth set of contact pads 450, 451 is connected to the WCK of the first rank 121 and the second rank 122. , WCKB clock signals can be transmitted. The fifth set of contact pads 450 and 451 are connected to wire bonds 45a, 45b, 45c and 45d connected to the memory dies 241 to 244 of the first rank 121 and the second rank 122. may be connected and transmit WCK and WCKB clock signals to the fifth set of die bond pads 350 of the memory dies 241 to 244.

Package substrate 220 includes a fourth set of contact pads 440-443, where contact pads 441 and 443 receive RDQS0 and RDQSOB clock signals and contact pads 440 and 442 receive second sets of contact pads 440-443. RDQS1 and RDQS1B clock signals of rank 122 may be received. The RDQS0 and RDQSOB clock signals may be used to provide read data timing with respect to the first rank 121 and the RDQS1 and RDQS1B clock signals may be used to provide read data timing with respect to the second rank 122.

Contact pad 441 is connected to wire bonds 44a, 44c connected to memory dies 242, 244 of first rank 121 and to die bond pads of fourth set of memory dies 242, 244 ( 340), the contact pad 440 is connected to the wire bonds 44b, 44d connected to the memory dies 241, 243 of the second rank 122, and the memory dies 241, 243 ) may receive the RDQS1 clock signal from the fourth set of die bond pads 340. Contact pad 443 is connected to wire bonds 44a, 44c connected to memory dies 242, 244 of first rank 121 and to die bond pads of fourth set of memory dies 242, 244 ( 340), the contact pad 442 is connected to the wire bonds 44b, 44d connected to the memory dies 241, 243 of the second rank 122, and the memory dies 241, 243 ) may receive the RDQS1B clock signal from the fourth set of die bond pads 340.

However, the wire bonds 44c 44d through which the RDQS0 clock signal of the first rank 121 and the RDQS1 clock signal of the second rank 122 are transmitted may be formed to overlap each other. As the wire bonds 44c 44d overlap each other, the wire bonds 44c 44d may be shorted. In addition, the wire bonds 44c 44d through which the RDQSOB clock signal of the first rank 121 and the RDQS1B clock signal of the second rank 122 are transmitted may also be shorted due to their overlapping shapes. Even if the semiconductor package 200 is not short-circuited in the initial packaging stage, the package quality may change over time, and the operation of the semiconductor package 200 may fail due to short-circuiting of the wire bonds 44c and 44d. You can. Accordingly, if die bond pads to which the RDQS and RDQSB clock signals for each rank are connected are added to each memory die, and wire bonds are connected so that the RDQS and RDQSB clock signals of the corresponding rank are transmitted to the added die bond pads, the semiconductor package The signal characteristics and/or performance of (200) may be improved.

5 to 6B are diagrams explaining semiconductor packages according to embodiments of the present invention. FIG. 6A illustrates the pad arrangement of the memory dies 242 and 244 included in the first rank 121 of the semiconductor package 200a of FIG. 5, and FIG. 6B illustrates the pad arrangement of the memory dies 242 and 244 included in the second rank 122 ( 241, 243) explains the pad arrangement. Hereinafter, the subscripts attached to the same reference numbers in different drawings (e.g., a in 200a) are used to distinguish multiple circuits that perform similar or identical functions. The semiconductor package 200a of FIG. 5 is different from the semiconductor package 200 of FIG. 4 in that it further includes die bond pads connected to RDQS clock signals for each rank. Descriptions that overlap with the semiconductor package 200 are omitted.

Referring to FIG. 5 , the semiconductor package 200a may form part of the semiconductor package 200 described with reference to FIGS. 1 to 4 . The semiconductor package 200a may include memory dies 242 and 244 constituting the first rank 121 and memory dies 241 and 243 constituting the second rank 122 on the package substrate 220. You can.

Each of the memory dies 241, 242, 243, and 244 includes a first set of die bond pads 310 including a plurality of CA pads CA0 to CA3 described with reference to FIGS. 3 and 4, A second set of die bond pads 320 including a plurality of lower DQ pads (DQ0 to DQ5), and a third set of die bond pads 330 including a plurality of upper DQ pads (DQ6 to DQ11). ) and a fifth set of die bond pads 350 including WCK pads (WCK, WCKB). And each of the memory dies 241, 242, 243, and 244 may include a fourth set of die bond pads 540 associated with RDQS pads RDQS and RDQSB. The fourth set of die bond pads 540 may include, for example, four die bond pads 541, 542, 543, and 544.

The four die bond pads 541, 542, 543, and 544 may be configured to have different wiring structures depending on whether the corresponding memory die is included in the first rank 121 or the second rank 122. 6A and 6B, each of the memory dies 241, 242, 243, and 244 may include a memory cell array (MCA) and peripheral circuits, and the peripheral circuits include data input/output circuits 610, 620, and 660. , 670), first and second clock circuits 630 and 640, and a third clock circuit 650. Although not shown in FIGS. 6A and 6B, each of the memory dies 241, 242, 243, and 244 may further include a row decoder, a column decoder, a read/write circuit, a control logic circuit, etc. The configurations of example memory dies 241, 242, 243, and 244 shown in FIGS. 6A and 6B do not represent or imply limitations to the present disclosure.

Meanwhile, the memory controller 112 may provide a command to the first rank 121 or the second rank 122 to perform a memory operation. Non-limiting examples of memory commands may include an access command for accessing memory, for example, a read command for performing a read operation and a write command for performing a write operation.

In operation, when a read command and a related address are provided by the memory controller 112 to a selected rank among the first and second ranks 121 and 122, the selected rank receives the read command and the related address, and performs a read operation. By performing , read data (DQ) can be output from the memory location corresponding to the related address. Read data DQ may be provided to the memory controller 112 by a memory die of a selected rank according to timing related to reception of a read command. For example, the timing is a read latency (RL) value indicating the number of clock cycles of the CK clock (referenced as tCK) after the read command when read data (DQ) is provided to the memory controller 112 by the memory die. It can be based on

When preparing a corresponding rank for providing read data (DQ) to the memory controller 112, the memory controller 112 may provide an active WCK clock signal to the memory die of the corresponding rank. The WCK clock signal can be used by the memory die to generate the RDQS clock signal. The clock signal is activated when it periodically transitions between low and high clock levels. Conversely, when the clock signal maintains a constant clock level and does not transition periodically, the clock signal is disabled. The RDQS clock signal may be provided to the memory controller 112 by the memory die that performed the read operation for timing of providing read data to the memory controller 112. The memory controller 112 may use the RDQS clock signal to receive read data (DQ).

In operation, when a write command and an associated address are provided to a rank selected by the memory controller 112, the memory die of the selected rank receives the write command and the associated address and performs a write operation to write a write command from the memory controller 112. Write data (DQ) can be written to a memory location corresponding to the associated address. Write data (DQ) is provided to the memory system 120 by the memory controller 112 according to timing related to reception of the write command. For example, the timing may be a write latency (WL) value representing the number of clock cycles (tCK) of the CK clock after the write command when write data (DQ) is provided to the memory system 120 by the memory controller 112. It can be based on

Upon preparation of a corresponding rank to receive write data (DQ) from memory controller 112, memory controller 112 may provide an active WCK clock to the memory die of that rank. The WCK clock signal may be used by the memory die to generate an internal clock signal for timing the operation of the circuit receiving write data (DQ). The write data DQ is provided by the memory controller 112, the memory die receives the write data DQ according to the WCK clock, and the write data DQ can be written to the memory corresponding to the memory address.

The data input/output circuits 610, 620, 660, and 670 transmit read data (DQ) synchronized to the RDQS clock signal to the memory controller 112, and transmit write data (DQ) synchronized to the WCK clock signal to the memory controller (112). ) can be configured to receive from. Data DQ transmitted and received by the data input/output circuits 610, 620, 660, and 670 may include a data width of 12 bits. The data width of 12 bits can be divided into a low-order byte of 6-bit data and a high-order byte of 6-bit data.

The first and second clock circuits 630 and 640 may be configured to generate RDQS and RDQSB clock signals and provide timing for providing read data to the memory controller 112. RDQS and RDQSB clock signals may be provided to the memory controller 112 by the first and second clock circuits 630 and 640 from the memory dies 241, 242, 243, and 244 that performed the read operation. The third clock circuit 650 may be configured to receive the WCK and WCKB clock signals and generate an internal clock signal for the operation timing of the circuit receiving the write data (DQ). The WCK and WCKB clock signals may be received by the third clock circuit 650 from the memory dies 241, 242, 243, and 244 that perform the write operation.

In FIG. 6A, the memory dies 242 and 244 constituting the first rank 121 are some of the die bond pads described with reference to FIG. 3 (e.g., DQ4, DQ5, WCK, WCKB, DQ6, and DQ7 die bond pads). ) and four die bond pads (541, 542, 543, 544). Each of the DQ4, DQ5, DQ6, and DQ7 die bond pads may be connected to the data input/output circuits 610, 620, 660, and 670 through the first metal wires 611, 621, 661, and 671. The WCK and WCKB die bond pads may be connected to the third clock circuit 650 through the first metal wires 651 and 652. Among the four die bond pads (541, 542, 543, 544), the right two die bond pads (543, 544) are connected to the first and second clock circuits (630) through the second metal wires (631, 641), respectively. , 640). The RDQS clock signal generated in the first clock circuit 630 may be provided to 543 die bond pads, and the RDQSB clock signal generated in the second clock circuit 640 may be provided to 544 die bond pads.

In FIG. 6B, the memory dies 241 and 243 constituting the second rank 122, as described in FIG. 6A, each of the DQ4, DQ5, DQ6 and DQ7 die bond pads is connected to the first metal wire 611, 621, 661, 671) are connected to the data input/output circuits (610, 620, 660, 670), and the WCK and WCKB die bond pads are connected to the third clock circuit (650) through the first metal wires (651, 652). can be connected Among the four die bond pads (541, 542, 543, 544), the left two die bond pads (541, 542) are connected to the first and second clock circuits (630) through the second metal wires (632, 642), respectively. , 640). The RDQS clock signal generated in the first clock circuit 630 may be provided to 541 die bond pads, and the RDQSB clock signal generated in the second clock circuit 640 may be provided to 542 die bond pads.

6A and 6B, the second metal wires 631, 632, 641, and 642 may be formed in a metal layer higher than the metal layer on which the first metal wires 611, 621, 651, 652, 661, and 671 are formed. there is. For example, the second metal wires 631, 632, 641, and 642 may be formed using the uppermost metal layer of the memory dies 241, 242, 243, and 244. Depending on the embodiment, each of the second metal wirings 631, 632, 641, and 642 may be formed using a plurality of redistribution layers. The plurality of redistribution layers may be extended to electrically connect internal and external connection pads of the memory dies 241, 242, 243, and 244. By connecting the RDQS and RDQSB clock signals for each rank to the die bond pads (541, 542, 543, and 544) using a plurality of redistribution layers, the memory die (241, 242, 243, 244) is formed without performing a separate process. ) can be easily configured.

Referring again to FIG. 5, a memory die stack 240 in which the memory dies 241, 242, 243, and 244 illustrated in FIGS. 6A and 6B are stacked in the continuously offset stepped configuration illustrated with reference to FIG. 2. It can be configured. The package substrate 220 includes a fourth set of contact pads 551 to 554, where the contact pads 553 and 554 receive the RDQS0 and RDQSOB clock signals of the first rank 121, and the contact pads 551 and 552 may receive the RDQS1 and RDQS1B clock signals of the second rank 122.

The contact pad 553 is connected to the wire bonds 53a and 53b connected to the memory dies 242 and 244 of the first rank 121 and connected to the 543 die bond pad of the memory dies 242 and 244. 1 The RDQS0 clock signal provided by the clock circuit 630 can be received. The contact pad 554 is connected to the wire bonds 54a and 54b connected to the memory dies 242 and 244 of the first rank 121 and connected to the 544 die bond pad of the memory dies 242 and 244. 2 The RDQS0B clock signal provided by the clock circuit 630 can be received.

The contact pad 551 is connected to the wire bonds 51a and 51b connected to the memory dies 241 and 243 of the second rank 122 and connected to the 541 die bond pad of the memory dies 241 and 243. 1 The RDQS1 clock signal provided by the clock circuit 630 can be received. The contact pad 552 is connected to the wire bonds 52a and 52b connected to the memory dies 241 and 243 of the second rank 122 and connected to the 542 die bond pad of the memory dies 241 and 243. 2 The RDQS1B clock signal provided by the clock circuit 630 can be received.

As can be seen in FIG. 5, wire bonds 51a, 51b, 52a, 52b, 53a transmitting the RDQS0 and RDQS0B clock signals of the first rank 121 and the RDQS1 and RDQS1B clock signals of the second rank 122. 53b, 54a, 54b) can be formed without overlapping. Accordingly, the signal characteristics and/or performance of the semiconductor package 200a can be improved.

7 is a diagram illustrating a semiconductor package according to embodiments of the present invention.

Referring to FIG. 7 , the semiconductor package 200b is different from the semiconductor package 200a of FIG. 5 in that data DQ transmitted and received with the memory controller 112 includes a data width of 8 bits. The data width of 8 bits can be separated into the lower byte of 4-bit data (DQ[3:0]) and the upper byte of 4-bit data (DQ[7:4)).

The package substrate 220 includes contact pads 420 to 423 that transmit lower byte data (DQ[3:0]) and contact pads 430 to 433 that transmit lower byte data (DQ[7:4]). ) may include. The contact pads 420 to 423 are connected to wire bonds 42a and 42b connected to the memory dies 242 and 244 of the first rank 121 and to the lower DQ die bonds of the corresponding memory dies 241 and 243. DQ[3:0] data can be transmitted and received from the pads 320. The contact pads 430 to 433 are connected to wire bonds 43a and 43b connected to the memory dies 241 and 243 of the second rank 122 and to the upper DQ die bonds of the corresponding memory dies 241 and 243. DQ[7:4] data can be transmitted to/from the pads 330.

8 is a diagram illustrating a semiconductor package according to embodiments of the present invention.

Referring to FIG. 8, the semiconductor package 200c is different from the semiconductor package 200a of FIG. 5 in that data DQ transmitted and received with the memory controller 112 includes a data width of 16 bits. The data width of 16 bits can be divided into the lower byte of 8-bit data (DQ[7:0]) and the upper byte of 4-bit data (DQ[15:8)).

The package substrate 220 includes contact pads 420 to 427 that transmit lower byte data (DQ[7:0]) and contact pads 430 to 437 that transmit lower byte data (DQ[15:7]). ) may include. The contact pads 420 to 427 are connected to wire bonds 42a and 42b connected to the memory dies 242 and 244 of the first rank 121 and to the lower DQ die bonds of the corresponding memory dies 241 and 243. DQ[7:0] data can be transmitted to/from the pads 320. The contact pads 430 to 433 are connected to wire bonds 43a and 43b connected to the memory dies 241 and 243 of the second rank 122 and to the upper DQ die bonds of the corresponding memory dies 241 and 243. DQ[15:8] data can be transmitted to/from the pads 330.

Figure 9 is a diagram explaining a memory system according to embodiments of the present invention. FIGS. 10A to 10D are diagrams explaining the memory chip configuration for each rank in FIG. 9 .

Referring to FIG. 9 , the memory controller 112 of the processor 110 may communicate with the memory system 900 through a channel 130. The memory system 900 includes a plurality of memory chips 940 to 947, and the plurality of memory chips 940 to 947 may be logically and/or physically divided into at least four ranks. The memory system 900 has a 4-rank structure, the memory chips 940 and 944 constitute the first rank 910, the memory chips 941 and 945 constitute the second rank 911, and the memory chips 940 and 944 constitute the first rank 910. The memory chips 942 and 946 constitute the third rank 912, and the memory chips 943 and 947 may be implemented as a multi-chip package forming the fourth rank 913.

Referring to FIG. 10A, each of the memory chips 940 and 944 of the first rank 910 includes an RDQS clock circuit 1030 that generates the RDQS clock signal described with reference to FIG. 6A and an RDQSB clock that generates the RDQSB clock signal. It may include circuit 1040. The RDQS and RDQSB clock signals may provide timing of the read data DQ when the read data DQ is transmitted through a plurality of lower and upper DQ pads (e.g., DQ0 to DQ5 and DQ6 to DQ11). Additionally, each of the memory chips 940 and 944 may include a plurality of die bond pads 1010 to 1017 connected to the RDQS clock circuit 1030 and the RDQSB clock circuit 1040. Exemplarily, 1010 and 1011 die bond pads transmit RDQS0 and RDQSOB clock signals of the first rank 910, and 1012 and 1013 die bond pads transmit RDQS1 and RDQS1B clock signals of the second rank 920, The 1014 and 1015 die bond pads may be configured to transmit the RDQS2 and RDQS2B clock signals of the third rank 930, and the 1016 and 1017 die bond pads may be configured to transmit the RDQS3 and RDQS3B clock signals of the fourth rank 940.

In FIG. 10A, die bond pads 1010 and 1011 may be connected to the RDQS and RDQSB clock circuits 1030 and 1040 through the top metal wiring or redistribution layers 1020 and 1021. The RDQS clock signal generated in the RDQS clock circuit 1030 may be provided to a 1010 die bond pad, and the RDQSB clock signal generated in the RDQSB clock circuit 1040 may be provided to a 1011 die bond pad.

In FIG. 10B, each of the memory chips 941 and 945 of the second rank 911 has die bond pads 1012 and 1013 connected to the RDQS and RDQSB clock circuits 1030 and 1040 through the uppermost metal wiring or redistribution layers 1022 and 1023. ) can be connected to. The RDQS clock signal generated in the RDQS clock circuit 1030 may be provided to a 1012 die bond pad, and the RDQSB clock signal generated in the RDQSB clock circuit 1040 may be provided to a 1013 die bond pad.

In FIG. 10C, the memory chips 942 and 946 of the third rank 912 each have die bond pads 1014 and 1015 connected to the RDQS and RDQSB clock circuits 1030 and 1040 through the top metal wiring or redistribution layers 1024 and 1025. ) can be connected to. The RDQS clock signal generated in the RDQS clock circuit 1030 may be provided to a 1014 die bond pad, and the RDQSB clock signal generated in the RDQSB clock circuit 1040 may be provided to a 1015 die bond pad.

In FIG. 10D, each of the memory chips 943 and 947 of the fourth rank 913 has die bond pads 1016 and 1017 connected to the RDQS and RDQSB clock circuits 1030 and 1040 through the uppermost metal wiring or redistribution layers 1026 and 1027. ) can be connected to. The RDQS clock signal generated in the RDQS clock circuit 1030 may be provided to a 1016 die bond pad, and the RDQSB clock signal generated in the RDQSB clock circuit 1040 may be provided to a 1017 die bond pad.

Each of the above-described memory chips 940 to 947 has die bond pads on which RDQS and RDQSB clock signals for each rank are loaded, and the die bond pads corresponding to the ranks are connected to the RDQS and RDQSB clocks through the uppermost metal wiring or redistribution layer. By connecting with the circuits 1030 and 1040, it is possible to easily configure the memory chips 940 to 947 without performing a separate process. And, as the RDQS and RDQSB die bond pads of the corresponding ranks between the memory die stacks in which the memory chips 940 to 947 are stacked are electrically connected to each other through wire bonds, the signal characteristics and/or performance of the multi-chip package can be improved. You can.

11 is a block diagram of a system for explaining an electronic device including a semiconductor package according to embodiments of the present invention.

Referring to FIG. 11, the system 2000 includes a camera 2100, a display 2200, an audio processor 2300, a modem 2400, DRAMs 2500a, 2500b, flash memories 2600a, 2600b, I /O devices 2700a and 2700b and an application processor 2800 (hereinafter referred to as “AP”) may be included. The system (2000) is implemented as a laptop computer, mobile phone, smart phone, tablet personal computer, wearable device, healthcare device, or IOT (Internet Of Things) device. It can be. Additionally, the system 2000 may be implemented as a server or personal computer.

The camera 2100 can capture still images or moving images under user control, and store or transmit the captured image/video data to the display 2200. The audio processing unit 2300 may process audio data included in flash memory devices 2600a and 2600b or network content. The modem 2400 modulates and transmits signals for wired/wireless data transmission and reception, and can be demodulated to restore the original signal at the receiving end. I/O devices 2700a and 2700b are digital inputs such as USB (Universal Serial Bus), storage, digital camera, SD (Secure Digital) card, DVD (Digital Versatile Disc), network adapter, touch screen, etc. and/or devices that provide output functions.

The AP (2800) can control the overall operation of the system (2000). The AP 2800 may include a control block 2810, an accelerator block or accelerator chip 2820, and an interface block 2830. The AP 2800 may control the display 2200 so that part of the content stored in the flash memory devices 2600a and 2600b is displayed on the display 2200. When a user input is received through the I/O devices 2700a and 2700b, the AP 2800 may perform a control operation corresponding to the user input. The AP (2800) may include an accelerator block, which is a dedicated circuit for AI (Artificial Intelligence) data calculation, or may be provided with an accelerator chip (2820) separate from the AP (2800). A DRAM 2500b may be additionally mounted on the accelerator block or accelerator chip 2820. The accelerator is a function block that specializes in performing specific functions of the AP (2800). The accelerator is a function block that specializes in graphics data processing, GPU, and a block in specializing in AI calculation and inference. It may include an NPU (Neural Processing Unit) and a DPU (Data Processing Unit), a block specializing in data transmission.

System 2000 may include a plurality of DRAMs 2500a and 2500b. The AP (2800) controls the DRAMs (2500a, 2500b) through command and mode register (MRS) settings that meet the Joint Electron Device Engineering Council (JEDEC) standard, or operates company-specific functions such as low voltage/high speed/reliability and CRC ( To use the Cyclic Redundancy Check/ECC (Error Correction Code) function, you can communicate by setting the DRAM interface protocol. For example, the AP (2800) can communicate with the DRAM (2500a) through an interface that complies with JEDEC standards such as LPDDR4 and LPDDR5, and the accelerator block or accelerator chip (2820) is an accelerator with a higher bandwidth than the DRAM (2500a). To control the DRAM 2500b, a new DRAM interface protocol can be set and communicated.

FIG. 11 shows only DRAMs 2500a and 2500b, but is not limited thereto and can be used as PRAM, SRAM, MRAM, RRAM, FRAM, or Hybrid RAM if it satisfies the bandwidth, response speed, and voltage conditions of the AP (2800) or accelerator chip (2820). Any memory, including memory, can be used. DRAMs 2500a and 2500b have relatively smaller latency and bandwidth than I/O devices 2700a and 2700b or flash memories 2600a and 2600b. The DRAMs 2500a and 2500b are initialized when the system 2000 is powered on, the operating system and application data are loaded, and can be used as a temporary storage location for the operating system and application data or as an execution space for various software codes. .

In the DRAMs 2500a and 2500b, addition/subtraction/multiplication/division arithmetic operations, vector operations, address operations, or FFT (Fast Fourier Transform) operations may be performed. Additionally, a function used for inference may be performed within the DRAMs 2500a and 2500b. Here, inference can be performed in a deep learning algorithm using an artificial neural network. Deep learning algorithms may include a training step to learn a model through various data and an inference step to recognize data with the learned model. As an embodiment, the image taken by the user through the camera 2100 is signal processed and stored in the DRAM 2500b, and the accelerator block or accelerator chip 2820 is used for inference with data stored in the DRAM 2500b. You can perform AI data operations that recognize data using the function.

System 2000 may include a plurality of storage units or a plurality of flash memories 2600a and 2600b with larger capacities than the DRAMs 2500a and 2500b. The accelerator block or accelerator chip 2820 can perform a training step and AI data operation using flash memories 2600a and 2600b. In one embodiment, the flash memories 2600a and 2600b include a memory controller 2610 and a flash memory device 2620, and the AP 2800 and/or The training step and inference AI data calculation performed by the accelerator chip 2820 can be performed more efficiently. The flash memories 2600a and 2600b can store photos taken through the camera 2100 or store data transmitted over a data network. For example, Augmented Reality/Virtual Reality, High Definition (HD), or Ultra High Definition (UHD) content can be stored.

In system 2000, DRAMs 2500a and 2500b may include the semiconductor package described with reference to FIGS. 1 to 10 . A semiconductor package is mounted on a package substrate and includes a memory die stack in which a plurality of memory dies are stacked, and the plurality of memory dies are composed of first rank memory dies and second rank memory dies. Each of the plurality of memory dies includes a clock circuit that generates a read clock signal for the lower byte and the upper byte constituting the data width, a first die bond pad that transmits a first rank read clock signal, and a second rank read clock. It includes a second die bond pad that transmits signals. The clock circuit is connected to a die bond pad that transmits a read clock signal of the rank to which the memory die belongs among the first and second die bond pads. Accordingly, the memory die includes die bond pads on which the read clock signal for each rank is loaded, and the read clock circuit shared by the lower and upper bytes of each memory die stack is loaded on the read clock signal of the rank to which the memory die belongs. By connecting to the die bond pad and wire bonding the corresponding ranks between the memory die stacks, the signal characteristics and/or performance of the semiconductor package can be improved. Additionally, by connecting die bond pads carrying read clock signals for each rank to the read clock circuit through a redistribution layer, it is possible to easily configure the memory die without performing a separate process.

The present invention has been described in relation to a limited number of embodiments shown in the drawings, but these are merely illustrative, and those skilled in the art will be able to make various changes and modifications and other equivalent implementations. It will be appreciated that examples are possible. Accordingly, the appended claims are intended to cover all such changes and modifications as fall within the true spirit and scope of the invention.

Claims (10)

In the memory die,
a first clock circuit that generates a read clock signal for lower bytes and upper bytes constituting the data width of the memory die; and
a plurality of first die bond pads corresponding to the number of ranks of a memory system in which the memory die is included, each of the plurality of first die bond pads being configured to be connected to a rank to which the memory die belongs,
The first clock circuit is a memory die connected to a corresponding rank die bond pad among the plurality of first die bond pads. According to paragraph 1,
The memory die connects the first clock circuit and the corresponding rank die bond pad using the uppermost metal layer of the memory die. According to paragraph 1,
The memory die connects the first clock circuit and the corresponding rank die bond pad using a redistribution layer of the memory die. The method of claim 1, wherein the memory die is:
a second clock circuit that receives data clock signals for the lower byte and the upper byte, the data clock signal being involved in a read operation and a write operation of the memory die; and
A memory die further comprising a second die bond pad connected to the second clock circuit. According to paragraph 1,
A memory die wherein the data width is comprised of 12 bits, and the lower and upper bytes are comprised of 6 bits. According to paragraph 1,
A memory die wherein the data width is comprised of 8 bits, and the lower and upper bytes are comprised of 4 bits. According to paragraph 1,
A memory die wherein the data width is comprised of 16 bits, and the lower and upper bytes are comprised of 8 bits. package substrate;
a memory die stack mounted on the package substrate and stacking a plurality of memory dies, the plurality of memory dies being composed of first rank memory dies and second rank memory dies;
first wire bonds connecting the memory dies of the first rank; and
comprising second wire bonds connecting the memory dies of the second rank,
Each of the multiple memory dies,
a clock circuit that generates a read clock signal for the lower byte and upper byte constituting the data width;
a first die bond pad transmitting the first rank read clock signal; and
A second die bond pad transmitting the second rank read clock signal,
The clock circuit is connected to a die bond pad that transmits the read clock signal of the rank to which the memory die belongs among the first and second die bond pads. According to clause 8,
A semiconductor package in which each of the plurality of memory dies connects the clock circuit and the die bond pad using the uppermost metal layer of the memory die. According to clause 8,
A semiconductor package in which each of the plurality of memory dies connects the clock circuit and the die bond pad using a redistribution layer of the corresponding memory die.

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