KR20240012838A - Pulse generating method using memristor, recording medium, and device for performing the method - Google Patents

Abstract

According to the present invention, a pulse generation method using a memristor includes the steps of inputting one or more clocks to a logic gate composed of a memristor; and outputting the one or more clock signals as one or more enable signals using spikes of the logic gate, wherein the enable signals include pulses occurring on both the rising and falling sides of the clock. As a result, the area overhead due to the inverter chain does not increase, and an enable signal with a very short pulse width can be generated. Additionally, this pulse signal can be used to drive a pulse latch that can reduce power consumption of the entire chip.

Description

Pulse generation method using memristor, recording medium and device for performing the same {PULSE GENERATING METHOD USING MEMRISTOR, RECORDING MEDIUM, AND DEVICE FOR PERFORMING THE METHOD }

This relates to a pulse generation method using a memristor, a recording medium, and a device for performing the same. More specifically, it relates to a pulse generation method on both the rising and falling sides of an input clock using the SPIKE phenomenon occurring in a logic gate composed of a memristor. It relates to a pulse generation technology that can generate an enable signal.

The development of binary computers has been based on improvements in integration technology through miniaturization of devices. FinFET and Nanosheet FET are good examples of this trend. However, as device miniaturization technology approaches several nanometers, the difficulty of the technology is rapidly increasing, and various studies predict that this development will soon reach its limit. Therefore, the industry is seeking new ways to improve computational performance.

The ternary arithmetic system requires approximately 36.9% fewer calculations and storage space than the binary arithmetic system. The characteristics of this ternary arithmetic system enable high-density, high-performance implementation of arithmetic circuits. Due to these advantages of the ternary calculation system, ternary semiconductors are currently receiving great attention as a key element for the development of computer performance.

In addition, as device technology has developed, various devices such as tenary CMOS, CNTFET, and memristor that can design ternary computers have appeared. The emergence of this technology provided a clear opportunity for the development of ternary computers.

Among the various devices that can implement ternary logic gates (Ternary CMOS, CNTFET, memristor, etc.), the ternary logic gate consisting of a memristor and MOSFET has the advantage of being the only one currently available using a commercial process. , it has the advantage of being able to achieve high integration as well.

Additionally, a pulse latch was proposed to replace the existing master-slave flip-flop. As sequential circuits occupy approximately 20% of the total chip area in recent digital VLSI design, designing sequential circuits with a small area is becoming important. A pulse latch is a sequential circuit that converts an existing clock into pulses of very short width and then receives input. It operates in the same way as a flip-flop that transmits values at the edge of the clock.

The pulse generation circuit used in the existing pulse latch is designed based on an inverter chain. Therefore, in order to implement a very short pulse width, there is a disadvantage that the area overhead due to the inverter chain increases.

KR 10-1689159 B1 KR 10-2018-0013789 A CN 111046617 A

Accordingly, the technical problem of the present invention was conceived from this point, and the purpose of the present invention is to relate to a pulse generation method using a memristor that can implement a very short pulse width without increasing the area overhead due to the inverter chain.

Another object of the present invention is to provide a recording medium on which a computer program for performing the pulse generation method using the memristor is recorded.

Another object of the present invention is to provide a pulse generating device using a memristor.

A pulse generation method using a memristor according to an embodiment for realizing the object of the present invention described above includes the steps of inputting one or more clocks to a logic gate composed of a memristor; and outputting the one or more clock signals as one or more enable signals using spikes of the logic gate, wherein the enable signals include pulses occurring on both the rising and falling sides of the clock.

In an embodiment of the present invention, the logic gate may include one or more of AND, TAND, OR, and TOR gates.

In an embodiment of the present invention, the width of the pulse may be different depending on the switching delay of the logic gate.

A computer program for performing a pulse generation method using a memristor may be recorded on a computer-readable storage medium on which a computer program according to an embodiment for realizing the above-described other object of the present invention is recorded.

A pulse generating device using a memristor according to an embodiment for realizing another object of the present invention described above includes a processor; Includes a memory connected to the processor, wherein the memory inputs one or more clock signals to a logic gate composed of a memristor, and outputs the one or more clock signals as one or more enable signals using a spike phenomenon of the logic gate. In addition, the enable signal may store program instructions executed by the processor such that it includes pulses occurring on both the rising and falling sides of the clock.

In an embodiment of the present invention, the logic gate may include one or more of AND, TAND, OR, and TOR gates.

In an embodiment of the present invention, the width of the pulse may be different depending on the switching delay of the logic gate.

According to this pulse generation method using a memristor, an enable signal with a very short pulse width can be generated without increasing the area overhead due to the inverter chain.

Additionally, this pulse signal can be used to drive a pulse latch that can reduce power consumption of the entire chip.

In addition, this pulse generation technology can be widely applied to necessary circuit configurations such as binary pulse latch and ternary pulse latch, which is attracting attention as a next-generation computing technology.

1 shows a conventional pulse latch and pulse generator.
Figure 2 shows a waveform generated by a conventional pulse generator.
Figure 3 shows the symbol and characteristics of a memristor and a schematic diagram and symbol of a logic gate using it.
Figure 4 shows a schematic diagram of NTI, PTI, and STI gates.
Figure 5 is a schematic diagram of a logic gate using a memristor, showing the state and spike phenomenon of the logic gate according to the input.
Figure 6 shows a schematic diagram of a ternary pulse latch using a memristor according to the present invention.
Figure 7 shows a schematic diagram of a pulse generator using a memristor according to the present invention.
Figure 8 shows a pulse generated by a pulse generator using a memristor according to the present invention.

The detailed description of the present invention described below refers to the accompanying drawings, which show by way of example specific embodiments in which the present invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. It should be understood that the various embodiments of the invention are different from one another but are not necessarily mutually exclusive. For example, specific shapes, structures and characteristics described herein with respect to one embodiment may be implemented in other embodiments without departing from the spirit and scope of the invention. Additionally, it should be understood that the location or arrangement of individual components within each disclosed embodiment may be changed without departing from the spirit and scope of the invention. Accordingly, the detailed description that follows is not intended to be taken in a limiting sense, and the scope of the invention is limited only by the appended claims, together with all equivalents to what those claims assert, if properly described. Similar reference numbers in the drawings refer to identical or similar functions across various aspects.

Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the drawings.

1 is a schematic diagram of a conventional pulse latch and pulse generator.

Referring to Figure 1, in modern digital VLSI, pulse latches are studied as an alternative to MSTFF to reduce the area due to series configuration, which occupies about 20% of the total silicon area.

A pulse latch performs the same role as a flip-flop that stores the input value as an output value from the edge of the clock (CLK). The biggest difference from a flip-flop is the enable signal, which has a narrow The point is to use a pulse signal. A pulse latch requires a pulse generator that converts the CLK signal into narrow pulses.

Figure 2 shows the waveform generated by the pulse generator. Referring to Figure 2, a conventional binary pulsed-latch (CBPL: binary pulsed-latch) using a pulse signal generated by the delay (td, _INV + (N × t _{d, BU F} )) of the inverter chain of the pulse generator is used. indicates.

A pulse on the rising edge of CLK is generated by a pulse generator. Due to this pulse, the pulse latch becomes transparent for a short time corresponding to the width of this pulse and stores the input value in the output Q.

FIG. 3 is a diagram for explaining the symbol and characteristics of a memristor and a schematic diagram and symbol of a logic gate made of a memristor. In this drawing, the TOR gate and TAND gate, which are ternary logic gates, are described, but the same memristor configuration can operate as the OR gate and AND gate, which are binary logic gates.

A memristor is a passive element whose resistance changes depending on the direction of the applied current. In Figure 3(a), when current flows from IN to OUT, the resistance of the memristor decreases to Ron. Conversely, when current flows from OUT to IN direction, the resistance of the memristor increases to Roff.

Conversely, the memristor resistance increases up to Roff when current flows from 'OUT' to 'IN'. Higher Ron and Roff values are required to reduce static current.

In the present invention, the ternary circuit uses MOSFETs in each of the following gate voltage (VGS) states.

VGS = 0: NMOS is OFF, PMOS is ON.

VGS = VDD/2: Both NMOS and PMOS are ON

VGS = VDD: NMOS ON, PMOS OFF

To ensure a performance trade-off, the typical ratio between VDD and Vth is 5:1 in CMOS circuits. Therefore, it is desirable for the MOSFET to be ON at VGS = VDD/2.

Figure 4 shows a schematic diagram and symbols of the ternary inverter (NTI, PTI, STI gate) of the present invention.

The ternary logic of the present invention can be designed based on a balanced ternary method with three logic values, for example, (-1, 0, +1) or (0, 1, 2). Logic values (-1, 0, +1) or (0, 1, 2) can be used as one of the voltage levels (GND, VDD/2, VDD).

Referring to Figure 4, ternary logic requires three types of inverters: negative ternary inverter (NTI), positive ternary inverter (PTI), and STI. Additionally, Table 1 below shows the truth table and behavior of these gates.

For NTI, NMOS turns on when the logic inputs are '0' (VDD/2) and '+1' (VDD). The resistance of the memristor must be high enough to pull down the output when the NMOS is turned on. For PTI, the PMOS is turned on when the logic inputs are '-1' (GND) and '0' (VDD/2).

For STI, when the applied logic input is '-1' (GND) or '+1' (VDD), the PMOS or NMOS is turned on and the output is pulled up to VDD or pulled down to GND.

Therefore, the operation of this STI is very similar to a binary inverter. However, when the applied logic input is '0' (VDD/2), the operation of the STI is very different from that of the binary inverter. At logic input '0' (VDD/2), both PMOS and NMOS are turned on and voltage distribution is applied between M1 and M2. Since the resistance of both memristors is the same, the voltage at the output node becomes VDD/2.

Figure 5 shows a schematic diagram of a logic gate, the state of the logic gate according to the input, and the spike phenomenon. In this drawing, the TOR gate and TAND gate, which are ternary logic gates, are described, but the same memristor configuration can operate as the OR gate and AND gate, which are binary logic gates.

Referring to Figure 5, memristor-based TAND (or AND) and TOR (or OR) have the advantage of occupying 'zero' silicon area because the memristor can be integrated into the BEOL. However, memristor-based logic gates generate unintended voltage spikes, as shown in Figure 5b.

For example, if IN1 is VDD and IN2 is 0V, the current flows from IN1 to IN2 and the TAND (or AND) gate becomes 'State 1'. Afterwards, when the input is inverted (IN1: VDD → 0V, IN2: 0V → VDD), the corresponding current flows from IN2 to IN1. At this time, the resistance of memristor 1 (M1) and memristor 2 (M2) begins to change ('state 2,' M1:Roff → Ron, M2:Ron → Roff), and a spike occurs at the output node according to the voltage distribution rule. do. After the memristor's resistance switching is completed, the state of the TAND eventually converges to 'state 3'. This spike occurs equally while changing the state from 'state 3 → state 4 → state 1'.

Figure 6 is a schematic diagram of a memristor-based ternary pulse latch according to the present invention.

By improving the above-mentioned CBPL, we provide the first memristor-based ternary pulsed latch (MTPL) that stores the ternary input value at the edge of CLK to the output Q.

Referring to FIG. 6, the pulse latch 10 proposed in the present invention has the same structure as the existing binary transmission gate-based latch described in FIG. 1A, but replaces the binary inverter with a ternary inverter (STI). ) was replaced with (110). Additionally, in this drawing, all inverters are described as STI, but only some of them may be replaced as needed.

7 is a schematic diagram of a memristor-based pulse generator according to the present invention. Referring to FIG. 7, the memristor-based pulse generator 20 according to the present invention is composed of a clock inverter 210 and a TAND gate 330, and receives a clock input to generate an enable signal. Additionally, this pulse generator can use AND gates, TOR, and OR gates instead of the TAND gate 330.

The spike phenomenon of the TAND gate 330 is used to generate a pulse, which is an enable signal rather than a delay of the inverter chain, and the pulse width varies depending on the switching delay of the TAND gate 330.

The MTPL 20 of the present invention may be composed of 16 transistors and 10 memristors. In this case, since the area of 16 transistors is used, it occupies only 72.7% of the silicon area compared to MSTFF.

Figure 8 shows a pulse generated from a memristor-based pulse generator according to the present invention. Referring to Figure 8, pulse signals, or spikes, occur on both the rising and falling edges of CLK relative to MTPL. The result is the same functionality as a double-edge-triggered flip-flop, allowing designers to use half the clock frequency of a single-triggered flip-flop. In other words, using this pulse latch, a slower frequency can be used because it can operate at the same frequency as the original frequency even at a frequency that is twice slower than the original frequency. This can reduce power consumption of the entire chip. Table 2 below compares the characteristics of MSTFF and MTPL.

Such a pulse generation method using a memristor and a MOSFET can be implemented as an application or in the form of program instructions that can be executed through various computer components and recorded on a computer-readable recording medium. The computer-readable recording medium may include program instructions, data files, data structures, etc., singly or in combination.

Additionally, the program may be stored in a memory connected to the processor and executed by the processor.

The program instructions recorded on the computer-readable recording medium may be those specifically designed and configured for the present invention, or may be known and usable by those skilled in the computer software field.

Examples of computer-readable recording media include magnetic media such as hard disks, floppy disks and magnetic tapes, optical recording media such as CD-ROMs and DVDs, and magneto-optical media such as floptical disks. optical media), and hardware devices specifically configured to store and execute program instructions, such as ROM, RAM, flash memory, etc.

Examples of program instructions include not only machine language code such as that created by a compiler, but also high-level language code that can be executed by a computer using an interpreter or the like. The hardware device may be configured to operate as one or more software modules to perform processing according to the invention and vice versa.

Although the above has been described with reference to the embodiments, those skilled in the art can make various modifications and changes to the present invention without departing from the spirit and scope of the present invention as set forth in the claims below. You will be able to do this.

The present invention can generate an enable signal with a very short pulse width without increasing area overhead. This technology can be widely applied to circuit configurations that require pulses and ternary arithmetic systems that are attracting attention as next-generation computing technologies, including binary pulse latches. Therefore, it can be usefully applied throughout the semiconductor industry.

10: pulse latch
110: Standard ternary inverter
130: enable signal
20: pulse generator
210: inverter
230: memristor gate

Claims (7)

Inputting one or more clocks to a logic gate composed of a memristor; and
Outputting the one or more clock signals as one or more enable signals using spikes of the logic gate,
The enable signal includes pulses generated on both the rising and falling sides of the clock.
According to clause 1,
A pulse generation method using a memristor, wherein the logic gate includes one or more of AND, TAND, OR, and TOR gates.
According to clause 1,
A pulse generation method using a memristor, wherein the width of the pulse varies depending on the switching delay of the logic gate.
A computer-readable storage medium on which a computer program for performing the pulse generation method using the memristor according to any one of claims 1 to 3 is recorded.
A pulse latch driving device using a memristor and MOSFET,
processor;
Including a memory connected to the processor,
The memory is,
Input one or more clocks to logic gates composed of memristors,
Outputting the one or more clock signals as one or more enable signals using spikes of the logic gate,
A pulse generating device using a memristor, wherein the enable signal stores program instructions executed by the processor such that it includes pulses generated at both rising and falling sides of the clock.
According to clause 5,
A pulse generator using a memristor, wherein the logic gate includes one or more of AND, TAND, OR, and TOR gates.
According to clause 5,
A pulse generator using a memristor, wherein the width of the pulse varies depending on the switching delay of the logic gate.

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