KR20240011571A - Multiple Patterning Method Of The Semiconductor Device - Google Patents

Abstract

A method of manufacturing a semiconductor device according to an embodiment of the present invention includes forming inclined first hard mask patterns on a substrate and forming a first space between the first hard mask patterns; forming first trenches by anisotropically etching the substrate using the first hard mask patterns as an etch mask; forming second hard mask patterns having a lower height than the upper surfaces of the first hard mask patterns by filling the first trench and the first space; forming third hard mask patterns by coating or depositing a third hard mask layer on the second hard mask patterns and removing the third hard mask layer to expose upper surfaces of the first hard mask patterns; etching the first hard mask patterns using the third hard mask patterns as an etch mask to form a second space and forming divided first hard mask patterns; and forming a second trench by etching the substrate using at least one of the third hard mask patterns, the second hard mask patterns, and the divided first hard mask patterns as an etch mask.

Description

{Multiple Patterning Method Of The Semiconductor Device}

The present invention relates to a method of manufacturing a semiconductor device, and more specifically, to a method of multiple patterning of a semiconductor device.

Due to the microprocessing limitations of single patterning, multiple patterning technology that can increase pattern density is required. Double patterning methods include the LLE (Litho-Litho-Etch) technique that exposes twice, the LELE (Litho-Etch-Litho-Etch) technique that exposes and etches twice using a hard mask, and spacer or anisotropic etching. There is a SADP (Self-Aligned Double Patterning) technique that uses a sidewall. SADP has high pattern alignment, but increases processing steps. Typical SADP can be used for Shallow Trench Isolation (STI), FIN formation in FINFET (Fin Field Effect Transistor), line and space formation, and formation of bitlines and word lines of memory.

The hard mask is mainly made of amorphous carbon layer (Armophous carbon layer, ACL), which is a hard mask mixed with carbon, and silicon oxide vapor layer (SiON). Amorphous carbon layer (ACL) and silicon oxide vapor layer (SiON) are mainly deposited by chemical vapor deposition (CVD). Therefore, CVD spinning hard masks are slower and cost more than spin coating methods. Recently, research has been conducted to form a carbon-containing spin coating layer and a silicon (Si)-containing spin coating layer through a spin coating method rather than a hard mask process using CVD.

One technical problem to be solved by the present invention is to provide a new multiple patterning method.

One technical problem to be solved by the present invention is to provide multiple patterning using a carbon-containing spin coating layer and a silicon (Si)-containing spin coating layer.

One technical problem to be solved by the present invention is to provide multiple patterning using a carbon-containing spin coating layer and a silicon (Si)-containing spin coating layer.

One technical problem to be solved by the present invention is to provide multiple patterning by gap filling the hard mask layer to have a step using a spin coating method.

A method of manufacturing a semiconductor device according to an embodiment of the present invention includes forming inclined first hard mask patterns on a substrate and forming a first space between the first hard mask patterns; forming first trenches by anisotropically etching the substrate using the first hard mask patterns as an etch mask; forming second hard mask patterns having a lower height than the upper surfaces of the first hard mask patterns by filling the first trench and the first space; forming third hard mask patterns by coating or depositing a third hard mask layer on the second hard mask patterns and removing the third hard mask layer to expose upper surfaces of the first hard mask patterns; etching the first hard mask patterns using the third hard mask patterns as an etch mask to form a second space and forming divided first hard mask patterns; and forming a second trench by etching the substrate using at least one of the third hard mask patterns, the second hard mask patterns, and the divided first hard mask patterns as an etch mask.

In one embodiment of the present invention, the first hard mask patterns are made of a material containing carbon and may be formed by spin coating.

In one embodiment of the present invention, the second hard mask patterns are made of a material containing carbon and may be formed by spin coating.

In one embodiment of the present invention, the third hard mask patterns are silicon-based and may be formed by spin coating.

In one embodiment of the present invention, the width of the first trench and the width of the second trench may be the same.

In one embodiment of the present invention, the thickness of the third hard mask patterns may be 1/10 or more of the thickness of the first hard mask pattern.

In one embodiment of the present invention, the inclination angle of the first hard mask patterns may be 80 degrees to 87 degrees.

In one embodiment of the present invention, forming inclined first hard mask patterns on a substrate and a first space between the first hard mask patterns includes: first hard masks sequentially stacked on the substrate; forming a layer, a preliminary hard mask layer, and a photoresist pattern on the preliminary hard mask layer, and patterning the preliminary hard mask layer to form a preliminary hard mask pattern; forming the first hard mask patterns by obliquely etching the first hard mask layer using the preliminary hard mask pattern as a mask; and forming the first trench by etching the substrate using the first hard mask patterns as an etch mask.

In one embodiment of the present invention, the method may further include removing the third hard mask patterns and the second hard mask patterns to expose the first trench and the second trench.

In one embodiment of the present invention, forming a conductive layer filling the first trench and the second trench; The method may further include chemically and mechanically polishing the conductive layer to expose the substrate to form a conductive pattern.

In one embodiment of the present invention, the substrate includes a semiconductor substrate and a lower hard mask layer on the semiconductor substrate, and the first trench and the second trench are formed in the lower hard mask layer to form a lower hard mask pattern. can be formed.

In one embodiment of the present invention, etching the semiconductor substrate using the lower hard mask pattern as a mask to form a trench for a device isolation layer and forming an active region; and filling the device isolation trench with a silicon oxide film.

In one embodiment of the present invention, forming inclined first hard mask patterns on a substrate and a first space between the first hard mask patterns includes: first hard masks sequentially stacked on the substrate; forming a preliminary hard mask pattern by forming a layer, a preliminary hard mask layer, and a photoresist pattern on the preliminary hard mask layer to pattern the preliminary hard mask layer; forming first hard mask patterns by vertically etching the first hard mask layer using the preliminary hard mask patterns as an etch mask; depositing a conformal thin film to cover the first hard mask patterns and anisotropically etching the thin film to provide inclined sidewalls on sidewalls of the first hard mask patterns to form inclined first hard mask patterns; and forming the first trench by etching the substrate using the inclined first hard mask patterns as an etch mask.

A method of manufacturing a semiconductor device according to an embodiment of the present invention includes forming inclined first hard mask patterns on a lower hard mask layer formed on a substrate and forming a first space between the first hard mask patterns; forming first trenches by anisotropically etching the lower hard mask layer using the first hard mask patterns as an etch mask; forming second hard mask patterns lower than upper surfaces of the first hard mask patterns by filling the first trench and the first space with a second hard mask layer; forming third hard mask patterns by coating or depositing a third hard mask layer on the second hard mask patterns and removing the third hard mask layer to expose the first hard mask patterns; obliquely etching the first hard mask patterns using the third hard mask patterns as an etch mask to form a second space and forming divided first hard mask patterns; A second trench is formed by anisotropically etching the lower hard mask layer using at least one of the third hard mask patterns, the divided first hard mask patterns, and the second hard mask patterns. It may include forming lower hard mask patterns including a first trench and a second trench.

In one embodiment of the present invention, forming inclined first hard mask patterns on a lower hard mask layer formed on a substrate and a first space between the first hard mask patterns includes: forming a first space between the first hard mask patterns on the substrate in order: Forming a preliminary hard mask pattern by forming a stacked main hard mask layer, a lower hard mask layer, a preliminary hard mask layer, and a photoresist pattern on the preliminary hard mask layer to pattern the preliminary hard mask layer; forming the first hard mask patterns by obliquely etching the first hard mask layer using the preliminary hard mask pattern as a mask; and forming the first trench by etching the substrate using the first hard mask patterns as an etch mask.

In one embodiment of the present invention, filling a second trench and a second space between the lower hard mask patterns with a gap fill material of the same material as the first hard mask layer; and etching the gap fill material, the first hard mask patterns, and the second hard mask patterns to expose the lower hard mask patterns.

In one embodiment of the present invention, the main hard mask layer is etched using the lower hard mask patterns as an etch mask to create inclined first main hard mask patterns and a first main space between the first main hard mask patterns. forming a; forming first main trenches by anisotropically etching the substrate using the first main hard mask patterns as an etch mask; forming second main hard mask patterns by filling the first main trench and the first main space with a second main hard mask layer so that the upper surfaces of the first main hard mask patterns are lower than the upper surfaces of the first main hard mask patterns; Forming third main hard mask patterns by coating or depositing a third main hard mask layer on the second main hard mask patterns and removing the third main hard mask layer to expose the first main hard mask patterns. step; obliquely etching the first main hard mask patterns using the third main hard mask patterns as an etch mask to form a second main space and forming divided first main hard mask patterns; forming a second main trench by anisotropically etching the substrate using at least one of the third hard mask patterns, the divided first main hard mask patterns, and the second main hard mask patterns; It can be included.

In one embodiment of the present invention, forming inclined first hard mask patterns on a lower hard mask layer formed on a substrate and a first space between the first hard mask patterns includes: forming a first space between the first hard mask patterns on the substrate in order: A photoresist pattern is formed on the stacked silicon oxide layer, the lower hard mask layer, the first hard mask layer, the preliminary hard mask layer, and the preliminary hard mask layer, and the preliminary hard mask layer is patterned to form a preliminary hard mask pattern. steps; forming the first hard mask patterns by obliquely etching the first hard mask layer using the preliminary hard mask pattern as a mask; and forming the first trench by etching the lower hard mask layer using the first hard mask patterns as an etch mask.

In one embodiment of the present invention, forming inclined first hard mask patterns on a lower hard mask layer formed on a substrate and a first space between the first hard mask patterns includes: forming a first space between the first hard mask patterns on the substrate in order: Patterning the preliminary hard mask layer by forming a laminated conductive layer, a first lower hard mask layer, a second lower hard mask layer, a first hard mask layer, a preliminary hard mask layer, and a photoresist pattern on the preliminary hard mask layer. forming a preliminary hard mask pattern; forming the first hard mask patterns by obliquely etching the first hard mask layer using the preliminary hard mask pattern as a mask; and forming the first trench by etching the first lower hard mask layer using the first hard mask patterns as an etch mask.

A method of manufacturing a semiconductor device according to an embodiment of the present invention includes low dielectric films sequentially stacked on a substrate, first hard mask patterns inclined on the low dielectric film, and a first space between the first hard mask patterns. forming step; forming first trenches by anisotropically etching the low dielectric layer using the first hard mask patterns as an etch mask; forming second hard mask patterns lower than upper surfaces of the first hard mask patterns by filling the first trench and the first space; A third hard mask layer is coated or deposited on the first hard mask patterns and the second hard mask patterns and the third hard mask layer is removed to expose the first hard mask patterns to form a third hard mask pattern. forming them; forming divided first hard mask patterns by obliquely etching the first hard mask patterns using the third hard mask patterns as an etch mask; and forming low-dielectric patterns having a second trench by etching the low-dielectric layer using an etch mask for the third hard mask pattern, the divided second hard mask patterns, and the second hard mask patterns. there is.

In one embodiment of the present invention, forming a low dielectric film sequentially stacked on a substrate, first hard mask patterns inclined on the low dielectric film, and a first space between the first hard mask patterns include: Forming a preliminary hard mask pattern by forming an etch stop layer, a low dielectric layer, a first hard mask layer, a preliminary hard mask layer, and a photoresist pattern sequentially stacked on a substrate and patterning the preliminary hard mask layer; forming the first hard mask patterns by obliquely etching the first hard mask layer using the preliminary hard mask pattern as a mask; and forming the first trench by etching the low dielectric layer using the first hard mask patterns as an etch mask.

In one embodiment of the present invention, filling the first trench and the second trench between the low dielectric patterns with a conductive layer; and exposing upper surfaces of the low dielectric patterns using the conductive layer using a chemical mechanical polishing process.

In one embodiment of the present invention, further comprising an etch stop layer below the low dielectric layer, forming a first auxiliary trench by etching the etch stop layer after forming the first trench; and forming a second auxiliary trench by etching the etch stop layer after forming the second trench.

The multiple patterning method according to an embodiment of the present invention has high pattern alignment and can reduce costs through a simple process.

1A to 1H are cross-sectional views showing a method of manufacturing a semiconductor device according to an embodiment of the present invention.
Figure 2 is a SEM photograph illustrating a first trench according to an embodiment of the present invention and a cross-sectional view illustrating the corresponding structure.
Figure 3 is a SEM photograph illustrating a third hard mask layer according to an embodiment of the present invention and a cross-sectional view illustrating the corresponding structure.
FIG. 4 is a SEM photograph illustrating a divided first hard mask pattern according to an embodiment of the present invention and a cross-sectional view illustrating a corresponding structure.
Figure 5 is a cross-sectional view illustrating a planar SEM of a line/space pattern and the corresponding structure according to an embodiment of the present invention.
6A to 6I are cross-sectional views showing a semiconductor manufacturing method according to another embodiment of the present invention.
7A to 7I are cross-sectional views illustrating a method of manufacturing a semiconductor device according to another embodiment of the present invention.
8A to 8I are cross-sectional views illustrating a method of manufacturing a semiconductor device according to another embodiment of the present invention.
9A to 9J are diagrams showing a method of forming a gate line according to an embodiment of the present invention.
10A to 10J are diagrams showing a method of forming an STI according to an embodiment of the present invention.
11A to 11J are diagrams showing a damascene process for a metal line according to an embodiment of the present invention.

The SADP process using a typical spacer forms a thin film to cover the line pattern using atomic layer deposition (ALD) or CVD, and then forms a spacer on the sidewall of the line pattern formed by anisotropic etching.

In the photolithography process, photoresist application and development are performed through a spin coating process on track equipment. Track equipment is inexpensive and highly productive.

The multiple patterning of the present invention can provide low cost and high productivity using a spin coating process on track equipment.

In the case of the currently used SADP process, there are some differences depending on the progress of the process, but four thin film deposition processes are performed, and more than 10 processes, including atomic layer deposition (ALD), are performed to proceed with the spacer process. Atomic layer deposition (ALD) requires a lot of processing time.

In the case of the double patterning process according to an embodiment of the present invention, it can be simplified into four processes through Photo-Etch-Track(Pattern)-Etch. Accordingly, the process TaT (Turn Around Time) can be reduced and the process cost can be reduced. Additionally, the process precision may be greater than that of a typical SADP.

According to one embodiment of the present invention, like a typical SADP, the photolithography process can be performed only once and self-aligned without overlay issues. Additionally, by performing the same process twice, the effect of self-aligned quadruple patterning (SAQP) can be expected.

One object of the present invention is to form inclined first hard mask patterns and a first trench on the substrate using a first hard mask layer. A second hard mask pattern is deposited or coated by partially gap-filling the first space between the first trench and the first hard mask patterns with a second hard mask material by spin coating. Accordingly, the second hard mask pattern and the first hard mask pattern may have a step difference. The second hard mask pattern using spin coating exposes the upper surfaces of the first hard mask patterns. These steps can selectively form a third hard mask pattern. That is, a third hard mask layer is formed on the second hard mask pattern. The third hard mask layer has a flat top surface due to the spin coating characteristics. The upper surface of the third hard mask layer is removed to expose the first hard mask pattern, or a third hard mask pattern is formed through a planarization process.

The third hard mask pattern is divided by etching the first hard mask pattern using an etch mask, and the substrate is etched using the third hard mask pattern, the first hard mask pattern, and the second hard mask pattern as an etch mask to form a second hard mask pattern. Form a trench. The first trench and the second trench may provide self-aligned double patterning.

The second hard mask layer and the third hard mask layer may be formed by spin coating on track equipment. The first and second hard mask layers may be a carbon-based spin coating material (spin on carbon (SOC)). The third hard mask layer may be a Si-based spin coating material (or multi-functional hard mask). The selection ratio between the third hard mask and the first hard mask may be 1:10 or more. Accordingly, the thin third hard mask pattern can divide the first hard mask pattern by a high etch selectivity. The first hard mask layer and the second hard mask layer can provide high selectivity to the substrate.

The present invention can be implemented as a pattern having a line width (critical dimension (CD)) of 1/2 the line width of the photolithography process. For example, for ArF exposure, if the minimum linewidth is 40 nm, using the present invention, the minimum linewidth can be reduced to 20 nm.

Another object of the present invention is to perform primary patterning to form a first trench in a substrate through an exposure process and an etching process. A first hard mask pattern is formed through primary patterning. Partially gap fill the space between the remaining first hard mask patterns and the first trench with a new second hard mask, and between the remaining first hard mask pattern and the new second hard mask. The process is simplified by using the step difference for bottom patterning.

According to one embodiment of the present invention, the first hard mask can be either a spin coating hard mask or a thin film material hard mask. In the case of the second hard mask, a liquid hard mask material that provides spin coating in track equipment (or spin coating equipment) can be used. Additionally, in the case of the third hard mask, a liquid hard mask material that provides spin coating in spin coating equipment can be used.

According to one embodiment of the present invention, carbonyl sulfur compound (COS) gas can change the plasma etching characteristics of a carbon type hard mask layer. Typically, oxygen (O2) is used as a plasma etchant for a carbon-based hard mask layer. Oxygen plasma (O2 plasma) etching can provide a vertical profile. When carbonyl sulfide (COS) Gas, a new additive gas, is added to oxygen plasma, the etching pattern profile can form an inclined pattern. Therefore, the present invention can use oxygen plasma to which carbonyl sulfide (COS) gas is added to form an inclined hard mask pattern.

For example, plasma etching is performed while reducing the open area of the hard mask using COS gas. Even when etching the lower film, COS gas can be used to reduce the pattern, thereby forming half the pattern compared to the exposure process.

In the present invention, for convenience of explanation, the lower film material is mainly expressed as a silicon oxide film, but conductive materials (polysilicon, metal, metal silicide) for the implementation of the gate line, and silicon single crystal for the implementation of Shallow Trench Isolation (STI) It can be applied to both silicon oxide and silicon nitride films for implementing (Si) and metal wiring.

According to one embodiment of the present invention, if the SADP of the present invention is applied N times, the pattern can be continuously reduced.

According to one embodiment of the present invention, the inclined pattern of the first hard mask may be manufactured using sidewall forming technology by conformal deposition and anisotropic etching.

According to one embodiment of the present invention, in order to simplify the process and maximize the benefit in terms of TaT (turnaround time)/cost, a hard mask (first hard mask, second hard mask, third hard mask) is made of a material capable of spin coating. It may be desirable to form a hard mask). However, a second hard mask pattern may be formed using a vacuum deposition process and chemical mechanical polishing (CMP), etc.

The patterning method according to an embodiment of the present invention can be applied to all processes using existing SADP.

In one embodiment of the present invention, the third hard mask may be a Si-based spin coating material, and the second hard mask may be a carbon-based spin coating material. In this case, the second hard mask and the third hard mask may have a high etch selectivity. However, other materials may be selected as long as they provide high selectivity.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided so that the disclosure will be thorough and complete and so that the spirit of the invention can be sufficiently conveyed to those skilled in the art. In the drawings, elements are exaggerated for clarity. Parts indicated with the same reference numerals throughout the specification represent the same elements.

1A to 1H are cross-sectional views showing a method of manufacturing a semiconductor device according to an embodiment of the present invention.

Referring to FIGS. 1A to 1H , the method of manufacturing a semiconductor device may form a line pattern extending in parallel or an island pattern extending in parallel.

A method of manufacturing a semiconductor device includes forming inclined first hard mask patterns 120a on a substrate 110 and forming a first space 122 between the first hard mask patterns 120a; forming first trenches 112 by anisotropically etching the substrate 110 using the first hard mask patterns 120a as an etch mask; forming second hard mask patterns 150 lower than the upper surfaces of the first hard mask patterns 120a by filling the first trench 112 and the first space 122; A third hard mask layer 160 is coated or deposited on the second hard mask patterns 150 and the third hard mask layer 160 is removed to expose the upper surfaces of the first hard mask patterns 150. forming three hard mask patterns 162; etching the first hard mask patterns 120a using the third hard mask patterns 162 as an etch mask to form a second space and forming divided first hard mask patterns 120b; and etching the substrate 110 using at least one of the third hard mask patterns 162, the second hard mask patterns 150, and the divided first hard mask patterns 120b as an etch mask. and forming a second trench 114.

Referring to FIG. 1A, a first hard mask layer 120, a preliminary hard mask layer 130, and a photoresist pattern 140 are formed on the substrate 110. . A preliminary hard mask pattern 132 is formed by patterning the preliminary hard mask layer 130 using the photoresist pattern 140 as a mask. The line width of the photoresist pattern 140 may be the same as the line width of the preliminary hard mask pattern 132.

The substrate 110 may include a semiconductor substrate or a thin film formed on a semiconductor substrate. The thin film may be a single-layer or multi-layer insulating film, or a conductive film. The thin film may form the underlying structure of the device. The device may be a semiconductor device or an optical device.

The photoresist pattern 140 may be formed through a photo lithography process. The photo lithography process can use KrF equipment, ArF equipment, or EUV equipment. The line width of the photoresist pattern 140 may be a. The photoresist pattern 140 may be a line/space pattern.

The first hard mask layer 120 may be a spin coating layer containing carbon, an amorphous carbon layer (armophous carbon layer, ACL), or polyimide. Preferably, the first hard mask layer 120 is a spin-coated carbon-based hard mask, and the carbon content may be 80 percent or more.

The preliminary hard mask layer 130 may be a spin coating layer containing silicon or a SiON material. The preliminary hard mask layer 130 may form the preliminary hard mask pattern 132 by plasma anisotropic etching. Preferably, the preliminary hard mask layer 130 may be a spin coating layer containing silicon or a spin coating Si-hard mask.

Referring to FIG. 1B, the first hard mask layer 120 is obliquely etched using the preliminary hard mask pattern 132 as a mask to form the first hard mask patterns 120a. While forming the first hard mask patterns 120a, the photoresist pattern 140 may be removed simultaneously. The inclined etching may be performed by oxygen plasma to which carbonyl sulfur compound (CARBONYL SULFIDE, COS) is added. By the inclined etching, the inclined first hard mask patterns 120a and the first space 122 between the first hard mask patterns may be formed. When the line width of the preliminary hard mask pattern 132 is a and the upper line width of the first space 122 is a, the line width W1 of the lower surface of the first space 122 may be a/2. .

Referring to FIG. 1C, inclined first hard mask patterns 120a and a first space 122 between the first hard mask patterns 120a are formed on the substrate 110. First trenches 112 are formed by anisotropically etching the substrate 110 using the preliminary hard mask pattern 132 and the first hard mask patterns 120a as an etch mask. The first trench 112 may be etched vertically. The preliminary hard mask pattern 132 may be removed simultaneously while forming the first trenches 112 . For example, if the substrate 110 includes a silicon oxide film, plasma etching using a CxFy series gas may be used to etch the silicon oxide film. The width of the first trench 112 may be a/2.

Referring to FIG. 1D , the first trench 112 and the first space 122 are filled to form second hard mask patterns 150 that are lower than the upper surfaces of the first hard mask patterns 120a. Accordingly, the upper surfaces of the second hard mask patterns 150 are lower than the upper surfaces of the first hard mask patterns 120 and have a step difference. This step may be tens of nm or more. The second hard mask patterns 150 may be formed by carbon-based spin coating. Accordingly, the upper surface of the second hard mask patterns 150 can fill the lower part of the first space 122 with a constant height. Additionally, the material of the second hard mask patterns 150 may be the same as the material of the first hard mask pattern 120a.

A third hard mask layer 160 is deposited or coated on the second hard mask patterns 150. The third hard mask layer 160 may be formed by spin coating a material containing silicon. By spin coating, the upper surface of the third hard mask layer 160 can be flattened. The third hard mask layer 160 may fill the step.

Referring to FIG. 1E, the third hard mask layer 160 is removed to expose the upper surfaces of the first hard mask patterns 120a to form third hard mask patterns 162. Partial removal of the third hard mask layer 160 may be performed by a planarization process such as etch back or CMP. The top surface of the third hard mask patterns 162 may be substantially the same as the top surface of the first hard mask patterns 120.

Referring to FIG. 1F, the first hard mask patterns 120 are obliquely etched using the third hard mask patterns 162 as an etch mask to create a second space 124 and divided first hard mask patterns ( 120b) can be formed. The cross-section of the divided first hard mask patterns 120b may have an isoplanar triangular shape.

Oblique etching can be performed by oxygen plasma to which carbonyl sulfur compound (CARBONYL SULFIDE, COS) is added. By the inclined etching, the divided first hard mask patterns 120b and the second space 124 between the divided first hard mask patterns may be formed. The line width of the upper surface of the second space 124 may be a, and the line width of the lower surface of the second space 124 may be a/2.

Referring to FIG. 1G, at least one of the third hard mask patterns 162, the second hard mask patterns 150, and the divided first hard mask patterns 120a is used as an etch mask on the substrate. The second trench 114 may be formed by etching 110 .

For example, the third hard mask patterns 162 may be removed while forming the second trench 114 . In the etching process for forming the second trench, after the third hard mask patterns 162 are removed, the second hard mask patterns 150 and the divided first hard mask patterns 120b are etched. The second trench 114 may be formed by continuously etching the substrate 110 using a mask. The second trench 114 may be formed by vertical etching. The line width of the second trench 114 may be a/2. The depth of the first trench may be the same as the depth of the second trench. Accordingly, the substrate may include a first trench 112 with a line width of a/2 and a second trench 114 with a line width of a/2. The depth of the first trench 112 may be the same as the depth of the second trench 114. Accordingly, a periodic line pattern may be formed on the substrate. The substrate can provide lines with a line width of a/2 and spaces with a line width of a/2.

Referring to FIG. 1H, the divided first hard mask patterns 120b and the second hard mask patterns 150 are removed to expose the first trench 112 and the second trench 114. You can. If the divided first hard mask patterns 120b and the second hard mask pattern 150 are spin coating layers containing carbon, they may be removed by oxygen plasma.

The substrate 110 may include a first trench 112 with a line width of a/2 and a second trench 114 with a line width of a/2. Alternatively, the substrate may provide a line with a line width of a/2 and a space with a line width of a/2. When the lines of the substrate are conductors, they can be used as patterns for conductive lines. Meanwhile, if the line is a dielectric, it can be used for a damascene process in which the trenches 112 and 114 are filled with a conductor and then planarized using CMP.

The conductive line may include at least one of an active region made of a semiconductor, a gate line including a conductor, a bit line including a conductor, and a wiring line including a conductor. Additionally, this line structure can be used as an optical element as a grating.

Figure 2 is a SEM photograph illustrating a first trench according to an embodiment of the present invention and a cross-sectional view illustrating the corresponding structure.

Referring to FIG. 2, the line width of the upper surface of the first hard mask pattern 120a is a (40 nm), the line width of the upper surface of the first space 122 is a, and the lower main surface of the first space 122 is a. The line width is a/2. Accordingly, the height of the first hard mask pattern 120a is given as a/4 tan(θ). The inclination angle (θ) may be 80 degrees or more. Preferably, the tilt angle (θ) may be 83 degrees to 86 degrees. The height (t) of the first hard mask pattern is greater than the line width (a) of the upper surface of the first hard mask pattern and may be 130 nm. More preferably, the tilt angle (θ) may be 84 degrees to 85 degrees.

Figure 3 is a SEM photograph illustrating a third hard mask layer according to an embodiment of the present invention and a cross-sectional view illustrating the corresponding structure.

FIG. 4 is a SEM photograph illustrating a divided first hard mask pattern according to an embodiment of the present invention and a cross-sectional view illustrating a corresponding structure.

Referring to FIGS. 3 and 4 , the etch selectivity of the third hard mask pattern 162 formed by spin coating containing silicon and the first hard mask pattern 120a containing carbon may be 10:1 or more. Preferably, the etch selectivity may be 30:1 or more. Accordingly, the step difference d between the first hard mask pattern 120a and the second hard mask pattern 150 or the height of the third hard mask pattern 162 is 1/10 of the height of the first hard mask pattern 120a. It could be at the ship level. For example, when the height (t) of the first hard mask pattern 120a is 130 nm, the step (d) may be 13 nm.

When the height (t) of the first hard mask pattern 120a is 1a to 3a, the height (d) of the third hard mask pattern is 1/10 of the height (t) of the first hard mask pattern. You can.

The inclination angle (θ’) of the divided first hard mask pattern 120b may be the same as the inclination angle (θ) of the first hard mask pattern before division. Accordingly, the width of the second trench 114 may be a/2.

Figure 5 is a cross-sectional view illustrating a planar SEM of a line/space pattern and the corresponding structure according to an embodiment of the present invention.

Referring to FIG. 5, the line width (a) of the line/space pattern is a 40 nm pattern, and through ArF Immersion, the line width was reduced by half based on the 40 nm PR pattern to realize a CD of 18 nm per line. The substrate is a silicon oxide film.

6A to 6I are cross-sectional views showing a semiconductor manufacturing method according to another embodiment of the present invention.

6A to 6I, the method of manufacturing a semiconductor device includes first hard mask patterns 220a inclined on a substrate 110 and a first space between the first hard mask patterns 220a. Forming 222); forming first trenches 112 by anisotropically etching the substrate 110 using the first hard mask patterns 220a as an etch mask; forming second hard mask patterns 150 lower than the upper surfaces of the first hard mask patterns 220a by filling the first trench 112 and the first space 222; A third hard mask layer 160 is coated or deposited on the second hard mask patterns 150, and the upper surfaces of the first hard mask patterns 220a are exposed to the third hard mask layer 160. forming third hard mask patterns 162 by removing them as much as possible; The first hard mask patterns 220a are obliquely etched using the third hard mask patterns 162 as an etch mask to form a second space 224 and form divided first hard mask patterns 220b. steps; and etching the substrate using at least one of the third hard mask patterns 162, the second hard mask patterns 150, and the divided first hard mask patterns 220b as an etch mask to form a second trench. It includes forming (114).

6A and 6B, forming inclined first hard mask patterns 220a on a substrate 110 and a first space 222 between the first hard mask patterns includes forming the first hard mask patterns 220a on the substrate 110. The preliminary hard mask layer 130 is formed by forming a first hard mask layer 220, a preliminary hard mask layer 130, and a photoresist pattern 140 on the preliminary hard mask layer, which are sequentially stacked on (110). patterning to form a preliminary hard mask pattern 132; forming first hard mask patterns 221 by vertically etching the first hard mask layer 120 using the preliminary hard mask patterns 132 as an etch mask; A conformal thin film is deposited to cover the first hard mask patterns 221 and the thin film is anisotropically etched to provide an inclined sidewall 221a on the sidewall of the first hard mask patterns 221 to form an inclined first hard mask. forming mask patterns 220a; and forming the first trench 112 by etching the substrate using the inclined first hard mask patterns 220a as an etch mask.

The substrate 110 may include a semiconductor substrate or a thin film formed on a semiconductor substrate. The thin film may be an insulating film or a conductive film. The photoresist pattern 140 may be formed through a photo lithography process. The preliminary hard mask layer 130 may be a spin coating layer containing silicon. The first hard mask layer 120 may be a spin coating layer containing carbon.

A first hard mask layer 120, a preliminary hard mask layer 130, and a photoresist pattern 140 are formed on the substrate 110. The preliminary hard mask layer 130 is etched using the photoresist pattern 140 as a mask to form a preliminary hard mask pattern 132. The first hard mask layer 120 is vertically etched using the preliminary hard mask pattern 132 as an etch mask to form the first hard mask pattern 221.

Referring to FIG. 6B, the preliminary hard mask layer is etched using the photoresist pattern 140 as a mask to form the preliminary hard mask patterns 132. First hard mask patterns 221 may be formed by vertically etching the first hard mask layer 120 using the preliminary hard mask patterns 132 as an etch mask.

Referring to FIG. 6C, a conformal thin film is deposited to cover the first hard mask patterns 221 and the thin film is anisotropically etched to form a side wall having an inclination on the side wall of the first hard mask patterns 221. By providing 221a, inclined first hard mask patterns 220a can be formed. The material of the conformal thin film may be an amorphous carbon layer. Accordingly, the material of the sidewall 221a may be substantially the same as the material of the first hard mask patterns 221.

Referring to FIG. 6D , the first trench 112 may be formed by etching the substrate using the inclined first hard mask patterns 220a as an etch mask.

Referring to FIG. 6E, the first trench 112 and the first space 222 may be filled to form second hard mask patterns 150 that are lower than the upper surfaces of the first hard mask patterns 220a. there is. The second hard mask patterns 150 may be a spin coding layer containing carbon.

Referring to FIG. 6F, a third hard mask layer is deposited or coated on the second hard mask patterns 150 and the third hard mask layer 160 is applied to the upper part of the first hard mask patterns 220a. Third hard mask patterns 162 can be formed by removing the surface to expose it. The third hard mask layer may be a spin coating layer containing silicon.

Referring to FIG. 6G, the first hard mask patterns 220a are obliquely etched using the third hard mask patterns 162 as an etch mask to form a second space 224, and the first hard mask pattern is divided. Fields 220b may be formed.

According to a modified embodiment, the first hard mask patterns 220a are vertically etched using the third hard mask patterns 162 as an etch mask to form a second space 224 and the divided first hard mask is formed. Patterns 220b may be formed. Next, sidewalls may be formed on the first hard mask patterns 220b to form inclined first hard mask patterns 220b.

Referring to FIGS. 6H and 6I, at least one of the third hard mask patterns 162, the second hard mask patterns 150, and the divided first hard mask patterns 220b is used as an etch mask. The second trench 114 may be formed by etching the substrate.

Subsequently, the third hard mask patterns, the second hard mask patterns, and the divided first hard mask patterns may be removed using oxygen plasma.

7A to 7I are cross-sectional views illustrating a method of manufacturing a semiconductor device according to another embodiment of the present invention.

Referring to FIGS. 7A to 7I , the method of manufacturing a semiconductor device includes forming inclined first hard mask patterns 120a on a lower hard mask layer 330 formed on a substrate 310 and the first hard mask patterns. forming a first space 122 between (120a); forming first trenches 332 by anisotropically etching the lower hard mask layer 330 using the first hard mask patterns 120a as an etch mask; forming second hard mask patterns 150 lower than the upper surfaces of the first hard mask patterns 120a by filling the first trench 332 and the first space 122; A third hard mask layer 160 is coated or deposited on the second hard mask patterns 150 and the third hard mask layer 160 is removed to expose the first hard mask patterns 120a. forming third hard mask patterns 162; The first hard mask patterns 120a are obliquely etched using the third hard mask patterns 162 as an etch mask to form a second space 124 and form divided first hard mask patterns 120b. steps; and the lower hard mask layer 330 using at least one of the third hard mask patterns 162, the divided first hard mask patterns 120b, and the second hard mask patterns 150. Anisotropic etching to form a second trench 334 and forming lower hard mask patterns 330b including the first trench 332 and the second trench 334.

The lower hard mask layer 330 may be double patterned and used as part of a device, or may be used as a hard mask to form a structure under the lower hard mask layer 330. When the lower hard mask layer 330 is used, it can be used in a device isolation film process, a FINFET FIN formation process, a word line, a bit line, and a metal line process. Alternatively, the lower hard mask layer can be used in a quadruple patterning process.

A process for a quadruple patterning process is described.

Referring to FIG. 7A, a main hard mask layer 320, a lower hard mask layer 330, a first hard mask layer 120, a preliminary hard mask layer 130, and A photoresist pattern 140 may be formed.

The main hard mask layer 320 may be a spin coating layer containing carbon. The lower hard mask layer 330 may be a spin coating layer containing silicon. The first hard mask layer 120 may be a spin coating layer containing carbon. The preliminary hard mask layer 130 may be a spin coating layer containing silicon.

To repeat double patterning twice, spin coating layers containing carbon/spin coating layers containing silicon may be alternately stacked on the substrate 310. The main hard mask layer 320 and the first hard mask layer 120 are spin coating layers containing carbon and are made of the same material and may have different thicknesses. The lower hard mask layer 330 and the preliminary hard mask layer 130 are spin coating layers containing silicon and may be made of the same material and have the same thickness.

Referring to FIGS. 7B and 7C , first hard mask patterns 120a inclined on the lower hard mask layer 330 formed on the substrate 310 and the first hard mask patterns 120a between the first hard mask patterns 120a. The step of forming the space 122 includes the main hard mask layer 320, the lower hard mask layer 330, the first hard mask layer 120, and the preliminary hard mask layer ( 130), and forming a photoresist pattern 140 and patterning the preliminary hard mask layer 130 to form a preliminary hard mask pattern 132; forming the first hard mask patterns 120a by obliquely etching the first hard mask layer 120 using the preliminary hard mask pattern 132 as a mask; and forming the first trench 332 by etching the lower hard mask layer 330 using the first hard mask patterns 120a as an etch mask.

Referring to FIG. 7D, the first trench 332 and the first space 122 may be filled to form second hard mask patterns 150 that are lower than the upper surfaces of the first hard mask patterns 120a. there is.

Referring to FIGS. 7D and 7E, a third hard mask layer 160 is coated or deposited on the second hard mask patterns 120a, and the third hard mask layer 160 is applied to the first hard mask pattern. The third hard mask patterns 162 may be formed by removing the areas 120a to expose them.

Referring to FIG. 7F, the first hard mask patterns 120a are obliquely etched using the third hard mask patterns 162 as an etch mask to form a second space 124, and the first hard mask pattern is divided. Fields 120b may be formed.

Referring to FIG. 7G, the lower hard mask pattern is formed using at least one of the third hard mask patterns 162, the divided first hard mask patterns 120b, and the second hard mask patterns 150. The mask layer 330a may be anisotropically etched to form a second trench 334 and lower hard mask patterns 330b including the first trench and the second trench.

The lower hard mask patterns 330b may be used to pattern a thin film or substrate disposed below the lower hard mask patterns 330b.

Referring to FIG. 7H, the second trench 334 and the second space 124 between the lower hard mask patterns 330b are formed with a gap fill material 390 made of the same material as the first hard mask layer 120. It can be filled. The gap fill material 390 may be a spin coating layer containing carbon. The gap fill material 390 may be the same as the material of the first hard mask layer.

Referring to FIG. 7I, the gap fill material 390, the first hard mask patterns 120b, and the second hard mask patterns 150 are etched to expose the lower hard mask patterns 330b. You can. The gap fill material 390, the first hard mask patterns 120b, and the second hard mask patterns 150 may be a spin coating material containing the same carbon. Accordingly, the etch-back process exposes the lower hard mask patterns 330b. Accordingly, the gap fill material 390a can prevent damage to the main hard mask layer 320. Accordingly, the line width of the lower hard mask pattern 330b is reduced by half according to the double patterning process.

The lower hard mask pattern 330b can be used in a quadruple patterning process by reapplying the double patterning process to the main hard mask layer below it.

8A to 8I are cross-sectional views illustrating a method of manufacturing a semiconductor device according to another embodiment of the present invention.

Referring to FIGS. 7I and 8A to 8I , the main hard mask layer 320 is etched using the lower hard mask patterns 330b as an etch mask to form inclined first main hard mask patterns 320a and the forming a first main space 322 between first main hard mask patterns 320a; forming first main trenches 312 by anisotropically etching the substrate 310 using the first main hard mask patterns 320a as an etch mask; forming second main hard mask patterns 350 lower than the upper surfaces of the first main hard mask patterns 320a by filling the first main trench 312 and the first main space 322; A third main hard mask layer 360 is deposited on the second main hard mask patterns 350 and the third main hard mask layer 360 is exposed so that the first main hard mask patterns 320a are exposed. forming third main hard mask patterns 362 by removing them; The first main hard mask patterns 320a are obliquely etched using the third main hard mask patterns 362 as an etch mask to form a second main space 324 and divide the first main hard mask patterns ( Forming 320b); and the substrate 310 using at least one of the third main hard mask patterns 362, the divided first main hard mask patterns 320b, and the second main hard mask patterns 350. The step of forming the second main trench 314 by anisotropically etching may be further included.

Referring to FIGS. 7I and 8A , the main hard mask layer 320, the lower hard mask patterns 330b, and the first trench 332 between the lower hard mask patterns 330b are formed on the substrate 310. ) and a gap fill material 390a that fills the second trench 334 is disposed.

Referring to FIGS. 8B and 8C, the main hard mask layer 320 is etched using the lower hard mask patterns 330b as an etch mask to form inclined first main hard mask patterns 320a and the first main hard mask pattern 320b. A first main space 322 is formed between the hard mask patterns. The inclination angle θ' of the first main hard mask patterns 320a may be 84 degrees. The height (t') of the first main hard mask patterns may be 1/2 of the height (t) of the first hard mask patterns 120b.

According to a modified embodiment, when the inclination angle (θ') is given, the height (t') of the first main hard mask patterns is given as follows. a is the line width of the first PR pattern.

[Equation 1]

t'=a/8 tan(θ')

Referring to FIG. 8C, the substrate 310 is etched using the first main hard mask patterns 320a as an etch mask to form a first main trench 312. The width of the first main trench 312 is a/4.

Referring to FIG. 8D, second main hard mask patterns 350 fill the first main trench 312 and the first main space 322 and are lower than the upper surfaces of the first main hard mask patterns 320a. can be formed. The second main hard mask patterns 350 may be a carbon-containing spin coating layer.

Referring to FIGS. 8E and 8F, a third main hard mask layer 360 is coated or deposited on the second main hard mask patterns 320a, and the third main hard mask layer is applied to the first main hard mask. Third main hard mask patterns 362 may be formed by removing the patterns 320a to expose them. The third main hard mask layer 360 may be a silicon-containing spin coating layer.

Referring to FIG. 8G, the first main hard mask patterns 320a are obliquely etched using the third main hard mask patterns 362 as an etch mask to form a second main space 324 and divide the first main space 324. Main hard mask patterns 320b may be formed.

Referring to FIG. 8H, using at least one of the third main hard mask patterns 362, the divided first main hard mask patterns 320b, and the second main hard mask patterns 350. The substrate 310 is anisotropically etched to form a second main trench 314 and main hard mask patterns including the first main trench and the second main trench. The width of the first main trench and the second main trench may be a/4.

Referring to FIG. 8I, the third main hard mask patterns 362, the divided first main hard mask patterns 320b, and the second main hard mask patterns 350 are removed to create a first The main trench 312 and the second main trench 314 are exposed. Accordingly, the line width of the line may be a/4. A quadruple pattern is performed.

The quadruple pattern can be used in semiconductor devices and optical devices in the same way as the double pattern.

9A to 9J are diagrams showing a method of forming a gate line according to an embodiment of the present invention.

Referring to FIGS. 9A to 9J, the method for manufacturing a semiconductor device according to an embodiment of the present invention is:

forming inclined first hard mask patterns 120a on the lower hard mask layer 440 formed on the substrate 410 and a first space 122 between the first hard mask patterns 120a; forming first trenches 442 by anisotropically etching the lower hard mask layer 440 using the first hard mask patterns 120a as an etch mask; forming second hard mask patterns 150 lower than the upper surfaces of the first hard mask patterns 120a by filling the first trench 442 and the first space 122; A third hard mask layer 160 is coated or deposited on the second hard mask patterns 150 and the third hard mask layer is removed to expose the first hard mask patterns 120a. forming mask patterns 162; The first hard mask patterns 120a are obliquely etched using the third hard mask patterns 162 as an etch mask to form a second space 124 and form divided first hard mask patterns 120b. steps; The lower hard mask layer 440a is formed using at least one of the third hard mask patterns 162, the divided first hard mask patterns 120b, and the second hard mask patterns 150. It includes forming a second trench 444 by anisotropic etching and forming lower hard mask patterns 440b including the first trench and the second trench.

Referring to FIG. 9A, a conductive layer 420, a first lower hard mask layer 430, a second lower hard mask layer 440, a first hard mask layer 120, are sequentially stacked on a substrate 410. A preliminary hard mask layer 130 and a photoresist pattern 140 may be formed. The conductive layer may be doped polysilicon or metal.

The conductive layer 420 may include at least one of a doped polysilicon layer and a metal layer. The conductive layer can be patterned and used as a gate line, word line, or bit line.

The first lower hard mask layer 430 may be a silicon nitride film or a silicon oxynitride film. The second lower hard mask layer 440 may be a polysilicon or silicon oxide film. The first hard mask layer 120 may be a carbon-containing spin coating layer. The preliminary hard mask layer 130 may be a silicon-containing spin coating layer.

The step of forming inclined first hard mask patterns 120a on the lower hard mask layer 440 formed on the substrate 410 and a first space 122 between the first hard mask patterns 120a includes: , a conductive layer 420, a first lower hard mask layer 430, a second lower hard mask layer 440, a first hard mask layer 120, and a preliminary hard mask layer sequentially stacked on the substrate 410. (130), and forming a photoresist pattern 140 to pattern the preliminary hard mask layer 130 to form a preliminary hard mask pattern 132; forming the first hard mask patterns 120a by obliquely etching the first hard mask layer 120 using the preliminary hard mask pattern 132 as a mask; and forming the first trench 442 by etching the second lower mask layer 440 using the first hard mask patterns 120a as an etch mask.

Referring to FIG. 9B, the preliminary hard mask layer 130 may be patterned to form the preliminary hard mask pattern 132. Subsequently, the first hard mask layer 120 may be obliquely etched using the preliminary hard mask pattern 132 as a mask to form the first hard mask patterns 120a.

Referring to FIG. 9C, the first trench 442 may be formed by etching the second lower mask layer 440 using the first hard mask patterns 120a as an etch mask.

Referring to FIG. 9D, second hard mask patterns 150 are formed by filling the first trench 442 and the first space 122 to be lower than the upper surfaces of the first hard mask patterns 120a. You can.

Referring to FIG. 9E, a third hard mask layer 160 is deposited or coated on the second hard mask patterns 150, and the first hard mask patterns 120a are exposed to the third hard mask layer. Third hard mask patterns 162 can be formed by removing as much as possible.

Referring to FIG. 9F, the first hard mask patterns 120a are obliquely etched using the third hard mask patterns 162 as an etch mask to form a second space 124 and the divided first hard mask pattern. Fields 120b may be formed.

Referring to FIG. 9G, the second hard mask pattern is formed using at least one of the third hard mask patterns 162, the divided first hard mask patterns 120b, and the second hard mask patterns 150. The lower hard mask layer 440a is anisotropically etched to form a second trench 444 and second lower hard mask patterns 440b including the first trench 442 and the second trench 444 are formed. You can.

Referring to FIG. 9H, the first lower mask layer 430 and the conductive layer 420 are etched using the second lower hard mask patterns 440b as an etch mask to form the first lower mask pattern 430a and the conductive line. A pattern 420a may be formed. The second lower hard mask patterns 440b may be removed simultaneously when the conductive layer 420 is etched.

Referring to FIGS. 9I and 9J , sidewalls 422 may be formed on sidewalls of the first lower mask pattern 430a and the conductive line pattern 420. Subsequently, after filling the space of the first lower mask pattern 430a and the conductive line pattern 420 with an insulator, the self-aligned contact process may be performed.

10A to 10J are diagrams showing a method of forming an STI according to an embodiment of the present invention.

10A to 10J, the substrate processing method according to an embodiment of the present invention includes first hard mask patterns 120a inclined on the lower hard mask layer 540 formed on the substrate 510, and the forming a first space 122 between first hard mask patterns 120a; forming first trenches 542 by anisotropically etching the lower hard mask layer 540 using the first hard mask patterns 120a as an etch mask; forming second hard mask patterns 150 lower than the upper surfaces of the first hard mask patterns 120a by filling the first trench 542 and the first space 122; A third hard mask layer 160 is coated or deposited on the second hard mask patterns 150 and the third hard mask layer 160 is removed to expose the first hard mask patterns 120a. forming third hard mask patterns 162; The first hard mask patterns 120a are obliquely etched using the third hard mask patterns 162 as an etch mask to form a second space 124 and form divided first hard mask patterns 120b. steps; A second trench 544 is formed by anisotropically etching the lower hard mask layer 540a using at least one of the third hard mask patterns, the divided first hard mask patterns, and the second hard mask patterns. and forming lower hard mask patterns 540b including the first trench and the second trench.

Referring to FIG. 10A, a silicon oxide layer 530, a lower hard mask layer 540, a first hard mask layer 120, a preliminary hard mask layer 130, and a photo layer are sequentially stacked on the substrate 510. A resist pattern 140 is formed.

The lower hard mask layer 540 may be a silicon nitride film or a polysilicon film. The first hard mask layer 120 may be a carbon-containing spin coating layer. The preliminary hard mask layer 130 may be a silicon-containing spin coating layer.

Forming inclined first hard mask patterns 120a on the lower hard mask layer 540 formed on the substrate 510 and a first space 122 between the first hard mask patterns 120a includes: , a silicon oxide layer 530, a lower hard mask layer 540, a first hard mask layer 120, a preliminary hard mask layer 130, and a photoresist pattern 140 sequentially stacked on the substrate 510. forming a preliminary hard mask pattern 132 by patterning the preliminary hard mask layer 130; forming the first hard mask patterns 120a by obliquely etching the first hard mask layer 120 using the preliminary hard mask pattern 132 as a mask; and forming the first trench 542 by etching the lower hard mask layer 540 using the first hard mask patterns 120a as an etch mask.

Referring to FIG. 10B, the preliminary hard mask layer 130 may be patterned to form the preliminary hard mask pattern 132. Subsequently, the first hard mask layer 120 may be obliquely etched using the preliminary hard mask pattern 132 as a mask to form the first hard mask patterns 120a.

Referring to FIG. 10C, the lower mask layer 540 may be etched using the first hard mask patterns 120a as an etch mask to form the first trench 542.

Referring to FIG. 10D, second hard mask patterns 150 that are lower than the upper surfaces of the first hard mask patterns 120a may be formed by filling the first trench 542 and the first space 122. there is.

Referring to FIG. 10E, a third hard mask layer 160 is deposited or coated on the second hard mask patterns 150 and the first hard mask patterns 120a are exposed to the third hard mask layer. Third hard mask patterns 162 can be formed by removing as much as possible.

Referring to FIG. 10F, the first hard mask patterns 120a are obliquely etched using the third hard mask patterns 162 as an etch mask to form a second space 124 and the divided first hard mask pattern. Fields 120b may be formed.

Referring to FIG. 10G, the second hard mask pattern is formed using at least one of the third hard mask patterns 162, the divided first hard mask patterns 120b, and the second hard mask patterns 150. The lower hard mask layer 540a may be anisotropically etched to form a second trench 544 and lower hard mask patterns 540b including the first trench 542 and the second trench 544. .

Referring to FIG. 10I , the silicon oxide layer 530 and the substrate 510 may be etched using the lower hard mask patterns 540b as an etch mask. Accordingly, the silicon oxide layer pattern 530a and the substrate trench 512 may be formed, respectively.

Referring to FIG. 10J, after filling the substrate trench 512 and the space above it with silicon oxide 501, a chemical-mechanical polishing process may be performed to expose the lower hard mask pattern 540b. Subsequently, the lower hard mask pattern 540b may be removed to form a device isolation layer. The area outside the substrate trench may provide an active area.

11A to 11J are diagrams showing a damascene process for a metal line according to an embodiment of the present invention.

Referring to FIGS. 11A to 11J, the substrate processing method according to an embodiment of the present invention includes a low-k dielectric film 640 sequentially stacked on a substrate 610 and a first hard mask inclined on the low-k dielectric film 640. forming a first space 122 between patterns 120a and the first hard mask patterns 120a; forming first trenches 642 by anisotropically etching the low dielectric layer 640 using the first hard mask patterns 120a as an etch mask; forming second hard mask patterns 150 by filling the first trench 642 and the first space 122 to be lower than the upper surfaces of the first hard mask patterns 120a; A third hard mask layer 160 is coated or deposited on the first hard mask patterns 120a and the second hard mask patterns 150, and the third hard mask layer is applied to the first hard mask patterns 120a. forming third hard mask patterns 162 by removing (120a) to expose; forming divided first hard mask patterns 120b by obliquely etching the first hard mask patterns 120a using the third hard mask patterns 162 as an etch mask; and etching the low-k dielectric layer 642a using an etch mask for the third hard mask pattern 162, the divided first hard mask patterns 120b, and the second hard mask patterns 150 to form a second trench ( It includes forming low dielectric patterns 640b having 644).

Referring to FIG. 11A, on the substrate 610, an interlayer insulating film 620, an etch stop film 630, a low dielectric film 640, a first hard mask layer 120, a preliminary hard mask layer 130, and A photoresist pattern 140 is formed.

The interlayer insulating film 620 may be a silicon oxide film. The etch stop layer 630 may be a silicon nitride layer. The low dielectric film 640 may be a low dielectric film such as a silicon oxide film or a silicon oxynitride film. The first hard mask layer 120 may be a carbon-containing spin coating layer. The preliminary hard mask layer 130 may be a silicon-containing spin coating layer.

A low dielectric film 640 sequentially stacked on the substrate 610, first hard mask patterns 120a inclined on the low dielectric film, and a first space 122 between the first hard mask patterns 120a. The forming step includes an etch stop film 630, a low dielectric film 640, a first hard mask layer 120, a preliminary hard mask layer 130, and a photoresist pattern ( 140) to form a preliminary hard mask pattern 132 by patterning the preliminary hard mask layer 130; forming the first hard mask patterns 120a by obliquely etching the first hard mask layer 120 using the preliminary hard mask pattern 132 as a mask; and The method may include forming the first trench 642 by etching the low dielectric layer 640 using the first hard mask patterns 120a as an etch mask.

Referring to FIG. 11B, the preliminary hard mask layer 130 may be patterned to form the preliminary hard mask pattern 132. Subsequently, the first hard mask layer 120 may be obliquely etched using the preliminary hard mask pattern 132 as a mask to form the first hard mask patterns 120a.

Referring to FIGS. 11C and 11D , the low dielectric layer 640 may be etched using the first hard mask patterns 120a as an etch mask to form the first trench 642. Accordingly, the low dielectric pattern 640a can be formed.

An etch stop layer 630 may be disposed below the low dielectric layer 640. After forming the first trench 642, the etch stop layer 630 may be etched to form a first auxiliary trench 632.

Referring to FIG. 11E, the first trench 642, the first auxiliary trench 632, and the first space 122 are filled to be lower than the upper surfaces of the first hard mask patterns 120a to form a second hard mask. Mask patterns 150 may be formed.

Referring to FIG. 11F, a third hard mask layer 160 is deposited or coated on the second hard mask patterns 150, and the first hard mask patterns 120a are exposed through the third hard mask layer. Third hard mask patterns 162 can be formed by removing as much as possible.

Referring to FIG. 11g, the first hard mask patterns 120a are obliquely etched using the third hard mask patterns 162 as an etch mask to form a second space 124 and the divided first hard mask pattern. Fields 120b may be formed.

Referring to FIG. 11H, the low dielectric layer is formed using at least one of the third hard mask patterns 162, the divided first hard mask patterns 120b, and the second hard mask patterns 150. 640a may be anisotropically etched to form a second trench 644 and low dielectric patterns 640b including the first trench 642 and the second trench 644 may be formed. After forming the second trench 644, the step of forming a second auxiliary trench 634 by etching the etch stop layer 630a may be further included.

Referring to FIG. 11I, the third hard mask patterns 162, the divided first hard mask patterns 120b, and the second hard mask patterns 150 may be removed by oxygen plasma. .

Referring to FIG. 11J, filling the first trench 642 and the second trench 644 between the low dielectric patterns 640b with a conductive layer 690; and exposing upper surfaces of the low dielectric patterns of the conductive layer 690 using a chemical mechanical polishing process.

Although the present invention has been shown and described with respect to specific preferred embodiments, the present invention is not limited to these embodiments, and the technical idea of the present invention as claimed in the claims by a person skilled in the art to which the invention pertains It includes various types of embodiments that can be implemented without departing from the scope.

110: substrate
112: first trench
114: second trench
120a: first hard mask patterns
122: First space
150: Second hard mask patterns
162: Third hard mask patterns

Claims (24)

forming inclined first hard mask patterns on a substrate and a first space between the first hard mask patterns;
forming first trenches by anisotropically etching the substrate using the first hard mask patterns as an etch mask;
forming second hard mask patterns having a lower height than the upper surfaces of the first hard mask patterns by filling the first trench and the first space;
forming third hard mask patterns by coating or depositing a third hard mask layer on the second hard mask patterns and removing the third hard mask layer to expose upper surfaces of the first hard mask patterns;
etching the first hard mask patterns using the third hard mask patterns as an etch mask to form a second space and forming divided first hard mask patterns; and
forming a second trench by etching the substrate using at least one of the third hard mask patterns, the second hard mask patterns, and the divided first hard mask patterns as an etch mask. Manufacturing method. According to claim 1,
A method of manufacturing a semiconductor device, wherein the first hard mask patterns are made of a material containing carbon and are formed by spin coating. According to claim 1,
A method of manufacturing a semiconductor device, wherein the second hard mask patterns are made of a material containing carbon and are formed by spin coating. According to claim 1,
A method of manufacturing a semiconductor device, wherein the third hard mask patterns are silicon-based and formed by spin coating. According to claim 1,
A method of manufacturing a semiconductor device, wherein the width of the first trench and the width of the second trench are the same. According to claim 1,
A method of manufacturing a semiconductor device, characterized in that the thickness of the third hard mask patterns is 1/10 or more of the thickness of the first hard mask pattern. According to claim 1,
A method of manufacturing a semiconductor device, characterized in that the inclination angle of the first hard mask patterns is 80 degrees to 87 degrees. According to claim 1,
Forming inclined first hard mask patterns on a substrate and a first space between the first hard mask patterns includes:
forming a photoresist pattern on a first hard mask layer, a preliminary hard mask layer, and the preliminary hard mask layer sequentially stacked on the substrate, and patterning the preliminary hard mask layer to form a preliminary hard mask pattern;
forming the first hard mask patterns by obliquely etching the first hard mask layer using the preliminary hard mask pattern as a mask; and
A method of manufacturing a semiconductor device, comprising etching the substrate using the first hard mask patterns as an etch mask to form the first trench. According to claim 1,
The method of manufacturing a semiconductor device further comprising removing the third hard mask patterns and the second hard mask patterns to expose the first trench and the second trench. According to clause 8,
forming a conductive layer filling the first trench and the second trench;
A method of manufacturing a semiconductor device, further comprising chemically mechanically polishing the conductive layer to expose the substrate to form a conductive pattern. According to claim 1,
The substrate includes a semiconductor substrate and a lower hard mask layer on the semiconductor substrate,
The first trench and the second trench are formed in the lower hard mask layer to form a lower hard mask pattern. According to claim 11,
etching the semiconductor substrate using the lower hard mask pattern as a mask to form a trench for a device isolation layer and forming an active region; and
A method of manufacturing a semiconductor device, further comprising filling the device isolation trench with a silicon oxide film. According to claim 1,
Forming inclined first hard mask patterns on a substrate and a first space between the first hard mask patterns includes:
forming a first hard mask layer, a preliminary hard mask layer, and a photoresist pattern on the preliminary hard mask layer, which are sequentially stacked on the substrate, and patterning the preliminary hard mask layer to form a preliminary hard mask pattern;
forming first hard mask patterns by vertically etching the first hard mask layer using the preliminary hard mask patterns as an etch mask;
depositing a conformal thin film to cover the first hard mask patterns and anisotropically etching the thin film to provide inclined sidewalls on sidewalls of the first hard mask patterns to form inclined first hard mask patterns;
A method of manufacturing a semiconductor device, comprising forming the first trench by etching the substrate using inclined first hard mask patterns as an etch mask. forming inclined first hard mask patterns on a lower hard mask layer formed on a substrate and a first space between the first hard mask patterns;
forming first trenches by anisotropically etching the lower hard mask layer using the first hard mask patterns as an etch mask;
forming second hard mask patterns lower than upper surfaces of the first hard mask patterns by filling the first trench and the first space with a second hard mask layer;
forming third hard mask patterns by coating or depositing a third hard mask layer on the second hard mask patterns and removing the third hard mask layer to expose the first hard mask patterns;
obliquely etching the first hard mask patterns using the third hard mask patterns as an etch mask to form a second space and forming divided first hard mask patterns; and
The lower hard mask layer is anisotropically etched using at least one of the third hard mask patterns, the divided first hard mask patterns, and the second hard mask patterns to form a second trench, and the first trench is anisotropically etched. A method of manufacturing a semiconductor device, comprising forming lower hard mask patterns including a trench and a second trench. According to claim 14,
The step of forming inclined first hard mask patterns on a lower hard mask layer formed on a substrate and a first space between the first hard mask patterns:
A main hard mask layer, a lower hard mask layer, a preliminary hard mask layer, and a photoresist pattern are formed on the preliminary hard mask layer sequentially stacked on the substrate to pattern the preliminary hard mask layer to form a preliminary hard mask pattern. step;
forming the first hard mask patterns by obliquely etching the first hard mask layer using the preliminary hard mask pattern as a mask; and
A method of manufacturing a semiconductor device, comprising etching the substrate using the first hard mask patterns as an etch mask to form the first trench. According to claim 14,
filling a second trench and a second space between the lower hard mask patterns with a gap fill material made of the same material as the first hard mask layer; and
A method of manufacturing a semiconductor device, further comprising etching the gap fill material, the first hard mask patterns, and the second hard mask patterns to expose the lower hard mask patterns. According to claim 15,
etching the main hard mask layer using the lower hard mask patterns as an etch mask to form inclined first main hard mask patterns and a first main space between the first main hard mask patterns;
forming first main trenches by anisotropically etching the substrate using the first main hard mask patterns as an etch mask;
forming second main hard mask patterns by filling the first main trench and the first main space with a second main hard mask layer so that the upper surfaces of the first main hard mask patterns are lower than the upper surfaces of the first main hard mask patterns;
Forming third main hard mask patterns by coating or depositing a third main hard mask layer on the second main hard mask patterns and removing the third main hard mask layer to expose the first main hard mask patterns. step;
obliquely etching the first main hard mask patterns using the third main hard mask patterns as an etch mask to form a second main space and forming divided first main hard mask patterns; and
forming a second main trench by anisotropically etching the substrate using at least one of the third hard mask patterns, the divided first main hard mask patterns, and the second main hard mask patterns; A method of manufacturing a semiconductor device comprising: According to claim 14,
The step of forming inclined first hard mask patterns on a lower hard mask layer formed on a substrate and a first space between the first hard mask patterns:
A silicon oxide layer sequentially stacked on the substrate, the lower hard mask layer, the first hard mask layer, the preliminary hard mask layer, and a photoresist pattern are formed on the preliminary hard mask layer to pattern the preliminary hard mask layer. forming a hard mask pattern;
forming the first hard mask patterns by obliquely etching the first hard mask layer using the preliminary hard mask pattern as a mask; and
A method of manufacturing a semiconductor device, comprising forming the first trench by etching the lower hard mask layer using the first hard mask patterns as an etch mask. According to claim 14,
The step of forming inclined first hard mask patterns on a lower hard mask layer formed on a substrate and a first space between the first hard mask patterns:
A conductive layer, a first lower hard mask layer, a second lower hard mask layer, a first hard mask layer, a preliminary hard mask layer, and a photoresist pattern are formed on the preliminary hard mask layer to form a preliminary hard mask layer sequentially laminated on the substrate. Patterning a hard mask layer to form a preliminary hard mask pattern;
forming the first hard mask patterns by obliquely etching the first hard mask layer using the preliminary hard mask pattern as a mask; and
A method of manufacturing a semiconductor device comprising forming the first trench by etching the first lower hard mask layer using the first hard mask patterns as an etch mask. forming a low dielectric layer sequentially stacked on a substrate, first hard mask patterns inclined on the low dielectric layer, and a first space between the first hard mask patterns;
forming first trenches by anisotropically etching the low dielectric layer using the first hard mask patterns as an etch mask;
forming second hard mask patterns lower than upper surfaces of the first hard mask patterns by filling the first trench and the first space;
A third hard mask layer is coated or deposited on the first hard mask patterns and the second hard mask patterns and the third hard mask layer is removed to expose the first hard mask patterns to form a third hard mask pattern. forming them;
forming divided first hard mask patterns by obliquely etching the first hard mask patterns using the third hard mask patterns as an etch mask; and
A semiconductor device comprising forming low dielectric patterns having a second trench by etching the low dielectric layer using an etch mask for the third hard mask pattern, the divided second hard mask patterns, and the second hard mask patterns. Manufacturing method. According to claim 20,
The steps of forming a low dielectric film sequentially stacked on a substrate, first hard mask patterns inclined on the low dielectric film, and a first space between the first hard mask patterns include:
forming a preliminary hard mask pattern by forming an etch stop layer, a low dielectric layer, a first hard mask layer, a preliminary hard mask layer, and a photoresist pattern sequentially stacked on the substrate and patterning the preliminary hard mask layer;
forming the first hard mask patterns by obliquely etching the first hard mask layer using the preliminary hard mask pattern as a mask; and
A method of manufacturing a semiconductor device, comprising forming the first trench by etching the low dielectric layer using the first hard mask patterns as an etch mask. According to claim 20,
filling the first trench and the second trench between the low dielectric patterns with a conductive layer; and
A method of manufacturing a semiconductor device, further comprising exposing upper surfaces of the low dielectric patterns using the conductive layer using a chemical mechanical polishing process. According to claim 20,
Further comprising an etch stop layer below the low dielectric layer,
forming a first auxiliary trench by etching the etch stop layer after forming the first trench; and
A method of manufacturing a semiconductor device, further comprising forming a second auxiliary trench by etching the etch stop layer after forming the second trench. A semiconductor device manufactured according to any one of claims 1 to 23.

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