KR20240007571A - Semiconductor package and method for fabricating the same - Google Patents

Abstract

A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a rewiring substrate, a first semiconductor substrate on the rewiring substrate, a first through via penetrating the first semiconductor substrate, and a first through via electrically connected to the first through via on the first semiconductor substrate. A first semiconductor chip including a bonding layer, a second semiconductor substrate, a second semiconductor chip including a second bonding layer bonded to the first bonding layer on the second semiconductor substrate, and a redistribution substrate, It includes a filling insulating film that covers the semiconductor chip and the second semiconductor chip, and the top surface of the filling insulating film is disposed above the top surfaces of the first semiconductor chip and the top surfaces of the second semiconductor chip.

Description

Semiconductor package and method for fabricating the same}

The present invention relates to a semiconductor package and a method of manufacturing the same.

Semiconductor packages are being developed to efficiently manufacture semiconductor chips with more diverse functions and higher reliability. Additionally, in order to mount more semiconductor chips in the same area, a stacked semiconductor package that stacks a plurality of such semiconductor chips has been proposed.

Such a semiconductor package may have a structure in which different types of semiconductor chips are stacked vertically. To implement this, a semiconductor package is being developed in which semiconductor chips including through silicon via (TSV) are stacked vertically.

The technical problem to be solved by the present invention is to provide a semiconductor package that can be manufactured at low cost by covering a first semiconductor chip and a second semiconductor chip with a single filling insulating film.

The technical problem to be solved by the present invention is to provide a method of manufacturing a semiconductor package that can be manufactured at low cost by covering a first semiconductor chip and a second semiconductor chip with a single filling insulating film.

The technical problems of the present invention are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the description below.

A semiconductor package according to some embodiments of the present invention for achieving the above technical problem includes a redistribution substrate, a first semiconductor substrate on the redistribution substrate, a first through via penetrating the first semiconductor substrate, and a first A first semiconductor chip including a first bonding layer electrically connected to a first through via on a semiconductor substrate, a second semiconductor substrate, and a second bonding layer bonded to the first bonding layer on the second semiconductor substrate. a second semiconductor chip, and a filling insulating film covering the first semiconductor chip and the second semiconductor chip on the redistribution substrate, wherein the top surface of the filling insulating film is higher than the top surface of the first semiconductor chip and the top surface of the second semiconductor chip. is placed in

A semiconductor package according to some embodiments of the present invention for achieving the above technical problem includes a redistribution substrate, a first semiconductor substrate on the redistribution substrate, a first through via penetrating the first semiconductor substrate, and a first A first semiconductor chip including a first bonding layer electrically connected to the first through via on the semiconductor substrate, a 1-1 dummy chip and a 1-2 dummy chip spaced apart from each other on the first semiconductor chip, 1 A first dummy bonding insulating film bonded to a first bonding layer between the semiconductor chip and the 1-1 dummy chip and between the first semiconductor chip and the 1-2 dummy chip, a 1-1 dummy chip on the first semiconductor chip and between the first and second dummy chips, a second semiconductor substrate, a second semiconductor chip including a second bonding layer bonded to the first bonding layer on the second semiconductor substrate, and a first semiconductor chip on the redistribution substrate. A filling insulating film covering the chip, the 1-1 dummy chip, the 1-2 dummy chip, and the second semiconductor chip, and the top surface of the filling insulating film is the top surface of the first semiconductor chip, the top surface of the 1-1 dummy chip, and the top surface of the 1-1 dummy chip. 2 is disposed above the upper surface of the dummy chip and the upper surface of the second semiconductor chip, and the entire 1-1 dummy chip and the entire 1-2 dummy chip are directed from the first semiconductor chip to the second semiconductor chip. It overlaps with the first semiconductor chip.

A semiconductor package manufacturing method according to some embodiments of the present invention for achieving the above technical problem includes forming a substrate bonding layer on a carrier, bonding the substrate bonding layer and a first semiconductor chip, and bonding the first semiconductor chip to the first semiconductor chip. The 1-1 bonding layer is bonded to the substrate bonding layer and the first semiconductor chip and the second semiconductor chip, and the second bonding layer of the second semiconductor chip is bonded to the 1-2 bonding layer of the first semiconductor chip. , and forming a filling insulating film covering the first semiconductor chip and the second semiconductor chip on the substrate bonding layer.

Specific details of other embodiments are included in the detailed description and drawings.

1 is a diagram for explaining a semiconductor package according to some embodiments.
2 to 6 are diagrams for explaining semiconductor packages according to some embodiments.
7 and 8 are diagrams for explaining semiconductor packages according to some embodiments.
9 to 15 are intermediate stage diagrams for explaining a method of manufacturing a semiconductor package according to some embodiments.

1 is a diagram for explaining a semiconductor package according to some embodiments.

Referring to FIG. 1, a semiconductor package according to some embodiments includes a first semiconductor chip 100, a second semiconductor chip 200, a first dummy chip 300, a first dummy bonding insulating layer 310, and a filling insulating layer. 400 , it may include a second dummy chip 500, a second dummy bonding insulating film 510, a redistribution substrate 600, and a connection terminal 650.

The first semiconductor chip 100 includes a first semiconductor substrate 110, a first semiconductor device layer 120, a first chip wiring layer 130, a 1-1 bonding layer 140, and a 1-2 bonding layer ( 150) may be included.

The first semiconductor substrate 110 may include a first surface 110A and a second surface 110B that are opposite to each other. The first surface 110A and the second surface 110B may be opposite to each other in the second direction DR2. Based on the second direction DR2, the first surface 110A may be the lower surface of the first semiconductor substrate 110, and the second surface 110B may be the upper surface of the first semiconductor substrate 110. In the following description, the upper and lower surfaces, and the upper and lower surfaces may be based on the second direction DR2.

The first semiconductor substrate 110 may be, for example, bulk silicon or SOI (silicon-on-insulator). The first semiconductor substrate 110 may be a silicon substrate, or may include other materials, such as silicon germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. . Alternatively, the first semiconductor substrate 110 may have an epitaxial layer formed on a base substrate.

The first semiconductor device layer 120 may be disposed on the first surface 110A of the first semiconductor substrate 110. The first semiconductor device layer 120 is a variety of microelectronic devices, for example, a metal-oxide-semiconductor field effect transistor (MOSFET) such as a complementary metal-insulator-semiconductor transistor (CMOS transistor), a system large scale integration (LSI), etc. ), flash memory, DRAM, SRAM, EEPROM, PRAM, MRAM, or RERAM, image sensors such as CIS (CMOS imaging sensor), MEMS (micro-electro-mechanical system), active elements, passive elements, etc. .

The first chip wiring layer 130 may be disposed on the first semiconductor device layer 120 . The first chip wiring layer 130 may include, for example, a first chip insulating layer 132 on the first semiconductor device layer 120 and a first chip wiring pattern 134 in the first chip insulating layer 132. The first chip wiring pattern 134 may include a multi-layered wiring layer and vias connecting the wiring layers. The arrangement, number of layers, number, etc. of the first chip wiring pattern 134 are illustrative only and are not limited thereto. The first semiconductor device layer 120 may be electrically connected to the first chip wiring pattern 134. . The first chip wiring layer 130 may be electrically connected to the first semiconductor device layer 120.

The first chip wiring pattern 134 may include, for example, a conductive film and a barrier film interposed between the conductive film and the first chip insulating film 132 . For example, the conductive layer of the first chip wiring pattern 134 may include, but is not limited to, at least one of tungsten (W), aluminum (Al), and copper (Cu). For example, the barrier layer of the first chip wiring pattern 134 may include at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN), but is not limited thereto. no.

The 1-1 bonding layer 140 may be disposed on the first chip wiring layer 130. For example, the 1-1 bonding layer 140 may include a 1-1 bonding insulating layer 142 and a 1-1 bonding pad 144 within the 1-1 bonding insulating layer 142. The 1-1 bonding pad 144 may contact the first chip wiring pattern 134 disposed at the lowest portion of the first chip wiring pattern 134 . Accordingly, the 1-1 bonding pad 144 may be electrically connected to the first chip wiring layer 130 and the first semiconductor device layer 120.

The 1-1 bonding pad 144 may include a metal, for example, copper (Cu), aluminum (Al), or tungsten (W), but is not limited thereto. The 1-1 bonding insulating film 142 may include at least one of an insulating material, for example, SiO, SiN, SiCN, SiOC, SiON, and SiOCN, but is not limited thereto.

The first through via 112 may penetrate the first semiconductor substrate 110 and the first semiconductor device layer 120. For example, the first through via 112 may contact the first chip wiring pattern 134 disposed at the top of the first chip wiring patterns 134 . Accordingly, the first through via 112 may be electrically connected to the first semiconductor chip 100.

For example, the first through via 112 may include a pillar-shaped conductive film penetrating the first semiconductor substrate 110 and a barrier film interposed between the conductive film and the first semiconductor substrate 110 . The conductive film of the first through via 112 is, for example, at least one of Cu alloy such as Cu, CuSn, CuMg, CuNi, CuZn, CuPd, CuAu, CuRe, CuW, W, W alloy, Ni, Ru, and Co. It may include, but is not limited to this. The barrier film of the first through via 112 is, for example, titanium (Ti), titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN), rubidium (Ru), cobalt (Co), manganese ( It may include at least one of Mn), tungsten nitride (WN), nickel (Ni), and nickel boronide (NiB), but is not limited thereto.

For example, the first through via 112 may further include an insulating film interposed between the barrier film and the first semiconductor substrate 110 . The insulating film of the first through via 112 may include, but is not limited to, at least one of, for example, an oxide film, a nitride film, a carbide film, a polymer, or a combination thereof.

The 1-2 bonding layer 150 may be disposed on the second surface 110B of the first semiconductor substrate 110. For example, the 1-2 bonding layer 150 may include a 1-2 bonding insulating layer 152 and a 1-2 bonding pad 154 within the 1-2 bonding insulating layer 152. The 1-2 bonding pad 154 may contact the first through via 112. Accordingly, the 1-2 bonding pad 154 may be electrically connected to the first semiconductor chip 100.

The first-second bonding pad 154 may include a metal, for example, copper (Cu), aluminum (Al), or tungsten (W), but is not limited thereto. The 1-2 bonding insulating film 152 may include at least one of an insulating material, for example, SiO, SiN, SiCN, SiOC, SiON, and SiOCN, but is not limited thereto.

The second semiconductor chip 200 may be disposed on the first semiconductor chip 100 . The second semiconductor chip 200 may include a second semiconductor substrate 210, a second semiconductor device layer 220, a second chip wiring layer 230, and a 2-1 bonding layer 240.

The second semiconductor substrate 210 may include a third surface 210A and a fourth surface 210B that are opposite to each other. The third surface 210A and the fourth surface 210B may be opposite to each other in the second direction DR2. The third surface 210A may be the lower surface of the second semiconductor substrate 210, and the second surface 110B may be the upper surface of the second semiconductor substrate 210. The third surface 210A of the second semiconductor substrate 210 may face the second surface 110B of the first semiconductor substrate 110.

The second semiconductor substrate 210 may be, for example, bulk silicon or SOI (silicon-on-insulator). The second semiconductor substrate 210 may be a silicon substrate, or may include other materials, such as silicon germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. . Alternatively, the second semiconductor substrate 210 may have an epitaxial layer formed on a base substrate.

The second semiconductor device layer 220 may be disposed on the third surface 210A of the second semiconductor substrate 210. The second semiconductor device layer 220 is a variety of microelectronic devices, for example, a metal-oxide-semiconductor field effect transistor (MOSFET) such as a complementary metal-insulator-semiconductor transistor (CMOS transistor), a system large scale integration (LSI), etc. ), flash memory, DRAM, SRAM, EEPROM, PRAM, MRAM, or RERAM, image sensors such as CIS (CMOS imaging sensor), MEMS (micro-electro-mechanical system), active elements, passive elements, etc. .

The second chip wiring layer 230 may be disposed on the second semiconductor device layer 220 . The second chip wiring layer 230 may include, for example, a second chip insulating layer 232 on the second semiconductor device layer 220 and a second chip wiring pattern 234 in the second chip insulating layer 232. The second chip wiring pattern 234 may include a multi-layered wiring layer and vias connecting the wiring layers. The arrangement, number of layers, and number of the second chip wiring patterns 234 are merely illustrative and are not limited thereto. The second semiconductor device layer 220 may be electrically connected to the second chip wiring pattern 234. The second chip wiring layer 230 may be electrically connected to the second semiconductor device layer 220.

The second chip wiring pattern 234 may include, for example, a conductive film and a barrier film interposed between the conductive film and the second chip insulating film 232 . For example, the conductive layer of the second chip wiring pattern 234 may include, but is not limited to, at least one of tungsten (W), aluminum (Al), and copper (Cu). For example, the barrier layer of the second chip wiring pattern 234 may include at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN), but is not limited thereto. no.

The 2-1 bonding layer 240 may be disposed on the second chip wiring layer 230. For example, the 2-1 bonding layer 240 may include a 2-1 bonding insulating film 242 and a 2-1 bonding pad 244 within the 2-1 bonding insulating film 242. The 2-1 bonding pad 244 may contact the second chip wiring pattern 234 disposed at the lowest portion of the second chip wiring pattern 234 . Accordingly, the 2-1 bonding pad 244 may be electrically connected to the second chip wiring layer 230 and the second semiconductor device layer 220.

The 2-1 bonding pad 244 may include a metal, for example, copper (Cu), aluminum (Al), or tungsten (W), but is not limited thereto. The 2-1 bonding insulating film 242 may include at least one of an insulating material, for example, SiO, SiN, SiCN, SiOC, SiON, and SiOCN, but is not limited thereto.

The 2-1 bonding layer 240 may be bonded to the 1-2 bonding layer 150. The first semiconductor chip 100 may be electrically connected to the second semiconductor chip 200.

The 1-2 bonding layer 150 and the 2-1 bonding layer 240 may be bonded using a hybrid bonding method. For example, the 2-1 bonding pad 244 may be attached to the 1-2 bonding pad 154, and the 2-1 bonding insulating film 242 may be attached to the 1-2 bonding insulating film 152. It can be. For example, the 1-2 bonding pad 154 and the 2-1 bonding pad 244 may be bonded by a copper (Cu)-copper (Cu) bonding method, and the 1-2 bonding insulating film 152 and the 2-1 bonding insulating film 242 may be bonded by a dielectric-dielectric bonding method.

The first semiconductor chip 100 and the second semiconductor chip 200 may be different types of semiconductor chips. For example, the first semiconductor chip 100 may be a logic semiconductor chip, and the second semiconductor chip 200 may be a memory semiconductor chip. The logic semiconductor chip may include, for example, a Central Processing Unit (CPU), a Graphic Processing Unit (GPU), a Field-Programmable Gate Array (FPGA), a digital signal processor, a cryptographic processor, a microprocessor, a microcontroller, and an Application-Specific IC (ASIC). It may be an application processor (AP) such as an IC, but is not limited thereto. The memory semiconductor chip may be, for example, volatile memory such as dynamic random access memory (DRAM) or static random access memory (SRAM), or flash memory, phase-change random access memory (PRAM), It may be non-volatile memory, such as Magnetoresistive Random Access Memory (MRAM), Ferroelectric Random Access Memory (FeRAM), or ResistiveRandom Access Memory (RRAM).

The first dummy chip 300 may be placed on the first semiconductor chip 100 . The first dummy chip 300 may be a semiconductor substrate that does not include a circuit layer. The first dummy chip 300 may be, for example, bulk silicon or SOI (silicon-on-insulator). The first dummy chip 300 may be a silicon substrate, or may include other materials, such as silicon germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. . Alternatively, the first semiconductor substrate 110 may have an epitaxial layer formed on a base substrate.

The first dummy bonding insulating film 310 may be disposed between the first dummy chip 300 and the first semiconductor chip 100. The first dummy bonding insulating film 310 may be disposed between the first dummy chip 300 and the 1-2 bonding layer 150. The first dummy bonding insulating film 310 may include at least one of an insulating material, for example, SiO, SiN, SiCN, SiOC, SiON, and SiOCN, but is not limited thereto.

The first dummy bonding insulating film 310 may be bonded to the 1-2 bonding layer 150. For example, the first dummy bonding insulating layer 310 may be attached to the 1-2 bonding insulating layer 152. For example, the first dummy bonding insulating layer 310 and the 1-2 bonding insulating layer 152 may be bonded using a dielectric-dielectric bonding method.

The first dummy chip 300 may be spaced apart from the second semiconductor chip 200 . The first dummy chip 300 may be disposed around the second semiconductor chip 200, for example. For example, the first dummy chip 300 may be placed on both walls of the second semiconductor chip 200. For example, the second semiconductor chip 200 may be disposed between adjacent first dummy chips 300 in the first direction DR1. The number of first dummy chips 300 is merely illustrative and is not limited thereto. Additionally, of course, the height (thickness in the second direction DR2) of the first dummy chip 300 may be different.

The entire first dummy chip 300 may overlap the first semiconductor chip 100 in the second direction DR2. In a semiconductor package according to some embodiments, one side wall of the first dummy chip 300 may be disposed on a different plane from one side wall of the first semiconductor chip 100. The sidewalls of the first dummy chip 300 may be disposed on the top of the first semiconductor chip 100. For example, both side walls of the first dummy chip 300 in the first direction DR1 may be disposed on the top of the first semiconductor chip 100 . The thickness of the filling insulating film 400 on the sidewall of the first dummy chip 300 may be greater than the thickness of the filling insulating film 400 on the sidewall of the first semiconductor chip 100. The thickness may be based on the first direction DR1.

In a semiconductor package according to some embodiments, the top surface 300US of the first dummy chip 300 may be disposed on substantially the same plane as the top surface 200US of the second semiconductor chip 200. The top surface 200US of the second semiconductor chip 200 may be the fourth surface 210B of the second semiconductor substrate 210. The thickness of the filling insulating film 400 on the top surface 300US of the first dummy chip 300 may be substantially the same as the thickness of the filling insulating film 400 on the top surface 200US of the second semiconductor chip 200.

The redistribution substrate 600 may include a redistribution layer 610, a substrate bonding layer 620, and a passivation layer 630. The first semiconductor chip 100 may be disposed on the redistribution substrate 600 .

The redistribution layer 610 may include, for example, a redistribution insulating layer 612 and a redistribution pattern 614 within the redistribution insulating layer 612 . The redistribution pattern 614 may include a multi-layered wiring layer and vias connecting the wiring layers. The arrangement, number of layers, number, etc. of the redistribution pattern 614 are illustrative only and are not limited thereto.

The substrate bonding layer 620 may be disposed on the redistribution layer 610 . The substrate bonding layer 620 may be disposed on the upper surface of the redistribution layer 610. The substrate bonding layer 620 may include, for example, a substrate bonding insulating layer 622 and a substrate bonding pad 624 within the substrate bonding insulating layer 622. The substrate bonding pad 624 may contact the redistribution pattern 614 disposed at the top of the redistribution patterns 614 . Accordingly, the substrate bonding pad 624 may be electrically connected to the redistribution layer 610.

The substrate bonding pad 624 may include a metal, for example, copper (Cu), aluminum (Al), or tungsten (W), but is not limited thereto. The substrate bonding insulating film 622 may include at least one of an insulating material, for example, SiO, SiN, SiCN, SiOC, SiON, and SiOCN, but is not limited thereto.

The substrate bonding layer 620 may be bonded to the 1-1 bonding layer 140. The first semiconductor chip 100 may be electrically connected to the redistribution substrate 600.

The substrate bonding layer 620 and the 1-1 bonding layer 140 may be bonded using a hybrid bonding method. For example, the substrate bonding pad 624 may be attached to the 1-1 bonding pad 144 and the substrate bonding insulating layer 622 may be attached to the 1-1 bonding insulating layer 142. For example, the substrate bonding pad 624 and the 1-1 bonding pad 144 may be bonded by a copper (Cu)-copper (Cu) bonding method, and the substrate bonding insulating film 622 and the 1-1 bonding pad 144 may be bonded using a copper (Cu)-copper (Cu) bonding method. The bonding insulating film 142 may be bonded using a dielectric-dielectric bonding method.

The passivation layer 630 may be disposed on the redistribution layer 610. The passivation layer 630 may be disposed on the lower surface of the redistribution layer 610. For example, the passivation layer 630 may expose at least a portion of the redistribution pattern 614 disposed at the bottom of the redistribution pattern 614 .

The connection terminal 650 may be disposed on the redistribution substrate 600 . For example, the connection terminal 650 may be disposed on the redistribution pattern 614 exposed by the passivation layer 630 . Accordingly, the connection terminal 650 may be electrically connected to the redistribution substrate 600, and the first semiconductor chip 100 and the second semiconductor chip 200 may be connected to an external device (e.g., electronic device) through the connection terminal 650. It can be electrically connected to the device's panel, etc.).

The connection terminal 650 may include, for example, a solder ball, a bump, or under bump metallurgy (UBM). The connection terminal 650 may include a metal such as tin (Sn), but is not limited thereto.

The filling insulating film 400 may surround the first semiconductor chip 100, the second semiconductor chip 200, and the first dummy chip 300 on the redistribution substrate 600. The filling insulating film 400 may cover the first semiconductor chip 100, the second semiconductor chip 200, and the first dummy chip 300 on the redistribution substrate 600. The filling insulating film 400 is formed on the top surface of the redistribution substrate 600, the top surface and sidewalls of the first semiconductor chip 100, the top surface and sidewalls of the second semiconductor chip 200, and the top surface and sidewalls of the first dummy chip 300. and may extend along the sidewall of the first dummy bonding insulating layer 310. The filling insulating film 400 may fill the space between the first dummy chip 300 and the second semiconductor chip 200. That is, the first semiconductor chip 100, the second semiconductor chip 200, and the first dummy chip 300 may be covered by one filling insulating film 400.

The top surface 400US of the filling insulating film 400 is disposed above the top surface of the first semiconductor chip 100, the top surface 300US of the first dummy chip 300, and the top surface 200US of the second semiconductor chip 200. It can be. At this time, the top surface 300US of the first dummy chip 300 may mean the top surface 300US of the first dummy chip 300 with the highest height among the plurality of first dummy chips 300. That is, the filling insulating film 400 may cover the entire upper surface of the plurality of first dummy chips 300.

The second dummy chip 500 may be disposed on the filling insulating film 400 . The second dummy chip 500 may be disposed on the top surface 400US of the filling insulating film 400. The second dummy chip 500 may be a semiconductor substrate that does not include a circuit layer. The second dummy chip 500 may be, for example, bulk silicon or SOI (silicon-on-insulator). The second dummy chip 500 may be a silicon substrate, or may include other materials, such as silicon germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. . Alternatively, the second dummy chip 500 may have an epitaxial layer formed on a base substrate.

The second dummy bonding insulating layer 510 may be disposed between the second dummy chip 500 and the filling insulating layer 400 . The second dummy bonding insulating layer 510 may include, but is not limited to, at least one of SiO, SiN, SiCN, SiOC, SiON, and SiOCN.

The second dummy bonding insulating layer 510 may be bonded to the filling insulating layer 400 . The second dummy bonding insulating layer 510 and the filling insulating layer 400 may be bonded using a dielectric-dielectric bonding method. For example, the second dummy bonding insulating layer 510 may be attached to the filling insulating layer 400 .

2 to 6 are diagrams for explaining semiconductor packages according to some embodiments. For convenience of explanation, the description will focus on differences from those described using FIG. 1.

Referring to FIG. 2, a semiconductor package according to some embodiments includes a first semiconductor chip 100, a second semiconductor chip 200, a first dummy chip 300, a filling insulating film 400, and a redistribution substrate 600. ) and a connection terminal 650. That is, compared to the semiconductor package explained using FIG. 1, it may not include the second dummy chip 500 and the second dummy bonding insulating film 510.

Referring to FIG. 3, in a semiconductor package according to some embodiments, the top surface 300US of the first dummy chip 300 may be disposed on a different plane from the top surface 200US of the second semiconductor chip 200. . The thickness of the filling insulating film 400 on the top surface 300US of the first dummy chip 300 may be different from the thickness of the filling insulating film 400 on the top surface 200US of the second semiconductor chip 200. The thickness of the first dummy chip 300 in the second direction DR2 may vary depending on the design.

For example, the top surface 300US of the first dummy chip 300 may be disposed lower than the top surface 200US of the second semiconductor chip 200. For another example, the top surface 300US of the first dummy chip 300 may be disposed above the top surface 200US of the second semiconductor chip 200. The filling insulating film 400 may cover the top surface 300US of the first dummy chip 300 and the top surface 200US of the second semiconductor chip 200.

Referring to FIG. 4 , in a semiconductor package according to some embodiments, one side wall of the first dummy chip 300 may be disposed on substantially the same plane as one side wall of the first semiconductor chip 100 . For example, one side wall of the first dummy chip 300 in the first direction DR1 may be disposed on substantially the same plane as one side wall of the first semiconductor chip 100 in the first direction DR1. there is. The thickness of the filling insulating film 400 on the sidewall of the first dummy chip 300 may be substantially the same as the thickness of the filling insulating film 400 on the sidewall of the first semiconductor chip 100. The thickness may be based on the first direction DR1.

Referring to FIG. 5, a semiconductor package according to some embodiments includes a first semiconductor chip 100, a second semiconductor chip 200, a filling insulating film 400, a pillar 450, and a second dummy chip 500. , may include a second dummy bonding insulating film 510, a dummy bonding pad 512, a redistribution substrate 600, and a connection terminal 650.

Pillars 450 may be disposed on the first semiconductor chip 100 . The pillar 450 may penetrate the filling insulating film 400. The pillar 450 may be disposed on the 1-2 bonding layer 150 of the first semiconductor chip 100 by penetrating the filling insulating film 400 from the top surface 400US of the filling insulating film 400. The top surface 450US of the pillar 450 may be disposed on substantially the same plane as the top surface 400US of the filling insulating film 400. This forms a filling insulating film 400 covering the first and second semiconductor chips 100 and 200 on the redistribution substrate 600 and forms a trench exposing at least a portion of the upper surface of the first semiconductor chip 100. Later, it may result from a process of forming pillars 450 that fill the trench. The filling insulating film 400 may contact the 1-2 bonding pad 154 within the 1-2 bonding layer 150.

The dummy bonding pad 512 may be disposed within the second dummy bonding insulating layer 510 . The pillar 450 may contact the dummy bonding pad 512 . The dummy bonding pad 512 may include a metal, for example, copper (Cu), aluminum (Al), or tungsten (W), but is not limited thereto.

The second dummy bonding insulating layer 510 may be attached to the filling insulating layer 400 , and the pillar 450 may be attached to the dummy bonding pad 512 . For example, the filling insulating layer 400 and the pillar 450, and the second dummy bonding insulating layer 510 and the dummy bonding pad 512 may be bonded using a hybrid bonding method. For example, the pillar 450 and the dummy bonding pad 512 may be bonded by a copper (Cu)-copper (Cu) bonding method, and the filling insulating layer 400 and the second dummy bonding insulating layer 510 may be formed using a dielectric- It can be bonded by a dielectric bonding method.

Referring to FIG. 6, a semiconductor package according to some embodiments includes a first semiconductor chip 100, a 2-1 semiconductor chip 200-1, a 2-2 semiconductor chip 200-2, and a first dummy. The chip 300, the first dummy bonding insulating film 310, the filling insulating film 400, the second dummy chip 500, the second dummy bonding insulating film 510, the redistribution substrate 600, and the connection terminal 650. It can be included.

The 2-1 semiconductor chip 200-1 includes a second semiconductor substrate 210, a 2-1 through via 212, a second semiconductor element layer 220, a second chip wiring layer 230, and a second- It may include a first bonding layer 240 and a second-second bonding layer 250.

The 2-1 through via 212 may penetrate the second semiconductor substrate 210 and the second semiconductor device layer 220. For example, the 2-1 through via 212 may contact the second chip wiring pattern 234 disposed at the top of the second chip wiring patterns 234 . Accordingly, the 2-1 through via 212 may be electrically connected to the 2-1 semiconductor chip 200-1.

For example, the 2-1 through via 212 may include a pillar-shaped conductive film penetrating the second semiconductor substrate 210 and a barrier film interposed between the conductive film and the second semiconductor substrate 210. there is. The conductive film of the 2-1 through via 212 is, for example, Cu alloy such as Cu, CuSn, CuMg, CuNi, CuZn, CuPd, CuAu, CuRe, CuW, W, W alloy, Ni, Ru, and Co. It may include at least one, but is not limited thereto. The barrier film of the 2-1 through via 212 is, for example, titanium (Ti), titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN), rubidium (Ru), cobalt (Co), It may include at least one of manganese (Mn), tungsten nitride (WN), nickel (Ni), and nickel boronide (NiB), but is not limited thereto.

For example, the 2-1 through via 212 may further include an insulating film interposed between the barrier film and the second semiconductor substrate 210 . The insulating film of the 2-1 through via 212 may include, but is not limited to, at least one of, for example, an oxide film, a nitride film, a carbonide film, a polymer, or a combination thereof.

The 2-2 bonding layer 250 may be disposed on the fourth surface 210B of the second semiconductor substrate 210 of the 2-1 semiconductor chip 200-1. For example, the 2-2 bonding layer 250 may include a 2-2 bonding insulating film 252 and a 2-2 bonding pad 254 within the 2-2 bonding insulating film 252. The 2-2 bonding pad 254 may contact the 2-1 through via 212. Accordingly, the 2-2 bonding pad 254 may be electrically connected to the 2-1 semiconductor chip 200-1.

The 2-2 bonding pad 254 may include a metal, for example, copper (Cu), aluminum (Al), or tungsten (W), but is not limited thereto. The 2-2 bonding insulating film 252 may include at least one of an insulating material, for example, SiO, SiN, SiCN, SiOC, SiON, and SiOCN, but is not limited thereto.

The 2-2 semiconductor chip 200-2 may be disposed on the 2-1 semiconductor chip 200-1. The 2-2 semiconductor chip 200-2 may include a second semiconductor substrate 210, a second semiconductor element layer 220, a second chip wiring layer 230, and a 2-1 bonding layer 240. there is.

The third surface 210A of the second semiconductor substrate 210 of the 2-2 semiconductor chip 200-2 is the fourth surface of the second semiconductor substrate 210 of the 2-1 semiconductor chip 200-1. Can be opposed to (210B). The second semiconductor element layer 220 of the 2-2 semiconductor chip 200-2 is disposed on the third surface 210A of the second semiconductor substrate 210 of the 2-2 semiconductor chip 200-2. It can be, and the second semiconductor element layer 220 of the 2-1 semiconductor chip 200-1 is the third surface 210A of the second semiconductor substrate 210 of the 2-1 semiconductor chip 200-1. ) can be placed on.

The 2-2 bonding layer 250 of the 2-1 semiconductor chip 200-1 may be bonded to the 2-1 bonding layer 240 of the 2-2 semiconductor chip 200-2. The 2-1 semiconductor chip 200-1 may be electrically connected to the 2-2 semiconductor chip 200-2.

The 2-2 bonding layer 250 of the 2-1 semiconductor chip 200-1 and the 2-1 bonding layer 240 of the 2-2 semiconductor chip 200-2 are bonded by a hybrid bonding method. It can be. For example, the 2-2 bonding pad 254 of the 2-1 semiconductor chip 200-1 may be attached to the 2-1 bonding pad 244 of the 2-2 semiconductor chip 200-2. The 2-2 bonding insulating film 252 of the 2-1 semiconductor chip 200-1 may be attached to the 2-1 bonding insulating film 242 of the 2-2 semiconductor chip 200-2. there is. For example, the 2-2 bonding pad 254 of the 2-1 semiconductor chip 200-1 and the 2-1 bonding pad 244 of the 2-2 semiconductor chip 200-2 are copper ( It can be bonded by a Cu)-copper (Cu) bonding method, and the 2-2 bonding insulating film 252 of the 2-1 semiconductor chip 200-1 and the 2-2 semiconductor chip 200-2 The 2-1 bonding insulating film 242 may be bonded using a dielectric-dielectric bonding method.

The 2-1 semiconductor chip 200-1 and the 2-2 semiconductor chip 200-2 may be the same type of semiconductor chip. For example, the 2-1 semiconductor chip 200-1 and the 2-2 semiconductor chip 200-2 may be memory semiconductor chips.

The 2-1 semiconductor chip 200-1 and the 2-2 semiconductor chip 200-2 may be disposed between adjacent first dummy chips 300.

The filling insulating film 400 is disposed on the redistribution substrate 600, the first semiconductor chip 100, the 2-1 semiconductor chip 200-1, the 2-2 semiconductor chip 200-2, and the first dummy. The chip 300 can be covered. The filling insulating film 400 is formed on the top surface of the redistribution substrate 600, the top surface and sidewalls of the first semiconductor chip 100, the top surface and sidewalls of the 2-1 semiconductor chip 200-1, and the 2-2 semiconductor chip ( 200-2), the top surface and sidewalls of the first dummy chip 300, and the sidewalls of the first dummy bonding insulating film 310 may be covered. The filling insulating film 400 may fill a gap between the first dummy chip 300 and the 2-1 semiconductor chip 200-1 and the 2-2 semiconductor chip 200-2.

The top surface 400US of the filling insulating film 400 may be disposed above the top surface 300US of the first dummy chip 300 and the top surface 200US of the 2-2 semiconductor chip 200-2. The top surface 200US of the 2-2 semiconductor chip 200-2 may be the fourth surface 210B of the second semiconductor substrate 210 of the 2-2 semiconductor chip 200-2.

7 and 8 are diagrams for explaining semiconductor packages according to some embodiments. For convenience of explanation, the description will focus on differences from those described using FIGS. 1 to 6.

Referring to FIG. 7, in the 2-2 semiconductor chip 200-2 of the semiconductor package according to some embodiments, the second semiconductor device layer 220 is formed on the fourth surface 210B of the second semiconductor substrate 210. ), and the 2-2 bonding layer 250 may be disposed on the third surface 210A of the second semiconductor substrate 210. In the 2-1 semiconductor chip 200-1, the second semiconductor element layer 220 may be disposed on the third surface 210A of the second semiconductor substrate 210.

The top surface 400US of the filling insulating film 400 may be disposed above the top surface 300US of the first dummy chip 300 and the top surface 200US of the 2-2 semiconductor chip 200-2. The top surface 200US of the 2-2 semiconductor chip 200-2 may be the top surface of the 2-1 bonding layer 240 of the 2-2 semiconductor chip 200-2.

Referring to FIG. 8 , in a semiconductor package according to some embodiments, a 1-1 dummy chip 300-1 may be disposed on the first semiconductor chip 100. The 2-1 semiconductor chip 200-1 may be disposed between the 1-1 dummy chip 300-1 on the first semiconductor chip 100.

The 1-2 dummy bonding insulating layer 310-2 may be bonded to the first filling insulating layer 400-1. The 1-2 dummy bonding insulating film 310-2 and the first filling insulating film 400-1 may be bonded using a dielectric-dielectric bonding method. For example, the 1-2 dummy bonding insulating layer 310-2 may be attached to the 1-2 dummy bonding insulating layer 310-2.

The first filling insulating film 400-1 is formed on the redistribution substrate 600, the first semiconductor chip 100, the 2-1 semiconductor chip 200-1, and the 1-1 dummy chip 300-1. can cover at least part of the The first filling insulating film 400-1 includes the top surface of the redistribution substrate 600, the top surface and sidewall of the first semiconductor chip 100, the sidewall of the 2-1 semiconductor chip 200-1, and the 1-1 dummy. The top surface and sidewall of the chip 300-1 and the sidewall of the 1-1 dummy bonding insulating film 310-1 may be covered. The first filling insulating film 400-1 may fill the space between the 1-1 dummy chip 300-1 and the 2-1 semiconductor chip 200-1. The first filling insulating film 400-1 may expose the top surface of the 2-1 semiconductor chip 200-2 and cover the top surface of the 1-1 dummy chip 300-1.

The top surface of the 2-1 semiconductor chip 200-1 may be disposed above the top surface of the 1-1 dummy chip 300-1 and is substantially the same as the top surface of the first filling insulating film 400-1. It can be placed on a plane.

The 1-2 dummy chip 300-2 may be disposed on the first filling insulating film 400-2. The 2-2 semiconductor chip 200-1 may be disposed between the 1-2 dummy chip 300-2.

The second filling insulating film 400-2 may cover the 2-2 semiconductor chip 200-2 and the 1-2 dummy chip 300-2 on the first filling insulating film 400-1. The second filling insulating film 400-2 includes the top surface of the first filling insulating film 400-1, the top surface (200US) and sidewall of the 2-2 semiconductor chip 200-2, and the 1-2 dummy chip 300-2. 2), the top surface (300US) and the sidewall and the sidewall of the 1-2 dummy bonding insulating film 310-2 can be covered. The second filling insulating film 400-2 may fill the space between the 1-2 dummy chip 300-2 and the 2-2 semiconductor chip 200-2. The second filling insulating film 400-2 may cover both the top surface 200US of the 2-2 semiconductor chip 200-2 and the top surface 300US of the 1-2 dummy chip 300-2.

The top surface (400US) of the second filling insulating film 400-2 is higher than the top surface (300US) of the 1-2 dummy chip 300-2 and the top surface (200US) of the 2-2 semiconductor chip 200-2. can be placed in The top surface 200US of the 2-2 semiconductor chip 200-2 may be the fourth surface 210B of the second semiconductor substrate 210 of the 2-2 semiconductor chip 200-2.

9 to 15 are intermediate stage diagrams for explaining a method of manufacturing a semiconductor package according to some embodiments.

Referring to FIG. 9 , a redistribution layer 610 and a substrate bonding layer 620 may be sequentially formed on the carrier 700. The redistribution layer 610 repeatedly performs a process of forming and patterning a redistribution insulating film 612 on the carrier 700 and a process of forming a redistribution pattern 614 on the patterned redistribution insulating film 612. It can be formed. The substrate bonding layer 620 performs a process of forming and patterning a substrate bonding insulating layer 622 on the redistribution layer 610, and forming a substrate bonding pad 624 on the patterned substrate bonding insulating layer 622. It can be formed.

The carrier 700 may include, for example, silicon, metal, glass, plastic, ceramic, etc.

Referring to FIG. 10, the first semiconductor device layer 120, the first chip wiring layer 130, and the 1-1 bonding layer 140 are sequentially formed on the first surface 110A of the first semiconductor substrate 110. may be formed, and the 1-2 bonding layer 150 may be formed on the second surface 110B of the first semiconductor substrate 110. That is, the 1-1 bonding layer 140 is formed on the first side 110A of the first semiconductor substrate 110, and the 1-2 bonding layer (140) is formed on the second side 110B of the first semiconductor substrate 110. A first semiconductor chip 100 on which 150) is formed may be provided.

The first semiconductor chip 100 may be mounted on the substrate bonding layer 620. The first semiconductor chip 100 is placed on the substrate bonding layer 620 so that the first surface 110A of the first semiconductor substrate 110 on which the first semiconductor device layer 120 is formed faces the substrate bonding layer 620. It can be installed.

The 1-1 bonding layer 140 of the first semiconductor chip 100 may be bonded to the substrate bonding layer 620. The 1-1 bonding insulating layer 142 may be bonded to the substrate bonding insulating layer 622, and the 1-1 bonding pad 144 may be bonded to the substrate bonding pad 624. Accordingly, the first semiconductor chip 100 can be bonded to the substrate bonding layer 620.

Referring to FIG. 11, a second semiconductor device layer 220, a second chip wiring layer 230, and a 2-1 bonding layer 240 are sequentially formed on the third surface 210A of the second semiconductor substrate 210. can be formed.

The second semiconductor chip 200 may be mounted on the first semiconductor chip 100. The second semiconductor chip 200 is formed so that the third side 210A of the second semiconductor substrate 210 on which the second semiconductor element layer 220 is formed faces the first semiconductor chip 100. It can be mounted on a

The 2-1 bonding layer 240 of the second semiconductor chip 200 may be bonded to the 1-2 bonding layer 150 of the first semiconductor chip 100. The 2-1 bonding insulating film 242 may be bonded to the 1-2 bonding insulating film 152, and the 2-1 bonding pad 244 may be bonded to the 1-2 bonding pad 154. Accordingly, the second semiconductor chip 200 can be bonded to the first semiconductor chip 100.

Referring to FIG. 12 , a first dummy chip 300 with a first dummy bonding insulating film 310 formed on the first semiconductor chip 100 may be mounted. The first dummy chip 300 may be mounted on the first semiconductor chip 100 so that the first dummy bonding insulating layer 310 faces the first semiconductor chip 100 .

The first dummy bonding insulating layer 310 may be bonded to the 1-2 bonding layer 150 of the first semiconductor chip 100. The first dummy bonding insulating layer 310 may be bonded to the 1-2 bonding insulating layer 152 . Accordingly, the first dummy chip 300 can be bonded to the first semiconductor chip 100.

For example, the first dummy chip 300 may be mounted around the second semiconductor chip 200 on the first semiconductor chip 100 .

Referring to FIG. 13, a filling insulating film 400 may be formed on the substrate bonding layer 620. The filling insulating film 400 may fill the space between the second semiconductor chip 200 and the first dummy chip 300. The filling insulating film 400 is formed on the top surface of the substrate bonding layer 620, the top surface and sidewalls of the first semiconductor chip 100, the top surface 200US and sidewalls of the second semiconductor chip 200, and the first dummy chip 300. The top surface 300US, the sidewall, and the sidewall of the first dummy bonding insulating film 310 may be covered.

A planarization process may be performed on the filling insulating film 400, and the top surface 400US of the filling insulating film 400 may be substantially flat. The top surface 400US of the filling insulating film 400 may be disposed above the top surface 300US of the first dummy chip 300 and the top surface 200US of the second semiconductor chip 200.

A semiconductor package according to some embodiments includes a filling insulating film 400 after the first semiconductor chip 100, the second semiconductor chip 200, and the first dummy chip 300 are mounted on the redistribution layer 610. can be formed. That is, the process of forming the filling insulating film 400 can be performed once to fill the space between the first semiconductor chip 100, the second semiconductor chip 200, and the first dummy chip 300. Therefore, compared to the manufacturing process of forming the filling insulating film 400 surrounding the first semiconductor chip 100 and the filling insulating film 400 surrounding the second semiconductor chip 200 and the first dummy chip 300, the manufacturing process is It can be simplified and costs can be reduced.

Referring to FIG. 14 , a second dummy chip 500 may be mounted on the filling insulating film 400 . For example, the second dummy chip 500 on which the second dummy bonding insulating film 510 is formed may be mounted on the filling insulating film 400 so that the second dummy bonding insulating film 510 faces the filling insulating film 400. Or, for example, a second dummy bonding insulating layer 510 may be formed on the filling insulating layer 400, and a second dummy chip 500 may be mounted on the second dummy bonding insulating layer 510.

The second dummy bonding insulating layer 510 may be bonded to the filling insulating layer 400 . Accordingly, the second dummy chip 500 can be bonded to the filling insulating film 400.

Referring to FIG. 15, the carrier 700 may be removed. Accordingly, the redistribution layer 610 may be exposed.

Next, referring to FIG. 1 , the lower surface of the redistribution pattern 614 disposed at the lowest part of the redistribution pattern 614 may be exposed in the second direction DR2.

Subsequently, a passivation layer 630 may be formed on the redistribution insulating film 612. The passivation layer 630 may expose at least a portion of the redistribution pattern 614 disposed at the bottom.

Subsequently, a connection terminal 650 may be formed on the redistribution pattern 614 exposed by the passivation layer 630.

Although embodiments of the present invention have been described above with reference to the attached drawings, the present invention is not limited to the above embodiments and can be manufactured in various different forms, and can be manufactured in various different forms by those skilled in the art. It will be understood by those who understand that the present invention can be implemented in other specific forms without changing its technical spirit or essential features. Therefore, the embodiments described above should be understood in all respects as illustrative and not restrictive.

100: first semiconductor chip 110: first semiconductor substrate
112: first through via 120: first semiconductor device layer
130: first chip wiring layer 140: first-1 bonding layer
150: 1-2 bonding layer 200: 2nd semiconductor chip
210: second semiconductor substrate 212: second through via
220: second semiconductor element layer 230: second chip wiring layer
240: 2-1 bonding layer 250: 2-2 bonding layer
300: first dummy chip 310: first dummy bonding insulating film
400: Filling insulating film 500: Second dummy chip
510: Second dummy bonding insulating film 600: Redistribution substrate
650: connection terminal

Claims (10)

rewiring board;
On the redistribution substrate, it includes a first semiconductor substrate, a first through via penetrating the first semiconductor substrate, and a first bonding layer electrically connected to the first through via on the first semiconductor substrate. a first semiconductor chip;
a second semiconductor chip including a second semiconductor substrate and a second bonding layer bonded to the first bonding layer on the second semiconductor substrate; and
A filling insulating film covering the first semiconductor chip and the second semiconductor chip on the redistribution substrate,
A semiconductor package wherein the top surface of the filling insulating film is disposed above the top surfaces of the first semiconductor chip and the top surfaces of the second semiconductor chip. According to clause 1,
The first bonding layer includes a first bonding insulating film on the first semiconductor substrate and a first bonding pad in the first bonding insulating film,
The second bonding layer includes a second bonding insulating film on the second semiconductor substrate and a second bonding pad in the second bonding insulating film,
The first bonding insulating film is bonded to the second bonding insulating film,
The first bonding pad is a semiconductor package bonded to the second bonding pad. According to clause 1,
a dummy bonding insulating film on the filling insulating film;
Further comprising a dummy chip on the dummy bonding insulating film,
A semiconductor package wherein the dummy bonding insulating layer is bonded to the filling insulating layer. According to clause 1,
A semiconductor package further comprising a pillar that penetrates the filling insulating film and is bonded to the first bonding layer. According to clause 1,
Further comprising a third semiconductor chip on the second semiconductor chip,
The filling insulating film covers the third semiconductor chip,
The top surface of the filling insulating film is disposed above the top surface of the third semiconductor chip,
The second semiconductor chip includes a third bonding layer between the second semiconductor substrate and the third semiconductor chip, and a second through via that penetrates the second semiconductor substrate and is electrically connected to the third bonding layer. do,
The third semiconductor chip is a semiconductor package including a third semiconductor substrate and a fourth bonding layer bonded to the third bonding layer on the third semiconductor substrate. According to clause 5,
The second semiconductor chip further includes a first semiconductor device layer on the first side of the second semiconductor substrate, and a first chip wiring layer between the first semiconductor device layer and the second bonding layer,
The third semiconductor chip includes a second semiconductor device layer on a second side of the third semiconductor substrate opposite to the first side of the second semiconductor substrate, and between the second semiconductor device layer and the fourth bonding layer. A semiconductor package further comprising a third chip wiring layer. According to clause 5,
The second semiconductor chip further includes a first semiconductor device layer on the first side of the second semiconductor substrate, and a first chip wiring layer between the first semiconductor device layer and the second bonding layer,
The third semiconductor chip includes a third through via that penetrates the third semiconductor substrate and is electrically connected to the fourth bonding layer on the second side of the third semiconductor substrate, and a third through via that is electrically connected to the fourth bonding layer on the second side of the third semiconductor substrate. It further includes a second semiconductor device layer on the second semiconductor device layer, and a second chip wiring layer on the second semiconductor device layer,
The semiconductor package wherein the second side of the third semiconductor substrate is opposite to the third side of the third semiconductor substrate and is opposite to the first side of the second semiconductor substrate. According to clause 5,
Further comprising a first dummy chip and a second dummy chip,
The filling insulating film includes a first filling insulating film and a second filling insulating film on the first filling insulating film,
The first dummy chip is spaced apart from the second semiconductor chip on the first semiconductor chip,
The first filling insulating film surrounds the first semiconductor chip and the first dummy chip on the redistribution substrate, covers a top surface of the first dummy chip, and exposes a top surface of the first semiconductor chip,
The second dummy chip is spaced apart from the third semiconductor chip on the first filling insulating film,
The second filling insulating film surrounds the third semiconductor chip and the second dummy chip on the first filling insulating film, and covers a top surface of the second dummy chip and a top surface of the third semiconductor chip. rewiring board;
On the redistribution substrate, it includes a first semiconductor substrate, a first through via penetrating the first semiconductor substrate, and a first bonding layer electrically connected to the first through via on the first semiconductor substrate. a first semiconductor chip;
A 1-1 dummy chip and a 1-2 dummy chip spaced apart from each other on the first semiconductor chip;
a first dummy bonding insulating layer bonded to the first bonding layer between the first semiconductor chip and the 1-1 dummy chip and between the first semiconductor chip and the 1-2 dummy chip;
A second semiconductor substrate is provided between the 1-1 dummy chip and the 1-2 dummy chip on the first semiconductor chip, and a second bonding layer bonded to the first bonding layer on the second semiconductor substrate. a second semiconductor chip comprising:
a filling insulating film covering the first semiconductor chip, the 1-1 dummy chip, the 1-2 dummy chip, and the second semiconductor chip on the redistribution substrate; and
The top surface of the filling insulating film is disposed above the top surface of the first semiconductor chip, the top surface of the 1-1 dummy chip, the top surface of the 1-2 dummy chip, and the top surface of the second semiconductor chip,
The entirety of the 1-1 dummy chip and the entirety of the 1-2 dummy chip overlap the first semiconductor chip in a direction from the first semiconductor chip to the second semiconductor chip. Forming a substrate bonding layer on the carrier,
Bonding the substrate bonding layer and the first semiconductor chip, wherein the 1-1 bonding layer of the first semiconductor chip is bonded to the substrate bonding layer,
Bonding the first semiconductor chip and the second semiconductor chip, wherein the second bonding layer of the second semiconductor chip is bonded to the 1-2 bonding layer of the first semiconductor chip,
A semiconductor package manufacturing method comprising forming a filling insulating film on the substrate bonding layer to cover the first semiconductor chip and the second semiconductor chip.

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