KR20240007234A - Automatic electrostatic chuck bias compensation during plasma processing - Google Patents

Abstract

Embodiments of the present disclosure relate to a system for pulsed direct current (DC) biasing and clamping of a substrate. In one embodiment, the system includes a plasma chamber with an electrostatic chuck (ESC) to support a substrate. Electrodes are embedded in the ESC and electrically coupled to a biasing and clamping network. The biasing and clamping network includes at least a shaped DC pulse voltage source and a clamping network. The clamping network includes a DC source and diode, and a resistor. The shaped DC pulse voltage source and clamping network are connected in parallel. The biasing and clamping network automatically maintains a substantially constant clamping voltage, the voltage drop across the electrode and substrate when the substrate is biased using a pulsed DC voltage, leading to improved clamping of the substrate.

Description

Automatic electrostatic chuck bias compensation during plasma processing

[0001] Embodiments of the present disclosure generally relate to systems used in semiconductor manufacturing. More specifically, embodiments of the present disclosure relate to a system for biasing and clamping a substrate during plasma processing.

[0002] Ion bombardment is often used as a source of activation energy for chemical and physical processes in plasma etching and plasma enhanced chemical vapor deposition (PECVD) processes for processing semiconductor substrates. High energy ions accelerated by a plasma sheath can also be used to etch highly directional, high aspect ratio features. Conventionally, a substrate may be biased using radio frequency (RF) power from an RF source. The RF source supplies an RF voltage to a first electrode that is embedded in an electrostatic chuck (ESC) or cathode. The first electrode is capacitively coupled to the plasma of the processing chamber through a layer of ceramic that is part of the ESC. The nonlinear diode-like nature of the plasma envelope causes rectification of the applied RF field, resulting in a direct-current (DC) voltage drop, or self-bias, between the substrate and the plasma. This voltage drop determines the average energy of the ions accelerated toward the substrate.

[0003] The ESC places the substrate on it by applying a fixed DC voltage to a second electrode embedded in the ESC to establish an electric field between the ESC and the substrate. The electric field induces charges of opposite polarity to accumulate on the substrate and the second electrode, respectively. Conversely, the electrostatic attraction between the polarized charges pulls the substrate toward the ESC, thereby securing the substrate. However, electrostatic forces are affected by the RF bias power supplied to the first electrode of the ESC, which can lead to under- or over-clamping of the substrate. Additionally, as large bias voltages become several kilovolts, variations in self-bias voltage relative to a fixed DC voltage can lead to an increased risk of arc discharge or sudden declamping and failure of the substrate. This is particularly problematic at the very high bias powers (kilovolt (kV) range) used during pulsed voltage type substrate biasing techniques.

[0004] Accordingly, an improved system for biasing and clamping the substrate is needed.

[0005] Embodiments of the present disclosure may provide a plasma processing chamber including a substrate support assembly, a waveform generator, a first power delivery line, a clamping network, a signal detection module, and a controller. The substrate support assembly includes a substrate supporting surface, a first biasing electrode, and a first dielectric layer disposed between the first biasing electrode and the substrate supporting surface. A first power delivery line electrically couples the waveform generator to the first biasing electrode, where the first power delivery line includes a blocking capacitor. The clamping network is coupled to the first power transmission line at a first point between the blocking capacitor and the biasing electrode, the clamping network includes a direct current (DC) voltage source coupled between the first point and ground, and a direct current (DC) voltage source coupled between the first point and ground. DC) includes a blocking resistor coupled between the outputs of the voltage source. The signal detection module is configured to receive a first electrical signal from a first signal trace coupled to the first power transmission line at a point disposed between the blocking capacitor and the biasing electrode. The controller is configured to communicate with the signal detection module and to control the magnitude of the voltage supplied to the first power delivery line at the first point by the direct current (DC) voltage source due to information received within the received electrical signal.

[0006] Embodiments of the present disclosure may further provide a plasma processing chamber including a substrate support assembly, a waveform generator, a first power delivery line, a clamping network, and a signal detection module. A first power delivery line electrically couples the waveform generator to the first electrode, where the first power delivery line includes a blocking capacitor. The clamping network is coupled to the first power transmission line at a first point between the blocking capacitor and the first electrode, the clamping network includes a direct current (DC) voltage source coupled between the first point and ground, and a direct current (DC) source coupled between the first point and ground. DC) includes a blocking resistor coupled between the voltage sources. The signal detection module is configured to receive a first electrical signal from a first signal trace coupled to the first power transmission line at a point disposed between the blocking capacitor and the first electrode.

[0007] Embodiments of the present disclosure may further provide a method for plasma processing a substrate, comprising: generating a plasma within a processing region of a processing chamber, the processing region comprising: a substrate support surface, a first via; a substrate support comprising a thinning electrode and a first dielectric layer disposed between the first biasing electrode and the substrate support surface; delivering a plurality of pulsed voltage waveforms from a waveform generator, during a first period of time, to a first biasing electrode via a first power delivery line, wherein the first power delivery line is disposed between the waveform generator and the biasing electrode. Includes blocking capacitor -; ceasing delivery of the plurality of pulsed voltage waveforms to the first biasing electrode for an entire second period of time; applying a first clamping voltage from the clamping network to the first biasing electrode; One or more pulses of a plurality of pulsed voltage waveforms delivered during a first period of time by receiving an electrical signal from a signal trace coupled to the first power transmission line at a first point disposed between the blocking capacitor and the biasing electrode. detecting at least one characteristic of the equation voltage waveforms; detecting at least one characteristic of an electrical signal received from the signal trace during a second period of time; and a first bias based on the detected characteristic of one or more of the delivered plurality of pulsed voltage waveforms and at least one characteristic of the electrical signal received from the signal trace during the first and second time periods. and adjusting the first clamping voltage applied to the single electrode.

[0008] Embodiments of the present disclosure may further provide a method for plasma processing a substrate, comprising: generating a plasma within a processing region of a processing chamber, the processing region comprising: a substrate support surface, a first via; a substrate support comprising a thinning electrode and a first dielectric layer disposed between the first biasing electrode and the substrate support surface; delivering one or more waveforms from a waveform generator through a first power delivery line to a first biasing electrode during a first period of time; ceasing delivery of one or more waveforms to the first biasing electrode for a second period of time; applying a first clamping voltage from the clamping network to the first biasing electrode; detecting at least one characteristic of one or more waveforms during a first period of time by receiving an electrical signal from a signal trace coupled to the first power transmission line at a first point disposed on the first power transmission line; detecting at least one characteristic of an electrical signal received from the signal trace during a second period of time; and, during a first time period, detected characteristics of one or more waveforms received from the signal trace; and adjusting the first clamping voltage applied to the first biasing electrode based on the at least one detected characteristic of the electrical signal received from the signal trace during the second period of time.

[0009] In such a way that the above-enumerated features of the disclosure may be understood in detail, a more specific description of the disclosure briefly summarized above may be made with reference to the embodiments, some of which are attached. Illustrated in the drawings. However, it should be noted that the accompanying drawings illustrate only exemplary embodiments of the disclosure and should not be considered limiting the scope of the disclosure, but may permit other equally effective embodiments.
[0010] Figure 1A is a schematic cross-sectional view of a processing chamber configured to practice methods described herein, according to one embodiment.
[0011] Figure 1B is an enlarged schematic cross-sectional view of a portion of the processing chamber illustrated in Figure 1A, according to one embodiment.
[0012] FIG. 1C is a functionally equivalent circuit diagram of a coulombic electrostatic chuck (ESC) that may be used in the process chamber illustrated in FIG. 1A, according to one embodiment.
[0013] FIG. 1D is a functionally equivalent circuit diagram of a Johnson-Rahbek electrostatic chuck (ESC) that may be used in the process chamber illustrated in FIG. 1A, according to one embodiment.
[0014] Figure 1E is a schematic diagram illustrating an example of a processing chamber including the feedback loop illustrated in Figure 1A, according to one embodiment.
[0015] Figure 2A is a functionally equivalent circuit diagram of a system that can be used to generate negative pulses in a process chamber, according to one embodiment.
[0016] FIG. 2B is a functionally equivalent circuit diagram of a system that can be used to generate positive pulses in a process chamber, according to one embodiment.
[0017] Figure 3A illustrates an example of pulsed voltage (PV) waveforms established in different portions of the functionally equivalent circuit diagram illustrated in Figure 3B, according to one embodiment.
[0018] FIG. 3B is a circuit diagram illustrating a system that may be used to perform one or more methods described herein, according to one embodiment.
[0019] Figure 4A illustrates an example of negative pulsed voltage (PV) waveforms established at a biasing electrode and substrate, according to one embodiment.
[0020] FIGS. 4B-4D illustrate examples of a series of pulsed voltage (PV) waveform bursts, according to one or more embodiments.
[0021] FIG. 5A is a functionally equivalent circuit diagram of a system that can be used to deliver an RF waveform to an electrode within a process chamber, according to one embodiment.
[0022] Figure 5B illustrates an example of RF waveforms established in different portions of the functionally equivalent circuit diagram illustrated in Figure 5A, according to one embodiment.
[0023] FIGS. 6A and 6B are process flow diagrams illustrating methods of biasing and clamping a substrate during plasma processing, according to one or more embodiments.
[0024] To facilitate understanding, identical reference numbers have been used where possible to designate identical elements that are common to the drawings. It is contemplated that elements and features of one embodiment may be beneficially incorporated into other embodiments without further recitation.

[0025] Embodiments of the disclosure provided herein include apparatus and methods for plasma processing a substrate in a processing chamber. Aspects of one or more of the embodiments disclosed herein include a system and method for reliably biasing and clamping a substrate during processing to improve plasma processing results. Embodiments of the present disclosure provide a pulsed voltage (PV) waveform delivered from one or more pulsed voltage (PV) generators to one or more electrodes in a processing chamber while biasing and clamping a substrate during a plasma process. It may include devices and methods for. In some embodiments, a radio frequency (RF) generated RF waveform is provided from an RF generator to one or more electrodes within the processing chamber to establish and maintain a plasma within the processing chamber, while PV waveform(s) are delivered from a PV generator. is configured to establish a substantially constant sheath voltage across the surface of the substrate. Establishing a substantially constant sheath voltage across the surface of the substrate can produce a desirable ion energy distribution function (IEDF) at the surface of the substrate during one or more plasma processing steps performed within the processing chamber. In some embodiments, the PV waveform is established by a PV generator electrically coupled to a biasing electrode disposed within a substrate support assembly disposed within the plasma processing chamber.

[0026] During some of the plasma processes, ions are intentionally accelerated toward the substrate by a voltage drop that forms in an electron-repelling sheath formed over the substrate disposed on top of the substrate support assembly. Although not intended to be a limitation as to the scope of the disclosure provided herein, the substrate support assembly is sometimes referred to herein as a “cathode assembly” or “cathode.” 1A is a schematic cross-sectional view of a processing chamber 100 in which a plasma 101 is formed during a plasma process being performed on a substrate 103. During one or more of the plasma processing methods disclosed herein, a pulsed voltage configured to establish a pulsed voltage waveform at the biasing electrode 104 (FIGS. 1A and 1B) disposed within the substrate support assembly 136. An ion accelerating cathode enclosure is typically formed during plasma processing by use of a (PV) generator 150. In some embodiments, substrate support assembly 136 (FIG. 1A) includes a substrate support 105 and a support base 107. Substrate support 105 may include an electrostatic chuck (ESC) assembly 105D configured to “clamp” or “chucking” (e.g., hold) a substrate 103 on substrate receiving surface 105A. In some embodiments, the biasing electrode 104 includes a chucking electrode separated from the substrate by a thin layer of dielectric material 105B (FIG. 1B) formed within the electrostatic chuck (ESC) assembly 105D and optionally, A portion of the edge control electrode 115 disposed within or beneath the edge ring 114 surrounding the substrate 103 when the substrate 103 is disposed on the substrate support surface 105A of the substrate support assembly 136. forms.

[0027] During plasma processing, vacuum pressure builds up in the processing volume 129 of the processing chamber 100 between the surfaces of components disposed therein, such as on the dielectric material of the substrate support 105 and the substrate receiving surface 105A. This results in poor heat conduction between the disposed substrates 103, which reduces the effectiveness of the substrate support in heating or cooling the substrate 103. Accordingly, the non-device side surface of the substrate 103 and the substrate receiving surface 105A of the substrate support 105 are thermally conductive and inert within a volume (not shown) disposed between them to improve heat transfer. It is often necessary to introduce a gas, typically helium, and maintain it at increased pressure (eg back pressure). Heat transfer gas provided by a heat transfer gas source (not shown) is disposed through the support base 107 and into the rear volume via a gas transfer path (not shown) further disposed through the substrate support 105. It flows.

[0028] In an effort to enable a higher relative pressure to be established behind the substrate, the substrate 103 is clamped to the substrate receiving surface by the use of a biasing and clamping network, also referred to herein simply as clamping network 116. A clamping voltage is applied to biasing electrode 104 to “clamp” or “chuck” 105A. In some embodiments, clamping network 116 includes a DC voltage source (P ₂ ) (FIGS. 2A and 2B), a blocking resistor (R ₁ ) (FIGS. 2A and 2B), and a diode (D ₁ ) (FIG. 2A). and, in some configurations, will also include resistor R ₂ ( FIGS. 2A and 2B ) and capacitor C ₆ ( FIGS. 2A and 2B ). The presence of the diode D ₁ is used to maintain a constant voltage difference between the waveform established at the biasing electrode 104 and the waveform established at the substrate surface. In some embodiments, PV generator 150 and clamping network 116 are connected in parallel. The clamping network 116 maintains the clamping voltage at a desired clamping voltage level to improve the plasma processing process results achieved on the substrate 103 and due to application of a clamping voltage that is too large or too small. To ensure that the clamped substrate 103 is not damaged during processing, the clamping voltage applied to the biasing electrode 104 is automatically adjusted. Application of a clamping voltage that is too large may result in “de-chucking” time (e.g., the time it takes for the charge to build up on the substrate to dissipate to reduce the attractive force of the substrate 103 to the substrate receiving surface 105A). time) and/or may cause the substrate to break due to application of too great a “clamping” or “chucking force” to the substrate 103 and/or the substrate backside and the clamping electrode 104. It can cause the thin dielectric in between to break down. Application of a clamping voltage that is too small may cause the substrate 103 to lose intimate contact with the substrate receiving surface 105A during processing. Backside helium can leak into the plasma chamber and the plasma paper can also leak into a position on the backside of the substrate, causing rapid pressure and gas composition changes at the backside of the substrate. Such sudden changes can ignite the plasma on the backside of the substrate, damaging the substrate and electrostatic chuck.

[0029] The plasma potential of the plasma 101 formed in the processing region 129 changes due to the application of a pulsed voltage (PV) or RF bias to one or more electrodes disposed within the plasma processing chamber. As discussed further below, changes in the plasma potential are required when controlling the clamping voltage applied to the clamping electrode and substrate 103 during processing to reliably generate the desired clamping voltage (V _DCV ) during the plasma process. needs to be considered. In one example, changes in plasma potential will occur within each pulse of a multiple pulsed PV waveform, and the pulsed voltage biasing parameters applied to the biasing electrode may be used to process one or more substrates in the processing chamber. This will occur when the characteristics of the PV waveforms delivered by PV generator 150 also change as they change within or from substrate processing recipe to substrate processing recipe. Conventional substrate clamping systems (e.g., electrostatic chucks) that provide a constant clamping voltage and do not account for and adjust for fluctuations in plasma potential often provide poor plasma processing results and/or damage the substrate during processing.

[0030] However, the ability to reliably measure or determine changes in the plasma potential in real time so that they can be taken into account during processing is not a simple task. The ability to reliably measure fluctuations or changes in plasma potential so that the clamping voltage can be adjusted as desired in a production-worthy plasma processing chamber capable of sequentially processing multiple substrates in succession is an additional challenge. Conventional methods of measuring plasma potential and substrate DC bias require the use of probes to directly measure the substrate surface potential, and while suitable for non-production laboratory testing, their presence in the chamber affects plasma processing results. It can cause harm. Conventional methods for estimating plasma potential and substrate DC bias are complex and involve the use of one or more models to correlate the directly measured substrate surface DC bias with the voltage, current and phase data to be measured at the RF match under several calibration conditions. and use the model to estimate the plasma potential and substrate DC bias when used in production device manufacturing processes. The devices and methods described herein can be used to reliably determine plasma potential as a function of time and then provide adjustments to the clamping voltage based on the measured plasma potential.

Plasma processing chamber example

[0031] 1A illustrates a processing chamber 100 in which a complex load 130 (FIGS. 2A and 2B) is formed during plasma processing. FIG. 1B is an enlarged schematic cross-sectional view of a portion of the substrate support assembly 136 illustrated in FIG. 1A , according to one embodiment. Typically, the process chamber 100 includes one or more PV generators 150 and/or one or more RF generators 118 to generate, control and maintain the plasma 101 in the processing volume 129 during plasma processing. It is designed to be used. 2A and 2B illustrate different configurations of an electrical circuit, or system, configured to deliver a plurality of voltage pulses provided from a PV generator 150 to a biasing electrode 104 disposed in the plasma processing chamber 100. do. The PV waveform generator 150 illustrated in FIGS. 2A and 2B is disposed within a first PV source assembly 196 (FIG. 1A) disposed within the processing chamber 100.

[0032] Processing chamber 100 is configured to implement one or more of the biasing schemes proposed herein, according to one or more embodiments. In one embodiment, processing chamber 100 is a plasma processing chamber, such as a reactive ion etch (RIE) plasma chamber. In some other embodiments, processing chamber 100 may be a plasma-enhanced chemical vapor deposition (PECVD) chamber, plasma-enhanced physical vapor deposition (PECVD) chamber, or plasma-enhanced physical vapor deposition (PECVD) chamber. ; PEPVD) chamber, or plasma-enhanced atomic layer deposition (PEALD) chamber. In some other embodiments, processing chamber 100 is a plasma processing chamber, or a plasma-based ion implantation chamber, such as a plasma doping (PLAD) chamber. In some embodiments, the plasma source is a capacitively coupled plasma that includes an electrode (e.g., chamber lid 123) disposed in the processing volume 129, opposite the substrate support assembly 136. (capacitively coupled plasma; CCP) source. As illustrated in FIG. 1A , an opposing electrode positioned opposite substrate support assembly 136, such as chamber lid 123, is electrically coupled to ground. However, in other alternative embodiments, the counter electrode is electrically coupled to the RF generator. In still other embodiments, processing chamber 100 may alternatively or additionally include an inductively coupled plasma (ICP) source electrically coupled to a radio frequency (RF) power supply.

[0033] Processing chamber 100 also includes a chamber body 113 that includes a chamber lid 123, one or more side walls 122, and a chamber base 124, defining a processing volume 129. One or more sidewalls 122 and chamber base 124 generally include materials sized and shaped to form structural support for elements of processing chamber 100 and support the processing chamber 100 during processing. ) is configured to withstand the pressures and added energy applied to the materials while the plasma 101 is generated within a vacuum environment maintained within the processing volume 129 of ). In one example, one or more side walls 122 and chamber base 124 are formed from metal, such as aluminum, aluminum alloy, or stainless steel. Gas inlet 128 disposed through chamber lid 123 is used to provide one or more processing gases to processing volume 129 from a processing gas source 119 in fluid communication therewith. Substrate 103 is loaded into processing volume 129 through an opening (not shown) in one of one or more side walls 122 that is sealed with a slit valve (not shown) during plasma processing of substrate 103. and is removed from it. Herein, the substrate 103 is transferred to and from the substrate receiving surface 105A of the substrate support 105 using a lift pin system (not shown).

[0034] Processing chamber 100 further includes a system controller 126, also referred to herein as a processing chamber controller. System controller 126 herein includes a central processing unit (CPU) 133, memory 134, and support circuits 135. System controller 126 is used to control the process sequence used to process substrate 103, including the substrate biasing methods described herein. CPU 133 is a general-purpose computer processor and its associated subprocessors configured for use in an industrial environment to control a processing chamber. Memory 134, described herein, which is generally non-volatile memory, may include random access memory, read-only memory, a floppy or hard disk drive, or other suitable forms of digital storage, local or remote. Support circuits 135 are typically coupled to CPU 133 and include cache, clock circuits, input/output subsystems, power supplies, etc., and combinations thereof. Software instructions (programs) and data may be coded and stored within memory 134 to instruct a processor within CPU 133. A software program (or computer instructions) readable by CPU 133 in system controller 126 determines which tasks can be performed by components within processing chamber 100. Preferably, the program readable by the CPU 133 in the system controller 126, when executed by the processor (CPU 133), performs tasks related to monitoring and execution of the electrode biasing scheme described herein. Contains the code that executes. The program may be used to perform various process tasks and various process sequences used to implement the electrode biasing scheme and method for reliably biasing and clamping a substrate during a plasma process, as described herein. It will contain instructions used to control hardware and electrical components. In one embodiment, the program includes instructions used to perform one or more of the operations described below with respect to FIGS. 6A and 6B.

[0035] In some embodiments, the RF source assembly 163, including the RF generator 118 and the RF generator assembly 160, generally generates a desired positive continuous wave at a desired, substantially fixed sinusoidal waveform frequency. CW) or pulsed RF power to the support base 107 based on control signals provided from the controller 126. During processing, RF source assembly 163 is configured to deliver RF power to a support base 107 disposed proximate to substrate support 105 and within substrate support assembly 136 . RF power delivered to the support base 107 is configured to ignite and maintain a processing plasma 101 formed by the use of processing gases disposed within the processing volume 129. In some embodiments, support base 107 is an RF electrode electrically coupled to RF generator 118 via RF matching circuit 162 and first filter assembly 161, which includes RF matching circuit 162 and first filter assembly 161. 1 Both filter assemblies 161 are disposed within RF generator assembly 160. The first filter assembly 161 is configured to substantially prevent current generated by the output of the PV waveform generator 150 from flowing through the RF power delivery line 167 and damaging the RF generator 118. It includes the above electrical elements. The first filter assembly 161 acts as a high impedance (e.g., high Z) for the PV signal generated from the PV pulse generator (P ₁ ) within the PV waveform generator 150, and thus acts as an RF matching circuit ( 162) and inhibit the flow of current to the RF generator 118.

[0036] In some embodiments, the plasma generator assembly 160 and the RF generator 118 are generated by processing gases disposed within the processing volume 129 and RF power provided to the support base 107 by the RF generator 118. It is used to ignite and maintain the processing plasma 101 using the generated fields. The processing volume 129 is configured to maintain the processing volume 129 at sub-atmospheric pressure conditions and exhaust processing and/or other gases therefrom through a vacuum outlet 120. It is coupled to dedicated vacuum pumps for fluid flow. A substrate support assembly 136 disposed within processing volume 129 is disposed on a support shaft 138 that is grounded and extends through chamber base 124. However, in some embodiments, the RF generator assembly 160 is configured to deliver RF power to a biasing electrode 104 disposed on the substrate support 105 relative to the support base 107.

[0037] Substrate support assembly 136 generally includes a substrate support 105 (eg, an ESC substrate support) and a support base 107, as briefly discussed above. In some embodiments, substrate support assembly 136 may further include an insulator plate 111 and a ground plate 112, as discussed further below. The support base 107 is electrically insulated from the chamber base 124 by an insulator plate 111, and the ground plate 112 is interposed between the insulator plate 111 and the chamber base 124. Substrate support 105 is thermally coupled to and disposed on support base 107. In some embodiments, support base 107 is configured to regulate the temperature of substrate support 105 and substrate 103 disposed on substrate support 105 during substrate processing. In some embodiments, the support base 107 is fluidly coupled to a coolant source (not shown), such as a refrigerant source or a water source with a relatively high electrical resistance. , and one or more cooling channels (not shown) disposed therein, in fluid communication therewith. In some embodiments, the substrate support 105 includes a heater (not shown), such as a resistive heating element embedded in its dielectric material. Herein, the support base 107 is formed of a corrosion-resistant, thermally conductive material, such as a corrosion-resistant metal, such as aluminum, aluminum alloy, or stainless steel, and is attached to the substrate support using an adhesive or by mechanical means. is combined with

[0038] Typically, the substrate support 105 is made of a dielectric material, such as a bulk sintered ceramic material, such as a corrosion-resistant metal oxide or metal nitride material, such as aluminum oxide (Al ₂ O ₃ ), It is formed of aluminum nitride (AlN), titanium oxide (TiO), titanium nitride (TiN), yttrium oxide (Y ₂ O ₃ ), mixtures thereof, or combinations thereof. In embodiments herein, the substrate support 105 further includes a biasing electrode 104 embedded in its dielectric material. In one configuration, the biasing electrode 104 is used to secure (i.e., churn) the substrate 103 to the substrate receiving surface 105A of the substrate support 105 and to perform pulsed voltage biasing as described herein. A chucking pole used to bias the substrate 103 with respect to the processing plasma 101 using one or more of the following methods. Typically, biasing electrode 104 is formed of one or more electrically conductive components, such as one or more metal meshes, foils, plates, or combinations thereof.

[0039] The biasing electrode 104 in the electrostatic chuck (ESC) is electrically coupled to the biasing and clamping network 116 illustrated in FIGS. 1A and 2A and 2B. Biasing and clamping network 116 includes a DC voltage source (P ₂ ). The clamping network 116 connects the biasing electrode 104 and the biasing electrode 104 when a plurality of PV waveforms are applied to the biasing electrode 104 by a pulsed-voltage waveform generator (PVWG) 150 during plasma processing. Automatically maintains a clamping voltage that is a constant voltage drop across the substrate 103, leading to improved clamping of the substrate 103. Clamping network 116 is further described below in connection with FIGS. 2A-4C. In some embodiments, clamping network 116 maintains a chucking voltage during processing, such as a static DC voltage between about -10,000 volts (V) and about 10,000 V, such as between -3,000 volts (V) and about 3,000 V. It is configured to be provided to the biasing electrode 104.

[0040] Referring to FIG. 1A , the substrate support assembly 136, when biased, generates plasma (at or outside the edge of the substrate 103) due to its position relative to the substrate 103. It may further include an edge control electrode 115 positioned below the edge ring 114 and surrounding the biasing electrode 104 so as to be able to influence or change a portion of the electrode 101 . Edge control electrode 115 is a pulsed-voltage waveform generator (PVWG) 150 that is different from the pulsed-voltage waveform generator (PVWG) 150 used to bias biasing electrode 104. It can be biased by the use of . In some embodiments, edge control electrode 115 is a pulsed voltage waveform generator (PVWG) that is also used to bias biasing electrode 104 by splitting a portion of the power to edge control electrode 115. 150) can be biased. In one configuration, the first PV waveform generator 150 of the first PV source assembly 196 is configured to bias the biasing electrode 104, and the second PV waveform generator 150 of the second PV source assembly 197 is configured to bias the biasing electrode 104. (150) is configured to bias the edge control electrode (115). In one embodiment, edge control electrode 115 is positioned within an area of substrate support 105, as shown in Figure 1A. Generally, for a processing chamber 100 configured to process circular substrates, the edge control electrode 115 is annular in shape, is made from a conductive material, and, as illustrated in FIG. 1A, the biasing electrode 104 It is configured to surround at least a portion of. In some embodiments, as illustrated in Figure 1A, edge control electrode 115 is disposed at a similar distance (i.e., in the Z direction) from surface 105A of substrate support 105 as biasing electrode 104. Includes a conductive mesh, foil, or plate. In some other embodiments, edge control electrode 115 is a conductive electrode positioned on or within an area of quartz pipe 110 surrounding at least a portion of biasing electrode 104 and/or substrate support 105. Includes mesh, foil or plate. Alternatively, in some other embodiments, edge control electrode 115 is positioned within or coupled to edge ring 114 disposed adjacent substrate support 105 . In this configuration, edge ring 114 is formed from a semiconductor or dielectric material (eg, AlN, etc.).

[0041] Referring to FIG. 1A, the second PV source assembly 197 is biased by a clamping network 116 in which the bias applied to the edge control electrode 115 is coupled within the first PV source assembly 196. It includes a clamping network 116 so that it can be configured similarly to the bias applied to the electrode 104. Applying similarly configured PV waveforms and clamping voltages to biasing electrode 104 and edge control electrode 115 helps improve plasma processing process results by improving plasma uniformity across the surface of the substrate during processing. It can be. For simplicity of discussion, various methods described herein can be used to determine the desired clamping voltage (V _DCV ) or DC bias voltage (e.g., equations (15) and/or (16)) to be applied to the biasing electrode 104. Operations described herein for determining and controlling the bias to be applied to the edge control electrode 115 by the clamping network 116 of the second PV source assembly 197, although primarily discussing the methods used to determine This discussion is not intended to be a limitation as to the scope of the disclosure provided herein, as one or more of the methods may also be used. In one example, the operations disclosed with respect to FIGS. 6A and 6B may be applied simultaneously to biasing electrode 104 and edge control electrode 115 during plasma processing.

[0042] In some embodiments, processing chamber 100 prevents substrate support 105, and/or support base 107 from contacting corrosive processing gases or plasma, cleaning gases or plasma, or by-products thereof. It further includes a quartz pipe (110), or collar, at least partially surrounding portions of the substrate support assembly (136) to prevent Typically, quartz pipe 110, insulator plate 111, and ground plate 112 are surrounded by liner 108. In some embodiments, the plasma screen 109 has a cathode liner 108 to prevent plasma from forming in the volume beneath the plasma screen 109 between the liner 108 and one or more sidewalls 122. and the side walls 122.

[0043] 1B is an enlarged view of the substrate support assembly 136 that includes a simplified electrical schematic representation of the electrical characteristics of various structural elements within one or more embodiments of the substrate support assembly 136. The substrate support assembly 136 includes a substrate support 105, a support base 107, an insulator plate 111, and a ground plate 112, each of which will be discussed in turn.

[0044] Structurally, in the electrostatic chuck (ESC) 191 version of the substrate support 105, the biasing electrode 104 is separated from the substrate receiving surface 105A of the substrate support 105 by a layer 105B of dielectric material. They are spaced apart. Typically, electrostatic chucks (ESCs) 191 can be classified into two main classes of electrostatic chucks, known as Coulomb ESCs or Johnson Rabek ESCs. Depending on the type of electrostatic chuck 191, such as a Coulomb ESC or a Johnson-Rabek ESC, the effective circuit elements used to describe the electrical coupling of the biasing electrode 104 to the plasma 101 will have slight differences. 1C is a functionally equivalent circuit diagram of a Coulomb ESC that may be used in the process chamber illustrated in FIG. 1A, according to one embodiment. 1D is a functionally equivalent circuit diagram of a Johnson Rabek ESC that may be used in the process chamber illustrated in FIG. 1A, according to one embodiment.

[0045] In the simplest case, such as that of a Coulombic ESC, the dielectric layer 105B will include a capacitance C ₁ as shown in FIGS. 1B and 1C, 2A and 3B. Typically, the layer 105B of dielectric material (e.g., aluminum oxide (Al ₂ O ₃ ), etc.) has a thickness of between about 0.1 mm and about 1 mm, such as between about 0.1 mm and about 0.5 mm, for example. , has a thickness of approximately 0.3 mm. In some embodiments, the dielectric material and layer thickness are such that the capacitance (C ₁ ) of the layer of dielectric material is between about 5 nF and about 100 nF, e.g., between about 7 nF and about 20 nF. can be selected to be

[0046] In more complex cases, such as the Johnson Rabek ESC case, the circuit model includes a capacitance (C 1 ) coupled in parallel with the dielectric material resistance (R _{J R} ) and the gap capacitance (C _{J R} ), as shown in Figure _1D . do. In the case of “Johnson Rabek ESCs”, the ESC dielectric layer is “leaky” in the sense that it is not a complete insulator and has some conductivity, for example because the dielectric material has a dielectric constant (ε) of about 9. ) This is because it may be doped aluminum nitride (AlN). As for the Coulomb chuck, there is a direct capacitance C ₁ between the electrode 104 and the substrate 103 through the thin dielectric 105B and the helium-filled gap. In one example, the volume resistivity of the dielectric layer within the Johnson Rabek ESC is less than about 10 ¹² ohm-cm (Ω-cm), or less than about 10 ¹⁰ Ω-cm, or even between 10 ⁸ Ω-cm and 10 ¹² Ω. -cm, and thus the layer of dielectric material 105B may have a dielectric material resistance R _JR in the range between 10 ⁶ and 10 ¹¹ Ω. Because a gap is typically formed between the substrate support surface 105A and the surface of the substrate 103, the gap capacitance (C _JR ) is adjusted to account for the gas-laden spaces between the substrate 103 and the substrate support surface 105A. It is used. The gap capacitance (C _JR ) is expected to have a slightly larger capacitance than the capacitance (C ₁ ).

[0047] For ease of discussion, the bottom dielectric layer of substrate 103 is typically made of a semiconductor material and/or dielectric material with a thin layer of an intrinsic dielectric layer on the bottom and top surfaces. may be considered to be electrically part of a dielectric layer disposed between biasing electrode 104 and substrate receiving surface 105A. Accordingly, in some applications, the effective capacitance C _E (not shown) formed between biasing electrode 104 and the top surface of substrate 103 is the combined series of dielectric material 105B and substrate bottom layer. It can be approximated by the capacitance (i.e., the substrate capacitance C _sub (Figure 1b)). In the Coulomb chuck case, the series capacitance is dominated by the capacitance (C ₁ ) because the substrate capacitance (C _sub ) is typically very large (>100 nF) or the substrate may be conductive (infinite capacitance). For the Johnson-Rabek ESC case, assuming that the substrate capacitance (C _sub ) is typically very large, the effective capacitance to clamp the substrate, C _E , will be dominated by the gap capacitance (C _{J R} ) to the DC clamping voltage (Figure 1d ). The finite resistance of top dielectric 105B results in a resistance (R _JR ) in series with the gap capacitance (C _JR ), both of which are in parallel with the direct coupling (C ₁ ) between electrode 104 and substrate 103. am. C ₁ is the capacitance that couples the RF frequency voltage from electrode 104 to substrate 103 during plasma processing.

[0048] Referring again to FIG. 1B, an electrical schematic representation of the circuit formed within the substrate support assembly 136 illustrates the capacitance of the dielectric layer positioned between the support base 107 and the biasing electrode 104. Includes the base dielectric layer capacitance (C ₂ ). In some embodiments, the thickness of the portion of dielectric material 105C disposed between support base 107 and biasing electrode 104 is greater than the thickness of the dielectric material disposed between biasing electrode 104 and substrate 103 ( 105B) is greater than the thickness. In some embodiments, the dielectric materials used to form the dielectric layers on either side of the biasing electrode are the same material and form the structural body of the substrate support 105. In one example, the thickness of dielectric material 105C (e.g., Al ₂ O ₃ or AlN), when measured in the direction extending between support base 107 and biasing electrode 104, is less than 1 mm. larger, for example having a thickness between about 1.5 mm and about 100 mm. The support base dielectric layer capacitance (C ₂ ) will typically have a capacitance between about 0.5 and about 10 nanofarads (nF).

[0049] An electrical schematic representation of the circuit formed within the substrate support assembly 136 includes the support base resistance (R _P ), the insulator plate capacitance (C ₃ ), and the ground plate resistance (R _{G )} coupled to ground on one end. ) also includes. Since the support base 107 and ground plate 111 are typically formed from metallic materials, the support base resistance R _P and ground plate resistance R _G are quite low, for example less than a few milliohms. The insulator plate capacitance C ₃ represents the capacitance of the dielectric layer positioned between the bottom surface of the support base 107 and the top surface of the ground plate 112 . In one example, the insulator plate capacitance C ₃ has a capacitance between about 0.1 and about 1 nF.

[0050] Referring again to FIG. 1A, a PV waveform is provided to the biasing electrode 104 by the PV waveform generator 150 of the first PV source assembly 196, and the PV waveform of the second PV source assembly 197 A PV waveform is provided to the edge control electrode 115 by the waveform generator 150 . Pulsed voltage waveforms are provided to a load (eg, composite load 130) disposed within processing chamber 100. PV waveform generators 150 may be a PV generator (P ₁ ), such as the PV generator (P1 _A ) of FIG. 2A or the PV generator (P1 A) of FIG. 2B, which is coupled to the biasing electrode 104 via a power transfer line 157. Includes P1 _B ). Although not intended to be a limitation as to the scope of the disclosure provided herein, and to simplify the discussion, an RF assembly (e.g., RF generator assembly 160 and RF generator 118) and a second PV source Components within assembly 197 are not shown schematically in FIGS. 2A and 2B. The overall control of the delivery of the PV waveform from each of the PV waveform generators 150 is controlled by the use of signals provided from the controller 126. In one embodiment, as illustrated in FIGS. 2A and 2B, PV waveform generator 150 generates a time interval of a predetermined length by use of a signal from a transistor-transistor logic (TTL) source. It is configured to output a periodic voltage function. The periodic voltage function may be two-state DC pulses between zero and a predetermined negative or positive voltage. In one embodiment, PV waveform generator 150 switches its output (i.e., to ground) for regularly recurring time intervals of predetermined length by repeatedly closing and opening one or more switches at a predetermined rate. ) is configured to maintain a predetermined substantially constant negative voltage throughout. In one example, during the first phase of the pulse interval, a first switch is used to couple the high voltage supply to the biasing electrode (104), and during the second phase of the pulse interval, the second switch is used to connect the biasing electrode (104). 104) is used to connect to ground. In another embodiment, as illustrated in FIG. 2B, PV waveform generator 150 generates regularly recurring waves of a predetermined length by repeatedly closing and opening its internal switches (not shown) at a predetermined rate. It is configured to maintain a predetermined, substantially constant positive voltage across its output (i.e., to ground) during time intervals. In one configuration of the embodiment shown in Figure 2B, a first switch is used to connect the biasing electrode 104 to ground during the first phase of the pulse interval, and a second switch is used to connect the high voltage supply during the second phase of the pulse interval. It is used to connect the part to the biasing electrode 104. In an alternative configuration of the embodiment shown in Figure 2b, during the first phase of the pulse interval the first switch is positioned in the open state, so that the biasing electrode 104 is disconnected from the high voltage supply and the biasing electrode 104 is coupled to ground through an impedance network (e.g., an inductor and resistor connected in series). Then, during the second phase of the pulse interval, the first switch is positioned in the closed state to connect the high voltage supply to the biasing electrode 104, while the biasing electrode 104 is coupled to ground via an impedance network. is maintained.

[0051] In FIGS. 2A and 2B, the PV waveform generators 150 have been reduced to the minimum combination of components that are important to understand their role in establishing the desired pulsed voltage waveform at the biasing electrode 104. Each PV waveform generator 150 includes a PV generator (P1 _A or P1 _B ) and a PV waveform configured to provide the output, such as high repetition rate switches (not shown), capacitors (not shown), and inductors. (not shown), fly back diodes (not shown), power transistors (not shown), and/or resistors (not shown). It will include the above electrical components. A practical PV waveform generator 150, which may be configured as a nanosecond pulse generator, may include any number of internal components and may be based on a more complex electrical circuit than that illustrated in FIGS. 2A and 2B. The schematic diagrams in FIGS. 2A and 2B each illustrate the basic principles of operation of the PV waveform generator, its interaction with the plasma in the processing volume, and the pulsed voltage waveform at the biasing electrode 104, such as the pulse in FIG. 3A. It is provided to help explain its role in establishing the linear voltage waveform 301 or the pulsed waveform 401 of FIG. 4A.

[0052] Power delivery line 157 (FIGS. 1A and 1B) electrically couples the output of PV waveform generator 150 to optional filter assembly 151 and biasing electrode 104. Although the following discussion primarily discusses the power transfer line 157 of the first PV source assembly 196 used to couple the PV waveform generator 150 to the biasing electrode 104, the PV waveform generator 150 The power delivery line 158 of the second PV source assembly 197 that couples to the edge control electrode 115 may include the same or similar components. 2A and 2B, the output of PV waveform generator 150 is provided to node N ₃ . The electrical conductor(s) within the various portions of the power transmission line 157 may include: (a) a coaxial transmission line, which may include a flexible coaxial cable in series with a rigid coaxial transmission line (e.g. For example, coaxial line 106), (b) insulated high-voltage corona-resistant hookup wire, (c) bare wire, (d) metal rod, ( e) an electrical connector, or (f) any combination of the electrical elements of (a) to (e). The power transmission line 157, such as the portion of the power transmission line 157 within the support shaft 138 (FIG. 1A) and the biasing electrode 104, has some combined stray capacitance (C _stray ) with respect to ground (not shown). ) will have. The optional filter assembly 151 is one or more electrical elements configured to substantially prevent current generated by the output of the RF generator 118 from flowing through the power delivery line 157 and damaging the PV waveform generator 150. includes them. Optional filter assembly 151 acts as a high impedance (e.g., high Z) to the RF signal generated by RF generator 118, thus inhibiting the flow of current to PV waveform generator 150.

[0053] In some embodiments, as shown in FIGS. 1A and 2A and 2B, the PV waveform generator 150 of the first PV source assembly 196 generates a pulsed voltage waveform signal to the biasing electrode 104. ) and, ultimately, the generated pulsed voltage waveforms to the node (N ₃ ) and blocking capacitor (C ₅ ), filter assembly 151, high voltage line inductance (L ₁ ), and capacitance (C ₁ ). It is configured to provide to the composite load 130 by transmitting it through. The PV waveform generator 150 is connected between the ground node (N _G ) and the node (N ₃ ). A capacitor C ₅ is additionally connected between node N ₃ and node N ₁ to which the clamping network 116 is attached. Clamping network 116 is connected between node N ₁ and ground node N _G . In one embodiment, as shown in Figure 2A, clamping network 116 includes at least a diode (D ₁ ), a capacitor (C ₆ ), a DC voltage source (P ₂ ), a current limiting resistor (R ₂ ), and a blocking circuit. Includes a resistor (R ₁ ). In this configuration, a diode (D ₁ ) and a blocking resistor (R ₁ ) are connected between node (N ₁ ) and node (N ₂ ), and a DC voltage circuit in series with the capacitor (C ₆ ) and current limiting resistor (R ₂ ). The voltage source (P ₂ ) is connected between the node (N ₂ ) and the ground node (N _G ). In other embodiments, as shown in Figure 2B, clamping network 116 includes a capacitor (C ₆ ), a DC voltage source (P ₂ ), a resistor (R ₂ ), and a blocking resistor (R ₁ ). . In this configuration, a blocking resistor (R ₁ ) is connected between node (N ₁ ) and node (N ₂ ), and a DC voltage source (P ₂ ) in series with a capacitor (C ₆ ) and a current limiting resistor (R ₂ ). is connected between the node (N ₂ ) and the ground node (N _G ). Typically a DC voltage source (P ₂ ) is used to establish the output voltage of the clamping network 116 which is the voltage difference across the capacitor (C ₆ ).

[0054] The clamping network 116, when used in combination, as shown in FIGS. 2A and 2B, forms a current suppression/filtering circuit for PV waveforms from the PV generator, resulting in the PV waveforms It induces no significant current to ground through clamping network 116. The influence of the clamping network 116 on the operation of the PV generator P1 _A (Figure 2a) or the PV generator P1 _B (Figure 2b) depends on the appropriately large blocking capacitor _C5 and blocking resistor _R1 . It can be made ignorable by selecting . The blocking resistor R ₁ schematically illustrates a resistor positioned within the components connecting the clamping network 116 to a point in the power transmission line 157 , such as a node N ₁ . The main function of the blocking capacitor (C ₅ ) is to protect the PV pulse generator (P1 _A ) from the DC voltage generated by the DC voltage source (P ₂ ), so that the DC voltage drops across the blocking capacitor (C ₅ ). and does not disturb the output of the PV waveform generator. The value of blocking capacitor C ₅ is such that it provides to node N ₃ while blocking only the DC voltage generated by DC voltage source P ₂ such that most of the pulsed voltage is delivered to composite load 130. It is selected to produce negligible impedance at the pulsed voltage output of the pulsed bias generator. By choosing a sufficiently large blocking capacitance (e.g., 10-80 nF), the blocking capacitor (C ₅ ) ensures that it _is much larger than any other relevant capacitance in the system and that the voltage drop across this element is 400 generated by PV waveform generator 150, in that it is very small compared to that across other relevant capacitors, such as the external capacitances C _SH and C _WALL (FIGS. 2A and 2B). Almost transparent to kHz PV waveform signals.

[0055] Referring to FIGS. 2A and 2B, the purpose of the blocking resistor (R ₁ ) of the clamping network 116 is to divert the pulsed voltage generated by the PV waveform generator 150 from the DC voltage supply (P ₂ ). It blocks enough to minimize the current it induces. This blocking resistor (R ₁ ) is sized to be large enough to effectively minimize the current (i ₁ ) passing through it. For example, to make negligible the current resulting from the transmission of the 400 kHz pulsed voltage signal into the clamping network 116 by the PV waveform generator 150 to the node N ₁ , the current is greater than 200 kOhm, for example 1. Resistors greater than MOhms, or greater than 10 MOhms, or even in the range between 200 kOhms and 50 MOhms are used. The average induced DC current is preferably less than about 40 mA, such as less than 30 mA, or less than 20 mA, or less than 10 mA, or less than 5 mA, or even between 1 μA and 20 mA.

[0056] In some configurations, blocking resistor (R ₁ ) is a charge/discharge path useful for resetting the clamping voltage that builds up across capacitor (C _{1 ) when diode (D 1 )} is not in forward bias mode. provides. For example, at the beginning of the plasma process, the substrate is clamped to the electrostatic chuck surface 105A by charging capacitor C ₁ to a predetermined voltage. Such charging current supplied to capacitor C ₁ may be provided by clamping network 116 via resistor R ₁ ( FIGS. 2A and 2B ). Similarly, during the dechucking step of the substrate, the discharge current from the capacitor C ₁ may flow through R ₁ . The charging or discharging current of the capacitor C ₁ determines the rate at which the steady state of either clamping (eg, chucking) or dechucking of the substrate is reached. Accordingly, in some embodiments, blocking resistor R ₁ is selected such that its resistance is not too large, such as less than about 50 MOhms.

[0057] In one embodiment of the processing chamber 100, as illustrated in FIG. 5A, the RF waveform is provided by the RF source assembly 163 to the support base 107, which is positioned at node N ₅ do. In some embodiments, RF source assembly 163 may be a multi-frequency RF source. In this configuration, the RF source assembly 163 is coupled to an electrode, such as a support base 107, via an effective capacitance C ₈ that is part of the RF match 162 and the first filter assembly 161, and a clamping network ( 116) is coupled to the biasing electrode 104 through a power transmission line 157. The RF waveform is provided to a load (e.g., composite load 130) disposed within processing chamber 100. RF source assembly 163 of FIG. 5A is capacitively coupled to load 130 through RF power transfer to support base 107. While not intended to be a limitation as to the scope of the disclosure provided herein, and to simplify the discussion, one or more optional PV source assemblies in this example are not schematically shown in FIG. 5A. The overall control of RF waveform propagation is controlled by the use of signals provided from controller 126. As illustrated in FIG. 5B , a sinusoidal RF waveform provided from RF source assembly 163 to processing region 129 is provided during a burst period 510 and interrupted during a burst-off period 514. . In FIG. 5A , the RF source assembly 163 has been reduced to the minimal combination of components that are important to understand its role in establishing the desired RF waveform for the support base 107. As discussed above, RF source assembly 163 may include components within RF matching circuit 162 and first filter assembly 161.

Process monitoring and control examples

[0058] In some embodiments, as illustrated in FIG. 1A, the processing chamber 100 is configured to detect within the processing chamber 100 by use of a plurality of signal lines 187, illustrated in FIG. 1E. It further includes a signal detection module 188 electrically coupled to one or more electrical components. 1E includes a number of signal traces 192 coupled to various electrical components within processing chamber 100 and configured to convey electrical signals to signal detection elements found within signal detection module 188. Illustrative schematic diagram of processing chamber 100. Typically, signal detection module 188 includes one or more input channels 172 and a high-speed data acquisition module 120. Each of the one or more input channels 172 is configured to receive electrical signals from signal trace 192 and is electrically coupled to high-speed data acquisition module 120. Received electrical signals may include one or more characteristics of the waveforms generated by PV waveform generator 150 and/or RF generator 118. In some embodiments, high-speed data acquisition module 120 is configured to generate control signals used to automatically control and maintain a substantially constant clamping voltage during processing, resulting in improved clamping of the substrate during plasma processing. Additionally, high-speed data acquisition module 120 includes one or more acquisition channels 122. Controller 126 provides signal via one or more signal lines 187 to signal detection module 188, processed by components to high-speed data acquisition module 120, and then received by controller 126. It is configured to generate a control signal used to automatically control and maintain the clamping voltage based on the signal information. The signal information received by the controller 126 then provides the desired real-time adjustment of the voltage applied by the DC voltage supply P ₂ of the clamping network 116 based on the analyzed characteristics of the received signal information. It can be analyzed to make it possible.

[0059] FIG. 1E schematically illustrates an example of a signal detection module 188 including multiple input channels 172, each electrically coupled to a corresponding acquisition channel 122 of the high-speed data acquisition module 120. Example: A plurality of input channels 172, such as input channels 172 ₁ - 172 ₃ , connect various portions of the first PV source assembly 196 to measure and collect electrical data from these connection points during processing. It is connected to the connection points positioned at. Additionally, multiple input channels 172, such as input channels 172 ₄ - 172 _N , for measuring and collecting electrical data from one or more points or nodes within RF source assembly 163 during processing. , coupled to connection points positioned at various parts of the RF source assembly 163 (Figure 1A). In one example, input channels 172 ₄ - 172 _N are configured to detect RF waveforms 181 that establish at different points within RF source assembly 163 during plasma processing. Multiple input channels 172 may also be coupled to various electrical sensing elements, such as current sensors, configured to measure and collect electrical data at various points within processing chamber 100. 1E schematically illustrates a configuration in which only a few input channels 172 are coupled to points within the first PV source assembly 196 and the RF source assembly 163, the number of input channels 172 may be as desired. This configuration is not intended to be a limitation on the scope of the disclosure provided herein, as it can be increased or decreased as needed to control chamber processing applications. In some embodiments, one or more input channels 172 are connected to different portions of the first PV source assembly 196, the second PV source assembly 197, and the RF source assembly 163.

[0060] One or more of the input channels 172 may include a conditioning circuit, such as, for example, a conditioning circuit 171 ₁ of the input channel 172 ₁ and a conditioning circuit 171 ₂ of the input channel 172 ₂ . 171) may be included. Additionally, one or more input channels 172 are configured to generate conditioned output waveforms. In some embodiments, each of conditioning circuits 171 may include a voltage divider, a low-pass filter, or both a voltage divider and a low-pass filter, or even in some cases a voltage divider or a low-pass filter. may also not include, which is referred to herein as an unattenuated conditioning circuit. Examples of various conditioning circuit elements, such as voltage dividers and filters, and their integration with input channels are further described in U.S. Pat. No. 10,916,408, which is incorporated herein by reference in its entirety.

[0061] FIG. 1E illustrates a configuration where the signal detection module 188 includes a plurality of input channels, such as input channels 172 ₁ - 172 _N , where N is generally a number greater than 1. Each of the input channels 172 ₁ - 172 _N may be connected to different points within the plasma processing chamber 100 . For example, input channel 172 ₁ may be connected to an electrical conductor used to couple PV waveform generator 150 to blocking capacitor C ₅ (FIG. 1E). In embodiments where the input channel 172 ₁ is coupled between the output of the PV waveform generator 150 and the blocking capacitor C ₅ , the input channel 172 ₁ generates an input pulsed voltage waveform ( For example, receiving a first input pulsed voltage waveform 182 (FIG. 1E), conditioning circuit 171 ₁ generates an output waveform (e.g., a conditioned waveform). In one example, the received or measured input pulsed voltage waveform exhibits positive and negative voltage levels within each of the different phases of the voltage pulses and high frequency oscillations within various phases of the pulse within the input pulsed voltage waveform. voltage pulses comprising voltage pulses, wherein the received or measured input pulsed voltage waveform, when conditioned by components within the conditioning circuit 171 ₁ , such as a voltage divider, results in at least a lower voltage level due to the use of the voltage divider. Forms the output waveform provided by . In one example, the voltage pulses include voltage pulses that include positive and negative voltage levels within different phases of each of the voltage pulses and high frequency oscillations within at least one of the phases of each pulse in the input pulsed voltage waveform. The input pulsed voltage waveform is received by the input channel 172 ₁ and then conditioned by components within the conditioning circuit 171 ₁ , such as a voltage divider and a low-pass filter, to produce a filtered waveform at a reduced voltage level. Forms an output waveform. In embodiments where input channel 172 ₂ is coupled between blocking capacitor C ₅ and biasing electrode 104 , input channel 172 ₂ is coupled to an input pulsed voltage waveform (e.g., a second input pulse receives the equation voltage waveform) and the conditioning circuit 171 ₂ generates an output waveform (e.g., a conditioned waveform). Generally, the first input pulsed voltage waveform received by input channel 172 ₁ has a power level within the plasma processing chamber 100 that is different from the second input pulsed voltage waveform received by input channel 172 ₂ . Due to the position of their individual connection points along the transmission line 157, they will have different waveform characteristics.

[0062] High-speed data acquisition module 120 is generally configured to receive analog voltage waveforms (e.g., conditioned waveforms) and to transmit digitized voltage waveforms. The high-speed data acquisition module 120 includes one or more acquisition channels 122, each of which is electrically coupled to a respective conditioning circuit 171 of the first input channel 172, and the high-speed data acquisition module 120 includes configured to generate a digitized voltage waveform from a received conditioned voltage waveform (e.g., an output waveform), wherein the data acquisition controller 123 of the high-speed data acquisition module 120 performs conditioning by analyzing the first digitized voltage waveform. and configured to determine one or more waveform characteristics of the voltage waveform.

[0063] As illustrated in FIG. 1E, the high-speed data acquisition module 120 includes a plurality of acquisition channels 122 ₁ -122 _N , a data acquisition controller 123, and memory 124 (e.g., non-volatile memory). Each of the acquisition channels 122 is electrically coupled to the output of a corresponding one of the input channels 172 such that the acquisition channel 122 receives an output waveform from the corresponding one of the input channels 172. . For example, the acquisition channel 122 ₁ is electrically coupled to the output end of the input channel 172 ₁ , and is connected according to the position of the connection point of the input end of the input channel 172 ₁ . , receives any one first output waveform. Additionally, acquisition channel 122 ₂ is electrically coupled to the output end of input channel 172 ₂ and receives a second output waveform. Additionally or alternatively, acquisition channel 122 ₃ is electrically coupled to the output end of input channel 172 ₃ and receives a third output waveform. Acquisition channel 122 _N is electrically coupled to the output terminal of input channel 172 _N and receives the Nth output waveform.

[0064] The data acquisition controller 123 is electrically coupled to the output of each of the acquisition channels 122 and is configured to receive a digitized voltage waveform from each of the acquisition channels 122. Additionally, algorithms stored within memory 124 of data acquisition controller 123 are adapted to determine one or more waveform characteristics of each of the conditioned waveforms by analyzing each of the digitized voltage waveforms. The analysis may include comparison of information received in the digitized voltage waveform with information regarding one or more stored waveform characteristics stored in memory 124 and discussed further below.

[0065] Data acquisition controller 123 includes an analog-to-digital converter (ADC) (not shown), a processor 121 (FIG. 1E), a communication interface (not shown), and a clock (not shown). and optional drivers (not shown). The processor may be any general computing processor. Additionally, the processor may be a Field Programmable Gate Array (FPGA). The ADC converts the signal in the output waveforms from the analog domain to the digital domain, and the ADC's output digital signal is provided to the processor 121 for processing. Processor 121 of data acquisition controller 123 determines one or more waveform characteristics of the output waveform by analyzing the output digital signal provided from the ADC.

[0066] In various embodiments, high-speed data acquisition module 120 additionally includes memory 124. Memory 124 may be any non-volatile memory. Additionally, data acquisition controller 123 is electrically coupled to memory 124 and is configured to cause waveform characteristics to be stored in memory 124. In various embodiments, memory 124 may cause data acquisition controller 123 to analyze the received output waveforms and/or transmit information corresponding to waveform characteristics determined based on the analysis of the received output waveforms. It includes instructions executable by the data acquisition controller 123 to do this. The waveform analyzer stored in memory 124 is executable by data acquisition controller 123 and includes instructions that, when executed, cause data acquisition controller 123 to analyze output waveforms to determine waveform characteristics. Information regarding the analyzed waveform characteristics may then be transmitted to one or more of feedback processor 125 and/or controller 126. The analysis performed by data acquisition controller 123 may include comparison of waveform characteristics and one or more waveform characteristic threshold values stored in memory.

[0067] In some embodiments, high-speed data acquisition module 120 is coupled to feedback processor 125 via data communication interface 125A, where feedback processor 125 is executed by a processor disposed within data acquisition controller 123. configured to generate one or more control parameters using one or more waveform characteristics determined by one or more algorithms. In general, feedback processor 125 may be any general computing processor. In some embodiments, feedback processor 125 generally includes: an external processor coupled to high-speed data acquisition module 120 via a data communication interface; one of the internal processors integrated within the high-speed data acquisition module 120; or is part of a substrate processing chamber controller (e.g., controller 126) coupled to a high-speed data acquisition module through a data communication interface. Data acquisition module 120 may transmit information corresponding to one or more of the received output waveforms to feedback processor 125. For example, data acquisition module 120 may convey information related to one or more detected and/or processed waveform characteristics of one or more of the received output waveforms to feedback processor 125. Additionally, feedback processor 125 may be communicatively coupled with plasma processing system 100 via communication link 350 (FIG. 3B).

[0068] In various embodiments, feedback processor 125 includes memory that further includes software algorithms for instructing a processor within feedback processor 125 to perform one or more portions of the methods described herein. The one or more algorithms, when executed by the processor 121 of the high-speed data acquisition module, cause the high-speed data acquisition module to process one or more output waveforms (e.g., conditioned voltage waveforms) to process one or more of the received output waveforms. Contains commands that allow you to determine waveform characteristics. Controller 126, or feedback processor 125 disposed within controller 126, when executed by a processor (CPU), causes controller 126 or feedback processor 125 to: and a memory containing instructions to generate one or more control parameters using the provided determined one or more waveform characteristics. Instructions executed by controller 126 or feedback processor 125 may also cause transmission of information regarding the generated one or more control parameters to clamping network 116 along communication link 350 (FIG. 3B). It may be further configured to cause. Clamping network 116 and/or controller 126, when executed by a processor of clamping network 116 and/or controller 126, causes clamping network 116 to: It may also include memory containing instructions to establish a desired chucking voltage level at the biasing electrode 104 based on one or more control parameters.

[0069] In one or more embodiments, high-speed data acquisition module 120 may be electrically coupled (wired or wirelessly) with the controller 126 of processing chamber 100. For example, high-speed data acquisition module 120 may transmit data to and/or receive data from controller 126. For example, high-speed data acquisition module 120 communicates information related to one or more waveform characteristics to controller 126. Additionally, processing chamber controller 126 may be communicatively coupled to clamping network 116 of processing chamber 100 via communication link 350. In various embodiments, processing chamber controller 126 is omitted. The algorithm stored within the memory of the processing chamber controller 126, when executed by the controller CPU, determines various process chamber set points based on information related to one or more waveform characteristics determined by the data acquisition controller 123. , for example, may include instructions that cause the chucking voltage set point on the chucking power supply to be adjusted.

Clamping module control methods and hardware examples

[0070] As discussed above, the ability to provide real-time control over the clamping voltage level applied to the clamping electrode (e.g., biasing electrode 104) during plasma processing is helpful in improving and achieving repeatable plasma processing results. And it is useful to ensure that clamped boards are not damaged during processing. FIG. 3A illustrates a burst 316 of pulsed voltage waveforms comprising a plurality of waveforms generated and transmitted from one or more sources to one or more electrodes disposed in the process chamber 100 . For example, each of waveforms 301-304 may be established at different points within system 300 (FIG. 3B) by delivery of a pulsed voltage waveform (not shown) generated by PV waveform generator 150. do. In some embodiments, a series of individual bursts 316 are provided to the biasing electrode 104, each separated by a burst off period 314. A burst cycle 317 comprising a burst of pulsed voltage waveforms 316 and a burst off period 314 performed sequentially, as discussed further below with respect to FIGS. 3A and 4B-4D, This may be repeated multiple times during substrate processing.

[0071] System 300 may include, for example, a process that includes from a PV waveform generator 150 of a first PV source assembly 196 (FIG. 1A) to a biasing electrode 104 disposed within a substrate support assembly 136. This is a simplified schematic diagram generally representing portions of chamber 100. Components within system 300 detect and determine waveform characteristics of one or more PV waveforms transmitted from PV waveform generator 150 by detecting characteristics of electrical signals detected at different points within system 300 at different times. It is used for. Signal lines 321-325 are similar to the plurality of signal lines 187 illustrated in Figure 1E and thus are connected to various points within the processing system and input channels 172 of signal detection module 188 (Figure 3B). is intended to illustrate connections between (not shown).

[0072] As illustrated in FIG. 3A, the plurality of measured PV waveforms 301-304 include a series of pulses provided during a PV wave burst 316. In this example, the last three of the series of pulses are shown within burst 316. Each of the three pulses within each of the PV waveforms 301-304 has a waveform period (T _p ). After delivery of the burst 316 of pulses having a burst-on period 310, the output of the PV waveform generator 150 is such that the system 300 generates any PV waveforms by the PV waveform generator 150. We are suspended to experience a period of time that is not created. The time during which no PV waveforms are formed is referred to herein as the non-burst period (314) or “burst off” period (314). There is a transition region between the burst 316 and the steady state portion of the non-burst period 314, which is referred to herein as the plasma relaxation period 312. At the end of the non-burst period 314, a second burst (not shown) comprising a plurality of pulses is generated and delivered from the PV waveform generator 150. During processing of a substrate, it is typical for each burst 316 within a series of bursts to be separated by burst off periods 314, resulting in burst 316 and burst off periods 314 (i.e., burst off periods 314). Cycles 317) are sequentially formed multiple times. Accordingly, a single burst cycle 317 comprising burst 316 and burst off period 314 is a burst cycle of burst on period 310 (i.e., T _ON ) and burst off period 314 (i.e., T _OFF ). It has the same length as the sum, which is also referred to herein as the burst period (T _BD ) (Figure 4b). In one example, the burst on period 310 is between about 100 microseconds (μs) and about 10 milliseconds (ms), such as between about 200 μs and about 5 ms. In one example, the waveform period (T _p ) is between about 1 μs and about 10 μs, such as about 2.5 μs. The burst duty cycle may be between about 5% and about 100%, such as between about 50% and 95%, where the duty cycle divides the burst on period 310 into a burst on period 310 and a non-burst period 314. It is a ratio divided by the added value.

[0073] The PV waveform 301 is measured, for example, at a point between the blocking capacitor C ₅ and the biasing electrode 104, illustrated as node N ₁ in FIG. 3B. Accordingly, the measured voltage is related to the actual voltage measured at the biasing electrode 104 during different phases of the processing sequence performed in the processing chamber. The measured voltage of the PV waveform, also referred to herein as the electrode voltage _V ), it changes over time. In one embodiment, PV waveform 301 is measured by an electrical coupling assembly (not shown) positioned at node N ₁ . An electrical coupling assembly is coupled to a signal trace 324 that communicates with an input channel 172 within signal detection module 188.

[0074] In some embodiments, the PV waveform (not shown) generated at the output of PV waveform generator 150 generates a voltage formed at an electrical coupling assembly (not shown) positioned at node N ₃ . Measurements are made and utilized in one or more of the processes described herein. The PV waveform measured in the PV waveform generator 150 will closely track the PV waveform 301 and the measured waveform will be offset from the PV waveform 301 by at least an amount related to the set point of the DC voltage supply (P ₂ ). It will have voltage. In this configuration, as shown in FIG. 3B, an electrical coupling assembly is coupled to a signal trace 321 that communicates with an input channel 172 within signal detection module 188.

[0075] PV waveform 302 is intended to represent the voltage established on substrate 103 during processing due to propagation of PV waveforms provided from PV waveform generator 150. As shown in FIG. 3A , PV waveform 302 tracks measured PV waveform 301 very closely, and as a result, PV waveform 302 is typically a fixed amount from PV waveform 301. It is considered to be offset by The offset voltage formed during processing between the electrode 104 and the substrate 103 is referred to herein as the clamping voltage and is mainly set by the set point of the DC voltage supply P ₂ . In some configurations, the PV waveform 302 is connected to a voltage probe attached to a signal trace 322 in good contact with the front or back side of the substrate 103 and in communication with the input channel 172 within the signal detection module 188. It can be measured by In most process chamber hardware configurations, substrate voltage is not easy to measure directly due to capacitive coupling between ESC hardware limitations, measurement signal integrity issues, and chamber component-related issues. By use of the methods described herein, the need for direct measurement of substrate voltage can be avoided by use of the various measurement techniques and processes described herein.

[0076] In some embodiments, the PV waveform 303 is measured at a node that is directly coupled to a second conductor plate positioned within the processing chamber 100. In one embodiment, the second conductor plate is a support base 107 positioned at node N ₅ in FIG. 3B. As shown in Figure 3b, the second conductor plate is positioned between capacitance C ₃ and capacitance C ₂ , which are formed by the presence of insulator plate 111 and dielectric layer 105C, respectively. It is intended to represent capacitances. Accordingly, the measured voltage is related to the actual voltage measured at the support base 107 during different phases of the processing sequence performed in the processing chamber. The measured voltage of the PV waveform, referred to herein as voltage V _C , is transferred from the PV waveform generator 150 to the biasing electrode 104 during processing of a series of bursts 316 and non-burst periods 314. As it is provided, it changes over time. In some embodiments, PV waveform 303 is formed by the use of a source, such as RF source assembly 163, coupled to the chamber through conductor plate 107. PV waveform 303 can be measured by the use of an electrical coupling assembly coupled to a signal trace 323 positioned at node N ₅ and communicating with an input channel 172 within signal detection module 188.

[0077] In some embodiments, PV waveform 304 is measured at a node that is directly coupled to PV source 150. The measured voltage of PV waveform 304, referred to herein as voltage V _R , is generated over time as a series of bursts 316 and non-burst periods 314 are provided from PV waveform generator 150 It changes. In some embodiments, PV waveform 304 is configured to achieve a desired voltage (V ₄ ) during non-burst periods 314 and thus does not electrically float during non-burst periods 314. In some embodiments, PV waveform 304 is configured to float electrically during non-burst periods 314. PV waveform 304 can be measured by use of an electrical coupling assembly coupled to node N ₃ and signal trace 321 in communication with input channel 172 within signal detection module 188.

[0078] FIG. 4A shows biasing electrode 104 by use of a DC voltage source (P ₂ ) of assembly 116 and a PV waveform generator 150 within a PV source assembly during a portion of the waveform period (T _p ). An example of the PV waveform 401 is illustrated. The PV waveform 402 is generated at the substrate due to the PV waveform 401 being established at the biasing electrode 104 by the PV waveform generator 150 and the DC voltage source P ₂ , as shown in Figure 4A. It includes a series of PV waveforms (e.g., V _W ) established in . PV waveforms 401 and 402 are intended to illustrate more detailed examples of portions of PV waveforms 301 and 302 illustrated in FIG. 3A.

[0079] The output of PV waveform generator 150, which can be controlled by settings of a plasma processing recipe stored in the memory of controller 126, is a peak-to-peak voltage, also referred to herein as pulse voltage level (V _pp ). A PV waveform 401 containing is formed. PV waveform 402, which is the waveform seen by substrate 103 due to the propagation of PV waveform 401, extends between point 420 and point 421, causing sheath decay and recharge phase 450 (or For simplicity, a sheath collapse phase 450), a sheath formation phase 451 extending between points 421 and 422, and a sheath formation phase 451 extending between points 422 and the next sequentially established point 420 of the pulse voltage waveform. characterized in that it comprises an ion current phase 452 extending back between the starting point at . Depending on the desired plasma processing conditions, at least PV waveform characteristics, such as PV waveform frequency (1/T _P ), pulse voltage level (V _pp ), pulse voltage on time, and/or other characteristics of the PV waveforms within burst 316 It is desirable to control and set parameters to achieve desirable plasma processing results on a substrate. In one example, the pulse voltage (PV) is defined as the ratio of the ion current time period (e.g., the time between point 422 and the subsequent point 420 in FIG. 4A) to the waveform period (T _p ). Time is varied from one plasma processing recipe to another to adjust the etch rate. In some embodiments, the PV on time is greater than 50%, or greater than 70%, such as between 80% and 95%.

[0080] FIG. 4B illustrates PV waveforms in which a series of bursts 462 of pulsed voltage waveforms are established at the biasing electrode 104 and the substrate surface. In the example illustrated in FIG. 4B , the plurality of pulses 461 within each burst 462 include a series of PV waveforms 401 that are established at the biasing electrode 104 . In this example, the bursts 462 each have pulses 461 with a PV waveform having a consistent pulsed voltage shape (e.g., a constant voltage magnitude is provided during a portion of each PV waveform 401); a burst propagation length (T _ON ) that does not vary from one burst 462 to another over time, and a burst rest length (T _OFF ) that does not vary in length over time. do. The burst pause length (T _OFF ) is formed by stopping the propagation of the PV waveforms provided during the burst propagation length (T _ON ) for a period of time. In this example, the burst ratio is the ratio of the length of time over which a plurality of pulses are delivered during a burst (i.e., the burst delivery length (T _ON )) divided by the duration of the burst period (i.e., T _BD = T _ON + T _OFF ). The duty cycle of fields 462 is also constant. For clarity of discussion, the sum of the burst on period 310 and burst off period 314 referenced in FIG. 3A is intended to be equal to the burst period T _BD referenced in FIG. 4B. It will be appreciated that in other processing methods, the plurality of pulses 461 may include negative pulse waveforms, shaped pulse waveforms or positive pulse waveforms, or combinations thereof. As illustrated in FIG. 4B , the biasing electrode potential curve 436 during the burst pause length (T _OFF ) is primarily controlled by the chucking voltage applied and controlled by the bias compensation module 116, and thus the plasma potential and may be at different voltage levels.

[0081] Figure 4C illustrates a PV waveform in which a series of multi-level bursts 490 of pulsed voltage waveforms are established at an electrode, such as a biasing electrode 104. During processing, a series of bursts 490 is provided to the biasing electrode 104, including a plurality of bursts 491 and 492 and a burst off period 493. The series of bursts 490, including the series of bursts 491 and 492 followed by a burst off period 493, may be sequentially repeated one or more times. In one example, each of the plurality of bursts 491 and 492 is supplied at different voltage levels, as illustrated by the difference in the levels of the respective peaks of each of the bursts 491 and 492. Includes PV waveforms 401. In some embodiments, the transition from burst 492 to burst 491 is separated by burst off period 493, while the transition from burst 491 to burst 492 is separated by burst off period 493. not separated. The series of bursts 490 is such that the pulse waveforms provided to the biasing electrode 104 during burst 491 have a higher pulse voltage level ( Due to having V _pp ) (Figure 4a), it is often referred to as a “high-low” series of bursts. Bursts 491 are often referred to herein as comprising a “high” pulse voltage level (V _pp ), and bursts 492 are often referred to herein as comprising a “low” pulse voltage level (V _pp ). do.

[0082] Figure 4D illustrates a PV waveform in which a series of multi-level bursts 494 of pulsed voltage waveforms are established at an electrode, such as biasing electrode 104. The series of bursts 494, which also includes a plurality of bursts 491 and 492 oriented in different “low-high” configurations and a burst off period 493, may be sequentially repeated one or more times. In one example, each of the plurality of bursts 491 and 492 is supplied at different voltage levels, as illustrated by the difference in the levels of the respective peaks of each of the bursts 491 and 492. Includes PV waveforms 401. In some embodiments, the transition from burst 492 to burst 491 is not separated by a burst off period 493, while the transition from burst 491 to the next burst 492 is separated by a burst off period 493. is separated by

[0083] FIG. 5B illustrates a burst of RF waveforms 516 comprising a plurality of waveforms generated and transmitted from the RF source assembly 163 to an electrode disposed in the process chamber 100. For example, waveforms 502-504 are each established at different points within system 500 (FIG. 5A) by propagation of RF waveform 501 generated by RF generator 118. The waveforms 502 - 504 include a waveform formed at the substrate (V _W ), a waveform formed at the surface of the electrostatic chuck (V _S ), and a waveform formed at the biasing electrode 104 (V _E ), respectively. FIG. 5A illustrates a system ( 500) Illustrates an example of a configuration. Signal traces 322-325 are similar to the plurality of signal traces 192 of the plurality of signal lines 187 illustrated in FIG. 1E and thus are used at various points within the processing system and signal detection module 188. It is intended to illustrate connections between input channels 172 (not shown in FIG. 3B).

[0084] As illustrated in FIG. 5B, the plurality of measured RF waveforms 501-504 include a series of pulses provided during an RF burst 516. In this example, two cycles of the RF waveform are shown within burst 516. The measured RF waveforms, such as RF waveforms 501-504, have a waveform frequency controlled by RF generator 118, which may be between 100 kHz and 120 MHz. After delivery of the RF burst 516 having a burst period 510, the output of the RF generator 118 is such that the system 500 has a period of time in which no RF waveforms are being generated by the RF generator 118. Stopped to experience. The time during which no RF waveforms are formed is referred to herein as a non-burst period 514 or a “burst off” period 514. There is a transition region between the burst 516 and the steady state portion of the non-burst period 514, which is referred to herein as the plasma relaxation period 512. At the end of the non-burst period 514, a second burst (not shown) comprising a plurality of RF waveforms is generated and delivered from the RF generator 118. During processing of a substrate, it is typical for each burst 516 within a series of bursts to be separated by non-burst periods 514, resulting in a series of bursts 516 and non-burst periods 514. is formed sequentially multiple times. In one example, the burst period 510 is between about 20 microseconds (μs) and about 100 milliseconds (ms), such as between about 200 μs and about 5 ms. The burst duty cycle may be between about 5% and 100%, such as between about 50% and about 95%, where the duty cycle is equal to the burst period 510 plus the burst period 510 and the non-burst period 514. It is a ratio divided by

Plasma potential analysis

[0085] In order to reliably generate the desired clamping voltage (V _DCV ) during the plasma process, changes in the plasma potential need to be taken into account when delivering the clamping voltage to the clamping electrode during processing. As discussed above, the ability to reliably measure and monitor plasma potential in a processing chamber configured to continuously process multiple substrates in a production environment is a critical task. In one or more of the embodiments of the disclosure provided herein, the plasma potential is determined based on measurements made at different points within the plasma processing system during different portions of the substrate processing sequence. 6A illustrates a processing method that can be used to measure, monitor, and control the attributes of a plasma formed in a processing chamber such that the desired clamping voltage can be reliably controlled and applied to a clamping electrode disposed within the substrate support. . The capacitance C ₁ is assumed to be the net series capacitance of dielectric layer 105B, the gap between dielectric surface 105A and the substrate backside, and the thinnest dielectric layer possible on the substrate backside surface.

[0086] The plasma potential curve 433 shown in FIG. 4A illustrates the local plasma potential during propagation of the PV waveform 401 established at the biasing electrode 104 by use of the PV waveform generator 150. During processing, the plasma potential is generally maintained at or near zero volts throughout most of the burst on period 310 and during the burst off period 314. The plasma potential will achieve its peak value (V _PL ) during the sheath collapse phase 450, which coincides with the time (T ₁ ) in FIGS. 3A and 4A. Additionally, at time T ₁ , when the multi-phase PV waveform 401 reaches its peak value, the voltage at the biased electrode (e.g., bias electrode 104) is connected to the DC voltage source ( It will be equal to the output voltage (V _BCM ) supplied by P ₂ ). Accordingly, fluctuations in plasma potential can be on the order of 1 kV or more, and thus substrate clamping systems that do not account for fluctuations in plasma potential due to transfer of bias to one or more electrodes within processing chamber 100 may result in poor plasma processing. This may lead to damage to the substrate and/or the substrate. Referring to Figure 4A, times T ₂ and T ₃ illustrate the beginning of the burst off period and the end of the transition period 312, respectively. The period of time between times T ₂ and T ₃ is referred to herein as the plasma relaxation time, which generally indicates that once PV waveforms and RF power delivery cease during the burst off period 314, the plasma dissipates. It's the time it takes to get there. Time T ₄ is intended to represent the time of the positioning measurement after the end of the transition period 312 and before the start of the next burst 316 (not shown).

[0087] In an effort to provide a desired clamping voltage (V _DCV ) at node N ₁ , V _BCM at node N ₂ , which is the set point of DC voltage source P ₂ , is a function of the change in plasma potential. is adjusted by the use of computer-implemented instructions configured to take that change into account accordingly. The desired clamping voltage (V _DCV ) set point is generally the peak plasma potential affected by plasma processing conditions and substrate surface material, plus the clamp voltage set point (V _clamp ) for the type of electrostatic chuck being used during processing. Same as (V _PL ). Accordingly, the desired clamping voltage set point (V _DCV ) can be written as shown in equation (1).

[0088] The clamp voltage set point (V _Clamp ) is a constant voltage value determined through preliminary testing and evaluation of the electrostatic chucking characteristics of an actual electrostatic chuck or a type of electrostatic chuck (eg, Coulomb electrostatic chuck). Preliminary testing and evaluation results indicate that the substrate has good thermal contact with the dielectric surface 105A and that there is negligible helium flow through the outer sealing band of the substrate support 105 when the substrate is clamped to the surface of the substrate support 105 during plasma processing. This is used to determine the minimum substrate clamping force voltage to ensure that there will be no leakage. The clamp voltage set point (V _Clamp ) value will vary due to the type of electrostatic chuck being used (e.g., Coulomb or Johnson Rabek electrostatic chuck), the back gas pressure being used during processing, and the temperature of the dielectric 105A during plasma processing. will be.

[0089] In some embodiments of clamping network 116, diode D ₁ electrically connects nodes N ₁ and N ₂ (see FIGS. 2A and 3B), and current flows through node N ₁ ) to N ₂ (i.e., the anode side of the diode D ₁ is coupled to the node N ₁ and the cathode side of the diode D ₁ is coupled to the node N ₂ ). Due to the configuration of the diode D ₁ , the voltage at node N ₁ is always limited to a value that is no higher than the voltage at node N ₂ (V _BCM ). Therefore, during each pulse period T _p of the PV waveform (Figure 3a), the peak voltage at node N ₁ is reset to the voltage V _BCM at node N ₂ , which has a large capacitance C ₆ ) (e.g., 0.5 to 10 μF) is the output voltage of the DC voltage source (P ₂ ) in steady state when used. The peak voltage at the node (N ₁ ) is the sum of the peak plasma potential (V _PL ) and the actual clamp voltage across the capacitor (C ₁ ). To achieve the clamp voltage set point, the set point (V _BCM ) of the DC voltage source (P ₂ ) is equal to the desired clamping voltage set point (V _DCV ), as shown in a rewritten version of equation (1) below: ) must be the same as

[0090] However, in some embodiments of clamping network 116, diode D ₁ is not used to connect nodes N ₁ and N ₂ (see FIGS. 2B and 5A). In this configuration, the voltage at node N ₂ (V _BCM ) will still be equal to the voltage at the DC voltage source (P ₂ ) at steady state given a large C ₆ (e.g. 0.5 to 10 μF). . In some embodiments, the resistor (R ₁ ) and capacitor (C ₆ ) values in clamping network 116 are such that the time constant of R ₁ *C ₆ is much greater than the burst period (T _BD ) (FIG. 4B). is selected, so that the voltage at node N ₂ is substantially constant within one burst period T _BD . Since nodes N ₁ and N ₂ are connected via resistor R ₁ , which is a high-resistance value resistor, the time-averaged voltage (of the burst period T _BD ) at node N ₁ is the clamping voltage. (V _BCM ) will be equal to the time averaged voltage (of the burst period (T _BD )) at the same node (N ₂ ). To achieve the clamp voltage set point (V _Clamp ) across the capacitor (C ₁ ), the time-averaged voltage (of the burst period (T _BD )) at the node (N ₁ ) sets the clamp voltage set point (V _Clamp ). This should be the time averaged board voltage value (over the burst period (T _BD )). As discussed further below, the time-averaged substrate voltage can be approximated by use of a PV waveform generated by PV waveform generator 150 and peak plasma potential (V _PL ). Therefore, the set point of the DC voltage source (P ₂ ) (DC voltage source output voltage (V _BCM )) is dependent on the pulse generator (pulser) voltage waveform, peak plasma potential (V _PL ), and clamp voltage set point (V _Clamp ). can be determined by

T_BD * V_BCM/R₁이다. 일부 실시예들에서, 저항기(R₁)의 저항은, 그것이 충분히 크도록 선택되고, 그 결과, 버스트 기간(T_BD)의 시간 규모에서 저항기(R₁)를 통해 흐르는 전하는, 예를 들면, 커패시터들(C₁, C₂, 및 C₅)에 저장되는 전하들과 비교하여 무시 가능하다. 따라서, 이 구성에서, 큰 차단 저항기(R₁)의 존재는, 커패시터(C₆)로 하여금, 기능적으로 노드(N₁)에 직접적으로 결합되지 않는 것처럼 보이게 할 것이고, 노드(N₁)에 연관되는 정전하(electrostatic charge)는, 노드(N₁)에 직접적으로 결합되는 커패시터들(C₁, C₂, 및 C₅)에 저장되는 정전하의 합이 될 것이다.[0091] As illustrated in FIG. 4A, the plasma potential V _Plasma (i.e., curve 433) is equal to or near zero for most of the time during processing and is at a peak level at time T ₁ . reach Therefore, in order to determine the peak plasma potential (V _PL ) of the surface of the formed substrate at time T ₁ , measurements are taken that take into account all the various factors that will affect the plasma potential, and the desired clamping voltage (V _DCV) is determined. ) is used to adjust the output voltage (V _BCM ) of the DC voltage source (P ₂ ) to achieve To determine the peak plasma potential (V _PL ), it is first assumed that the system is configured such that charge conservation is maintained at one or more nodes in the electrode biasing circuit on the time scale of the burst period (T _BD ). In some embodiments, charge conservation is maintained at node N ₁ of the electrode biasing circuit, as shown in FIGS. 2A and 2B, 3B and 5A. In one embodiment, capacitors C ₁ , C ₂ , and C ₅ are coupled directly to node N ₁ and inductor L ₁ (e.g., line illustrated in FIGS. 2A and 2B It is assumed that the inductance) is small enough to induce negligible voltage oscillations compared to the PV voltages generated by the PV waveform generator 150. As illustrated in FIGS. 2A and 2B , 3B and 5A , node N ₁ is also coupled to resistor R ₁ and then to capacitor C ₆ . Therefore, on the time scale of the burst period (T _BD ), the total charge (Q _T ) flowing through the resistor (R ₁ ) is approximately Q _T

T _BD * V _BCM /R ₁ . In some embodiments, the resistance of resistor R ₁ is selected such that it is sufficiently large, such that the charge flowing through resistor R ₁ on the time scale of the burst period T _BD is greater than that of, for example, a capacitor. It is negligible compared to the charges stored in (C ₁ , C ₂ , and C ₅ ). Therefore, in this configuration, the presence of a large blocking resistor R ₁ will cause capacitor C ₆ to appear functionally not directly coupled to node N ₁ , but rather connected to node N ₁ . The resulting electrostatic charge will be the sum of the electrostatic charges stored in the capacitors (C ₁ , C ₂ , and C ₅ ) directly coupled to the node (N ₁ ).

[0092] Equation (2) below is used to describe charge conservation at the node of the electrode biasing circuit, where the sum of the electrostatic charges (Q _Burst ) measured during one portion of the burst on period 310 is the burst on This means that it is equal to the amount of stored charge (Q _Off ) measured during the burst off period 314 immediately after period 310 .

[0093] FIGS. 2A, 2B and 3A provide examples of system configurations in which the charges stored in the capacitances C ₁ , C ₂ and C ₅ can be assumed to be conserved, and thus the peak plasma potential V Allows _PL ) to be determined by use of one or more of the methods described herein. Electrical signals detected within one or more methods described herein may include one or more characteristics of the waveforms generated by PV waveform generator 150 and/or RF generator 118. One or more waveform characteristics detected may include, but are not limited to, voltage at one or more times within a pulse, slope at one or more times within a pulse, pulse period, and pulse repetition frequency. . However, the assumption that charge is conserved in the area around the node, e.g., node N ₁ in FIGS. 2A and 2B and 3B, means that the current flowing to ground, e.g., the current flowing to ground through the blocking resistor R ₁ (i ₁ ) (Figure 3b) is limited by or dependent on the amount of stored charge loss due to its size. As discussed further below, the ability to accurately determine peak plasma potential (V _PL ) depends on one or more of the phases of the burst sequence, including at least one burst on period 310 and burst off period 314. It relies on the ability of the blocking resistor to ensure that the amount of charge loss is negligible before the signal detection module 188 measures the electrical signals generated during the circuit. As mentioned above, the resistance of the resistor R ₁ should preferably exceed, for example, 100 kOhm.

Example 1

[0094] In one example, based on the system 300 configuration illustrated in FIGS. 3A and 3B, for node N ₁ , equation (2) is rewritten as shown in equation (3): can be written

In equation (3), C ₁ , C ₂ , and C ₅ are known capacitances, and ΔV ₁ , ΔV ₂ , and ΔV ₅ are the burst voltages of the capacitor plates directly coupled to node N ₁ It is a value obtained by subtracting the voltages of opposing capacitor plates for the capacitances C ₁ , C ₂ and C ₅ measured during either the on period 310 or the burst off period 314. Accordingly, if the measurement made during the burst on period 310 is made at one of the time T ₁ moments in time, and the measurement made during the burst off period 314 is made at time T ₄ , then equation (3) ) can be rewritten as equation (4).

In equation (4), voltage V ₁ is the voltage of electrode 104 at time T ₁ during burst on period 310 and peak plasma potential (V _PL ) is during burst on period 310 is the plasma potential at time T ₁ , voltage V ₅ is the voltage measured at node N ₅ at time T ₁ during the burst on period 310, and voltage V ₃ is the burst on period 310 is the voltage measured at node N ₃ at time T ₁ during 310, and voltage V ₂ is the voltage measured at node N ₁ during burst off period 314, and voltage V ₆ is the voltage measured at node N ₅ during the burst off period 314 , and voltage V ₄ is the voltage measured at node N ₃ during the burst off period 314 . As noted above, the plasma potential is substantially zero during the burst off period and therefore the charge stored in capacitor C ₁ during burst off period 314 is the product of voltage V ₂ and capacitance C ₁ is substantially the same as The actual clamping voltage during the burst-off period is V ₂ . Therefore, after reorganizing equation (4) shown in equation (5), the peak plasma potential (V _PL ) can be obtained by solving equation (5) for the system configuration illustrated in FIG. 3B .

For simplicity of discussion, each of the capacitance terms multiplied by the voltage difference terms in Equation (5), and any of the equations provided below, is referred to as the "combined circuit capacitance" with a combined circuit capacitance value. As is generally referred to herein, the combined circuit capacitance value is a function of the various connected circuit elements (e.g., electrostatic chuck 191, RF generator 118, etc.) for a desired node (e.g., node N ₁ ). and capacitances (e.g., capacitances C ₁ , C ₂ , and C ₅ in equation (5)) based on the configuration of the PV waveform generator 150). .

[0095] However, in configurations where the biasing element (e.g., PV source 150) connected at node N ₃ is floating during the burst off period, or is disconnected from ground during the burst off period, node N A capacitor (C ₅ ) directly coupled to ₃ ) will have no current passing through it during the transition from burst on to burst off. In other words, the charge stored in the capacitor C ₅ is the same during the burst-on to burst-off transition, so its effect can be eliminated from the charge conservation equations (2), (3), and (4) . The equation used to calculate the voltage (V _PL ) can be simplified to equation (6).

[0096] In some embodiments, there is negligible current flowing through RF source assembly 163 and into capacitor C ₂ coupled to node N ₅ during the burst on to burst off transition, resulting in: Most of the current flowing through C ₂ also flows through C ₃ . Therefore, the series C ₂ and C ₃ can be treated as one capacitor of value (C ₂ C ₃ )/(C ₂ + C ₃ ) and grounded. Therefore, in equation (6), V ₅ = V ₆ = 0 and C ₂ is replaced by (C ₂ C ₃ )/(C ₂ + C ₃ ).

[0097] Therefore, since the capacitance (C ₁ ) is typically much larger than the capacitances (C ₂ and C ₃ ) of most systems, equation (7) is expressed in equation (8), in this example: can be reduced to a simple mathematical equation for a floating biasing element.

[0098] In any case, knowledge of the capacitance values of any of equations (5), (6), (7) or (8), C ₁ , C ₂ , C ₃ , and/or C ₅ , and Using the measured voltages detected during the burst on period 310 and burst off period 314 by use of the signal detection module 188, the peak plasma potential (V _PL ) can be determined so that the desired clamping voltage (V _DCV ) can be determined. ) can be calculated.

Example 2

[0099] In another example, a biasing element (e.g., PV source 150) connected at node N ₃ is controlled at a constant voltage V ₄ (e.g., zero) during the burst off period. In some embodiments, during the burst on to burst off transition there is negligible current flowing through RF source assembly 163 into capacitor C ₂ coupled to node N ₅ , resulting in C ₂ Most of the current flowing through also flows through C ₃ . The voltage V _PL can then be obtained by solving equation (9) for the system configuration illustrated in FIG. 3B.

[0100 _] In this _case , the burst on _{period 310} and Using the measured voltages during the burst off period 314, the peak plasma potential (V _PL ) can be calculated so that the desired clamping voltage (V _DCV ) can be determined.

Example 3

[0101] In another example, based on the system 500 configuration illustrated in FIG. 5A, equation (2) can be rewritten as shown in equation (10). In this example, as schematically shown in Figure 5A, RF source assembly 163 is connected to node N ₅ and utilized to generate a substrate bias voltage during plasma processing. In this example, PV waveform generator 150 is not coupled to system 500. Therefore, equation (2) can be rewritten as shown in equation (10).

[0102] Therefore, the voltage (V _PL ) can be obtained by using equation (11).

[0103] In this case, measurements during burst on period 510 and burst off period 514 by use of equation (11), knowledge of the capacitance values of C ₁ and C ₂ , and signal detection module 188. Using the voltages, the peak plasma potential (V _PL ) can be calculated so that the desired clamping voltage (V _DCV ) can be determined.

Plasma processing method examples

[0104] FIG. 6A is a process flow diagram of a method 600 for determining a desired clamping voltage based on application of a process recipe used during plasma processing of a substrate in a processing chamber. In addition to Figure 6A, method 600 is described with reference to Figures 1A and 5B. In one embodiment, method 600 may be performed by CPU 133 executing computer implemented instructions stored within memory 134 of controller 126. In one embodiment, method 600 includes at least a clamping voltage determination process 605 that includes operations 606-614.

[0105] At operation 602 , in processing chamber 100 , a processing recipe is initiated that causes plasma 101 to form in processing region 129 of processing chamber 100 . In some embodiments, during this operation, RF source assembly 163 delivers sufficient RF power at an RF frequency to an electrode within the processing chamber to form plasma 101. In one example, RF source assembly 163 delivers RF power at an RF frequency between 400 kHz and 100 MHz, such as 40 MHz, to support base 107 disposed within substrate support assembly 136. RF power delivered to the support base 107 is configured to ignite and maintain a processing plasma 101 formed by the use of processing gases disposed within the processing volume 129.

[0106] In operation 604, the controller 126 sends a command signal to the DC voltage source P ₂ to initiate and establish a first clamping voltage at the biasing electrode 104. The size of the first clamping voltage is set to the clamping voltage of the recipe stored in the memory of the controller 126. The recipe set point is generally determined by initial testing or by common knowledge to have a magnitude low enough not to cause dielectric breakdown of the top dielectric layer within the substrate support, but with sufficient ventilation of the substrate backside gas (e.g., helium). It is set at a level with a dimension high enough to achieve good thermal contact with the substrate receiving surface 105A for sealing.

[0107] At operation 606, in one embodiment, PV waveform generator 150 begins generating a series of PV waveforms that establish the PV waveform at biasing electrode 104. During operation 606 , PV generator 150 may be configured to generate bursts 316 of PV waveforms and provide them to biasing electrode 104 within processing chamber 100 . In an alternative embodiment, RF source assembly 163 generates bursts of RF waveforms at an electrode (e.g., support base 107) within processing chamber 100, as discussed with respect to FIG. 5B. I start to do it.

[0108] In some embodiments, during operation 606, the pulse voltage level (e.g., V _pp ) applied to an electrode, such as biasing electrode 104, is controlled by resistors R ₁ and R ₂ (FIG. Via 3b), the capacitors C ₅ and C ₆ are preferably controlled at a desired ramp rate that is no greater than the rate at which they are charged or discharged, respectively, so that V _DCV and V _PL are pulsed. While ramped with voltage V _pp , the actual clamp voltage across capacitor C ₁ remains constant. If such ramp rate relationship is satisfied according to equation (1), the actual clamp voltage across capacitor C ₁ will remain close to the clamp voltage set point V _Clamp during pulse voltage ramping. The charging or discharging rate of the capacitor (C ₅ ) through the resistor (R ₁ ) is determined by the RC time constant.

The charging or discharging rate of the capacitor (C ₆ ) through the resistor (R ₂ ) is determined by the RC time constant.

및

)보다 더 커야 한다. 일부 실시예들에서, 펄스 전압 레벨(V_pp)에 대한 램프 시간은 RC 시상수들( 및 ) 중 더 큰 것의 적어도 세 배가 되도록 설정된다.Therefore, the ramp time for a change in pulse voltage level (V _pp ) is determined by the RC time constants (

and

) must be larger than In some embodiments, the ramp time for pulse voltage level (V _pp ) is determined by the RC time constants ( and ) is set to be at least three times the larger of the

[0109] At operation 608, while ramping the pulse voltage level (e.g., V _pp ) applied to the biasing electrode 104, the signal detection module 188 controls the processing chamber ( 100) is used to monitor the waveforms established within different parts of the device. In one example, signal detection module 188 is configured to monitor waveforms that establish at biasing electrode 104 and support base 107 over time while the pulsed voltage level is ramped. In one example, the waveforms established at biasing electrode 104 and support base 107 are at nodes N ₁ and N ₅ within illustrated system 300 or 500, respectively, in FIG. 3B or 5A. It can be detected by measuring the waveform signals that are established. Generally, during operation 608, signal detection module 188 detects waveform signals at one or more of the times T ₁ -T ₅ illustrated in Figures 3A, 4A, or 5B. It is used to continuously monitor or repeatedly sample waveform signals that are established at various nodes in the system over time.

[0110] In operation 610, the information collected during operation 608 is Equation (2), such as Equations (5), (6), (7), (8), (9), or (11) ) is used to calculate the plasma potential during the plasma process by use of at least one equation derived from The desired equation to be used to determine the peak plasma potential (V _PL ) is based on knowledge of the system configuration being used during plasma processing and/or settings found in software instructions stored in memory. Typically, when pulse voltage levels, RF power, or other plasma-related parameters (e.g., pressure, gas composition, etc.) change during plasma processing, relevant instructions are incorporated into instructions stored in the memory of controller 126. One or more of the equations may be used during execution of stored instructions by CPU 133 to determine peak plasma potential (V _PL ) at any time during processing.

[0111] In operation 612, the desired clamping voltage (V _DCV ) to be used during the subsequent portion of the current plasma process is determined by use of equation (1) and the results of operation 610. As discussed above, the clamp voltage set point (V _Clamp ), obtained from equation (1), is the clamp voltage set point of the recipe, which is typically a predetermined value stored within the memory of the controller 126.

[0112] In operation 614, the desired clamping voltage (V _DCV ) is then applied to the biasing electrode 104 by appropriately setting the DC voltage source (P ₂ ) voltage, as discussed above. A command signal is transmitted to the DC voltage source (P ₂ ) by the controller 126, or the feedback processor 125. In some embodiments, the operations 606-614 of the clamping voltage determination process 605 are repeated at least one more time during the pulse voltage ramping phase, or during the burst on period 310 during plasma processing to achieve the desired pulse voltage level ( For example, it is repeated until V _pp ) is achieved. In some other embodiments, only operations 608-614 of the clamping voltage determination process 605 are repeated more than once during plasma processing. In one example, once the desired pulse voltage level (e.g., V _pp ) is achieved during burst on period 310, operations 608-614 are repeated one or more times.

[0113] After performing operations 608-614 one or more times and a steady-state value for the pulse voltage level (e.g., V _pp ) is achieved, a DC voltage source (P ₂ ), or a DC voltage source An operation 616 is performed in which the set point of the output voltage (V _BCM ) is stored in the memory. In some embodiments, an intermediate set point of DC voltage source output voltage (V _BCM ) values (e.g., non-final values determined during the pulse voltage ramping phase) can be used as a baseline in future plasma processing sequences. It is desirable to store it in memory. The set point of the DC voltage source output voltage (V _BCM ) stored in memory can be used in future plasma processes performed on additional substrates processed using the same or similar plasma processing recipe. As briefly discussed above, plasma processing recipes generally include one or more processing steps adapted to control one or more plasma processing parameters performed on a substrate disposed within a processing chamber. One or more plasma processing parameters include PV waveform characteristics (e.g., duty cycle, pulse voltage level (V _pp ), burst period, burst off period, pulse voltage on time, etc.), chamber pressure, substrate temperature, gas flow rates, gas composition, and other useful parameters. For example, the PV waveform generator 150 is configured to provide pulses with a pulse voltage level (e.g., V _pp ) from 0.01 kV to 10 kV, and the DC voltage source output voltage of the clamping network 116 ( V _BCM ) is set to a constant DC voltage between -3 kV and +3 kV, for example +2.5 kV.

[0114] Referring to FIG. 4C, in some embodiments, the generated series of PV waveforms formed during operation 606 includes establishing a series of PV waveforms within burst 490. The “low” pulse voltage level (V _pp ) found in the PV waveforms formed during burst 492 has a significantly lower magnitude than the “high” pulse voltage level (V _pp ) found in burst 491 . The “high” pulse voltage level (V _pp ) found in burst 491 will have the greatest impact on the desired clamping voltage (V _DCV ) set point due to the larger peak-to-peak pulse voltage. Accordingly _, in some embodiments, the peak plasma potential (V _PL ), although the “low” pulse voltage level (V _pp ) comprising burst 492 is positioned between the “high” pulse voltage level (V _pp ) comprising burst 491 and the burst off period 493 , can be used to determine the set point of the DC voltage source output voltage (V _BCM ). In one example, one of equations (5), (6), (7), (8), (9), or (11) can be used to determine the plasma potential during plasma processing.

[0115] Referring to Figure 4D, in some embodiments, the generated series of PV waveforms formed during operation 606 includes establishing a series of PV waveforms within burst 494. In some embodiments, because the system is configured such that charge conservation is maintained within the region of the electrode biasing circuit, the peak plasma potential (V _PL ) achieved during the “high” pulse voltage level (V _pp ) is, even though the burst ( Although the “low” pulse voltage level (V _pp ) comprising the burst 492) is positioned between the “high” pulse voltage level (V _pp ) comprising the burst 491 and the burst off period 493, the DC voltage source output voltage (V _BCM ) can be determined and used to determine the set point. Accordingly, equations (5), (6), (7), (8), (9), or (11) can be used to determine the plasma potential during plasma processing.

[0116] FIG. 6B illustrates, for example, after performing method 600 at least once, a desired clamping voltage (V _DCV ) based on determination of the set point of the DC voltage source output voltage (V _BCM ) in a previous plasma processing sequence. This is a process flow diagram of the method 650 used to deliver. Method 650 may be performed by CPU 133 executing computer implemented instructions stored within memory 134 of controller 126.

[0117] At operation 652, a processing recipe is initiated in the processing chamber by forming a plasma 101 in the processing region 129 of the processing chamber. Operation 652 may be performed in a manner similar to the methods described above with respect to operation 602.

[0118] In operation 654, the controller 126 sends a command signal to the DC voltage source P ₂ to initiate and establish a first clamping voltage at the biasing electrode 104. The magnitude of the first clamping voltage is set based on the set point of the processing recipe or stored in the memory of the controller 126. In one embodiment, the stored set point is a DC voltage source output voltage (V _BCM ) value used during a previously performed process, such as a result from performance of one of the operations found in method 600. It is based on

[0119] At operation 656, in one embodiment, PV waveform generator 150 begins generating a series of PV waveforms that establish the PV waveform at biasing electrode 104. In an alternative embodiment, RF source assembly 163 begins generating an RF waveform that establishes the RF waveform at an electrode within processing chamber 100, such as support base 107. As discussed above in connection with operation 606, a pulse voltage level (e.g., V _pp ) applied to the electrode is used to charge or discharge C ₅ through R ₁ and C ₆ through R ₂ . It is ramped within a time period that is larger (eg, two or three times larger) than the RC time constants. Typically, operation 656 is performed in a manner similar to the methods described above with respect to operation 606.

[0120] In operation 659, concurrently with operation 656, a desired clamping voltage (V _DCV ) is applied to the substrate by biasing electrode 104 by DC voltage source (P ₂ ) during at least some of the processing steps. ), a command signal is transmitted by the controller 126, or feedback processor 125, to the DC voltage source (P ₂ ) to reach the set point of the DC voltage source output voltage (V _BCM ). Method 650 may be further performed on all substrates subsequently processed in the processing chamber. However, if one or more plasma processing recipe parameters are changed in any subsequent plasma processes, method 600 is performed for all subsequent processes performed using these changed plasma processing recipe parameters, and then the method It may be desirable to perform (650).

[0121] In some embodiments, steps 608-614 of method 600 include adjusting the plasma properties and DC voltage source (P ₂ ) to maintain the clamp voltage set point (V _Clamp ). It can be used repeatedly within a processing step to adjust the peak plasma potential (V _PL ) drift resulting in different DC voltage source output voltages (V _BCM ).

DC Bias Analysis Example

[0122] In some embodiments, the amount of DC bias (V _{DC Bias} ) applied to the substrate during processing is calculated and then used to adjust one or more of the processing parameters during one or more portions of the plasma processing recipe. It is used. The DC bias at any time during plasma processing where a symmetrical waveform (e.g., a sinusoidal (RF waveform) or sigmoidal waveform) is delivered can be calculated by use of equation (14).

[0123] During one or more of the operations described herein, signal detection module 188 and controller 126 are used to detect and monitor waveform signals that establish at various nodes within the system over time, As a result, one or more computer implemented instructions may be used to determine the DC bias and/or peak DC bias.

[0124] Aspects of one or more of the embodiments disclosed herein include a system and method for reliably biasing and clamping a substrate during processing to improve plasma processing results performed on a plurality of substrates.

[0125] The disclosed technology may be represented in a number of non-limiting examples provided below.

[0126] Example 1: A plasma processing chamber, the plasma processing chamber comprising: a substrate support assembly—the substrate support assembly includes: a substrate support surface; a first biasing electrode; comprising a first dielectric layer disposed between the first biasing electrode and the substrate support surface; waveform generator; a first power delivery line electrically coupling the waveform generator to the first biasing electrode, the first power delivery line comprising a blocking capacitor; A clamping network coupled to a first power transmission line at a first point between the blocking capacitor and the biasing electrode, the clamping network comprising: a direct current (DC) voltage source coupled between the first point and ground; and

comprising a blocking resistor coupled between the first point and the output of the direct current (DC) voltage source; a signal detection module configured to receive a first electrical signal from a first signal trace coupled to the first power transmission line at a point disposed between the blocking capacitor and the biasing electrode; and a controller configured to communicate with the signal detection module and to control the magnitude of the voltage supplied to the first power delivery line at the first point by the direct current (DC) voltage source due to information received within the received electrical signal. Includes.

[0127] Example 2: The plasma processing chamber of Example 1, wherein the waveform generator is configured to generate the plurality of pulsed voltage waveforms for a first time period and to stop generating the plurality of pulsed voltage waveforms for a second time period, and During a one time period, the first portion of the electrical signal received by the signal detection module includes a first portion of a generated plurality of pulsed voltage waveforms comprising a first voltage level, and during a second time period: The second portion of the electrical signal received by the signal detection module includes a second voltage level, and computer implemented instructions stored in the memory, when executed by the processor, adjust the magnitude of the voltage supplied to the first power delivery line. The controller is configured to compare the first voltage level with the second voltage level before taking control.

[0128] Example 3: The plasma processing chamber of Example 1, wherein the substrate support assembly includes an electrostatic chuck, and the electrostatic chuck includes a first dielectric layer and a first biasing electrode.

[0129] Example 4: The plasma processing chamber of Example 1, wherein the blocking resistor has a resistance greater than 100 kOhms.

[0130] Example 5: The plasma processing chamber of Example 1, wherein the substrate support assembly includes: a support base; and a second dielectric layer disposed between the support base and the first biasing electrode; and the waveform generator includes a pulsed voltage waveform generator electrically coupled to the first biasing electrode through a first electrical conductor, configured to establish a pulsed voltage waveform at the first biasing electrode, and the radio frequency generator includes a first biasing electrode. electrically coupled to a support base via two power transmission lines, configured to establish a radio frequency voltage waveform at the support base, and a signal detection module configured to detect a second electrical signal from a second signal trace coupled to the second power transmission line. It is further configured to receive.

[0131] Example 6: The plasma processing chamber of Example 1, wherein the first dielectric layer has a thickness of about 0.1 mm to about 2 mm.

[0132] Example 7: The plasma processing chamber of Example 1, wherein the clamping network is connected in parallel with the waveform generator, and the clamping network includes: a first diode coupled in parallel with a blocking resistor between a first point and a direct current (DC) voltage source—a diode. the anode side of is coupled to the first point; A first capacitor coupled between the cathode side of the diode and ground; and a second resistor in series with the DC voltage source coupled in parallel with the first capacitor.

[0133] Example 8: The plasma processing chamber of Example 1, wherein the substrate support assembly further includes a second biasing electrode, the first biasing electrode and the second biasing electrode being an edge control electrode and a chucking pole electrode, respectively. ) is selected from the group containing.

[0134] Example 9:

A plasma processing chamber, the plasma processing chamber comprising: a substrate support assembly—a substrate support assembly comprising: a substrate support surface; first electrode; comprising a first dielectric layer disposed between the first electrode and the substrate support surface; waveform generator; a first power delivery line electrically coupling the waveform generator to the first electrode, the first power delivery line including a blocking capacitor; A clamping network coupled to a first power transmission line at a first point between the blocking capacitor and the first electrode, the clamping network comprising: a direct current (DC) voltage source coupled between the first point and ground; and a blocking resistor coupled between the first point and the direct current (DC) voltage source; and a signal detection module configured to receive a first electrical signal from a first signal trace coupled to the first power transmission line at a point disposed between the blocking capacitor and the first electrode.

[0135] Example 10: The plasma processing chamber of Example 9, further comprising a diode coupled in parallel with a blocking resistor between a first point and a direct current (DC) voltage source, wherein the anode side of the diode is coupled to the first point.

[0136] Example 11: The plasma processing chamber of Example 9, wherein the waveform generator is configured to generate the plurality of pulsed voltage waveforms during a first period of time and to stop generating the plurality of pulsed voltage waveforms during a second period of time, and During a first time period, the first portion of the electrical signal received by the signal detection module includes a first portion of a generated plurality of pulsed voltage waveforms comprising a first voltage level, and during a second time period while the second portion of the electrical signal received by the signal detection module includes a second voltage level, and the computer-implemented instructions stored in the memory, when executed by the processor, include a magnitude of the voltage supplied to the first power delivery line. The controller is configured to compare the first voltage level with the second voltage level before controlling.

[0137] Example 12: The plasma processing chamber of Example 9, wherein the substrate support assembly includes an electrostatic chuck, and the electrostatic chuck includes a first dielectric layer and a first electrode.

[0138] Example 13: The plasma processing chamber of Example 9, wherein the blocking resistor has a resistance greater than 100 kOhms.

[0139] Example 14: The plasma processing chamber of Example 9, wherein the substrate support assembly includes: a support base; and a second dielectric layer disposed between the support base and the first electrode; and the waveform generator includes a pulsed voltage waveform generator electrically coupled to the first electrode through a first electrical conductor, configured to establish a pulsed voltage waveform at the first electrode, and wherein the radio frequency generator is connected to the second power delivery line. electrically coupled to the support base via, configured to establish a radio frequency voltage waveform at the support base, and the signal detection module further configured to receive a second electrical signal from the second signal trace coupled to the second power transmission line. It is composed.

[0140] Example 15: The plasma processing chamber of Example 9, wherein the first dielectric layer has a thickness of about 0.1 mm to about 2 mm.

[0141] Example 16: The plasma processing chamber of Example 9, wherein the clamping network is connected in parallel with the waveform generator, and the clamping network comprises: a first diode coupled in parallel with a blocking resistor between a first point and a direct current (DC) voltage source; The anode side of the diode is coupled to the first point; A first capacitor coupled between the cathode side of the diode and ground; and a second resistor in series with the DC voltage source coupled in parallel with the first capacitor.

[0142] Example 17: The plasma processing chamber of Example 9, wherein the first electrode includes an edge control electrode or a chucking pole electrode.

[0143] Example 18: A method for plasma processing a substrate: generating a plasma in a processing region of a processing chamber, the processing region comprising: a substrate support surface, a first biasing electrode, and between the first biasing electrode and the substrate support surface. comprising a substrate support comprising a first dielectric layer disposed on; delivering one or more waveforms from a waveform generator through a first power delivery line to a first biasing electrode during a first period of time; ceasing delivery of one or more waveforms to the first biasing electrode for a second period of time; applying a first clamping voltage from the clamping network to the first biasing electrode; detecting at least one characteristic of one or more waveforms during a first period of time by receiving an electrical signal from a signal trace coupled to the first power transmission line at a first point disposed on the first power transmission line; detecting at least one characteristic of an electrical signal received from the signal trace during a second period of time; and a first clamping voltage applied to the first biasing electrode, comprising: a detected characteristic of one or more waveforms received from the signal trace during a first period of time; and adjusting based on at least one detected characteristic of the electrical signal received from the signal trace during the second period of time.

[0144] Example 19: The method of Example 18, wherein a plurality of pulses are provided from a waveform generator during a first time period, each of the plurality of pulses having a pulse voltage level, and the plurality of pulses during a second portion of the first time period. The pulse voltage level of one or more pulses is increased relative to the one or more pulses provided within the first portion of the first time period.

[0145] Example 20: The method of Example 19, wherein applying the first clamping voltage during a portion of the first time period includes increasing the voltage supplied to the biasing electrode by the clamping network.

[0146] Example 21: The method of Example 18, wherein the clamping network includes: a direct current (DC) voltage source coupled between a first point and ground; and a blocking resistor coupled between the first point and the DC source.

[0147] Example 22: The method of Example 21, wherein the one or more waveforms each include a pulse voltage level, and the pulse voltage level increases from the first voltage level to the second voltage level during a portion of the first time period.

[0148] Example 23: The method of Example 22, wherein the first power transmission line includes a blocking capacitor disposed between the waveform generator and the biasing electrode, and the voltage of the clamping network ramps at a rate substantially equal to the ramp of the voltage across the blocking capacitor. do.

[0149] Example 24: As in Example 21, the blocking resistor has a resistance greater than 100 kOhms.

[0150] Example 25: The method of Example 21, wherein the DC current flowing through the blocking resistor to ground at any moment in time is less than about 20 mA.

[0151] Example 26: The method of Example 18, wherein applying the first clamping voltage during a portion of the first time period includes increasing the voltage supplied to the biasing electrode by the clamping network.

[0152] Example 27: The method of Example 18, wherein applying the first clamping voltage during a portion of the first time period includes reducing the voltage supplied to the biasing electrode by the clamping network.

[0153] Example 28: The method of Example 18, wherein, during a first period of time, the peak plasma potential achieved comprises: during a first period of time, at least one characteristic of the one or more waveforms that are detected; and determining by analyzing at least one characteristic of the electrical signal detected during the second period of time.

[0154] Example 29: The method of Example 28, wherein adjusting the first clamping voltage includes:

forming a desired clamping voltage by adding the determined peak plasma potential to a clamp voltage set point constant value stored in a memory; and delivering a control signal to a direct current (DC) voltage source of the clamping network, wherein the control signal includes information regarding the desired clamping voltage to be formed.

[0155] Example 30: The method of Example 18, wherein detecting at least one characteristic of the one or more waveforms during the first time period comprises detecting the first voltage at a peak of the one or more pulsed voltage waveforms. and detecting at least one characteristic of the one or more waveforms during the second period of time includes detecting a second voltage during the second period of time.

[0156] Example 31: The method of Example 30, wherein adjusting the first clamping voltage applied to the first biasing electrode based on the detected characteristic includes: determining a difference between the first voltage and the second voltage; and determining a plasma potential value based on the determined difference between the first voltage and the second voltage, and adjusting the first clamping voltage comprises delivering a substrate biasing voltage to the first biasing electrode. and wherein the substrate biasing voltage includes the sum of the determined plasma potential value and the previously determined clamp voltage set point value.

[0157] Example 32: The method of Example 31, wherein determining the plasma potential value further includes multiplying the determined difference between the first voltage and the second voltage by a combined circuit capacitance value, wherein the combined circuit capacitance value is the first voltage. Contains capacitance values of circuit elements directly coupled to the point.

[0158] Example 33: A method for plasma processing a substrate, comprising generating a plasma within a processing region of a processing chamber, the processing region comprising: a substrate support surface, a first biasing electrode, and between the first biasing electrode and the substrate support surface. comprising a substrate support comprising a first dielectric layer disposed on; delivering a plurality of pulsed voltage waveforms from a waveform generator, during a first period of time, to a first biasing electrode via a first power delivery line, wherein the first power delivery line is disposed between the waveform generator and the biasing electrode. Includes blocking capacitor -; ceasing delivery of the plurality of pulsed voltage waveforms to the first biasing electrode for an entire second period of time; applying a first clamping voltage from the clamping network to the first biasing electrode; One or more pulses of a plurality of pulsed voltage waveforms delivered during a first period of time by receiving an electrical signal from a signal trace coupled to the first power transmission line at a first point disposed between the blocking capacitor and the biasing electrode. detecting at least one characteristic of the equation voltage waveforms; detecting at least one characteristic of an electrical signal received from the signal trace during a second period of time; and a first bias based on the detected characteristic of one or more of the delivered plurality of pulsed voltage waveforms and at least one characteristic of the electrical signal received from the signal trace during the first and second time periods. and adjusting the first clamping voltage applied to the single electrode.

[0159] Example 34: The method of Example 33, wherein a plurality of pulsed voltage waveforms are provided from a waveform generator during a first time period, each of the plurality of pulses having a pulse voltage level, and the plurality of pulsed voltage waveforms are provided during a second portion of the first time period. The pulse voltage level of one or more of the pulses is increased relative to the one or more pulses provided within the first portion of the first time period.

[0160] Example 35: The method of Example 34, wherein applying the first clamping voltage for a portion of the first time period includes increasing the voltage supplied to the biasing electrode by the clamping network.

[0161] Example 36: The method of Example 33, wherein the clamping network includes: a direct current (DC) voltage source coupled between a first point and ground; and a blocking resistor coupled between the first point and the DC source.

[0162] Example 37: The method of Example 36, wherein the one or more waveforms each include a pulse voltage level, and the pulse voltage level increases from the first voltage level to the second voltage level during a portion of the first period of time.

[0163] Example 38: The method of Example 36, wherein the DC current flowing through the blocking resistor to ground at any moment in time is less than about 20 mA.

[0164] Example 39: The method of Example 33, wherein, during a first period of time, the peak plasma potential achieved comprises: during the first period of time, at least one characteristic of the one or more waveforms that are detected; and determining by analyzing at least one characteristic of the electrical signal detected during the second period of time.

[0165] Example 40: The method of Example 39, wherein adjusting the first clamping voltage includes: adding the determined peak plasma potential to a clamp voltage set point constant value stored in memory to form a desired clamping voltage; and delivering a control signal to a direct current (DC) voltage source of the clamping network, wherein the control signal includes information regarding the desired clamping voltage to be formed.

[0166] Example 41: The method of Example 33, wherein detecting at least one characteristic of the one or more waveforms during the first time period comprises detecting the first voltage at a peak of the one or more pulsed voltage waveforms. and detecting at least one characteristic of the one or more waveforms during the second period of time includes detecting a second voltage during the second period of time.

[0167] Example 42: The method of Example 41, wherein adjusting the first clamping voltage applied to the first biasing electrode based on the detected characteristic includes: determining a difference between the first voltage and the second voltage; and determining a plasma potential value based on the determined difference between the first voltage and the second voltage, and adjusting the first clamping voltage comprises delivering a substrate biasing voltage to the first biasing electrode. and wherein the substrate biasing voltage includes the sum of the determined plasma potential value and the previously determined clamp voltage set point value.

[0168] Example 43: The method of Example 42, wherein determining the plasma potential value further includes multiplying the determined difference between the first voltage and the second voltage by a combined circuit capacitance value, wherein the combined circuit capacitance value is the first voltage. Contains capacitance values of circuit elements directly coupled to the point.

[0169] Although the foregoing relates to embodiments of the disclosure, other and additional embodiments of the disclosure may be devised without departing from the basic scope of the disclosure, the scope of which is determined by the claims that follow. do.

Claims (43)

As a plasma processing chamber,
Substrate support assembly—The substrate support assembly includes:
substrate support surface;
first biasing electrode;
comprising a first dielectric layer disposed between the first biasing electrode and the substrate support surface;
waveform generator;
a first power delivery line electrically coupling the waveform generator to the first biasing electrode, the first power delivery line comprising a blocking capacitor;
A clamping network coupled to the first power transmission line at a first point between the blocking capacitor and the biasing electrode, the clamping network comprising:
a direct-current (DC) voltage source coupled between the first point and ground; and
comprising a blocking resistor coupled between the first point and the output of the direct current (DC) voltage source;
a signal detection module configured to receive a first electrical signal from a first signal trace coupled to the first power transmission line at a point disposed between the blocking capacitor and the biasing electrode; and
communicate with the signal detection module and control the magnitude of the voltage supplied to the first power delivery line at the first point by the direct current (DC) voltage source due to information received within the received electrical signal. A plasma processing chamber, comprising a controller configured to: According to paragraph 1,
the waveform generator is configured to generate a plurality of pulsed voltage waveforms during a first period of time and to stop generating the plurality of pulsed voltage waveforms during a second period of time;
During the first time period, the first portion of the electrical signal received by the signal detection module includes a first portion of the generated plurality of pulsed voltage waveforms comprising a first voltage level, and
a second portion of the electrical signal received by the signal detection module during the second time period includes a second voltage level, and
Computer-implemented instructions stored in a memory, when executed by a processor, are configured to compare the first voltage level with the second voltage level before the controller controls the magnitude of the voltage supplied to the first power transmission line. , plasma processing chamber. According to paragraph 1,
wherein the substrate support assembly includes an electrostatic chuck, the electrostatic chuck including the first dielectric layer and the first biasing electrode. According to paragraph 1,
The blocking resistor has a resistance greater than 100 kOhms. According to paragraph 1,
The substrate support assembly:
support base; and
further comprising a second dielectric layer disposed between the support base and the first biasing electrode; and
the waveform generator comprising a pulsed voltage waveform generator electrically coupled to the first biasing electrode through a first electrical conductor, and configured to establish a pulsed voltage waveform at the first biasing electrode;
A radio frequency generator is electrically coupled to the support base via a second power transmission line and is configured to establish a radio frequency voltage waveform at the support base, and
wherein the signal detection module is further configured to receive a second electrical signal from a second signal trace coupled to the second power delivery line. According to paragraph 1,
The first dielectric layer has a thickness of about 0.1 mm to about 2 mm. According to paragraph 1,
The clamping network is connected in parallel with the waveform generator, and the clamping network is:
a first diode coupled in parallel with the blocking resistor between the first point and the direct current (DC) voltage source, the anode side of the diode coupled to the first point;
a first capacitor coupled between the cathode side of the diode and ground; and
The plasma processing chamber further comprising a second resistor in series with a DC voltage source coupled in parallel with the first capacitor. According to paragraph 1,
The substrate support assembly further includes a second biasing electrode, wherein the first biasing electrode and the second biasing electrode are each selected from the group comprising an edge control electrode and a chucking pole electrode. , plasma processing chamber. As a plasma processing chamber,
Substrate support assembly—the substrate support assembly:
substrate support surface;
first electrode;
comprising a first dielectric layer disposed between the first electrode and the substrate support surface;
waveform generator;
a first power delivery line electrically coupling the waveform generator to the first electrode, the first power delivery line comprising a blocking capacitor;
A clamping network coupled to the first power transmission line at a first point between the blocking capacitor and the first electrode, the clamping network comprising:
a direct current (DC) voltage source coupled between the first point and ground; and
comprising a blocking resistor coupled between the first point and the direct current (DC) voltage source; and
and a signal detection module configured to receive a first electrical signal from a first signal trace coupled to the first power transmission line at a point disposed between the blocking capacitor and the first electrode. According to clause 9,
A plasma processing chamber further comprising a diode coupled in parallel with the blocking resistor between the first point and the direct current (DC) voltage source, wherein an anode side of the diode is coupled to the first point. According to clause 9,
the waveform generator is configured to generate a plurality of pulsed voltage waveforms during a first period of time and to stop generating the plurality of pulsed voltage waveforms during a second period of time;
During the first time period, the first portion of the electrical signal received by the signal detection module includes a first portion of the generated plurality of pulsed voltage waveforms comprising a first voltage level, and
a second portion of the electrical signal received by the signal detection module during the second time period includes a second voltage level, and
Computer-implemented instructions stored in a memory, when executed by a processor, are configured to compare the first voltage level with the second voltage level before the controller controls the magnitude of the voltage supplied to the first power transmission line, Plasma processing chamber. According to clause 9,
wherein the substrate support assembly includes an electrostatic chuck, the electrostatic chuck including the first dielectric layer and the first electrode. According to clause 9,
The blocking resistor has a resistance greater than 100 kOhms. According to clause 9,
The substrate support assembly:
support base; and
further comprising a second dielectric layer disposed between the support base and the first electrode; and
the waveform generator comprising a pulsed voltage waveform generator electrically coupled to the first electrode through a first electrical conductor, and configured to establish a pulsed voltage waveform at the first electrode;
A radio frequency generator is electrically coupled to the support base via a second power transmission line and is configured to establish a radio frequency voltage waveform at the support base, and
wherein the signal detection module is further configured to receive a second electrical signal from a second signal trace coupled to the second power delivery line. According to clause 9,
wherein the first dielectric layer has a thickness of about 0.1 mm to about 2 mm. According to clause 9,
The clamping network is connected in parallel with the waveform generator, and the clamping network is:
a first diode coupled in parallel with the blocking resistor between the first point and the direct current (DC) voltage source, the anode side of the diode coupled to the first point;
a first capacitor coupled between the cathode side of the diode and ground; and
The plasma processing chamber further comprising a second resistor in series with a DC voltage source coupled in parallel with the first capacitor. According to clause 9,
wherein the first electrode comprises an edge control electrode or a chucking pole electrode. A method for plasma processing a substrate, comprising:
Generating a plasma within a processing region of a processing chamber, the processing region comprising a substrate support surface, a first biasing electrode, and a first dielectric layer disposed between the first biasing electrode and the substrate support surface. Includes a substrate support that -;
delivering one or more waveforms from a waveform generator to the first biasing electrode through a first power delivery line during a first period of time;
ceasing delivery of the one or more waveforms to the first biasing electrode for a second period of time;
applying a first clamping voltage from a clamping network to the first biasing electrode;
detecting at least one characteristic of the one or more waveforms during the first period of time by receiving an electrical signal from a signal trace coupled to the first power transmission line at a first point disposed on the first power transmission line. step;
detecting at least one characteristic of an electrical signal received from the signal trace during the second period of time; and
The first clamping voltage applied to the first biasing electrode is:
During the first time period, detected characteristics of one or more waveforms received from the signal trace; and
At least one detected characteristic of an electrical signal received from the signal trace during the second time period
A method for plasma processing a substrate, comprising adjusting based on . According to clause 18,
A plurality of pulses are provided from the waveform generator during the first time period, each of the plurality of pulses having a pulse voltage level, and at least one pulse of the plurality of pulses during a second portion of the first time period. wherein the pulse voltage level of the pulses is increased relative to one or more pulses provided within a first portion of the first time period. According to clause 19,
Wherein applying the first clamping voltage during portion of the first time period includes increasing the voltage supplied to the biasing electrode by the clamping network. According to clause 18,
The clamping network is:
a direct current (DC) voltage source coupled between the first point and ground; and
A method for plasma processing a substrate, comprising a blocking resistor coupled between the first point and the DC source. According to clause 21,
wherein the one or more waveforms each include a pulse voltage level, wherein the pulse voltage level increases from a first voltage level to a second voltage level during a portion of the first time period. According to clause 22,
The first power transmission line includes a blocking capacitor disposed between the waveform generator and the biasing electrode, and the voltage of the clamping network is ramped at a rate substantially equal to the ramp of the voltage across the blocking capacitor. , a method for plasma processing a substrate. According to clause 21,
wherein the blocking resistor has a resistance greater than 100 kOhms. According to clause 21,
A method for plasma processing a substrate, wherein the DC current flowing through the blocking resistor to ground at any moment in time is less than about 20 mA. According to clause 18,
Wherein applying the first clamping voltage during a portion of the first time period includes increasing the voltage supplied to the biasing electrode by the clamping network. According to clause 18,
Wherein applying the first clamping voltage during a portion of the first time period includes reducing the voltage supplied to the biasing electrode by the clamping network. According to clause 18,
During the first time period, the peak plasma potential achieved is:
During the first time period, at least one characteristic of one or more waveforms detected; and
At least one characteristic of the electrical signal detected during the second time period
A method for plasma processing a substrate, further comprising determining by analyzing . According to clause 28,
Adjusting the first clamping voltage includes:
forming a desired clamping voltage by adding the determined peak plasma potential to a clamp voltage set point constant value stored in a memory; and
Further comprising transmitting a control signal to a direct current (DC) voltage source of the clamping network,
wherein the control signal includes information regarding the desired clamping voltage generated. According to clause 18,
Detecting at least one characteristic of the one or more waveforms during the first time period includes detecting a first voltage at a peak of a pulsed voltage waveform of the one or more pulsed voltage waveforms, and
and detecting at least one characteristic of the one or more waveforms during the second time period includes detecting a second voltage during the second time period. According to clause 30,
The step of adjusting the first clamping voltage applied to the first biasing electrode based on the detected characteristic is:
determining a difference between the first voltage and the second voltage; and
further comprising determining a plasma potential value based on the determined difference between the first voltage and the second voltage, and
Adjusting the first clamping voltage includes delivering a substrate biasing voltage to the first biasing electrode, wherein the substrate biasing voltage is equal to the difference between the determined plasma potential value and the previously determined clamp voltage set point value. A method for plasma processing a substrate, comprising: According to clause 31,
Determining the plasma potential value further includes multiplying the determined difference between the first voltage and the second voltage by a combined circuit capacitance value, wherein the combined circuit capacitance value is directly at the first point. A method for plasma processing a substrate, comprising capacitance values of circuit elements being coupled. A method for plasma processing a substrate, comprising:
Generating a plasma within a processing region of a processing chamber, the processing region comprising a substrate support surface, a first biasing electrode, and a first dielectric layer disposed between the first biasing electrode and the substrate support surface. Includes a substrate support that -;
delivering a plurality of pulsed voltage waveforms from a waveform generator, during a first period of time, to the first biasing electrode through a first power delivery line, wherein the first power delivery line is connected to the waveform generator and the biasing electrode. Includes a blocking capacitor disposed between -;
ceasing delivery of the plurality of pulsed voltage waveforms to the first biasing electrode for an entire second period of time;
applying a first clamping voltage from a clamping network to the first biasing electrode;
By receiving an electrical signal from a signal trace coupled to the first power delivery line at a first point disposed between the blocking capacitor and the biasing electrode, during the first period of time, the delivered plurality of pulsed voltage waveforms detecting at least one characteristic of one or more of the pulsed voltage waveforms;
detecting at least one characteristic of an electrical signal received from the signal trace during the second period of time; and
a detected characteristic of the one or more of the delivered plurality of pulsed voltage waveforms, and at least one characteristic of an electrical signal received from the signal trace during the first time period and the second time period A method for plasma processing a substrate, comprising adjusting a first clamping voltage applied to the first biasing electrode based on the first clamping voltage applied to the first biasing electrode. According to clause 33,
A plurality of pulsed voltage waveforms are provided from the waveform generator during the first time period, each of the plurality of pulses having a pulse voltage level, and one of the plurality of pulses during a second portion of the first time period. wherein the pulse voltage level of the one or more pulses is increased relative to one or more pulses provided within a first portion of the first time period. According to clause 34,
Wherein applying the first clamping voltage for a portion of the first time period includes increasing the voltage supplied to the biasing electrode by the clamping network. According to clause 33,
The clamping network is:
a direct current (DC) voltage source coupled between the first point and ground; and
A method for plasma processing a substrate, comprising a blocking resistor coupled between the first point and the DC source. According to clause 36,
The method of claim 1 , wherein the one or more waveforms each include a pulse voltage level, wherein the pulse voltage level increases from a first voltage level to a second voltage level during a portion of the first time period. According to clause 36,
A method for plasma processing a substrate, wherein the DC current flowing through the blocking resistor to ground at any moment in time is less than about 20 mA. According to clause 33,
During the first time period, the peak plasma potential achieved is:
During the first time period, at least one characteristic of one or more waveforms detected; and
At least one characteristic of the electrical signal detected during the second time period
A method for plasma processing a substrate, further comprising determining by analyzing . According to clause 39,
Adjusting the first clamping voltage includes:
forming a desired clamping voltage by adding the determined peak plasma potential to a clamp voltage set point constant value stored in a memory; and
Further comprising transmitting a control signal to a direct current (DC) voltage source of the clamping network,
wherein the control signal includes information regarding the desired clamping voltage generated. According to clause 33,
Detecting at least one characteristic of the one or more waveforms during the first time period includes detecting a first voltage at a peak of a pulsed voltage waveform of the one or more pulsed voltage waveforms, and
and detecting at least one characteristic of the one or more waveforms during the second time period includes detecting a second voltage during the second time period. According to clause 41,
The step of adjusting the first clamping voltage applied to the first biasing electrode based on the detected characteristic is:
determining a difference between the first voltage and the second voltage; and
further comprising determining a plasma potential value based on the determined difference between the first voltage and the second voltage, and
Adjusting the first clamping voltage includes delivering a substrate biasing voltage to the first biasing electrode, wherein the substrate biasing voltage is equal to the difference between the determined plasma potential value and the previously determined clamp voltage set point value. A method for plasma processing a substrate, comprising: According to clause 42,
Determining the plasma potential value further includes multiplying the determined difference between the first voltage and the second voltage by a combined circuit capacitance value, wherein the combined circuit capacitance value is directly at the first point. A method for plasma processing a substrate, comprising capacitance values of circuit elements being coupled.