KR20240002890A - Electrostatic discharge protection circuit and electronic device including the same - Google Patents

Abstract

The present disclosure relates to an electrostatic discharge protection circuit and an electronic device including the same. In one embodiment, the electronic device includes an electrostatic discharge protection circuit including a connector terminal portion, an integrated circuit, and a first line connecting the connector terminal portion and the integrated circuit on a PCB board, wherein the electrostatic discharge protection circuit includes a first line. A first pad connected to the first node of the line, a second pad disposed spaced apart from the first pad and connected to the ground voltage terminal, and connected to a second node of the first line that is different from the first node and the first node. It includes a first resistor, and a first capacitor connected to the second node and the ground voltage terminal.

Description

Electrostatic discharge protection circuit and electronic device including same {ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT AND ELECTRONIC DEVICE INCLUDING THE SAME}

The present disclosure relates to an electrostatic discharge protection circuit and an electronic device including the same, and more specifically, to an electrostatic discharge protection circuit in which a spark gap is disposed in front of a resistor element on a PCB to prevent electrostatic discharge pulses coming from a connector from flowing into the electronic device. Pertains to a discharge protection circuit and an electronic device including the same.

The internal circuits of electronic devices may be damaged by electrostatic discharge generated during the production process or during use. In particular, when an electronic device is connected to another electronic device by wire, the internal circuit may be damaged by ESD pulses flowing from the connector.

As technology develops, the distance between pads on a PCB for placing circuit elements has become shorter, and a method for preventing electrostatic discharge between pads is required. To prevent such electrostatic discharge, circuit designs or circuit elements have been studied. For example, methods of changing the flow of current of ESD pulses flowing into an element or circuit to be protected by additionally mounting ESD protection elements in the circuit have been actively studied.

In one embodiment, the electrostatic discharge protection circuit on the PCB board includes a first pad connected to a first node, a second pad disposed spaced apart from the first pad and connected to a ground voltage terminal, the first node, and It may include a first resistor connected to a second node different from the first node and a first capacitor connected to the second node and the ground voltage terminal.

In one embodiment, an electronic device for preventing electrostatic discharge includes a connector terminal portion, an integrated circuit, and a first line connecting the connector terminal portion and the integrated circuit on a printed circuit board (PCB) substrate. A circuit comprising: a first pad connected to a first node of the first line, a second pad spaced apart from the first pad and connected to a ground voltage terminal, and the first pad connected to the first node of the first line. It may include a first resistor connected to a node and a second node of the first line that is different from the first node, and a first capacitor connected to the second node and the ground voltage terminal.

In one embodiment, a printed circuit board assembly (PCB assembly) on which an electrostatic discharge protection circuit is mounted includes a first signal wire connected to a connector terminal, a second signal wire connected to an integrated circuit, and a first signal wire connected to the first signal wire. a first pad, disposed to be spaced apart from the first pad, a second pad connected to a ground voltage terminal, a third pad connected to the first signal line, disposed to be spaced apart from the third pad, and the second A fourth pad connected to a signal wire, a first resistor element connected to the third pad and the fourth pad, a fifth pad connected to the second signal wire, disposed to be spaced apart from the fifth pad, and the ground. It may include a sixth pad connected to a voltage terminal, and a first capacitor element connected to the fifth pad and the sixth pad.

In one embodiment, a method of protecting against electrostatic discharge on a PCB board includes the steps of receiving an electrostatic discharge (ESD) pulse flowing into the PCB board from a connector terminal part, connected to the connector terminal part and on the PCB board. Reflecting at least a portion of the ESD pulse by a resistor element disposed, and a first pad connected to the connector terminal portion and the resistor element and disposed on the PCB board, and spaced apart from the first pad on the PCB It may include discharging the received ESD pulse and the reflected ESD pulse to a ground voltage terminal connected to the second pad through an arc between second pads disposed on the substrate.

1 is a conceptual diagram illustrating an electronic device according to an embodiment.
Figure 2 is a circuit diagram showing an electrostatic discharge protection circuit according to one embodiment.
3A to 3G are plan views showing a pattern design of a PCB board on which an electrostatic discharge protection circuit is mounted according to an embodiment.
Figure 4 is a plan view showing a pattern design of a PCB board on which an electrostatic discharge protection circuit is mounted according to an embodiment.
Figure 5 is a circuit diagram showing an electrostatic discharge protection circuit according to one embodiment.
Figure 6 is a diagram showing the shape of a pad according to one embodiment.
Figure 7 is a flowchart showing a method for protecting against electrostatic discharge according to an embodiment.
Figure 8 is a block diagram showing an electronic device according to an embodiment.

Terms used in the present disclosure will be briefly described, and an embodiment of the present disclosure will be described in detail.

The terms used in the present disclosure have selected general terms that are currently widely used as much as possible while considering the function in an embodiment of the present disclosure, but this may vary depending on the intention or precedent of a person working in the art, the emergence of new technology, etc. there is. In addition, in certain cases, there are terms arbitrarily selected by the applicant, and in this case, the meaning will be described in detail in the description of the corresponding embodiment of the present disclosure. Therefore, the terms used in this disclosure should be defined based on the meaning of the term and the overall content of this disclosure, rather than simply the name of the term.

Throughout the present disclosure, when a part “includes” a certain element, this means that it may further include other elements rather than excluding other elements, unless specifically stated to the contrary. In addition, terms such as "... unit" and "module" described in the present disclosure refer to a unit that processes at least one function or operation, which may be implemented as hardware or software, or as a combination of hardware and software. there is.

Below, with reference to the attached drawings, embodiments of the present disclosure will be described in detail so that those skilled in the art can easily practice them. However, an embodiment of the present disclosure may be implemented in various different forms and is not limited to the embodiment described herein. In order to clearly describe an embodiment of the present disclosure in the drawings, parts that are not related to the description are omitted, and similar parts are assigned similar reference numerals throughout the present disclosure.

In the present disclosure, a pad refers to a metal plate disposed on a printed circuit board (PCB) substrate. For example, pads can be used to mount circuit elements such as resistor elements on a PCB board. For example, the pad may be used to form a spark gap. In the present disclosure, a pad may also be referred to as an electrode.

In the present disclosure, a spark gap may consist of an array of at least two conductive electrodes. For example, the conductive electrode array may include pads spaced apart on a PCB substrate. For example, if the potential difference between spaced apart pads exceeds the breakdown voltage of the air between the pads, a spark may be formed between the pads. The spark gap may be formed by placing at least two pads spaced apart on the PCB.

In the present disclosure, a complete circuit board in which circuit elements or components for implementing an electrostatic discharge protection circuit are assembled on a PCB board may also be referred to as a PCB assembly.

In the present disclosure, the ground voltage terminal may represent the frame ground (FRAME Ground) of the PCB board. The ground voltage terminal may be connected to the earth voltage terminal, but may not be connected.

1 is a conceptual diagram illustrating an electronic device according to an embodiment.

Referring to FIG. 1, the electronic device 100 may be a device that operates using electrical energy as power. The electronic device 100 may operate by receiving electrical energy from the outside. For example, the electronic device 100 may include a smart phone, a smart pad, a wearable device, a digital camera, a television, a monitor, and a laptop computer ( It may include various electronic devices that can receive power, such as a laptop computer, black-box, robot, etc. For example, the electronic device 100 may be a home appliance. For example, the electronic device 100 may be a device installed in a house to help a user with housework, such as an air conditioner, refrigerator, washing machine, dishwasher, and vacuum cleaner.

The electronic device 100 may include a connector terminal unit 110, an electrostatic discharge protection circuit 120, and an integrated circuit 130. At least some of the components of the electronic device 100 may be disposed on a PCB board.

The connector terminal unit 110 may include a plurality of terminals for connecting an external electronic device (not shown) or a power source to the electronic device 100 by wire. For example, the connector terminal unit 110 includes a Universal Serial Bus (USB) connector, an Institute of Electrical and Electronics Engineers (IEEE) 1394 connector, a D-subminiature (D-Sub) connector, a ribbon cable connector, and an edge ( edge) connector, PS/2 (Personal System/2) connector, DIN (Deutsche Industrie Normen) connector, RJ (Registered Jack) connector, MT (Mechanically Transferable) connector, MPO (Multi-fiber Push-on) connector, RS- 232C (Recommended Standard 232C) connector, V.35 connector, DP (DisplayPort) connector, DVI (Digital Visual Interface) connector, HDMI (High Definition Multimedia Interface) connector, phone plug, RCA (Radio Corporation of America) Connector, It may include terminals corresponding to at least one of the SubMiniature version A) type connectors. However, the present disclosure is not limited to the types of terminals listed, and the connector terminal unit 110 may be implemented to include terminals for transmitting and receiving various types of signals.

The connector terminal portion 110 may be provided on a PCB board. The connector terminal unit 110 may include a plurality of terminals for receiving signals from the outside or outputting signals to the outside. In one embodiment, the plurality of terminals may be exposed to the outside and may be surface treated such as plating to prevent discoloration or surface oxidation. The connector terminal unit 110 and the integrated circuit 130 may be connected through at least one line. In one embodiment, between the connector terminal unit 110, the electrostatic discharge protection circuit 120, and the integrated circuit 130, wires corresponding to at least one line may be disposed on the PCB. The wires may form a path for transmitting a signal input through the connector terminal 110 to the integrated circuit 130 or a path for transmitting a signal from the integrated circuit 130 to the connector terminal 110.

The connector 10 may be inserted into the connector terminal portion 110. In the present disclosure, the retraction operation may include a withdrawal operation or an insertion fixation operation by the user. For example, the connector 10 may be implemented as a cable electrically connected to an external electronic device or a power source. The moment the connector is inserted into the connector terminal 110, a pulse due to an electrostatic discharge (ESD) phenomenon (i.e., an ESD pulse) may be applied (or introduced) into the electronic device 100.

The electrostatic discharge protection circuit 120 may protect the electronic device 100 from ESD pulses. For example, an ESD pulse may destroy semiconductor devices and/or wiring within the integrated circuit 130 and cause malfunction of the integrated circuit 130. The electrostatic discharge protection circuit 120 may operate to prevent ESD pulses from flowing into the integrated circuit 130 .

The electrostatic discharge protection circuit 120 may be provided on a PCB board. The electrostatic discharge protection circuit 120 may be connected to the connector terminal portion 110 through wiring on the PCB board. In one embodiment, the electrostatic discharge protection circuit 120 may include a first pad and a second pad formed on one side of the PCB board. The first pad may be connected to a wire connecting the connector terminal portion 110 and the integrated circuit 130. The second pad may be connected to the ground voltage terminal. The first pad and the second pad may be spaced apart from each other at a predetermined interval and placed on the PCB board. In one embodiment, the first pad and the second pad can form a spark gap. An arc may be formed in the spark gap formed between the first pad and the second pad by the ESD pulse flowing into the wiring. That is, arc discharge may occur in the spark gap formed between the first pad and the second pad. The incoming ESD pulse can flow to the ground voltage terminal through the path formed by the arc.

The integrated circuit 130 may control the operation of the electronic device 100 or perform a function. For example, the integrated circuit 130 may receive electrical energy or transmit and receive electrical signals through the connector terminal portion 110. For example, the integrated circuit 130 may supply electrical energy inside the electronic device 100. For example, the integrated circuit 130 may include a communication circuit that performs a communication function of the electronic device 100.

Integrated circuit 130 may be connected to electrostatic discharge protection circuit 120. Voltage, current, and/or signals from the connector terminal portion 110 may be transmitted to the integrated circuit 130 through wiring. In one embodiment, the electrostatic discharge protection circuit 120 may be disposed between the connector terminal 110 and the integrated circuit 130, and the ESD pulse input through the wiring is connected to the spark gap of the electrostatic discharge protection circuit 120. It can be discharged through. According to one embodiment, the integrated circuit 130 may be protected from ESD pulses by the spark gap of the electrostatic discharge protection circuit 120.

Figure 2 is a circuit diagram showing an electrostatic discharge protection circuit according to one embodiment. The configuration, operation, and function of the connector terminal portion 110, the electrostatic discharge protection circuit 120, and the integrated circuit 130 described in FIG. 1 are similar to those of the connector terminal portion 210, the electrostatic discharge protection circuit 220, and the integrated circuit of FIG. 2. Since it corresponds to the configuration, operation, and function of the circuit 230, redundant content will be omitted.

Referring to FIG. 2, the connector terminal unit 210 may be connected to the integrated circuit 230 through at least one line. For convenience of explanation, it is assumed that the connector terminal unit 210 and the integrated circuit 230 are connected by one line, but the present disclosure is not limited to this.

The electrostatic discharge protection circuit 220 may include a first pad (PAD1), a second pad (PAD2), a first resistor (R1), and a first capacitor (C1).

The first pad PAD1 may be connected to the first node N1. The first node N1 may be located on a line connecting the connector terminal 210 and the integrated circuit 230. The first node N1 may be connected to the connector terminal portion 210.

The second pad PAD2 is disposed to be spaced apart from the first pad PAD1 and may be connected to the ground voltage terminal. The first pad PAD1 and the second pad PAD2 may form a spark gap. The spark gap may represent an interval between the first pad (PAD1) and the second pad (PAD2) to generate a spark by forming an arc in the air. The first pad (PAD1) and the second pad (PAD2) may be formed on one side of the PCB board.

In one embodiment, the distance G1 between the first pad PAD1 and the second pad PAD2 (i.e., the size of the spark gap) may be 10 μm to 100 μm. According to one embodiment, the narrower the gap G1 between the first pad PAD1 and the second pad PAD2 is, the easier it is for sparks to be generated. Preferably, it is easy to generate sparks when the distance G1 between the first pad (PAD1) and the second pad (PAD2) is 100 μm or less. However, if the gap G1 between the first pad PAD1 and the second pad PAD2 is too narrow, a short circuit may occur, so it is limited to 10 μm or more. However, the present disclosure is not limited thereto, and it should be understood that as technology progresses, the gap G1 between the first pad PAD1 and the second pad PAD2 may become narrower or wider.

The first resistor R1 may be connected to the first node N1 and the second node N2. The first end of the first resistor R1 may be connected to the first node N1. The second end of the first resistor R1 may be connected to the second node N2. The second node N2 may be connected to the integrated circuit 230 . The second node N2 may be located on a line connecting the connector terminal 210 and the integrated circuit 230. The second node (N2) may be different from the first node (N1).

When there is no spark gap between the first pad PAD1 and the second pad PAD2, the ESD pulse may be directly applied to the resistor element corresponding to the first resistor R1. In this case, the temperature of the resistance element rises instantaneously, causing a problem in which the resistance element is melted or an internal temperature difference occurs, causing cracks to occur in the resistance element. However, according to one embodiment, a spark gap is provided in front of the first resistor R1 (that is, the first stage), so that the resistance value of the first resistor R1 can be maintained.

As the resistance element is miniaturized, ESD discharge may occur between the pads on which the resistor element is mounted beyond the resistor element. However, according to one embodiment, a spark gap is provided in front of the first resistor R1 (i.e., the first stage), thereby preventing ESD between pads on which the resistor element corresponding to the first resistor R1 is mounted. Discharge can be prevented.

According to one embodiment, the first resistor R1 may include an anti-surge resistance element. In this case, damage due to large power momentarily applied to the circuit can be prevented and improved immunity to ESD pulses can be provided.

The first capacitor C1 may be connected to the second node N2 and the ground voltage terminal. The first terminal of the first capacitor C1 may be connected to the second node N2. The second terminal of the first capacitor C1 may be connected to the ground voltage terminal. The first resistor (R1) and the first capacitor (C1) may operate as a low pass filter.

According to one embodiment, by configuring the low-pass filter with an RC filter rather than an LC filter, the electrostatic discharge circuit 220 can be mounted on a PCB board at a low cost. According to one embodiment, by configuring the low-pass filter with an RC filter rather than an LC filter, the same impedance is implemented in the entire frequency band, so that high impedance can be implemented even at low frequencies compared to the LC filter. According to one embodiment, the first resistor R1 may function as a damping resistor for ESD pulses.

According to one embodiment, an ESD protection function for the integrated circuit 230 may be performed by the first pad (PAD1) and the second pad (PAD2). The first pad (PAD1) and the second pad (PAD2) are disposed on the PCB board, so that the ESD protection function is performed without additional mounting of ESD protection elements (e.g., TVS (Transient Voltage Suppressor) diode, varistor, etc.) It can be. That is, since the ESD protection element does not need to be mounted on the PCB board, the electrostatic discharge protection circuit 220 and/or the electronic device including the electrostatic discharge protection circuit 220 can be miniaturized.

If an ESD protection element is additionally mounted in the electrostatic discharge protection circuit 220, the signal may be distorted due to the capacitance of the ESD protection element, and separate tuning work may be required due to signal distortion. In particular, in the case of circuits (e.g., touch sensor circuits, high-speed communication circuits, etc.) whose operation and/or function is affected by even small capacitances, the above problem may occur. Additionally, as ESD protection elements are additionally mounted on the PCB board, material and processing costs may increase. In addition, the entire circuit may malfunction due to a defect (eg, short circuit) in the ESD protection element. However, the electrostatic discharge protection circuit 220 according to one embodiment performs the ESD protection function without additional mounting of an ESD protection element, so the above-mentioned problem does not occur.

When an ESD pulse flows into the line through the connector terminal 210, a portion of the ESD pulse passes through the first resistor (R1) and flows into the integrated circuit 230, and the remaining portion of the ESD pulse passes through the first resistor (R1). ) (or a load including the first resistor (R1)). The reflection coefficient for the ESD pulse may follow the relationship in Equation 1.

는 반사 계수로 정의된다. ZL은 로드 임피던스(load impedance)로 정의되고, ZC는 특성 임피던스(characteristic impedance)로 정의된다. 예를 들어, ESD 펄스의 전압이 라인에 걸려서 부하로 전달될 수 있다. 여기서, 부하는 제1 저항(R1), 제1 커패시터(C1), 및 집적 회로(230)로 구성될 수 있다. 일 예로, 로드 임피던스의 값은 300 Ω 이고, 특성 임피던스의 값은 50 Ω 인 것을 가정한다. 이 경우, 반사 계수의 값은 0.75이다. 즉, ESD 펄스의 전압 중 75%에 대응하는 전압이 제1 노드(N1)에 추가적으로 가해지게 되며, 결과적으로 ESD 펄스의 전압의 175%에 대응하는 전압이 제1 노드(N1)에 가해지게 된다.Referring to Equation 1,

is defined as the reflection coefficient. ZL is defined as load impedance, and ZC is defined as characteristic impedance. For example, the voltage of an ESD pulse can be transmitted to a load through a line. Here, the load may be composed of a first resistor (R1), a first capacitor (C1), and an integrated circuit 230. As an example, assume that the value of the load impedance is 300 Ω and the value of the characteristic impedance is 50 Ω. In this case, the value of the reflection coefficient is 0.75. That is, a voltage corresponding to 75% of the voltage of the ESD pulse is additionally applied to the first node (N1), and as a result, a voltage corresponding to 175% of the voltage of the ESD pulse is applied to the first node (N1). .

A voltage greater than the voltage of the ESD pulse may be applied to the first pad PAD1 connected to the first node N1 by the first resistor R1. According to Equation 1, the larger the value of the first resistance (R1), the larger the reflection coefficient, making it easier to generate sparks. According to one embodiment, at least a portion of the ESD pulse is reflected by the first resistor R1 and diverted to the first pad PAD1, thereby forming two pads for mounting a device corresponding to the first resistor R1. Arc discharge in between can be prevented.

3A to 3G are plan views showing a pattern design of a PCB board on which an electrostatic discharge protection circuit is mounted according to an embodiment. The electrostatic discharge protection circuits 120 and 220 of FIG. 1 or FIG. 2 may be provided on a PCB board. For convenience of explanation, content that overlaps with the content described in FIGS. 1 and 2 will be omitted as the raw second node (N2). Since the height of the exposed portion on the PCB board is significantly smaller than the height of the PCB board, for convenience of explanation, it is assumed that the shape of the pads disposed on the PCB board is two-dimensional.

Referring to FIGS. 1 and 2 along with FIG. 3A, a first signal wire (the signal wire may also be referred to as a wire or a wire pattern) (SL1a) and a second signal wire (SL1a) are formed on one side of the PCB board 300a. SL2a) may be formed. The first side of the PCB board 300a may be electrically connected to the connector terminal portions 110 and 210 through the first signal wire SL1a, and the second side may be electrically connected to the integrated circuits 130 and 230 through the second signal wire SL2a. ) can be electrically connected to. The connector terminal portions 110 and 210 and the integrated circuits 130 and 230 may be electrically connected through a resistance element Ra connected in series to the first signal wire SL1a and the second signal wire SL2a. .

The first pad PAD1a may be electrically connected to the first signal line SL1a. The second pad PAD2a may be arranged to be spaced apart from the first pad PAD1a. The first pad (PAD1a) and the second pad (PAD2a) may be arranged to face each other. The second pad PAD2a may be electrically connected to the ground wire GDa, which provides a path to the ground voltage terminal (eg, ground plane).

In one embodiment, the first side of the first pad PAD1a and the first side of the second pad PAD2a may face each other. For example, lines where the first pad PAD1a and the second pad PAD2a face each other may be parallel to each other. For example, the lines where the first pad (PAD1a) and the second pad (PAD2a) face each other may be straight lines. For example, the first pad (PAD1a) and the second pad (PAD2a) may have a rectangular shape. The first pad (PAD1a) and the second pad (PAD2a) are not processed with PSR (Photo Solder Resist), and the ground wire (GNDa) is processed with PSR.

The third pad RP1a may be electrically connected to the first signal line SL1a. The fourth pad RP2a may be arranged to be spaced apart from the third pad RP1a. The fourth pad RP2a may be connected to the second signal line SL2a. A resistance element Ra may be disposed between the third pad RP1a and the fourth pad RP2a. The first end of the resistance element Ra may be electrically connected to the third pad RP1a, and the second end may be electrically connected to the fourth pad RP2a. The first signal line SL1a and the second signal line SL2a may be electrically connected through a resistance element Ra connected in series.

The fifth pad CP1a may be electrically connected to the second signal line SL2a. The sixth pad CP2a may be arranged to be spaced apart from the fifth pad CP1a. The sixth pad CP2a may be connected to the ground voltage terminal. A capacitor element Ca may be disposed between the fifth pad CP1a and the sixth pad CP2a. The first end of the capacitor element Ca may be electrically connected to the fifth pad CP1a, and the second end may be electrically connected to the sixth pad CP2a.

For convenience of explanation, FIG. 3B will be described with reference to FIGS. 1 to 3A. A first signal wire (SL1b), a second signal wire (SL2b), a first pad (PAD1b), a second pad (PAD2b), and a ground wire (GNDb) disposed on one side of the PCB board 300b of FIG. 3B, The third pad (RP1b), the fourth pad (RP2b), the resistor element (Rb), the fifth pad (CP1b), the sixth pad (CP2b), and the capacitor element (Cb) are of the PCB substrate 300a of FIG. 3A. The first signal wire (SL1a), the second signal wire (SL2a), the first pad (PAD1a), the second pad (PAD2a), the ground wire (GNDa), the third pad (RP1a), and the fourth signal wire (SL1a) disposed on one side. Since it corresponds to the pad RP2a, the resistance element Ra, the fifth pad CP1a, the sixth pad CP2a, and the capacitor element Ca, overlapping descriptions will be omitted.

Referring to FIG. 3B, the first side of the first pad PAD1b and the first side of the second pad PAD2b may face each other. For example, the first side of the first pad PAD1b and the first side of the second pad PAD2b may have a curved shape. For example, the first point on the first side of the first pad PAD1b may be closest among the first sides of the second pad PAD2b. For example, the second point on the first side of the second pad PAD2b may be closest to the first side of the first pad PAD1b. As the distance between the first point and the second point increases, the distance between the first side of the first pad PAD1b and the first side of the second pad PAD2b may increase. For example, the first pad PAD1a and the second pad PAD2a may have an elliptical shape or a semi-elliptical shape. The first pad (PAD1b) and the second pad (PAD2b) are not PSR processed, and the ground wire (GNDb) is PSR processed.

For convenience of explanation, FIG. 3C will be described with reference to FIGS. 1 to 3A. A first signal wire (SL1c), a second signal wire (SL2c), a first pad (PAD1c), a second pad (PAD2c), and a ground wire (GNDc) disposed on one side of the PCB board 300c of FIG. 3C, The third pad (RP1c), the fourth pad (RP2c), the resistor element (Rc), the fifth pad (CP1c), the sixth pad (CP2c), and the capacitor element (Cc) are of the PCB substrate 300a of FIG. 3A. The first signal wire (SL1a), the second signal wire (SL2a), the first pad (PAD1a), the second pad (PAD2a), the ground wire (GNDa), the third pad (RP1a), and the fourth signal wire (SL1a) disposed on one side. Since it corresponds to the pad RP2a, the resistance element Ra, the fifth pad CP1a, the sixth pad CP2a, and the capacitor element Ca, overlapping descriptions will be omitted.

Referring to FIG. 3C, the first point where the first side and the second side of the first pad (PAD1c) meet and the second point where the first side and the second side of the second pad (PAD2c) meet may face each other. there is. For example, the first and second sides of the first pad PAD1c and the first and second sides of the second pad PAD2c may be straight. For example, the distance between the first point and the second point may be the closest distance between the first pad (PAD1c) and the second pad (PAD2c). As the distance between the first point and the second point increases, the distance between the first pad PAD1c and the second pad PAD2c may increase. For example, the first pad (PAD1c) and the second pad (PAD2c) may have a triangular shape. The first pad (PAD1c) and the second pad (PAD2c) are not PSR processed, and the ground wire (GNDc) is PSR processed.

For convenience of explanation, FIG. 3D will be described with reference to FIGS. 1 to 3A. The first signal wire (SL1d), the second signal wire (SL2d), the first pad (PAD1d), the ground wire (GNDd), and the third pad (RP1d) disposed on one side of the PCB board 300d of FIG. 3D, The fourth pad (RP2d), the resistor element (Rd), the fifth pad (CP1d), the sixth pad (CP2d), and the capacitor element (Cd) are the first pad disposed on one surface of the PCB board 300a of FIG. 3A. Signal wire (SL1a), second signal wire (SL2a), first pad (PAD1a), ground wire (GNDa), third pad (RP1a), fourth pad (RP2a), resistor element (Ra), fifth pad Since it corresponds to (CP1a), the sixth pad (CP2a), and the capacitor element (Ca), overlapping descriptions will be omitted.

Referring to FIG. 3D, similar to the first pad PAD1a of FIG. 3A, the first pad PAD1c may have a rectangular shape. The first pad (PAD1d) and the ground wire (GNDd) are not PSR processed. In the embodiment shown in FIG. 3D, the pad corresponding to the second pad (PAD2a) of FIG. 3A may be a ground wire (GNDd) connected to the ground voltage terminal. That is, the ground wire (GNDd) may not be PSR-processed, and the ground wire (GNDd) may be disposed to be spaced apart from the first pad (PAD1d). The first pad (PAD1d) and the ground wire (GNDd) may form a spark gap.

For convenience of explanation, FIG. 3E will be described with reference to FIGS. 1 to 3B. The first signal wire (SL1e), the second signal wire (SL2e), the first pad (PAD1e), the ground wire (GNDe), and the third pad (RP1e) disposed on one side of the PCB board 300e of FIG. 3E, The fourth pad (RP2e), the resistor element (Re), the fifth pad (CP1e), the sixth pad (CP2e), and the capacitor element (Ce) are the first pads disposed on one side of the PCB board 300b of FIG. 3B. Signal wire (SL1b), second signal wire (SL2b), first pad (PAD1b), ground wire (GNDb), third pad (RP1b), fourth pad (RP2b), resistor element (Rb), fifth pad Since it corresponds to (CP1b), the sixth pad (CP2b), and the capacitor element (Cb), overlapping descriptions will be omitted.

Referring to FIG. 3E, similar to the first pad PAD1b of FIG. 3B, the first pad PAD1e may have an elliptical shape or a semi-elliptical shape. The first pad (PAD1e) and the ground wire (GNDe) are not PSR processed. In the embodiment shown in FIG. 3E, the pad corresponding to the second pad (PAD2b) in FIG. 3B may be the ground wire (GNDd) connected to the ground voltage terminal. That is, the ground wire GNDe may not be PSR-processed, and the ground wire GNDe may be disposed to be spaced apart from the first pad PAD1e. The first pad (PAD1e) and the ground wire (GNDe) may form a spark gap.

For convenience of explanation, FIG. 3F will be described with reference to FIGS. 1 to 3C. A first signal wire (SL1f), a second signal wire (SL2f), a first pad (PAD1f), a ground wire (GNDf), a third pad (RP1f) disposed on one side of the PCB board 300f of FIG. 3F, The fourth pad (RP2f), the resistor element (Rf), the fifth pad (CP1f), the sixth pad (CP2f), and the capacitor element (Cf) are the first pads disposed on one surface of the PCB board 300c of FIG. 3C. Signal wire (SL1c), second signal wire (SL2c), first pad (PAD1c), ground wire (GNDc), third pad (RP1c), fourth pad (RP2c), resistor element (Rc), fifth pad Since it corresponds to (CP1c), the sixth pad (CP2c), and the capacitor element (Cc), overlapping descriptions will be omitted.

Referring to FIG. 3F, similar to the first pad PAD1c of FIG. 3C, the first pad PAD1f may have a triangular shape. The first pad (PAD1f) and the ground wire (GNDf) are not PSR processed. In the embodiment shown in FIG. 3F, the pad corresponding to the second pad (PAD2c) in FIG. 3C may be a ground wire (GNDf) connected to the ground voltage terminal. That is, the ground wire (GNDf) may not be PSR-processed, and the ground wire (GNDf) may be disposed to be spaced apart from the first pad (PAD1f). The first pad (PAD1f) and the ground wire (GNDf) may form a spark gap.

Referring to Figures 1 and 2 along with Figure 3g, the PCB board 300g may be a double-sided PCB board. The PCB substrate 300g may include a first side 300g_1 and a second side 300g_2. A first signal wire (SL1g) may be formed on the first side (300g_1) of the PCB board. The first side of the first surface 300g_1 of the PCB board may be electrically connected to the connector terminal portions 110 and 210 through the first signal wire SL1g.

The first pad VP1 may be electrically connected to the first signal line SL1g. The first pad VP1 may correspond to an area exposed on the first side 300g_1 in a via hole that electrically connects the first side 300g_1 and the second side 300g_2 of the PCB board. . The first pad VP1 is not PSR processed. The ground wire (GNDg) may be formed on the first side (300g_1) of the PCB board. The first pad VP1 and the ground wire GNDg may be arranged to be spaced apart from each other. The first pad VP1 and the ground wire GNDg may form a spark gap.

The ground wire (GNDg) may not be PSR processed, but the present disclosure is not limited thereto. Accordingly, the ground wire (GNDg) is PSR-processed, and although not shown, a second pad (e.g., the second pad (PAD2a, PAD2b, PAD2c) of FIGS. 3A to 3C) that is not PSR-treated is connected to the first side (300g_1) of the PCB board. ) can be placed on. The second pad (not shown) may be connected to the ground wire (GNDg). In this case, the first pad VP1 and the second pad (not shown) may be arranged to be spaced apart. The first pad VP1 and the second pad (not shown) may be arranged to face each other. The first pad VP1 and the second pad (not shown) may form a spark gap.

A second signal wire (SL2g) and a third signal wire (SL3g) may be formed on the second surface (300g_2) of the PCB board. The first side of the second side 300g_2 of the PCB board may be electrically connected to the integrated circuits 130 and 230 through the third signal wire SL3g. Integrated with the connector terminal portions 110 and 210 through the first signal wire (SL1g), via hole, second signal wire (SL2g), third signal wire (SL3g), and resistance element (Rg) connected in series. Circuits 130 and 230 may be electrically connected.

The second signal line SL2g may be electrically connected to the first signal line SL1g through a via hole corresponding to the first pad VP1. For example, the second signal wire (SL2g) is exposed on the second side (300g_2) in a via hole that electrically connects the first side (300g_1) and the second side (300g_2) of the PCB board. It can be connected to area (VP2).

The third pad RP1g may be electrically connected to the second signal line SL2g. The third pad RP1g may be disposed on the second side 300g_2 of the PCB board. The fourth pad RP2g may be arranged to be spaced apart from the third pad RP1g. The fourth pad RP2g may be connected to the third signal line SL3g. The fourth pad RP2g may be disposed on the second side 300g_2 of the PCB board. A resistance element Rg may be disposed between the third pad RP1g and the fourth pad RP2g. The first end of the resistance element Rg may be electrically connected to the third pad RP1g, and the second end may be electrically connected to the fourth pad RP2g. The resistance element Rg may be disposed on the second side 300g_2 of the PCB board. The second signal wire SL2g and the third signal wire SL3g may be electrically connected through a resistor element Rg connected in series.

The fifth pad CP1g may be electrically connected to the third signal line SL3g. The fifth pad CP1g may be disposed on the second side 300g_2 of the PCB board. The sixth pad CP2g may be arranged to be spaced apart from the fifth pad CP1g. The sixth pad CP2g may be connected to the ground voltage terminal. The sixth pad CP2g may be disposed on the second side 300g_2 of the PCB board. A capacitor element Cg may be disposed between the fifth pad CP1g and the sixth pad CP2g. The first end of the capacitor element Cg may be electrically connected to the fifth pad CP1g, and the second end may be electrically connected to the sixth pad CP2g. The capacitor element Cg may be disposed on the second side 300g_2 of the PCB board.

The embodiments described in FIGS. 3A to 3G are exemplary embodiments of the present disclosure, and therefore the disclosure is not limited thereto. Accordingly, the electrostatic discharge protection circuit can be implemented in any combination of the embodiments shown in FIGS. 3A to 3G. For example, the shapes of the first pads (PAD1a, PAD1b, and PAD1c) and the shapes of the second pads (PAD2a, PAD2b, and PAD2c) may be implemented in various shapes. The shapes of the first pads (PAD1a, PAD1b, and PAD1c) and the shapes of the second pads (PAD2a, PAD2b, and PAD2c) may be the same or different from each other. For example, the first pads (PAD1a, PAD1b, PAD1c) and the second pads (PAD2a, PAD2b, PAD2c) may be formed on a PCB board in at least one of a square shape, a triangular shape, a semicircular shape, and a semielliptical shape. .

The embodiments described in FIGS. 3A to 3G show an example in which one of the lines between the connector terminal portion (FIG. 1, 110) and the integrated circuit (FIG. 1, 130) is disposed on the PCB board. In one embodiment, the second pad (PAD2a, PAD2b, PAD2c) and/or the ground wire (GNDa, GNDb, GNDc, GNDd, GNDe, GNDf, GNDg) are not dedicated to one line, but are shared by other lines. It can be. In the embodiment described in FIG. 3G, an example in which the ground wire (GNDg) is shared by a plurality of lines will be described in detail in FIG. 4.

Figure 4 is a plan view showing a pattern design of a PCB board on which an electrostatic discharge protection circuit is mounted according to an embodiment. For convenience of explanation, FIG. 4 will be described with reference to FIG. 3G.

Referring to FIGS. 1 and 3G along with FIG. 4 , at least some of the lines between the connector terminal portion 110 and the integrated circuit 130 may be disposed on the PCB board. In FIG. 4 , the number of lines disposed on the PCB board among the lines between the connector terminal unit 110 and the integrated circuit 130 is exemplarily shown as three, but the present disclosure is not limited thereto. For example, among the lines between the connector terminal unit 110 and the integrated circuit 130, lines disposed on the PCB board may be referred to as a first line, a second line, and a third line.

The first side 400_1 of the PCB substrate may correspond to the first side 300g_1 of the PCB substrate in FIG. 3G. The first signal line SL1 may correspond to the first line. For example, the first signal line SL1 may correspond to the first signal line SL1g of FIG. 3G. The first pad VP1 may be electrically connected to the first signal line SL1. The first pad VP1 may correspond to an area exposed on the first side 400_1 in the first via hole that electrically connects the first side 400_1 and the second side (not shown) of the PCB board. For example, the first pad VP1 may correspond to the first pad VP1 in FIG. 3G.

The second signal line SL2 may correspond to the second line. The second pad VP2 may be electrically connected to the first signal line SL2. The second pad VP2 may correspond to an area exposed on the first side 400_1 in the second via hole that electrically connects the first side 400_1 and the second side (not shown) of the PCB board. The third signal line SL3 may correspond to the third line. The third pad VP3 may be electrically connected to the third signal line SL3. The third pad VP3 may correspond to an area exposed on the first side 400_1 in the third via hole that electrically connects the first side 400_1 and the second side (not shown) of the PCB board. The first pad (VP1), the second pad (VP2), and the third pad (VP3) are not PSR processed.

The ground wire (GNDg) may be formed on the first side (300g_1) of the PCB board. The ground wire (GNDg) may correspond to the ground wire (GNDg) of FIG. 3G. The first pad VP1 and the ground wire GNDg may be arranged to be spaced apart from each other. The first pad VP1 and the ground wire GNDg may form a first spark gap. The second pad VP2 and the ground wire GNDg may be arranged to be spaced apart from each other. The second pad VP2 and the ground wire GNDg may form a second spark gap. The third pad VP3 and the ground wire GNDg may be arranged to be spaced apart from each other. The third pad VP3 and the ground wire GNDg may form a third spark gap. The sizes of each of the first to third spark gaps may be the same or different from each other.

Figure 5 is a circuit diagram showing an electrostatic discharge protection circuit according to one embodiment. The configuration, function, and operation of the connector terminal portion 510 and the integrated circuit 530 are similar to the configuration, function, and operation of the connector terminal portion 110 and 210 and the integrated circuit 130 and 230 described in FIGS. 1 and 2, so there is no overlap. Content is omitted.

Referring to FIG. 5 , the connector terminal unit 510 may include a first terminal (T1), a second terminal (T2), a third terminal (T3), and a fourth terminal (T4). The first terminal T1 may be connected to the ground voltage terminal. The second terminal T2 may be connected to the first line L1. The third terminal T3 may be connected to the second line L2. The fourth terminal T4 may be connected to the third line L3. The connector terminal portion 510 may be connected to the integrated circuit 530 through the first line (L1), the second line (L2), and the third line (L3). In FIG. 5 , the number of terminals included in the connector terminal unit 510 is shown to be four, but the present disclosure is not limited thereto, and the connector terminal unit 510 may include at least one terminal.

The electrostatic discharge protection circuit 520 includes a first line (L1), a second line (L2), and a third line (L3), and a first line (L1), a second line (L2), and a third line ( It may include circuit elements connected to L3). For example, the electrostatic discharge protection circuit 520 includes a first pad (PAD1), a second pad (PAD2), a third pad (PAD3), a fourth pad (PAD4), a first resistor (R1), and a second resistor. (R2), a first capacitor (C1), a second capacitor (C2), and an ESD protection element (V1).

Each of the first line L1 and the second line L2 may correspond to a line connecting the connector terminal portion 210 of the electrostatic discharge protection circuit 220 of FIG. 2 and the integrated circuit 230.

The first pad PAD1 may be connected to the first node N1. The first node N1 may be connected to the second terminal T2. The first node N1 may be located on the first line L1 connecting the second terminal T2 and the integrated circuit 530. The second pad PAD2 is disposed to be spaced apart from the first pad PAD1 and may be connected to the ground voltage terminal. The first pad PAD1 and the second pad PAD2 may form a spark gap. The first resistor R1 may be connected to the first node N1 and the second node N2. The first end of the first resistor R1 may be connected to the first node N1. The second end of the first resistor R1 may be connected to the second node N2. The second node N2 may be connected to the integrated circuit 530. The second node N2 may be located on the first line L1 connecting the second terminal T2 and the integrated circuit 530. The first capacitor C1 may be connected to the second node N2 and the ground voltage terminal. The first terminal of the first capacitor C1 may be connected to the second node N2. The second terminal of the first capacitor C1 may be connected to the ground voltage terminal. The first resistor (R1) and the first capacitor (C1) may operate as a low-pass filter.

The third pad PAD3 may be connected to the third node N3. The third pad PAD3 may be connected to the third terminal T3. The third node N3 may be located on the second line L2 connecting the third terminal T3 and the integrated circuit 530. The fourth pad (PAD4) is disposed to be spaced apart from the third pad (PAD3) and may be connected to the ground voltage terminal. The third pad PAD3 and fourth pad PAD4 may form a spark gap. The second resistor R2 may be connected to the third node N3 and the fourth node N4. The first end of the second resistor R2 may be connected to the third node N3. The second end of the second resistor R2 may be connected to the fourth node N4. The fourth node N4 may be connected to the integrated circuit 530. The fourth node N4 may be located on the second line L2 connecting the third terminal T3 and the integrated circuit 530. The second capacitor C2 may be connected to the fourth node N4 and the ground voltage terminal. The first terminal of the second capacitor C2 may be connected to the fourth node N4. The second terminal of the second capacitor C2 may be connected to the ground voltage terminal. The second resistor R2 and the second capacitor C2 may operate as a low-pass filter.

Unlike the first line (L1) or the second line (L2), a resistor connected in series to the third line (L3) may not be provided. Accordingly, in order to prevent ESD pulses from flowing into the integrated circuit 530 through the third line L3, an ESD protection element V1 may be provided on the third line L3. The ESD protection element V1 may be connected to the fifth node N5. The fifth node N5 may be located on the third line L3 connected to the fourth terminal T4 and the integrated circuit 530. The ESD protection element V1 may be connected to the fifth node N5 and the ground voltage terminal. The first end of the ESD protection element V1 may be connected to the fifth node N5. The second terminal of the ESD protection element V1 may be connected to the ground voltage terminal. For example, the ESD protection element V1 may include a TVS diode or a varistor.

Figure 6 is a diagram showing the shape of a pad according to one embodiment. The first pad (PAD1) and the second pad (PAD2) are the first pads (PAD1, PAD1a, PAD1b, PAD1c, PAD1d, PAD1e, PAD1f, PAD1g) and the second pads (PAD2, PAD2a) shown in FIGS. 1 to 5. , PAD2b, PAD2c). The first pad PAD1 may be formed on the PCB board to protrude from the signal line Signal. That is, the area protruding from the signal line (Signal) may be referred to as the first pad (PAD1). The area protruding from the first pad (PAD1) or the signal line (Signal) is not PSR processed. The second pad PAD2 may be formed on the PCB board to protrude from the ground wire (Ground). That is, the area protruding from the ground wire (Ground) may be referred to as the second pad (PAD2). The area protruding from the second pad PAD2 or the ground line is not PSR processed. The first pad PAD1 and the second pad PAD2 may protrude to have an elliptical or semi-elliptical shape. For example, the distance between the maximum protrusion point of the first pad PAD1 and the maximum protrusion point of the second pad PAD2 may be 65.051 μm. The first pad PAD1 and the second pad PAD2 may form a spark gap. In the spark gap, sparks caused by ESD pulses can occur.

Figure 7 is a flowchart showing a method for protecting against electrostatic discharge according to an embodiment. For convenience of explanation, the electrostatic discharge protection method will be described with reference to FIGS. 2 and 3A. The electrostatic discharge protection method can be implemented by operating the electrostatic discharge protection circuit 220 provided on the PCB board 300a.

In step S710, the electrostatic discharge protection circuit 220 may receive the ESD pulse flowing from the connector terminal portion 210 to the PCB board 300a.

In step S720, the resistance element Ra connected to the connector terminal 210 and disposed on the PCB board 300a may reflect at least a portion of the ESD pulse. Resistor element Ra may correspond to first resistor R1.

In step S730, the electrostatic discharge protection circuit 220 includes first pads (PAD1 and PAD1a) connected to the connector terminal portion 210 and the resistance element Ra and disposed on the PCB board 300a, and a first pad ( The received ESD pulse and the reflected ESD pulse are connected to the second pads (PAD2, PAD2a) through an arc between PAD1, PAD1a) and the second pads (PAD2, PAD2a) spaced apart from each other and disposed on the PCB board 300a. It can be discharged to the ground voltage terminal. In one embodiment, the second pad (PAD2, PAD2a) may be a ground wire (GNDa) connected to the ground voltage terminal, or may be a pad connected to the ground voltage terminal. For example, if the second pad (PAD2, PAD2a) is a ground wire (GNDa) connected to the ground voltage terminal, the ground wire (GNDa) may not be PSR processed.

Figure 8 is a block diagram showing an electronic device according to an embodiment. The configuration, operation, and function of the electronic device 1000 shown in FIG. 8 may correspond to the configuration, operation, and function of the electronic device 100 and 200 described in FIGS. 1 and 2.

Referring to FIG. 8 , the electronic device 1000 may include a processor 1100, a communication interface 1200, a user interface 1300, a memory 1400, and a power supply device 1500. Not all components of the electronic device 1000 are essential, and each component may be added or subtracted according to the manufacturer's design philosophy.

The processor 1100 controls the overall operation of the electronic device 1000. The processor 1100 may control the communication interface 1200, the user interface 1300, the memory 1400, and the power supply device 1500 by executing programs stored in the memory 1400.

The processor 1100 may be implemented through a combination of a general-purpose processor, such as an application processor (AP), a central processing unit (CPU), or a graphic processing unit (GPU), and software. In the case of a dedicated processor, it may include a memory for implementing an embodiment of the present disclosure, or a memory processing unit for using an external memory.

The processor 1100 may be composed of a plurality of processors. In this case, it may be implemented through a combination of dedicated processors, or it may be implemented through a combination of software and multiple general-purpose processors such as AP, CPU, or GPU.

In one embodiment, the processor 1100 may be equipped with an artificial intelligence (AI) processor. Artificial intelligence (AI) processors may be manufactured in the form of dedicated hardware chips for artificial intelligence (AI), or may be manufactured as part of an existing general-purpose processor (e.g. CPU or application processor) or graphics-specific processor (e.g. GPU). It may also be mounted on the electronic device 1000.

In one embodiment, the processor 1100 may control the operation of the connectors 1231 and 1501 and the electrostatic discharge protection circuits 1232 and 1502 included in the wired communication unit 1230 or the power supply device 1500.

The electronic device 1000 may include a communication interface 1200 to operate on an IoT (Internet of Things) network or a home network, as needed.

The communication interface 1200 may include a short-range communication unit 1210, a long-distance communication unit 1220, and a wired communication unit 1230.

The short-range wireless communication interface (1210) includes a Bluetooth communication unit, a Bluetooth Low Energy (BLE) communication unit, a Near Field Communication interface, a WLAN (Wi-Fi) communication unit, a Zigbee communication unit, and an infrared (IrDA) communication unit. , infrared Data Association) communication unit, WFD (Wi-Fi Direct) communication unit, UWB (Ultra Wideband) communication unit, Ant+ communication unit, etc., but is not limited thereto.

The long-distance communication unit 1220 transmits and receives wireless signals with at least one of a base station, an external terminal, and a server on a mobile communication network. Here, the wireless signal may include various types of data according to voice call signals, video call signals, or text/multimedia message transmission and reception. The long-distance communication unit 1220 may include, but is not limited to, a 3G module, 4G module, 5G module, LTE module, NB-IoT module, LTE-M module, etc.

The wired communication unit 1230 transmits and receives wired signals from an external terminal or server connected to the electronic device 1000 by wire. Here, the wired signal may be a signal containing various types of data, such as a control signal, an audio signal, and a video signal.

The wired communication unit 1230 may include a connector terminal unit 1231 and an electrostatic discharge protection circuit 1232. The configuration, operation, and function of the connector terminal portion 1231 and the electrostatic discharge protection circuit 1232 are the same as those of the connector terminal portions 110 and 210 and the electrostatic discharge protection circuit 120 and 220 of FIGS. 1 and 2. Since it corresponds to , duplicate content is omitted.

The connector terminal unit 1231 may include at least one terminal for transmitting and receiving signals corresponding to various protocols. In one embodiment, the connector terminal portion 1231 may be a female connector terminal portion into which various types of connectors can be inserted. The electrostatic discharge protection circuit 1232 uses the spark gap formed on the PCB board to cause the ESD pulse generated when the connector is inserted into the connector terminal portion 1231 to be transmitted to the integrated circuit of the electronic device 1000 (e.g., processor 1100). ), memory 1400, etc.) can be prevented from flowing into the memory.

The user interface 1300 may include an input interface 1310 and an output interface 1320.

The input interface 1310 is for receiving input from a user (hereinafter referred to as user input). The input interface 1310 includes a key pad, a dome switch, and a touch pad (contact capacitive type, pressure resistance type, infrared detection type, surface ultrasonic conduction type, integral tension measurement type, It may be at least one of a piezo effect type, etc.), a jog wheel, and a jog switch, but is not limited thereto. In one embodiment, when an ESD pulse is generated in the process of receiving a user input, the electrostatic discharge protection circuits 1232 and 1502 may prevent the ESD pulse from entering the integrated circuit of the electronic device 1000.

The input interface 1310 may include a voice recognition module. For example, the electronic device 1000 may receive a voice signal, which is an analog signal, through a microphone, and convert the voice portion into computer-readable text using an Automatic Speech Recognition (ASR) model. The electronic device 1000 may acquire the user's utterance intention by interpreting the converted text using a Natural Language Understanding (NLU) model. Here, the ASR model or NLU model may be an artificial intelligence model. Artificial intelligence models can be processed by an artificial intelligence-specific processor designed with a hardware structure specialized for processing artificial intelligence models. Artificial intelligence models can be created through learning. Here, being created through learning means that the basic artificial intelligence model is learned using a large number of learning data by a learning algorithm, thereby creating a predefined operation rule or artificial intelligence model set to perform the desired characteristics (or purpose). It means burden. An artificial intelligence model may be composed of multiple neural network layers. Each of the plurality of neural network layers has a plurality of weight values, and neural network calculation is performed through calculation between the calculation result of the previous layer and the plurality of weights.

Linguistic understanding is a technology that recognizes and applies/processes human language/characters, including Natural Language Processing, Machine Translation, Dialog System, Question Answering, and Voice Recognition. /Speech Recognition/Synthesis, etc.

The output interface 1320 is for outputting audio signals or video signals, and may include, for example, a display or speaker.

According to one embodiment, the electronic device 1000 may display information related to the electronic device 1000 through a display. For example, the ESD pulse detection status of the electronic device 1000 may be displayed on the display.

When the display and the touchpad form a layered structure to form a touch screen, the display can be used as an input device in addition to an output device. Displays include liquid crystal display, thin film transistor-liquid crystal display, light-emitting diode (LED), organic light-emitting diode, and flexible display. It may include at least one of a display, a 3D display, and an electrophoretic display. Additionally, depending on the implementation form of the electronic device 1000, it may include two or more displays.

The speaker may output audio data received from the communication interface 1200 or stored in the memory 1400. Additionally, the speaker may output sound signals related to functions performed in the electronic device 1000.

The memory 1400 may store programs for processing and control of the processor 1100, and may also store input/output data (eg, HDMI data, USB data, etc.). The memory 1400 may store an artificial intelligence model.

The memory 1400 may be a flash memory type, a hard disk type, a multimedia card micro type, a card type memory (for example, SD or XD memory, etc.), or RAM. (RAM, Random Access Memory) SRAM (Static Random Access Memory), ROM (Read-Only Memory), EEPROM (Electrically Erasable Programmable Read-Only Memory), PROM (Programmable Read-Only Memory), magnetic memory, magnetic disk , and may include at least one type of storage medium among optical disks. Additionally, the electronic device 1000 may operate a web storage or cloud server that performs a storage function on the Internet.

The power supply device 1500 may receive power from an external power source and supply current to a load according to a driving control signal from the processor 1100. The power supply device 1500 may include a connector terminal portion 1501 and an electrostatic discharge protection circuit 1502. The configuration, operation, and function of the connector terminal portion 1501 and the electrostatic discharge protection circuit 1502 are the same as those of the connector terminal portions 110 and 210 and the electrostatic discharge protection circuit 120 and 220 of FIGS. 1 and 2. Since it corresponds to , duplicate content is omitted. In one embodiment, the connector terminal portion 1501 and the electrostatic discharge protection circuit 1502 may be the connector terminal portion 1231 and the electrostatic discharge protection circuit 1232, but the present disclosure is not limited thereto, and they are separate components. It can be implemented.

The connector terminal unit 1501 may include at least one terminal for receiving power from an external power source. In one embodiment, the connector terminal portion 1501 may be a female connector terminal portion into which various types of connectors can be inserted. The electrostatic discharge protection circuit 1502 uses a spark gap formed on the PCB board to cause the ESD pulse generated when the connector is inserted into the connector terminal portion 1501 to be transmitted to the integrated circuit of the electronic device 1000 (e.g., processor 1100). ), memory 1400, etc.) can be prevented from flowing into the memory.

The electronic devices 100, 200, and 1000 according to an embodiment of the present disclosure may be applied to home appliances, but are not limited thereto. Additionally, the electronic devices 100, 200, and 1000 according to an embodiment of the present disclosure may include a dishwasher, an air conditioner, a washing machine, a dryer, a lamp, a TV, a heating device, and a styler, etc. It is not limited to this. Heating devices may include, but are not limited to, a smart kettle, teapot, coffee pot, induction device, toast, air fryer, highlighter, rice cooker, etc.

Not all of the components shown in the electronic devices 100, 200, and 1000 according to an embodiment of the present disclosure are essential components. The electronic devices 100, 200, and 1000 may be implemented with more components than the illustrated components, or the electronic devices 100, 200, and 1000 may be implemented with fewer components than the illustrated components. Throughout this specification, the electronic devices 100, 200, and 1000 may be referred to as home appliances, home appliances, cooking appliances, or electric devices, and these terms may be used interchangeably or interchangeably. Additionally, throughout this specification, electric devices including electronic devices 100, 200, and 1000 may be independently sold home appliances or may be devices that form part of a home appliance.

In one embodiment, the electrostatic discharge protection circuit on the PCB board includes a first pad connected to a first node, a second pad disposed spaced apart from the first pad and connected to a ground voltage terminal, the first node, and It may include a first resistor connected to a second node different from the first node, and a first capacitor connected to the second node and the ground voltage terminal.

In the electrostatic discharge protection circuit according to an embodiment, a connector terminal is connected to the first node, an integrated circuit is connected to the second node, and an electrostatic discharge (ESD) pulse is transmitted from the connector terminal to the first node. The ESD pulse may flow into node 1 and be diverted to the ground voltage terminal connected to the second pad.

In the electrostatic discharge protection circuit according to one embodiment, the first pad and the second pad may be formed on the PCB board in at least one of a square shape, a triangular shape, a semicircular shape, and a semielliptical shape.

In the electrostatic discharge protection circuit according to one embodiment, the second pad may be a ground wire connected to the ground voltage terminal.

In the electrostatic discharge protection circuit according to one embodiment, the PCB board is a double-sided PCB board including a first side and a second side, and the first pad is a via hole connecting the first side and the second side. corresponds to an area exposed on the first surface in a via hole, the second pad is formed on the first surface, and the first resistor and the first capacitor are disposed on the second surface. You can.

In the electrostatic discharge protection circuit according to one embodiment, the first resistor may include an anti-surge resistor element.

In the electrostatic discharge protection circuit according to one embodiment, the first pad and the second pad may form a spark gap.

In the electrostatic discharge protection circuit according to one embodiment, the distance between the first pad and the second pad may be 10 μm to 100 μm.

In one embodiment, an electronic device for preventing electrostatic discharge includes a connector terminal portion, an integrated circuit, and a first line connecting the connector terminal portion and the integrated circuit on a printed circuit board (PCB) substrate. A circuit comprising: a first pad connected to a first node of the first line, a second pad spaced apart from the first pad and connected to a ground voltage terminal, and the first pad connected to the first node of the first line. It may include a first resistor connected to a node and a second node of the first line that is different from the first node, and a first capacitor connected to the second node and the ground voltage terminal.

In an electronic device according to an embodiment, the electrostatic discharge protection circuit includes a second line connecting the connector and the integrated circuit, wherein the electrostatic discharge protection circuit includes: a third node of the second line and the It may include an ESD protection element connected to the ground voltage terminal.

In an electronic device according to an embodiment, the ESD protection element may include a Transient Voltage Suppression (TVS) diode or a varistor.

In an electronic device according to an embodiment, the connector terminal portion is connected to the first node, the integrated circuit is connected to the second node, and an electrostatic discharge (ESD) pulse is transmitted from the connector terminal portion to the first node. The ESD pulse may flow into node 1 and be diverted to the ground voltage terminal connected to the second pad.

In an electronic device according to an embodiment, the first pad and the second pad may be formed on the PCB board in at least one of a square shape, a triangular shape, a semicircular shape, and a semielliptical shape.

In an electronic device according to an embodiment, the second pad may be a ground wire connected to the ground voltage terminal.

In the electronic device according to one embodiment, the PCB board is a double-sided PCB board including a first side and a second side, and the first pad has a via hole connecting the first side and the second side. hole), the second pad may be formed on the first side, and the first resistor and the first capacitor may be disposed on the second side. .

In the electronic device according to one embodiment, the first resistor may include an anti-surge resistance element.

In an electronic device according to an embodiment, the first pad and the second pad may form a spark gap.

In the electronic device according to one embodiment, the distance between the first pad and the second pad may be 10 μm to 100 μm.

In one embodiment, a method of protecting against electrostatic discharge on a PCB board includes the steps of receiving an electrostatic discharge (ESD) pulse flowing into the PCB board from a connector terminal part, connected to the connector terminal part and on the PCB board. Reflecting at least a portion of the ESD pulse by a resistor element disposed, and a first pad connected to the connector terminal portion and the resistor element and disposed on the PCB board, and spaced apart from the first pad on the PCB It may include discharging the received ESD pulse and the reflected ESD pulse to a ground voltage terminal connected to the second pad through an arc between second pads disposed on the substrate.

In the electrostatic discharge protection method according to an embodiment, the second pad may be a ground wire connected to the ground voltage terminal or a pad connected to the ground voltage terminal.

In one embodiment, a printed circuit board assembly (PCB assembly) on which an electrostatic discharge protection circuit is mounted includes a first signal wire connected to a connector terminal, a second signal wire connected to an integrated circuit, and a first signal wire connected to the first signal wire. a first pad, disposed to be spaced apart from the first pad, a second pad connected to a ground voltage terminal, a third pad connected to the first signal line, disposed to be spaced apart from the third pad, and the second A fourth pad connected to a signal wire, a first resistor element connected to the third pad and the fourth pad, a fifth pad connected to the second signal wire, disposed to be spaced apart from the fifth pad, and the ground. It may include a sixth pad connected to a voltage terminal, and a first capacitor element connected to the fifth pad and the sixth pad.

In the PCB assembly according to one embodiment, the second pad may be a ground wire connected to the ground voltage terminal or a pad connected to the ground voltage terminal.

Claims (10)

In the electronic device (100; 200; 500) for preventing electrostatic discharge (ESD),
Connector terminal portion (110; 210; 510);
integrated circuits (130; 230; 530);
On a printed circuit board (PCB) board (300a; 300b; 300c; 300d; 300e; 300f; 300g), a first circuit connecting the connector terminal portion (110; 210; 510) and the integrated circuit (130; 230; 530) An electrostatic discharge protection circuit (120; 220; 520) including a line,
The electrostatic discharge protection circuit (120; 220; 520):
a first pad connected to a first node of the first line;
a second pad spaced apart from the first pad and connected to a ground voltage terminal;
a first resistor connected to the first node and a second node of the first line that is different from the first node; and
An electronic device (100; 200; 500) including a first capacitor connected to the second node and the ground voltage terminal.
According to paragraph 1,
The electrostatic discharge protection circuit (120; 220; 520) includes a second line connecting the connector terminal portion (110; 210; 510) and the integrated circuit (130; 230; 530),
The electrostatic discharge protection circuit (120; 220; 520):
The electronic device (100; 200; 500) further includes an ESD protection element connected to a third node of the second line and the ground voltage terminal.
According to paragraph 2,
The ESD protection element is an electronic device (100; 200; 500) including a Transient Voltage Suppression (TVS) diode or varistor.
According to any one of claims 1 to 3,
The connector terminal portion (110; 210; 510) is connected to the first node,
The integrated circuit (130; 230; 530) is connected to the second node,
ESD pulses flow into the first node from the connector terminal portion (110; 210; 510),
An electronic device (100; 200; 500) in which the ESD pulse is diverted to the ground voltage terminal connected to the second pad.
According to any one of claims 1 to 4,
The first pad and the second pad are formed on the PCB board in at least one of a square shape, a triangular shape, a semi-circular shape, and a semi-elliptical shape.
According to any one of claims 1 to 5,
The second pad is a ground wire connected to the ground voltage terminal of the electronic device (100; 200; 500).
According to clause 6,
The PCB board (300g) is a double-sided PCB board including a first side (300g_1) and a second side (300g_2),
The first pad corresponds to an area exposed on the first surface (300g_1) in a via hole connecting the first surface (300g_1) and the second surface (300g_2),
The second pad is formed on the first surface (300g_1),
The first resistor and the first capacitor are disposed on the second surface (300g_2), the electronic device (100; 200; 500).
According to any one of claims 1 to 7,
The first resistor includes an anti-surge resistance element (100; 200; 500).
According to any one of claims 1 to 8,
The first pad and the second pad form a spark gap (100; 200; 500).
According to any one of claims 1 to 9,
The electronic device (100; 200; 500) wherein the distance between the first pad and the second pad is 10 μm to 100 μm.

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