KR20240001245A - Methods for efficient implementation of the unitary operators of Clifford's algebra as quantum circuits and their application to linear algebra and machine learning - Google Patents

Abstract

This disclosure relates to methods of constructing efficient quantum circuits for Clifford loaders and variations of these methods that follow a similar approach.

Description

Methods for efficient implementation of the unitary operators of Clifford's algebra as quantum circuits and their application to linear algebra and machine learning

This disclosure is within the field of quantum algorithms and quantum linear algebra. In particular, the present disclosure provides a logarithmic depth construction for quantum circuits called a Clifford loader. This disclosure also lies within the field of quantum machine learning. In particular, this disclosure provides applications for quantum machine learning of Clifford Loader circuits.

Determinant sampling using a classical computer reduces the complexity of calculating the determinant of a single d-dimensional matrix. Since it changes as follows, the calculation cost is high. Theoretically, to calculate a single determinant There are complex theoretical constructs that can achieve , but they only outperform standard methods for very large d due to the large constant factor overhead. Moreover, most classical determinant sampling algorithms require calculating multiple determinants, which leads to higher computational demands.

This disclosure provides a logarithmic depth construction for quantum circuits called a Clifford loader. These circuits implement specific unitary operations of Clifford algebra and have applications in quantum linear algebra and quantum machine learning. The constructed circuits are optimized in terms of the number of qubits, the depth of the quantum circuit, and the type of gates within the circuit.

Quantum machine learning and linear algebra algorithms can rely on the ability to represent classical data as quantum states to use quantum procedures for linear algebra tasks. This disclosure provides procedures for efficiently representing subspaces spanned by k-vectors as quantum states using Clifford Loader. Embodiments of the present disclosure relate to quantum machine learning, for example, for tasks of determinant sampling and topological data analysis, and to quantum linear algebra, for example, for projection and solution of low-dimensional linear systems. Applies.

Some embodiments relate to quantum circuits for execution by a quantum computer, where the quantum computer includes at least N qubits (q _n ). The quantum circuit includes a first sub-circuit, a second sub-circuit, and a gadget circuit. The first sub-circuit includes quantum gates applied to N/2 qubits (q ₁ -q _N/2 ), and after execution of the first sub-circuit, the value of the qubit (q ₂ ) is It represents the parity of (q ₂ -q _N/2 ). The second sub-circuit is arranged to run concurrently with the first sub-circuit and includes quantum gates applied to N/2 qubits (q _(N/2+1) -q _N ). The gadget circuit is arranged to run after the first and second subcircuits. The gadget circuit includes quantum gates applied to the qubits q ₁ , q ₂ , and q _(N/2+1) , where one of the quantum gates of the gadget circuit is the BS(θ) gate. The BS(θ) gate is a single parameterized two-qubit quantum gate. If the value of qubit (q ₂ ) is 0, the gadget circuit applies the BS(θ) gate to qubits (q ₁ and q _{(N/2+1) )} . If the value of qubit (q ₂ ) is 1, the gadget circuit instead applies the conjugate of the BS(θ) gate to qubits (q ₁ and q _(N/2+1) ).

In some embodiments, the first sub-circuit includes a third sub-circuit, a fourth sub-circuit, and a second gadget circuit. The third sub-circuit includes quantum gates applied to N/4 qubits (q ₁ -q _N/4 ), where after execution of the third sub-circuit, the value of the qubit (q ₂ ) is qubit It represents the parity of (q ₂ -q _N/4 ). The fourth sub-circuit is arranged to run concurrently with the third sub-circuit and includes quantum gates applied to N/4 qubits (q _(N/4+1) -q _N/2 ). The second gadget circuit is behind the third and fourth subcircuits. The second gadget circuit includes quantum gates applied to the qubits (q ₁ , q ₂ , and q _(N/4+1) ), where one of the quantum gates of the second gadget circuit is connected to the second BS ( θ) is the gate. If the value of qubit (q ₂ ) is 0, the second BS(θ) gate is applied to qubits (q ₁ and q _(N/4+1) ), and if the value of qubit (q ₂ ) is 1 , then the conjugate of the second BS(θ) gate is applied to the qubits q ₁ and q _(N/4+1) .

In some embodiments, the quantum circuit further includes an X gate applied to qubit (q1) after the gadget circuit. In some embodiments, the quantum circuit further includes a second gadget circuit after the X gate. The second gadget circuit includes quantum gates applied to the qubits (q ₁ , q ₂ , and q _(N/2+1) ), where one of the quantum gates of the second gadget circuit is connected to the second BS ( θ) is the gate. If the value of qubit (q ₂ ) is 0, then the conjugate of the BS(θ) gate is applied to qubits (q ₁ and q _(N/2+1) ), and if the value of qubit (q ₂ ) is 1 , then the BS(θ) gate is applied to the qubits q ₁ and q _(N/2+1) . In some embodiments, the quantum circuit further includes a third sub-circuit after the second gadget circuit. The third sub-circuit includes quantum gates applied to N/2 qubits (q ₁ -q _N/2 ), where the quantum gates of the third sub-circuit are arranged in reverse order. and is identical to the quantum gates of the first subcircuit except that the BS(θ) gate is conjugated. In some embodiments, the quantum circuit further includes a fourth sub-circuit arranged to execute concurrently with the third sub-circuit. The fourth sub-circuit includes quantum gates applied to N/2 qubits (q _(N/2+1) -q _N ), where the quantum gates of the fourth sub-circuit are: is identical to the quantum gates of the second subcircuit except that they are arranged in reverse order and the BS(θ) gates are conjugated.

In some embodiments, the quantum circuit applies a second BS(θ) gate to qubits q ₁ and q ₂ and a third BS(θ) gate to qubits q ₃ and q ₄ A first layer that does; a second layer applying a first CZ gate to the qubits (q ₁ and q ₂ ), where the CZ gate is a controlled Z gate; a third layer applying a fourth BS(θ) gate to the qubits (q ₁ and q ₃ ); a fourth layer applying a second CZ gate to qubits (q ₁ and q ₂ ) and a first CX gate to qubits (q ₃ and q ₄ ), where the CX gate is a controlled and a fifth layer that applies a second CX gate to the qubits (q ₂ and q ₃ ).

In some embodiments, the gadget subcircuit includes: a first layer applying a first CZ gate to qubits (q ₁ and q ₂ ), where the CZ gate is a controlled Z gate; a second layer applying a BS(θ) gate to the qubits (q ₁ and q _{(N/2+1) )} ; and a third layer that applies a second CZ gate to the qubits (q ₁ and q ₂ ).

Some embodiments relate to quantum circuits for execution by quantum computers. Note that the following circuit contains nested subcircuits. A quantum circuit has N qubits (q _n ), where N=2 ^K and K≥2; and K recursive circuit levels, where k=1 to K. Each circuit level k includes (N/2 ^k ) level-k circuits, and each level-k circuit includes one or more quantum gates applied to 2 ^k of the qubits (q _n ). The 2 ^k qubits for each level-k circuit include the first qubit and the second qubit for that level-k circuit. Each level-1 circuit includes a BS gate applied to two of the qubits (q _n ), where one of the two qubits is the first qubit of the level-1 circuit and the other of the two qubits is This is the second qubit of the level-1 circuit. For k≥2, each level-k circuit includes one of the level-(k-1) circuits as a first sub-circuit and another one of the level-(k-1) circuits as a second sub-circuit. and a gadget circuit including a BS gate. If the value of the second qubit of the first subcircuit is 0, the gadget circuit applies the BS gate to the first qubit of the first subcircuit and the first qubit of the second subcircuit. If the value of the second qubit of the first subcircuit is 1, the gadget circuit applies the conjugate of the BS gate to the first qubit of the first subcircuit and the first qubit of the second subcircuit.

Some embodiments relate to quantum circuits for execution by a quantum computer, where the quantum computer includes at least N qubits (q _n ). The circuit includes a set of N-1 layers and additional layers. A set of N-1 layers sequentially applies N-1 BS gates to N qubits (q _n ). Each BS(θ) gate is a single parameterized two-qubit gate. Each layer applies a BS gate to two qubits, and each subsequent layer applies a BS gate to one of the two qubits in that layer and a new qubit. An additional layer follows a set of N-1 layers and applies an X gate to one of the qubits.

In some embodiments, the new qubit in each subsequent layer is a qubit to which previous layers did not apply a BS gate.

The X gate is applied to a new qubit in the N-1th layer.

In some embodiments, the quantum circuit further includes a second set of N-1 layers after the additional layer. A second set of N-1 layers applies N-1 BS gates to N qubits, each layer applies a BS gate to two qubits, and each subsequent layer applies N-1 BS gates to N qubits, and each subsequent layer applies N-1 BS gates to N qubits. Apply a BS gate to one of the bits and a new qubit. In some embodiments, the second set of N-1 layer BS gates are conjugate gates corresponding to one set of N-1 layer BS gates.

Other aspects include components, devices, systems, improvements, methods, processes, applications, computer-readable storage media, and other technologies related to the above.

Embodiments of the present disclosure, designated Clifford Lauder, have other advantages and features that will become more readily apparent from the following detailed description and claims, when understood in conjunction with the accompanying illustrative drawings.
The Clifford Loader is parameterized by a single vector in N dimensions, so that for each vector x = (x ₁ , x ₂ ,…,x _N ) with Euclidean norm 1, There is a corresponding Clifford loader specified as . 1 shows, according to a first embodiment, a single parameterized two-qubit gate (referred to as “BS”) and a two-qubit controlled This is a diagram showing the quantum circuit used to implement the Clifford loader.
Figure 2 is a diagram showing a quantum circuit for implementing a Clifford loader for a given vector of dimension 8, according to a second embodiment.
Figures 3A and 3B show a 16-dimensional This is a diagram showing the quantum circuit used to implement the Clifford loader for a given vector.
The drawings depict various embodiments for illustrative purposes only. Those skilled in the art will readily recognize from the following discussion that alternative embodiments of the structures and methods illustrated herein may be employed without departing from the principles described herein. This might be done, for example, by changing the details of the BS gate, or by using a different/less optimized method for parity calculations using controlled Z gates.

The drawings and the following description relate to preferred embodiments by way of example only. It should be noted that from the following discussion, alternative embodiments of the structures and methods disclosed herein will be readily recognized as viable alternatives that may be employed without departing from the principles disclosed.

Part 1: Clifford Lauder

Classical vectors are expressed as N-dimensional coordinates (x ₁ , x ₂ ,…, x _N ) , where x _i is a real number and the Euclidean norm of the vector is 1. For clarity of presentation of this particular aspect, we assume that N is a power of 2, but the method can be extended to the general case.

For _the classical vector x ₌ ( x ₁ ,

The Pauli matrices X and Z correspond to the single qubit bit flip operator and phase flip operator, and they are anti-commuting matrices of dimension 2. , where the string represents the tensor product of N Pauli operators, and the X operator is at position i. The unitary operator implemented by Clifford Loader on vector x operates on N qubits and is given by:

(One)

Operator is square to the identity and therefore is unitary for all vectors x with Euclidean norm 1. this is Generators of Clifford's algebra for Since it is a linear combination of , it belongs to Clifford algebra. as a procession silver dimensions There is no a priori reason to expect that this can be implemented as a quantum circuit using a polynomial (input size N) number of 2-qubit gates. This disclosure provides such an implementation for these circuits, and furthermore, the circuit depth for an implementation of the invention is logarithmic of N, making these circuits very efficient.

A type of parameterized two-qubit gate will be used, called BS( θ ) and with the following description on a standard basis:

(2)

By permuting the rows and columns of the above matrix, or by introducing a phase element e^{i*p} instead of the last 1, or by adding two elements sin( θ ) and -sin( θ ), for example, Note that other similar gates derived by changing i*sin( θ ) and i*sin( θ ) can be used. All of these gates are substantially the same, and the method of the present invention can use any one of them. The conjugate of the BS gate is obtained by reversing the angle, i.e. am.

Also in the standard basis controlled Z gates and controlled X gates are used, with the following descriptions:

(3)

Here the second qubit is being used as the control qubit for both gates. It is noted that the application of CX gates can be viewed as a parity calculation. for example, . Parity indicates whether the sum of two numbers (e.g., x ₁ and x ₂ ) is odd or even.

Two matrix identities are introduced that can be verified through direct calculations on the four-dimensional matrices given above. These identities gate strings XI and ZZ. It is used to illustrate the effect of conjugation with and later to establish the accuracy of the compositions of the present invention.

(4)

(5)

For the construction of a Clifford Loader circuit, a gadget (in circuit complexity theory, a subcircuit that performs a specific function) operates on the following three qubits (in ascending order, e.g. 1, 2 and 3 for convenience): terminology used for): If qubit 2 is 0 (e.g., in the standard basis), then this is the applies to qubits 1 and 3, and if qubit 2 is 1 (e.g., in the standard basis), this is the operation Apply instead. This gadget is , for example, three gates in a sequence It can be implemented using , where the CZ gates have qubit 2 as control. The gate operates on qubits 1 and 3. The operation of this gadget described above can be verified by calculating the product of three matrices. In another example, the gadget circuit is It is implemented by treating the gate as three turns in a sequence rather than as a single gate.

In addition to the gadgets, the Clifford loader contains a sequence of angles that are used as input to the BS gate. The angles in this sequence are calculated from the vector x. One sequence of angles for both embodiments is described below. It is noted that the angle sequence for the first embodiment is identical to the sequence described in US Patent Application No. 16/986,553, which is incorporated by reference in its entirety. The angle sequence for the second embodiment is specific to the present disclosure.

Although the angle sequence for the first embodiment is identical to the sequence described in US patent application Ser. No. 16/986,553, it is briefly described herein for completeness. First, the auxiliary series of mid-square amplitudes for vector x is defined. Last N/2 values is defined as follows (index In the case of):

(6)

The first N/2-1 values are defined as follows (where index j starts at N/2 and goes down to 1):

(7)

Last N/2 angles is defined as follows:

, If is positive, and (8)

, If is negative, (9)

1st N/2 angles silver In the case of It is defined as.

The angle sequence for the second embodiment is defined as follows. The first angle is:

(10)

Subsequent angles, for 1 < i < N, are defined as follows,

(11)

A similar method of defining the values of the angles is possible and falls within the same method as the present methods for both embodiments. For example, the signs for angles may be reversed or multiples of π may be added to the angles.

Now we have a random vector Clifford Lauder for Two different quantum circuits can be defined to implement. The first step in construction is the calculation of the angle sequence (as described above). Both of these sequences can be calculated and used as parameters for the Clifford loader circuit. The computational time to determine the angle sequence can be linearly proportional to the dimension of the vector x.

A first embodiment for constructing a Clifford loader is described herein, which is illustrated for an 8-dimensional vector in Figure 1 and for a 16-dimensional vector in Figures 3A and 3B (Figure 3B represents the levels of the circuit). The Clifford Loader circuit according to the first embodiment is the quantum circuit on the left. and its adjoint on the right ( ) sandwiched between (where and contains an X gate on the first qubit, each with logarithmic depth, i.e. am. An iterative explanation using gadgets is provided below. Additionally, it is explicitly shown that the total circuit depth is logarithmic of N. In the case, the gates are is inverted and conjugated compared to (note that CX and CZ are self-conjugate).

Two different quantum circuits and Several notations used to construct are introduced. In this description, quantum circuits run in parallel on separate sets of qubits and About notation is used, a notation to represent the sequential configuration of circuits on the same set of qubits. is used. Note that a circuit is an ordered collection of one or more gates. For example, a circuit may include only a single gate. A subcircuit may refer to a circuit that is part of a larger circuit. Also included are auxiliary circuits that form a Clifford loader with CX gates. Parity of qubits from 2 to N at the end of qubit 2 calculation To include, Define to be C(x) followed by a sequence of CX gates (e.g., the circuit of Figure 1 reference).

An example recursive construction for circuits C(x) of Figure 1 is now provided. As explained above, the Clifford loader can be obtained by applying circuit C(x) and circuit C(x)* with an X gate between them. The dimension of vector x (i.e. N) is assumed to be a power of 2. This assumption can be made without loss of generality since we can pad the vector x with 0, making its dimension a power of 2. 2D unit vector For, by definition, Clifford Lauder has a circuit and where , and therefore, using the identity in equation 4, am. This two-dimensional construction is used as a base case for recursive construction and is used to build Clifford loaders for higher-dimensional vectors. Next, for higher dimensional vectors and A recursive definition is provided. and to the two halves of vector x, i.e. and Assuming an N/2-dimensional vector representing

(12)

(13)

Here G _ijk is a three-qubit gadget, represents controlled X gates with qubit i serving as the control qubit.

The circuit depth for C(x) can be obtained from recursive relationships. Let d(N) be the circuit depth as a function of dimension, then d(2)=1 and from recursion and is saved. When the circuit is implemented using these recursive relations, gadget G _ijk has depth 3 and CX(N/2+2, N/2+1) can be performed in parallel with the third layer of gadget G _ijk . Therefore, the explicit solution for this recurrence is for N powers of 2 greater than 2. am.

The recursion is solved and the 4-dimensional and 8-dimensional vectors An explicit explanation is provided. A four-dimensional C(x) circuit has depth 4*(2-1) = 4. This is the angle with respect to the vector x calculated according to the first embodiment (as described above) as input to the BS gate. Use . Gate level descriptions of the four layers within circuit C(x) are provided.

Layer 1:

Layer 2:

Layer 3:

Layer 4:

An 8-dimensional C(x) circuit has depth 4*(3-1) = 8, as described above. Angles about vector x are calculated according to the first embodiment (as described above) and are the inputs to the BS gates in C(x). Gate level descriptions are provided for all eight layers in the circuit C(x) illustrated in Figure 1:

Layer 1:

Layer 2:

Layer 3:

Layer 4:

Layer 5:

Layer 6:

Layer 7:

Layer 8:

Layers 2 to 4 and Layers 6 to 8 implement gadget G _ijk with some parity calculations performed in parallel in layer 4. Specifically, parity calculations are represented by CX gates, and CZ gates are part of the gadget G _ijk . Note that going through circuit C(x) in Figure 1 from bottom to top, left to right, the calculated angle sequence is used in reverse order.

A second embodiment of the Clifford Loader uses the angle sequence described with reference to Equations 10 and 11. If is an angle sequence, the Clifford loader according to the second embodiment is It can be implemented as:

(14)

Unlike the first embodiment, this is a Clifford Loader for n-dimensional vector x To implement, (n-1) BS gates are used sequentially and have a linear circuit depth. An exemplary circuit Clifford loader circuit according to the second embodiment is shown in FIG. 2 .

Part 2: Applications of Clifford Lauder

We now describe how to use Clifford Loader for applications in quantum machine learning involving determinant sampling. In particular, a method of using Clifford Loader to solve the fundamental problem of sampling according to determinant distributions and its application to representative feature selection is described.

Determinant sampling using classical computers reduces the complexity of calculating the determinant of a single d-dimensional matrix. Since it changes as follows, the calculation cost is high. Theoretically, to calculate a single determinant There are complex theoretical constructs that can achieve , but they only outperform standard methods for very large d due to the large constant argument overhead. Moreover, most classical determinant sampling algorithms require calculating multiple determinants, which leads to higher computational demands. In contrast, the quantum algorithms described in this disclosure have complexity has

The input to the determinant sampling problem is a matrix , which is a matrix containing n row vectors each with dimension d. The output is, The probability of choosing Proportional to the square of the volume of the parallelepiped across my vectors in subset am. More formally,

(15)

ego, is obtained by selecting the rows of A that belong to S. Represents a matrix. It is clear that all probabilities are positive, and the sum of the probabilities for all possible S is 1 by the Cauchy Binet identities.

Since the determinant is maximized when the vectors are orthogonal and is small if any of the vectors is a linear combination of the others, the output of the determinant sampler is a set S containing d 'almost orthogonal' vectors. The row vectors in the output of the determinant sampler are: Therefore, it is guaranteed that there is no linear dependency between them, and if there is a linear dependency, in this case S will not appear in the output of the sampler. The output of the determinant sampler is a set of diverse, representative vectors. This can be useful in machine learning applications where the goal is to sample a set of representative features.

As an example use case, a large dataset of users and features associated with users is considered, where the goal is to select a set of users with representative and diverse features. Determinant sampling selects a diverse group of users to represent a dataset. This is a technique to obtain a concise summary of a large dataset containing all of the various groups of users present within it.

The output of a determinant sampler can also be used for approximation of low rank by row selection and as input to clustering algorithms, which have been found to improve upon standard methods.

The following explains how to perform determinant sampling using a combination of Clifford Loader. From Part 1, Clifford Lauder Recall that is a unitary operator defined for all N-dimensional vectors x. Additionally, with regard to the first embodiment, two qubit gates and An implementation example for a Clifford loader is provided using a circuit depth of .

The determinant sampling algorithm using Clifford Loader is as follows. a matrix Assume that these are the columns of . quantum circuit

(16)

Apply and measure the resulting state on a standard basis. The result of these operations is that the amplitude of a bit string with d 1s and (Nd) 0s is determined by the determinant Quantum superposition of bit strings. Therefore, what we measure from the standard basis is from the determinant distribution. Sample using . The quantum algorithm measures from a standard basis to obtain an N-bit output string. Assuming S is a set of 1s in the output string, if |S|=d, then it outputs S.

The above procedure uses N qubits and sequentially continues applying d Clifford Loader circuits, using the first embodiment of Part 1 to obtain the circuit depth. has The procedure succeeds with probability 1 if the columns of matrix A are orthogonal. More generally, the probability of success is am.

If the procedure described above with reference to Equation 16 is successful, the output S is a sample according to the determinant distribution. That is, the procedure is accurate and time-sensitive to the determinant sampling problem. Solve it accurately within

The success probability of a determinant sampler is first multiplied by matrix A by a random sign matrix or Hadamard matrix, This can be improved by running a determinant sampler on . Using state-of-the-art procedures for multiplication by Hadamard matrices, this preprocessing can be performed linearly in time on the number of non-zero entries of A.

If A is an orthogonal matrix, running time A quantum determinant sampling algorithm with running time It provides a speedup compared to the most well-known classical algorithm with .

More generally, a sequence of Clifford Loader operations silver vectors Provides a representation of a k-dimensional subspace expanded by . Also, if the vectors are orthogonal, the probability of success in obtaining this representation is higher. This makes the Clifford Loader useful for finding projections of low-dimensional subspaces onto linear subspaces.

Clifford Lauder also said, can be useful in quantum topological data analysis where can be used to generate block encodings for the Dirac operators of simple complexes.

Although Part 2 is described with reference to Clifford Rodder's first embodiment, Clifford Roder's second embodiment may alternatively be used. In this case, the execution time will be .

Additional Considerations

Quantum processing devices (also called quantum computers) utilize the laws of quantum mechanics to perform calculations. Quantum processing devices generally use so-called qubits or quantum bits. Classical bits always have a value of 0 or 1, while qubits have values of 0, 1, or a superposition of both. It is a quantum mechanical system that can have the value of , where and am. Exemplary physical implementations of qubits include superconducting qubits, ion traps, and photonics systems (eg, photonics in a waveguide).

A quantum circuit is an ordered collection of one or more gates. A subcircuit may refer to a circuit that is part of a larger circuit. A gate represents a unitary operation performed on one or more qubits. Quantum computers can use a universal set of one- and two-qubit gates, broadly meaning that arbitrary quantum circuits can be written as combinations of these gates. Quantum gates can be described using unitary matrices. The depth of a quantum circuit is the minimum number of steps required to run the circuit on a quantum computer. A layer in a quantum circuit can refer to one level of the circuit.

Instructions for executing a quantum circuit on one or more quantum computers may be stored in a non-transitory computer-readable storage medium. The term “computer-readable storage medium” should be considered to include a single medium or multiple media (eg, centralized or distributed databases, associated caches and servers) capable of storing instructions. The term “computer-readable medium” should also be considered to include any medium capable of storing instructions for execution by a quantum computer and causing a quantum computer to perform one or more of the methods disclosed herein. The term “computer-readable media” includes, but is not limited to, data storage in the form of solid-state memory, optical media, and magnetic media.

The above-described approach can be applied to cloud quantum computing systems where quantum computing is provided as a shared service to separate users. One example is described in patent application Ser. No. 15/446,973, entitled “Quantum Computing as a Service,” which is incorporated herein by reference.

Some portions of the above description describe embodiments in terms of algorithmic processes or operations. These algorithmic descriptions and representations are commonly used by people skilled in the computing arts to effectively convey the content of their work to others skilled in the art. These operations are described functionally, computationally, or logically, but are understood to be implemented by a computer program containing instructions for execution by a processor, an equivalent electric circuit, microcode, etc. Moreover, without loss of generality, it has sometimes proven convenient to refer to these arrangements of functional tasks as modules.

As used herein, any reference to “one embodiment” or “one embodiment” means that a particular element, feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment. means that The phrases “in one embodiment” appearing in various places in the specification are not necessarily all referring to the same embodiment. Likewise, using “one” or “one” in front of an element or component is done for convenience only. Unless it is clear that otherwise is meant, the description should be understood to mean that one or more elements or components are present.

When values are described as “approximately” or “substantially” (or derivatives thereof), such values should be construed to an accuracy of +/- 10%, unless a different meaning is clear from the context. For example, “approximately 10” should be understood to mean “in the range from 9 to 11.”

As used herein, the terms “comprise,” “including,” “have,” “having,” “comprising,” “equipped with,” or any other variations thereof are intended to encompass non-exclusive inclusions. do. For example, a process, method, article or device containing a list of elements is not necessarily limited to only those elements and may include other elements not explicitly listed or inherent in such process, method, article or device. can do. Additionally, unless explicitly stated otherwise, “or” means ‘inclusive or’ rather than ‘exclusive or’. For example, condition A or B is satisfied by either: A is true (or exists) and B is false (or does not exist), A is false (or does not exist) and B is true ( or exists), and both A and B are true (or exist).

Various other modifications, changes and variations, which will be apparent to those skilled in the art, may be made in the arrangement, operation and details of the methods and devices disclosed herein without departing from the spirit and scope as defined in the appended claims. Therefore, the scope of the present invention should be determined by the appended claims and their legal equivalents.

Alternative embodiments are implemented in computer hardware, firmware, software, and/or combinations thereof. Implementations may be implemented as a computer program product tangibly embodied in a machine-readable storage device for execution by a programmable processor, wherein the method steps include the programmable processor executing a program of instructions to operate on input data and output This can be done by creating and executing the function. Embodiments advantageously include at least one programmable processor coupled to receive data and instructions from, and transmit data and instructions to, a data storage system, at least one input device, and at least one output device. It may be implemented as one or more computer programs executable on a programmable system. Each computer program may be implemented in a high-level procedural or object-oriented programming language, or, if desired, in assembly or machine language, in either case the language may be a compiled or interpreted language. . Suitable processors include, for example, both general-purpose microprocessors and special-purpose microprocessors. Typically, a processor will receive instructions and data from read-only memory and/or random access memory. Typically, a computer includes one or more mass storage devices for storing data files, including magnetic disks such as internal hard disks and removable disks; magneto-optical disk; and optical disks. Storage devices suitable for tangibly implementing computer program instructions and data include semiconductor memory devices such as EPROM, EEPROM, flash memory devices, etc.; Magnetic disks such as built-in hard disks and removable disks; magneto-optical disk; and all forms of non-volatile memory, including CD-ROM disks. The foregoing may be supplemented or integrated with application-specified integrated circuits (ASICs) and other types of hardware.

Claims (40)

1. A non-transitory computer-readable storage medium containing stored instructions for executing a quantum circuit by a quantum computer, the quantum computer comprising at least N qubits (q _n ), the stored instructions comprising: When executed by a quantum computer, it causes the quantum computer to perform operations, the operations comprising:
executing a first sub-circuit comprising quantum gates applied to N/2 qubits (q ₁ -q _N/2 ) - after execution of the first sub-circuit, the value of the qubits (q ₂ ) represents the parity of qubits (q ₂ -q _N/2 ) -;
executing a second sub-circuit simultaneously with the first sub-circuit, wherein the second sub-circuit includes quantum gates applied to N/2 qubits (q _(N/2+1) -q _N ); ; and
Executing a gadget circuit after the first sub-circuit and the second sub-circuit, wherein the gadget circuit is applied to qubits (q ₁ , q ₂ , and q _(N/2+1)) comprising quantum gates, wherein one of the quantum gates of the gadget circuit is a BS(θ) gate, and the BS(θ) gate is a single parameterized two-qubit quantum gate,
If the value of the qubit (q ₂ ) is 0, the BS(θ) gate is applied to the qubits (q ₁ and q _(N/2+1) ),
If the value of the qubit (q ₂ ) is 1, then the conjugate of the BS(θ) gate is applied to the qubits (q ₁ and q _(N/2+1)). media. 2. The method of claim 1, wherein executing the first sub-circuit comprises:
executing a third sub-circuit comprising quantum gates applied to N/4 qubits (q ₁ -q _N/4 ) - after execution of the third sub-circuit, the value of the qubit (q ₂ ) represents the parity of qubits (q ₂ -q _N/4 ) -;
executing a fourth sub-circuit simultaneously with the third sub-circuit and including quantum gates applied to N/4 qubits (q _(N/4+1) -q _N/2 ); and
executing a second gadget circuit after the third sub-circuit and the fourth sub-circuit, wherein the second gadget circuit applies to qubits (q ₁ , q ₂ , and q _(N/4+1)) wherein one of the quantum gates of the second gadget circuit is a second BS(θ) gate,
If the value of the qubit (q ₂ ) is 0, the second BS(θ) gate is applied to the qubits (q ₁ and q _(N/4+1) ),
If the value of the qubit (q ₂ ) is 1, then the conjugate of the second BS(θ) gate is applied to the qubits (q ₁ and q _(N/4+1)). . 2. The non-transitory computer-readable storage medium of claim 1, wherein the operations further comprise executing an X gate applied to a qubit (q ₁ ) after the gadget circuit. The method of claim 3, wherein the operations are:
Further _comprising executing _a second gadget circuit after _the wherein one of the quantum gates of the second gadget circuit is a second BS(θ) gate,
If the value of the qubit (q ₂ ) is 0, the conjugate of the BS(θ) gate is applied to the qubits (q ₁ and q _(N/2+1) ),
If the value of qubit (q ₂ ) is 1, then the BS(θ) gate is applied to qubits (q ₁ and q _(N/2+1)) . The method of claim 4, wherein the operations are:
further comprising executing a third sub-circuit after the second gadget circuit, wherein the third sub-circuit includes quantum gates applied to N/2 qubits (q ₁ -q _N/2 ), The quantum gates of the third sub-circuit are identical to the quantum gates of the first sub-circuit except that the quantum gates of the third sub-circuit are arranged in reverse order and the BS(θ) gate is conjugated. A non-transitory computer-readable storage medium that The method of claim 5, wherein the operations are:
Further comprising executing a fourth sub-circuit simultaneously with the third sub-circuit, wherein the fourth sub-circuit is a quantum gate applied to N/2 qubits (q _(N/2+1) -q _N ). wherein the quantum gates of the fourth sub-circuit are the quantum gates of the second sub-circuit except that the quantum gates of the fourth sub-circuit are arranged in reverse order and the BS(θ) gates are conjugated. A non-transitory computer-readable storage medium consistent with gates. 2. The method of claim 1, wherein executing the first sub-circuit comprises:
Executing a first layer applying a second BS(θ) gate to the qubits (q ₁ and q ₂ ) and a third BS(θ) gate to the qubits (q ₃ and q ₄ ) steps;
executing a second layer applying a first CZ gate to the qubits (q ₁ and q ₂ ), where the CZ gate is a controlled Z gate;
executing a third layer applying a fourth BS(θ) gate to qubits (q ₁ and q ₃ );
Executing a fourth layer applying a second CZ gate to qubits (q ₁ and q ₂ ) and a first CX gate to qubits (q ₃ and q ₄ ), wherein the CX gate is controlled X gate -; and
A non-transitory computer-readable storage medium comprising executing a fifth layer applying a second CX gate to qubits (q ₂ and q ₃ ). The method of claim 1, wherein executing the gadget sub-circuit comprises:
executing the first layer applying a first CZ gate to the qubits (q ₁ and q ₂ ), where the CZ gate is a controlled Z gate;
executing a second layer applying the BS(θ) gate to qubits (q ₁ and q _(N/2+1) ); and
A non-transitory computer-readable storage medium comprising executing a third layer applying a second CZ gate to qubits (q ₁ and q ₂ ). 2. The non-transitory computer-readable storage medium of claim 1, wherein the conjugate of the BS(θ) gate is BS(-θ). 2. The method of claim 1, wherein the BS(θ) gate has the form:
BS(θ) = [[1, 0, 0, 0], [0, cos(θ), sin(θ), 0], [0, -sin(θ), cos(θ), 0], [ 0, 0, 0, 1]]. A method for executing a quantum circuit by a quantum computer comprising at least N qubits (q _n ), comprising:
executing, by the quantum computer, a first sub-circuit comprising quantum gates applied to N/2 qubits (q ₁ -q _N/2 ) - after execution of the first sub-circuit, a queue The value of the bit (q ₂ ) represents the parity of the qubits (q ₂ -q _N/2 ) -;
Executing, by the quantum computer, a second sub-circuit simultaneously with the first sub-circuit, wherein the second sub-circuit is applied to N/2 qubits (q _(N/2+1) -q _N ). Contains quantum gates that are -; and
executing, by the quantum computer, a gadget circuit after the first sub-circuit and the second sub-circuit, wherein the gadget circuit includes qubits (q ₁ , q ₂ , and q _(N/2+1) ), wherein one of the quantum gates of the gadget circuit is a BS(θ) gate, and the BS(θ) gate is a single parameterized two-qubit quantum gate. ,
If the value of the qubit (q ₂ ) is 0, then the BS(θ) gate is applied to the qubits (q ₁ and q _(N/2+1) ), and the BS(θ) gate is a single parameterized 2 -Qubit gate,
If the value of the qubit (q ₂ ) is 1, then the conjugate of the BS(θ) gate is applied to the qubits (q ₁ and q _(N/2+1) ). 12. The method of claim 11, wherein executing the first sub-circuit comprises:
executing a third sub-circuit comprising quantum gates applied to N/4 qubits (q ₁ -q _N/4 ) - after execution of the third sub-circuit, the value of the qubit (q ₂ ) represents the parity of qubits (q ₂ -q _N/4 ) -;
executing a fourth sub-circuit simultaneously with the third sub-circuit and including quantum gates applied to N/4 qubits (q _(N/4+1) -q _N/2 ); and
executing a second gadget circuit after the third sub-circuit and the fourth sub-circuit, wherein the second gadget circuit applies to qubits (q ₁ , q ₂ , and q _(N/4+1)) wherein one of the quantum gates of the second gadget circuit is a second BS(θ) gate,
If the value of the qubit (q ₂ ) is 0, the second BS(θ) gate is applied to the qubits (q ₁ and q _(N/4+1) ),
If the value of the qubit (q ₂ ) is 1, then the conjugate of the second BS(θ) gate is applied to the qubits (q ₁ and q _(N/4+1)) . 12. The method of claim 11, further comprising executing an X gate applied to a qubit (q ₁ ) after the gadget circuit. The method of claim 13, wherein the method
Further _comprising executing _a second gadget circuit after _the wherein one of the quantum gates of the second gadget circuit is a second BS(θ) gate,
If the value of the qubit (q ₂ ) is 0, the conjugate of the BS(θ) gate is applied to the qubits (q ₁ and q _(N/2+1) ),
If the value of qubit (q ₂ ) is 1, then the BS(θ) gate is applied to qubits (q ₁ and q _(N/2+1) ). The method of claim 14, wherein the method
further comprising executing a third sub-circuit after the second gadget circuit, wherein the third sub-circuit includes quantum gates applied to N/2 qubits (q ₁ -q _N/2 ), The quantum gates of the third sub-circuit are identical to the quantum gates of the first sub-circuit except that the quantum gates of the third sub-circuit are arranged in reverse order and the BS(θ) gate is conjugated. How to. The method of claim 15, wherein the method
Further comprising executing a fourth sub-circuit simultaneously with the third sub-circuit, wherein the fourth sub-circuit is a quantum gate applied to N/2 qubits (q _(N/2+1) -q _N ). wherein the quantum gates of the fourth sub-circuit are the quantum gates of the second sub-circuit except that the quantum gates of the fourth sub-circuit are arranged in reverse order and the BS(θ) gates are conjugated. Method, which matches the gates. 12. The method of claim 11, wherein executing the first sub-circuit comprises:
Executing a first layer applying a second BS(θ) gate to the qubits (q ₁ and q ₂ ) and a third BS(θ) gate to the qubits (q ₃ and q ₄ ) steps;
executing a second layer applying a first CZ gate to the qubits (q ₁ and q ₂ ), where the CZ gate is a controlled Z gate;
executing a third layer applying a fourth BS(θ) gate to qubits (q ₁ and q ₃ );
Executing a fourth layer applying a second CZ gate to qubits (q ₁ and q ₂ ) and a first CX gate to qubits (q ₃ and q ₄ ), wherein the CX gate is controlled X gate -; and
A method comprising executing a fifth layer applying a second CX gate to qubits (q ₂ and q ₃ ). 12. The method of claim 11, wherein executing the gadget sub-circuit comprises:
executing the first layer applying a first CZ gate to the qubits (q ₁ and q ₂ ), where the CZ gate is a controlled Z gate;
executing a second layer applying the BS(θ) gate to qubits (q ₁ and q _(N/2+1) ); and
A method comprising executing a third layer applying a second CZ gate to qubits (q ₁ and q ₂ ). 12. The method of claim 11, wherein the conjugate of the BS(θ) gate is BS(-θ). A quantum circuit for execution by a quantum computer, comprising:
N qubits (q _n ) - where N=2 ^K and K≥2 -; and
Contains K recursive circuit levels, where k=1 to K,
Each circuit level k includes (N/2 ^k ) level-k circuits, and each level-k circuit includes one or more quantum gates applied to 2 ^k of the qubits (q _n ), , the 2 ^k qubits for each level-k circuit include the first qubit and the second qubit for that level-k circuit,
Each level-1 circuit includes a BS gate applied to two of the qubits (q _n ), where one of the two qubits is the first qubit of the level-1 circuit and the two cubits Another one of the bits is the second qubit of the level-1 circuit,
For k≥2, each level-k circuit is:
comprising one of said level-(k-1) circuits as a first sub-circuit and another one of said level-(k-1) circuits as a second sub-circuit;
A gadget circuit including a BS gate,
If the value of the second qubit of the first subcircuit is 0, the BS gate is applied to the first qubit of the first subcircuit and the first qubit of the second subcircuit,
If the value of the second qubit of the first subcircuit is 1, then the conjugate of the BS gate is applied to the first qubit of the first subcircuit and the first qubit of the second subcircuit, Quantum circuit. 1. A non-transitory computer-readable storage medium containing stored instructions for executing a quantum circuit by a quantum computer, the quantum computer comprising at least N qubits, the stored instructions, when executed by the quantum computer, causing the quantum computer to perform operations, the operations comprising:
Executing a set of N-1 layers applying N-1 BS gates to N qubits - each BS gate is a single parameterized 2-qubit gate, and each layer is a BS gate to two qubits and each subsequent layer applies a BS gate to one of said two qubits and a new qubit in that layer -; and
executing an additional layer after the set of N-1 layers, wherein the layer applies an X gate to one of the qubits. 22. The non-transitory computer-readable storage medium of claim 21, wherein the new qubit of each subsequent layer is a qubit to which the previous layers did not apply a BS gate. 22. The non-transitory computer-readable storage medium of claim 21, wherein the X gate is applied to a new qubit in the N-1th layer. 22. The method of claim 21, wherein the operations are:
executing a second set of N-1 layers after the additional layer, wherein the second set of N-1 layers apply N-1 BS gates to the N qubits, A non-transitory computer-readable storage medium, wherein each layer applies a BS gate to two qubits and each subsequent layer applies a BS gate to one of the two qubits in that layer and a new qubit. 25. The non-transitory computer-readable storage medium of claim 24, wherein the BS gates of the second set of N-1 layers are conjugate gates corresponding to the BS gates of the one set of N-1 layers. 22. The non-transitory computer-readable storage medium of claim 21, wherein N is a power of 2. 22. The method of claim 21, wherein each BS gate has the form:
BS(θ) = [[1, 0, 0, 0], [0, cos(θ), sin(θ), 0], [0, -sin(θ), cos(θ), 0], [ 0, 0, 0, 1]]. A method for executing a quantum circuit by a quantum computer comprising at least N qubits, comprising:
Executing a set of N-1 layers applying N-1 BS gates to N qubits - each BS gate is a single parameterized 2-qubit gate, and each layer is a BS gate to two qubits and each subsequent layer applies a BS gate to one of said two qubits and a new qubit in that layer -; and
Executing an additional layer after the set of N-1 layers, wherein the layer applies an X gate to one of the qubits. 29. The method of claim 28, wherein the new qubit of each subsequent layer is a qubit to which the previous layers did not apply a BS gate. 29. The method of claim 28, wherein the X gate is applied to a new qubit in the N-1th layer. The method of claim 28, wherein the method
executing a second set of N-1 layers after the additional layer, wherein the second set of N-1 layers apply N-1 BS gates to the N qubits, Each layer applies a BS gate to two qubits and each subsequent layer applies a BS gate to one of the two qubits of that layer and a new qubit. 32. The method of claim 31, wherein the BS gates of the second set of N-1 layers are conjugate gates corresponding to the BS gates of the one set of N-1 layers. 29. The method of claim 28, wherein N is a power of 2. 29. The method of claim 28, wherein each BS gate has the form:
BS(θ) = [[1, 0, 0, 0], [0, cos(θ), sin(θ), 0], [0, -sin(θ), cos(θ), 0], [ 0, 0, 0, 1]], method. A quantum circuit for execution by a quantum computer comprising at least N qubits, comprising:
A set of N-1 layers applying N-1 BS gates to N qubits (q _n ) - each BS gate is a single parameterized 2-qubit gate, and each layer is a BS gate to two qubits and each subsequent layer applies a BS gate to one of the two qubits and a new qubit -; and
A quantum circuit, comprising an additional layer after the set of N-1 layers, wherein the layer applies an X gate to one of the qubits. 36. The quantum circuit of claim 35, wherein the new qubit of each subsequent layer is a qubit to which the previous layers did not apply a BS gate. 36. The quantum circuit of claim 35, wherein the X gate is applied to a new qubit in the N-1th layer. 36. The method of claim 35, wherein the quantum circuit is
After the additional layer, it further includes a second set of N-1 layers, wherein the N-1 layers of the second set apply N-1 BS gates to the N qubits, and each layer has A quantum circuit that applies a BS gate to two qubits and each subsequent layer applies a BS gate to one of the two qubits and a new qubit. 39. The quantum circuit of claim 38, wherein the BS gates of the second set of N-1 layers are conjugate gates corresponding to the BS gates of the one set of N-1 layers. 36. The quantum circuit of claim 35, wherein N is a power of 2.

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