KR20230173059A - Smart memory module and operating method thereof - Google Patents

Abstract

A smart memory module according to the present invention includes at least one volatile memory device, a plurality of non-volatile memory devices connected in a mesh structure, and a plurality of devices that perform data transfer between the plurality of non-volatile memory devices in the at least one volatile memory device. child controllers, and a mother controller that communicates with an external device through a CXL (Compute Express Link) interface and controls the at least one volatile memory device and the plurality of child controllers, each of the plurality of child controllers Characterized in that a read operation or a write operation is performed by transmitting a command and a DMA (Direct Memory Access) instruction to at least one non-volatile memory device allocated to an activation die among the plurality of non-volatile memory devices.

Description

Smart memory module and operating method thereof {SMART MEMORY MODULE AND OPERATING METHOD THEREOF}

The present invention relates to a smart memory module and a method of operating the same.

In general, Compute Express Link (CXL) is an interface and protocol for sharing and communicating data between processors and accelerators in high-performance computer systems. CXL has the following important features, allowing it to connect and use memory and other storage devices: CXL supports cache coherence to maintain data consistency between processors and accelerators. This prevents problems that occur when data is accessed or modified on multiple devices simultaneously and ensures data integrity. CXL has high bandwidth and can transmit data very quickly. It is suitable for high-performance applications such as big data analysis, machine learning, graphics processing, etc. in data centers and high-performance computing environments. CXL allows you to expand your system's memory. This allows large amounts of memory to be used to process larger data sets or support memory-intensive applications. CXL is designed to be standards-based, allowing a variety of hardware manufacturers to implement and support the technology. This standardization improves compatibility and portability and provides interoperability between various systems. CXL can be used in a variety of applications. For example, it can be used to connect graphics cards, field programmable gate arrays (FPGAs), artificial intelligence (AI) accelerators, and other accelerators to enable high-performance computing, or to support virtualized and containerized applications in data centers.

The purpose of the present invention is to provide a novel smart memory module and a method of operating the same.

A smart memory module according to an embodiment of the present invention includes: at least one volatile memory device; A plurality of non-volatile memory devices connected in a mesh structure; a plurality of child controllers that perform data transfer from the at least one volatile memory device to the plurality of non-volatile memory devices; and a mother controller that communicates with an external device through a CXL (Compute Express Link) interface and controls the at least one volatile memory device and the plurality of child controllers, wherein each of the plurality of child controllers is configured to control the plurality of child controllers. It is characterized in that a read operation or a write operation is performed by transmitting a command and a DMA (Direct Memory Access) instruction to at least one non-volatile memory device allocated to an activation die among volatile memory devices.

A method of operating a smart memory module includes at least one volatile memory device, a plurality of non-volatile memory devices connected in a mesh structure, and storing data of the at least one volatile memory device into the plurality of non-volatile memory devices. A plurality of child controllers that transmit data, and a mother controller that controls the at least one volatile memory device and the plurality of child controllers, wherein the method includes: When transmitting data to a plurality of non-volatile memory devices, managing activation and deactivation of each of the plurality of non-volatile memory devices; and controlling, by the mother controller, a Direct Memory Access (DMA) operation for at least one non-volatile memory device among the plurality of non-volatile memory devices.

The smart memory module and its operating method according to an embodiment of the present invention can overcome differences in data transmission bandwidth between heterogeneous devices by performing data distribution/collection and DMA control on non-volatile memory devices connected in a mesh structure.

The smart memory module and its operating method according to an embodiment of the present invention can simultaneously perform read and write operations on non-volatile memory devices through a plurality of child controllers.

The smart memory module and its operating method according to an embodiment of the present invention enable data access to a specific non-volatile memory die even if the input/output bus is occupied by data transfer between the storage controller and the non-volatile memory dies.

The drawings attached below are intended to aid understanding of the present embodiment and provide examples along with a detailed description.
FIG. 1 is a diagram illustrating a conventional smart memory module 100.
Figure 2 is a diagram illustrating a smart memory module according to an embodiment of the present invention.
Figure 3 is a flowchart exemplarily showing the operation of a smart memory module according to an embodiment of the present invention.
Figure 4 is a diagram visually showing a smart memory module 300 according to another embodiment of the present invention.
Figure 5 is a block diagram showing a computing system according to an embodiment of the present invention.
Figure 6 is a block diagram showing a computing system according to an embodiment of the present invention.
Figure 7 is a block diagram showing a computing system according to an embodiment of the present invention.
Figure 8 is a block diagram showing a data center to which a computing system according to the present invention is applied.

Below, using the drawings, the content of the present invention will be described clearly and in detail so that a person skilled in the art can easily implement it.

The smart memory module (or CXL (Compute Express Link) storage device) and its operating method according to an embodiment of the present invention use Distributed & Aggregation DMA for accessing Byte Addressable data rather than the Block Storage concept during read/write operations. (Direct Memory Access) technology can be implemented to overcome the difference in bandwidth between storage and memory. In particular, the CXL storage device of the present invention can overcome bandwidth limitations due to the controller's PCIe (Peripheral Component Interconnect Express) generation and number of lanes.

A smart memory module and its operating method according to an embodiment of the present invention, Byte-Addressable DMA split & aggregation is implemented in hardware/software considering memory expansion applications, and the characteristics and disadvantages of non-volatile memory devices that are insufficient for memory applications can be reinforced.

FIG. 1 is a diagram illustrating a conventional smart memory module 100. Referring to FIG. 1, the smart memory module 100 includes at least one volatile memory device 110 (DRAM), at least one non-volatile memory device 120 (NAND), a main controller 130 (Main CTRL), and a storage controller. Includes (140, SSD CTRL).

At least one volatile memory device 110 may be implemented with at least one dynamic random access memory (DRAM). At least one non-volatile memory device 120 (NAND) may be implemented with a plurality of NAND flash memories. The main controller 130 performs CXL I/F to NVMe interface conversion, memory command (Load/Store) conversion, and DRAM Management. The storage controller 140 performs functions such as reading/writing, error handling, and power loss for at least one non-volatile memory device 120.

In the case of DRAM mounted on general storage devices, it is used for the operation of the storage device, such as L2P (Logical to Physical) Map and Data Buffer. The smart memory module 100 with the CXL interface goes beyond the existing DRAM function and role and also performs the CXL memory Load/Store function for data transmission and reception with the host. However, as shown in FIG. 1, the smart memory module 100 to which the CXL interface is applied has a difference in bandwidth between the volatile memory device 110 (DRAM) and the internal storage controller 140 (SSD CTRL).

For example, when DRAM and NAND, which are heterogeneous media devices, are used simultaneously to transmit and receive data inside the smart memory module 100, there is a difference in data transfer bandwidth between the two media devices. This causes limitations in the bandwidth of the CXL interface connected to the applied DRAM and host device. For example, when CXL I/F = PCIe Gen5x8, NAND CTRL = PCIe Gen5 x 4L, the DRAM bandwidth is 25.6GB/s and the SSD bandwidth is 16GB/s (32Gbps x 4). To solve this problem, there is a patented technology to improve performance with the concept of a master controller and multiple flash memory modules, but due to the structure in which NAND Dies are bound to a specific flash controller, there are restrictions on the use of NAND Dies and management of NAND Dies. A large number of flash controllers must be installed for this purpose.

A smart memory module to which a CXL interface is applied according to an embodiment of the present invention uses a mother controller and a plurality of child controllers between a volatile memory device (e.g., DRAM) and a device controller (e.g., SSD-CTRL). The existing bandwidth gap can be overcome. The smart memory module of the present invention can simultaneously read/write to a plurality of non-volatile memory dies (NAND Dies) through a plurality of child controllers. In addition, the smart memory module of the present invention cannot be used even in situations where the input/output bus (IO bus) of the storage controller (SSD CTRL) is occupied by data transfer with the storage controller (SSD CTRL) and specific non-volatile memory dies (NAND Dies). It enables access and data transfer to non-volatile memory dies.

Figure 2 is a diagram illustrating a smart memory module 200 according to an embodiment of the present invention. Referring to FIG. 2, the smart memory module 200 includes at least one volatile memory device 210, a plurality of non-volatile memory devices 220 connected in a mesh structure 201, and a plurality of child controllers 231 and 232. , 233, ..., 23M), a mother controller 240, and a non-volatile memory die management and DMA controller 250.

At least one volatile memory device 210 may be implemented with static random access memory (SRAM), dynamic RAM (DRAM), synchronous RAM (SDRAM), etc.

Each of the plurality of non-volatile memory devices 220 includes NAND flash memory, Noah flash memory, PRAM (Phase-change RAM), MRAM (Magneto-resistive RAM), ReRAM (Resistive RAM), and FRAM (Ferro-electric RAM). It can be implemented as follows.

Each of the child controllers 231 to 23M may be connected to a plurality of non-volatile memory dies in a mesh structure 201. Each of the child controllers 231 to 23M will be implemented to perform I/F switching for data transfer to DRAM to NAND, commands to non-volatile memory devices 220, and read/write operations through DMA instruction transfer. You can.

Mother controller 240 may be implemented to manage data transfer between a volatile memory device (e.g., DRAM) and a non-volatile memory device (e.g., NAND). In particular, the mother controller 240 controls Active & In- You can monitor the status of active Dies.

In addition, the mother controller 240 allocates Active Dies to enable a write operation of data striping (Sequential Address) operation through a plurality of child-controllers 231 to 23M.

In general, data striping refers to a technology that stores data by distributing it across multiple physical storage devices. This technology is mainly used to quickly read and write large amounts of data or to improve data availability and durability. It is mainly associated with RAID (Redundant Array of Independent Disks), but can also be used in file systems or databases. Divide large amounts of data into blocks or stripes of a certain size. Each stripe is stored on a storage device. These stripes are distributed and stored across different physical storage devices. At this time, fast data read and write speeds are guaranteed by evenly distributing data across several available disks or drives. Striping improves data access performance by allowing data to be read and written to multiple storage devices simultaneously. Data striping is primarily used in RAID level 0.

In addition, when small chunk, Quality of Service (QoS) critical data management is required, the mother controller 240 performs a read operation through direct access to specific non-volatile memory dies without child-controllers 231 to 23M. Or, you can perform a write operation.

The non-volatile memory die management and DMA controller 250 can be implemented to perform Active & In-Active monitoring and DMA roles of each non-volatile memory device in consideration of the efficiency (Cost, Power, Size, etc.) of controller chip development. there is. Meanwhile, the non-volatile memory die management and DMA controller 250 can be implemented in the mother controller 240 in hardware/software/firmware.

The smart memory module 200 according to an embodiment of the present invention can simultaneously perform a read operation and a write operation with a plurality of non-volatile memory devices 220 through a plurality of child controllers 231 to 23M. In addition, the smart memory module 200 of the present invention can access and transmit data to an unused non-volatile memory device even in a situation where the input/output bus is occupied by the storage controller and data transmission of a specific non-volatile memory device.

Figure 3 is a flowchart illustrating the operation of the smart memory module 200 according to an embodiment of the present invention. Referring to Figures 2 and 3, the smart memory module 200 may operate as follows. The non-volatile memory die management and DMA controller 250 of the smart memory module 200 may manage activation and deactivation of each of the non-volatile memory devices 220 (S110). The non-volatile memory die management and DMA controller 250 may control NAND DMA operations according to the control of the mother controller 240 (S120). In an embodiment, at least one of the plurality of child controllers may perform a write operation while at least one other child controller may perform a read operation.

Meanwhile, the non-volatile memory devices 220 described in FIGS. 2 and 3 are connected in a mesh structure, but the present invention is not limited thereto. The non-volatile memory devices of the present invention may be implemented in a structure connected to each of the child controllers.

Figure 4 is a diagram illustrating a smart memory module 300 according to another embodiment of the present invention. Referring to FIG. 4, the smart memory module 300 includes at least one volatile memory device 310, a plurality of non-volatile memory devices 320, and a plurality of child controllers 331, 332, 333, ..., 33N. , a mother controller 340, and a data distribution and collection engine 350. The smart memory module 300 may be implemented in a shared structure between a plurality of child controllers 331 to 33N and at least one volatile memory device 310. The smart memory module 300 applies a plurality of child controllers 331 to 33N in a single device in the volatile memory device 310.

Each of the child controllers 331 to 33N may be implemented to control a plurality of non-volatile memory devices 320 .

The mother controller 340 may be implemented to overall manage the smart memory module 300. The mother controller 340 may be implemented to control at least one volatile memory device 310 and a plurality of child controllers 331 to 33N.

The data distribution and collection engine 350 may be implemented to perform Byte Addressable Data Distribution & Aggregation. The data distribution and collection engine 350 may perform data split operations and data placement operations. The data split operation can be performed during a DMA operation by splitting or merging data into multiple child-controllers during a data load/store operation between DRAM and multiple child controllers. These functions may be performed in the mother controller 340. In the data placement operation, the data in each DRAM is written in the form of sequential data striping to multiple child controllers during the memory store operation, and the data transmitted from each child controller can be aggregated into one during the memory load operation. This can improve read and write bandwidth.

The smart memory module 300 of the present invention can be implemented in the form of mother-child controllers to support data striping and aggregation, and a master-slave structure between the mother-child controllers.

The smart memory module 300 of the present invention places a Data Split and Data Placement Engine in the form of H/W or S/W between the volatile memory device 310 (DRAM) and the child controllers 331 to 33N, and Can be managed by the mother controller 340.

In typical CXL interface-based storage devices, there is a bandwidth difference between DRAM (volatile memory) and the internal SSD CTRL (storage controller). The smart memory module of the present invention can realize the maximum performance of DRAM by overcoming the insufficient bandwidth of the SSD CTRL stage. System performance and latency can be improved by efficiently using non-volatile memory in byte-level read/write at the 32/64/128 byte level through byte addressable DMA split & aggregation.

Figure 5 is a block diagram showing a computing system according to an embodiment of the present invention. Referring to FIG. 5 , the computing system 10 may include a host 11, a plurality of memory devices 12a and 12b, and a storage device 13. The host 11 can control overall operations of the computing system 10. The plurality of memory devices 12a and 12b may be used as operating memory or system memory of the host 11.

Storage device 13 may include a storage controller 13a, buffer memory 13b, and non-volatile memory 13c. The storage controller 13a may store data in the non-volatile memory 13c or transmit data stored in the non-volatile memory 13c to the host 11 under the control of the host 11.

The buffer memory 13b can store various information necessary for the storage device 13 to operate. For example, storage controller 13a may use map data to manage data stored in non-volatile memory 13c. The map data may include information about the relationship between the logical block address managed by the host 11 and the physical block address of the non-volatile memory 13c. The storage controller 13a can load and use map data into the buffer memory 13b.

In an embodiment, the buffer memory 13b may be a high-speed memory such as DRAM. As the capacity of the non-volatile memory 13c increases, the size of required map data may increase. However, since the capacity of the buffer memory 13b included in the single storage device 13 is limited, there is a problem in that it cannot cope with an increase in the size of map data due to an increase in the capacity of the non-volatile memory 13c.

Figure 6 is a block diagram showing a computing system according to an embodiment of the present invention. Referring to FIG. 6, the computing system 400 includes a host 401, a plurality of memory devices 402a and 402b, a CXL switch (SW_CXL), a plurality of CXL storage devices 410_1 to 410_m, and a plurality of CXLs. It may include memories 420_1 to 420_n.

The host 401 may be directly connected to a plurality of memory devices 402a and 402b. The host 401, the plurality of CXL storage devices 410_1 to 410_m, and the plurality of CXL memories 420_1 to 420_n may be connected to the CXL switch (SW_CXL), and each communicates with each other through the CXL switch (SW_CXL). can do. Each of the plurality of CXL storage devices 410_1 to 410_m may be implemented as a smart memory module applying the CXL interface described in FIGS. 2 to 4.

In an embodiment, the host 401 may manage a plurality of CXL storage devices 410_1 to 410_m as one storage cluster and manage a plurality of CXL memories 420_1 to 420_n as one memory cluster. . For one storage cluster, the host 401 may allocate a portion of the memory cluster as a dedicated area (i.e., an area for storing map data of the storage cluster). Alternatively, the host 401 may allocate areas of the plurality of CXL memories 420_1 to 420_m to the plurality of CXL storage devices 410_1 to 410_m, respectively, as dedicated areas.

Figure 7 is a block diagram showing a computing system 1000 according to an embodiment of the present invention. Referring to FIG. 7, the computing system 1000 includes a first CPU 1110, a second CPU 1120, a GPU 1130, an NPU 1140, a CXL switch (SW_CXL), a CXL storage device 1210, and a CXL It may include a memory device 1220, a PCIe device 1310, and an accelerator (CXL device) 1320.

First CPU 1110, second CPU 1120, GPU 1130, NPU 1140, CXL storage device 1210, CXL memory device 1220, PCIe device 1310, and accelerator (CXL device) 1320 may be commonly connected to the CXL switch (SW_CXL), and each may communicate with each other through the CXL switch (SW_CXL). In an embodiment, each of the first CPU 1110, the second CPU 1120, the GPU 1130, and the NPU 1140 may be directly connected to individual memory devices.

In an embodiment, the CXL storage device 1210 and the CXL memory device 1220 are one or more of the first CPU 1110, the second CPU 1120, the GPU 1130, and the NPU 1140. By , at least a portion of the area of the CXL memory device 1220 may be allocated as a dedicated area for the CXL storage device 1210. That is, the CXL storage device 1210 and the CXL memory device 1220 may be used as a storage space (STR) of the computing system 1000. As described in FIGS. 2 to 4, the CXL storage device 1210 simultaneously performs read and write operations with non-volatile memory dies through a plurality of child controllers, and the mother controller operates even if the input/output bus of the child controllers is occupied. Unused non-volatile memory dies can be directly accessed.

In an embodiment, the CXL switch (SW_CXL) may be connected to a PCIe device 1310 or accelerator 1320 configured to support various functions, and the PCIe device 1310 or accelerator 1320 may be connected to the CXL switch (SW_CXL). A storage space (STR) that communicates with each of the first CPU 1110, the second CPU 1120, the GPU 1130, and the NPU 1140, or includes the CXL storage device 1210 and the CXL memory device 1220. ) can be accessed.

In an embodiment, the CXL switch (SW_CXL) may be connected to an external network or fabric, and may be configured to communicate with an external server through the external network or fabric.

Figure 8 is a block diagram showing a data center to which a computing system according to the present invention is applied. Referring to FIG. 8, the data center 2000 is a facility that collects various data and provides services, and may also be referred to as a data storage center. The data center 2000 may be a system for operating a search engine and database, and may be a computing system used in companies such as banks or government agencies. Data center 2000 may include application servers 2110 to 21m0 and storage servers 2210 to 22n0. The number of application servers and the number of storage servers may be selected in various ways depending on the embodiment, and the number of application servers and the number of storage servers may be different.

Below, the configuration of the first storage server 2210 is mainly explained. Each of the application servers 2110 to 21m0 and the storage servers 2210 to 22n0 may have a similar structure, and the application servers 2110 to 21m0 and the storage servers 2210 to 22n0 operate the network NT. Through this, they can communicate with each other.

The first storage server 2210 may include a processor 2211, a memory 2212, a switch 2213, a storage device 2215, a CXL memory 2214, and a network interface card (NIC) 2216. The processor 2211 can control the overall operation of the first storage server 2210 and access the memory 2212 to execute instructions loaded into the memory 2212 or process data. The memory 2212 is DDR SDRAM (Double Data Rate Synchronous DRAM), HBM (High Bandwidth Memory), HMC (Hybrid Memory Cube), DIMM (Dual In-line Memory Module), Optane DIMM, and/or NVDIMM (Non-Volatile DIMM). ) can be. The processor 2211 and the memory 2212 may be directly connected, and the number of processors 2211 and memories 2212 included in one storage server 2210 may be selected in various ways.

In an embodiment, the processor 2211 and the memory 2212 may provide a processor-memory pair. In an embodiment, the number of processors 2211 and memories 2212 may be different. The processor 2211 may include a single core processor or a multi-core processor. The above description of the storage server 2210 can be similarly applied to each of the application servers 2110 to 21m0.

The switch 2213 may be configured to mediate or route communication between various components included in the first storage server 2210. In an embodiment, switch 2213 may be a CXL switch (SW_CXL). That is, the switch 2213 may be a switch implemented based on the CXL protocol.

CXL memory 2214 may be connected to switch 2213. In an embodiment, the CXL memory 2214 may be used as a memory expander for the processor 2211. Alternatively, the CXL memory 2214 may be allocated as a dedicated memory or buffer memory for the storage device 2215.

The storage device 2215 may include a CXL interface circuit (CXL_IF), a controller (CTRL), and NAND flash (NAND). The storage device 2215 may store data or output the stored data according to a request from the processor 2211. In an embodiment, storage device 2215 may be the CXL storage described. In an embodiment, the storage device 2215 may allocate at least a portion of the CXL memory 2214 as a dedicated area and use the dedicated area as a buffer memory (i.e., map data is stored in the CXL memory 2214). )can do. The storage device 2215 may be implemented with the smart memory module and its operating method described in FIGS. 2 to 7.

In an embodiment, the application servers 2110 to 21m0 may not include the storage device 2215. The storage server 2210 may include at least one storage device 2215. The number of storage devices 2215 included in the storage server 2210 may be selected in various ways depending on the embodiment.

A network interface card (NIC) 2216 may be connected to the CXL switch (SW_CXL). The NIC 2216 may communicate with other storage servers 2220 to 22n0 or other application servers 2110 to 21m0 through a network (NT).

In an embodiment, the NIC 2216 may include a network interface card, a network adapter, etc. The NIC 2216 may be connected to the network NT by a wired interface, a wireless interface, a Bluetooth interface, an optical interface, etc. The NIC 2216 may include internal memory, a digital signal processor (DSP), a host bus interface, etc., and may be connected to the processor 2211 and/or the switch 2213 through the host bus interface. In an embodiment, the NIC 2216 may be integrated with at least one of the processor 2211, the switch 2213, and the storage device 2215.

In an embodiment, the network (NT) may be implemented using Fiber Channel (FC) or Ethernet. At this time, FC is a medium used for relatively high-speed data transmission, and an optical switch that provides high performance/high availability can be used. Depending on the network (NT) access method, storage servers can provide file storage, block storage, or object storage.

In an embodiment, the network NT may be a storage-only network such as a storage area network (SAN). For example, the SAN may be an FC-SAN that uses an FC network and is implemented according to the FC Protocol (FCP). As another example, the SAN may be an IP-SAN that uses a TCP/IP network and is implemented according to the iSCSI (SCSI over TCP/IP or Internet SCSI) protocol. In an embodiment, the network NT may be a general network such as a TCP/IP network. For example, the network (NT) may be implemented according to protocols such as FC over Ethernet (FCoE), Network Attached Storage (NAS), and NVMe over Fabrics (NVMe-oF).

In an embodiment, at least one of the application servers 2110 to 21m0 may store data requested by a user or client to be stored in one of the storage servers 2210 to 22n0 through the network NT. At least one of the application servers 2110 to 21m0 may obtain data requested to be read by a user or client from one of the storage servers 2210 to 22n0 through the network NT. For example, at least one of the application servers 2110 to 21m0 may be implemented as a web server or a database management system (DBMS).

In an embodiment, at least one of the application servers 2110 to 21m0 may access memory, CXL memory, or a storage device included in another application server through the network NT, or through the network NT. It is possible to access memories, CXL memories, or storage devices included in the storage servers 2210 to 22n0. Accordingly, at least one of the application servers 2110 to 21m0 can perform various operations on data stored in other application servers and/or storage servers. For example, at least one of the application servers 2110 to 21m0 may execute a command to move or copy data between other application servers and/or storage servers. At this time, data may be moved from the storage devices of the storage servers through the memories of the storage servers or CXL memories, or directly to the memory of the application servers or CXL memories. Data moving over a network may be encrypted for security or privacy.

In an embodiment, the storage device included in at least one of the application servers 2110 to 21m0 and the storage servers 2210 to 22n0 is at least one of the application servers 2110 to 21m0 and the storage servers 2210 to 22n0. The CXL memory included in one can be allocated as a dedicated area, and the storage device can use the allocated dedicated area as a buffer memory (i.e., store map data). For example, the storage device 2215 included in the storage server 2210 may be allocated the CXL memory included in another storage server (e.g., 22n0), through the switch 2213 and the NIC 2216. , it is possible to access CXL memory contained in another storage server (e.g., 22n0). In this case, map data for the storage device 2215 of the first storage server 2210 may be stored in the CXL memory of the other storage server 22n0. That is, storage devices and CXL memories of a data center according to the present invention can be connected and implemented in various ways.

In the above-described embodiments, components according to the technical idea of the present invention have been described using terms such as first, second, third, etc. However, terms such as first, second, third, etc. are used to distinguish components from each other and do not limit the present invention. For example, terms such as first, second, third, etc. do not imply an order or any form of numerical meaning.

The device described above may be implemented with hardware components, software components, and/or a combination of hardware components and software components. For example, the devices and components described in the embodiment include a processor, a controller, an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), and a programmable logic unit (PLU). It may be implemented using one or more general-purpose or special-purpose computers, such as a unit, microprocessor, or any other device capable of executing and responding to instructions. The processing device may execute an operating system (OS) and one or more software applications running on the operating system. Additionally, a processing device may access, store, manipulate, process, and generate data in response to the execution of software. For ease of understanding, a single processing device may be described as being used; however, those skilled in the art will understand that a processing device includes multiple processing elements or multiple types of processing elements. You can see that it can be done. For example, a processing device may include a plurality of processors or one processor and one controller. Additionally, other processing configurations, such as parallel processors, are possible.

Software may include a computer program, code, instructions, or a combination of one or more of these, and may configure a processing unit to operate as desired, or to process independently or collectively. You can command the device. Software and/or data may be used by any type of machine, component, physical device, virtual equipment, computer storage medium or device to be interpreted by or to provide instructions or data to a processing device. It can be embodied in . Software may be distributed over networked computer systems and stored or executed in a distributed manner. Software and data may be stored on one or more computer-readable recording media.

A smart memory module according to an embodiment of the present invention may be implemented in the form of a mesh structure in which multiple Flash Memory Controllers and all NAND Dies are connected to each other.

In an embodiment, in the case where Flash Memory CTRL-NAND Dies are H/W dedicated, if the Flash Memory CTRL is operating, it is dedicated to the corresponding CTRL and access to unused NAND Dies is possible. In an embodiment, child CTRLs can be added or subtracted through the mesh structure, and cost saving is possible by reducing the number of unnecessary NAND CTRLs compared to existing patents. There are NAND dies that allow direct access and data read/write to Mother CTRL to NAND Dies.

Meanwhile, the contents of the present invention described above are only specific examples for carrying out the invention. The present invention will include not only concrete and practically usable means, but also technical ideas, which are abstract and conceptual ideas that can be used as technology in the future.

200: Smart memory module
210: volatile memory device
220: Non-volatile memory devices
231, 232, 232, 23M: Child controller
240: Mother controller
250: Non-volatile die management and DMA controller

Claims (10)

at least one volatile memory device;
A plurality of non-volatile memory devices connected in a mesh structure;
a plurality of child controllers that perform data transfer from the at least one volatile memory device to the plurality of non-volatile memory devices; and
Comprising a mother controller that communicates with an external device through a CXL (Compute Express Link) interface and controls the at least one volatile memory device and the plurality of child controllers,
Each of the plurality of child controllers performs a read or write operation by transmitting a command and a direct memory access (DMA) instruction to at least one non-volatile memory device allocated to an activation die among the plurality of non-volatile memory devices. A smart memory module characterized in that. According to claim 1,
The mother controller monitors the activation and deactivation status of each of the plurality of non-volatile memory devices, and performs a data striping operation through the plurality of child controllers by allocating deactivated dies. Smart memory module. According to claim 1,
A smart memory module, wherein the mother controller performs a read/write operation through direct access to at least one of the plurality of non-volatile memory devices. According to claim 1,
A smart memory module further comprising a non-volatile die management and DMA controller that monitors activation and deactivation of each of the plurality of non-volatile memory devices and controls DMA operations of assigned dies. According to claim 4,
A smart memory module, wherein the non-volatile die management and DMA controller controls distributing data or collecting data in at least one read/write operation among the plurality of non-volatile memory devices. According to claim 4,
A smart memory module, wherein the non-volatile die management and DMA controller controls the mother controller to directly write data to or read data directly from at least one of the plurality of non-volatile memory devices. According to claim 1,
When management of small chunk or service quality-related important data is required, read/write operations are performed by the mother controller directly accessing at least one predetermined non-volatile memory device regardless of the plurality of child controllers. A smart memory module, characterized in that: According to claim 1,
A smart memory module, wherein the read operation and the write operation are performed simultaneously through the plurality of child controllers. In a method of operating a smart memory module, the smart memory module includes at least one volatile memory device, a plurality of non-volatile memory devices connected in a mesh structure, and data of the at least one volatile memory device to the plurality of non-volatile memory devices. a plurality of child controllers that transmit data to the device, and a mother controller that controls the at least one volatile memory device and the plurality of child controllers, the method comprising:
Managing activation and deactivation of each of the plurality of non-volatile memory devices when transferring data from the at least one volatile memory device to the plurality of non-volatile memory devices through the plurality of child controllers; and
A method comprising controlling, by the mother controller, a Direct Memory Access (DMA) operation for at least one non-volatile memory device among the plurality of non-volatile memory devices. According to clause 9,
A method wherein at least one of the plurality of child controllers performs a write operation and at least one other child controller performs a read operation.