KR20230170566A - Semiconductor device and method for making the same - Google Patents

Abstract

The semiconductor device includes a substrate, at least one electronic component mounted on the substrate, an encapsulant formed on the substrate and at least partially encapsulating the at least one electronic component, a shielding layer formed on the encapsulant, and a thermal interface formed on the shielding layer. layer, and a metal cover formed on the thermal interface layer.

Description

Semiconductor device and method of manufacturing the same {SEMICONDUCTOR DEVICE AND METHOD FOR MAKING THE SAME}

This application relates generally to semiconductor devices, and more specifically to semiconductor devices and methods of manufacturing the same.

As consumers want their electronic devices to be smaller, faster, and have higher performance, the semiconductor industry continually faces complex integration challenges. In cutting-edge 5G devices, such as portable multimedia devices, it is common to integrate both the processing system and antenna(s) into one package. In this configuration, multiple electronic components can be integrated into a smaller package, meeting consumers' need to include more functional modules in smaller devices. However, this high level of integration requires more interface fin-counts and less thickness, thus generating more heat and lacking effective heat dissipation. In such cases, heat built up within the package can cause package warping problems and impair the functionality of the system.

Therefore, a semiconductor package with improved thermal management is needed.

The purpose of this application is to provide an apparatus for thermal management of semiconductor devices.

According to aspects of the embodiments of the present application, a semiconductor device is provided. The semiconductor device includes: a substrate; At least one electronic component mounted on a substrate; an encapsulant formed on the substrate and at least partially encapsulates the at least one electronic component; A shielding layer formed on the encapsulant; A thermal interface layer formed on the shielding layer; and a metal cover formed on the thermal interface layer.

According to aspects of the embodiments of the present application, a semiconductor device is provided. The semiconductor device includes: a substrate; At least one electronic component mounted on a substrate; an encapsulant formed on the substrate and at least partially encapsulates the at least one electronic component; A thermal interface layer formed on the encapsulant; A metal cover formed on the thermal interface layer; and a shielding layer formed on the substrate and covering the metal cap, thermal interface layer, and encapsulant.

According to another aspect of the embodiments of the present application, methods for manufacturing semiconductor devices according to the above aspects are provided.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not limiting of the invention. Additionally, the accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

The drawings referred to herein form part of the specification. The features shown in the drawings exemplify only some embodiments of the application, and not all embodiments of the application, unless the detailed description explicitly dictates otherwise, and readers of the specification should not be given a contrary meaning.
1A is a cross-sectional view illustrating a semiconductor device according to an embodiment of the present application.
1B and 1C are enlarged views illustrating a portion of the semiconductor device of FIG. 1A according to some embodiments of the present application.
1D is a cross-sectional view illustrating a semiconductor device with discrete antenna packages according to an embodiment of the present application.
2A is a cross-sectional view illustrating a semiconductor device with top surfaces of two electronic components exposed to a shielding layer according to another embodiment of the present application.
2B and 2C are enlarged views illustrating a portion of the semiconductor device of FIG. 2A according to some embodiments of the present application.
3A, 3B, and 4 are cross-sectional views illustrating a semiconductor device with a sealed semiconductor package mounted on a substrate according to some embodiments of the present application.
5A is a cross-sectional view illustrating a semiconductor device according to another embodiment of the present application.
5B and 5C are enlarged views illustrating a portion of the semiconductor device of FIG. 5A according to some embodiments of the present application.
FIG. 6A is a cross-sectional view illustrating a semiconductor device according to another embodiment of the present application.
6B and 6C are enlarged views illustrating a portion of the semiconductor device of FIG. 6A according to some embodiments of the present application.
7 and 8 are cross-sectional views illustrating a semiconductor device with a sealed semiconductor package mounted on a substrate according to some embodiments of the present application.
FIG. 9A is a flow chart illustrating a method 900 for manufacturing a semiconductor device according to an embodiment of the present application.
Figures 9B-9F are cross-sectional views illustrating various steps of the method for manufacturing the semiconductor device shown in Figure 9A.
10A is a flow chart illustrating a method 1000 for manufacturing a semiconductor device according to another embodiment of the present application.
Figures 10B-10F are cross-sectional views illustrating various steps of the method for manufacturing the semiconductor device shown in Figure 10A.
Identical reference numbers will be used throughout the drawings to indicate identical or similar parts.

The following detailed description of exemplary embodiments of the present application refers to the accompanying drawings, which form a part of the description. The drawings illustrate certain example embodiments in which the present application may be practiced. The detailed description, including the drawings, describes these embodiments in sufficient detail to enable those skilled in the art to practice the application. A person skilled in the art may further utilize other embodiments of the present application and make logical, mechanical, and other changes without departing from the spirit or scope of the present application. Accordingly, readers of the following detailed description should not interpret the description in a limiting sense, and the appended claims alone define the scope of the embodiments of the present application.

In this application, uses of the singular form singular include the plural form unless specifically stated otherwise. In this application, the use of “or” means “and/or” unless otherwise specified. Moreover, the use of the term “comprising” as well as other forms such as “comprises” and “included” is not limiting. Additionally, terms such as “element” or “component” refer to both elements and components comprising one unit and elements and components comprising more than one subunit, unless specifically stated otherwise. Includes. Additionally, the section headings used herein are for organizational purposes only and should not be construed as limiting the subject matter described.

As used herein, “beneath”, “below”, “above”, “over”, “on”, “upper”, “ Spatially relative terms such as "lower", "left", "right", "vertical", "horizontal", "side" and similar may be used herein for convenience of explanation, to describe the relationship of one element or feature to another element(s) or feature(s) as illustrated in the drawings. Spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to the orientation shown in the figures. The device may be oriented in other ways (rotated 90 degrees or rotated to other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. When an element is referred to as being “connected” or “coupled” to another element, it should be understood that the element may be directly connected or coupled to the other element or there may be intervening elements.

1A shows a semiconductor device 100 having multiple electronic components mounted on a substrate 110 of the semiconductor device 100, according to an embodiment of the present application. As shown in FIG. 1A , some of the electronic components are encapsulated and include a shielding layer, a thermal interface layer, and a metal cover that together provide thermal management for the semiconductor device 100, particularly the electronic components encapsulated therein. It is additionally covered by a lid).

Specifically, a plurality of electronic components 120, 130, 140, and 150 are mounted on both sides of the substrate 110, and the electronic components are electrically connected to a conductive structure (not shown) within the substrate 110. In one embodiment, substrate 110 includes one or more embedded antenna elements (not shown). Electronic components mounted on substrate 110 may be semiconductor dies 120, individual devices 130 and 140, and dielectric members 150. Dielectric elements 150 may improve transmission and reception of corresponding embedded antenna elements, respectively. In some embodiments, individual device 140 is a board-to-board connector that can be electrically connected to an electronic component of semiconductor device 100 or to substrate 110 and may be configured to electrically connect to other devices. You can. Preferably, a board-to-board connector electrically connects the embedded antenna elements to other devices. Some of the electronic components, such as semiconductor dies 120 and individual devices 130, may require encapsulation and EMI shielding, while some other electronic components, such as individual devices 140 and dielectric members 150, may require encapsulation and EMI shielding. may not require the same protections. The present application achieves improved thermal management by further layering a multilayer structure with sealing and shielding layers, which are described further below.

Referring further to semiconductor device 100 shown in Figure 1A, in a preferred embodiment, semiconductor dies 120, individual devices 130, 140 may be mounted on one side of substrate 110, and the dielectric member Fields 150 may be mounted on the other side of substrate 110 . As mentioned above, due to different practical needs in manufacturing and use, the semiconductor dies 120 and individual devices 130, and the individual devices 140 and dielectric members 150 have the same sealing and EMI shielding. may not be requested. Accordingly, encapsulant 160 is disposed on a portion of the electronic components mounted on substrate 110, i.e., encapsulant 160 covers semiconductor dies 120 and individual devices 130. In contrast, the other electronic components, namely individual devices 140 and dielectric members 150, remain unsealed and unshielded. Encapsulant 160 covering some of the electronic components may form an encapsulant cube on substrate 110 . Shielding layer 170 is formed to cover at least a portion of the outer surface of the encapsulant cube. Preferably, shielding layer 170 covers the entire exterior surface of the encapsulant cube. As such, the shielding layer 170 includes a top section covering the top surface of the encapsulant cube, and a side section covering the lateral surfaces of the encapsulant cube, whereby the shielding layer 170 is configured to cover the encapsulant 160 It has a shape that matches the shape of.

A thermal interface layer 180 is further formed on shielding layer 170. Preferably, thermal interface layer 180 may completely cover the top section of shielding layer 170, but may not cover side sections of shielding layer 170. That is, thermal interface layer 180 conforms to the top section of shielding layer 170. A metal cover 190 is further disposed on the thermal interface layer 180. Desirably, metal cover 190 can completely cover the top surface of thermal interface layer 180. That is, metal cover 190 conforms to the top surface of thermal interface layer 180.

As illustrated above, in the semiconductor device 100 shown in FIG. 1A, the electronic components 120 and 130 are comprised in the order from bottom to top: encapsulant 160, shielding layer 170, and thermal interface layer. It is covered by a stack-up structure of (180) and a metal cover (190). Note that the heights of the layers of the layered structure shown in FIG. 1A are exemplary only and do not represent the actual ratio of the heights of the layers in the layered structure. Shielding layer 170 may be formed by depositing shielding materials such as metals, conductive plastics, and conductive polymers. Thermal interface layer 180 may be formed on shielding layer 170 by dispensing a thermal interface material on shielding layer 170 . Thermal interface layer 180 is used to enhance thermal coupling between the heat generating device and the heat dissipating device. Specifically, at each contact interface, a thermal boundary resistance exists to impede heat dissipation, and under continuous overheating and large thermal stress at the contact interfaces, electronic performance and device lifetime can be dramatically degraded. The thermal interface layer 180 reduces the thermal boundary resistance between layers and provides thermal management performance as well as tackle applications such as low thermal stress, low elastic modulus or viscosity, flexibility, and reusability between materials of different thermal expansion coefficients. Requirements can be improved. The thermal interface layer 180 transfers heat from the electronic components beneath the thermal interface layer 180 through the encapsulant 160 and shielding layer 170 to the heat spreading metal cover 190. In some embodiments, the thermal interface material may be thermally conductive, dispensable materials, preferably thermal greases, thermal adhesives, thermal gap fillers, liquid metal, and solder paste. In an embodiment, the thermal interface material is an epoxy compound that can be used for easy bonding with metals, ceramics, most plastics, and a wide variety of other materials. In another embodiment, the thermal interface material includes a solder paste that has improved thermal conductivity compared to typical thermal interface materials. Preferably, the soldering paste is an Ag-In soldering alloy. Specifically, the thermal interface material may be a solder preform, i.e., a solid, flat, manufactured shape of the solder, and flux may be applied to coat the solder preform. Metal cover 190 is generally made of highly thermally conductive metal materials for efficient heat dissipation from the devices within the semiconductor package. In the present application, the metal cover 190 may function in combination with the thermal interface layer 180 to provide better heat dissipation to the electronic components within the corresponding encapsulant. Metal cover 190 is preferably made of copper, aluminum, and copper-tungsten alloy. It will be appreciated that other suitable materials may be used to form metal cover 190. With thermal interface layer 180 and metal cover 190 conducting heat away from the electronic components, power consumption may be reduced by maintaining the electronic components at a lower operating temperature.

Shielding layer 170 of FIG. 1A may further include sublayers illustratively shown by enlarging portion 101 of semiconductor device 100 of FIGS. 1B and 1C. Portions 101b and 101c shown in FIGS. 1B and 1C are cross-sectional views of layered structures on encapsulants 160b and 160c, respectively, covering electronic components. Note that the heights of the layers of the layered structures shown in FIGS. 1B and 1C are exemplary only and do not represent the actual ratio of the heights of the layers in the layered structures.

Referring to Figure 1B, the enlarged portion 101b shows that the shielding layer 170b may include three sub-layers according to a preferred embodiment. Specifically, shielding layer 170b may include, from bottom to top, a wet sublayer 171b, a shielding sublayer 172b, and a protective sublayer 173b. That is, wet sublayer 171b is formed on encapsulant 160b. The shielding sublayer 172b on the wet sublayer 171b can be formed by sputtering, plasma deposition, or spraying to prevent external interference such as electromagnetic interference. Preferably, the shielding sublayer 172b is formed by sputtering. The protective sublayer 173b is preferably formed on the shielding sublayer 172b comprising stainless steel, an organic soldering preservative, or nickel to provide better resistance such as oxidation resistance, thermal shock resistance, moisture resistance, and corrosion resistance. You can. A thermal interface layer 180b is then disposed on the protective sublayer 173b, and a metal cover 190b is further disposed on the thermal interface layer 180b. In some embodiments, the thickness of wet sublayer 171b is 1 μm or less. In some embodiments, the thickness of shielding sublayer 172b is between 2 μm and 10 μm, such as 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, 10 μm. is the range. In some embodiments, the thickness of protective sublayer 173b is 1 μm or less. However, the respective thicknesses of the above-described lower layers 171b, 172b, and 173b are not limited to these examples. According to the scope of the present application, the thickness of the sublayers 171b, 172b, and 173b may include any thickness that can effectively perform wetting, shielding, and protection, respectively.

In another embodiment, i.e., portion 101c shown in FIG. 1C, the shielding layer 170c is comprised of two layers, a wet sublayer 171c on encapsulant 160c and a shielding sublayer 172c on wet sublayer 171c, respectively. It can only include lower layers. A thermal interface layer 180c is disposed on the shielding sublayer 172c, and a metal cover 190c is further disposed on the thermal interface layer 180c. Wetting sublayers 171b, 171c are generally used to provide better wetting to the layers with which they are in contact. Specifically, the wetting sublayers 171b and 171c may allow the shielding sublayers 172b and 172c to adhere more completely and uniformly to the encapsulants 160b and 160c, respectively. The wet sublayers 171b, 171c are preferably made of a material comprising at least one of gold, silver, indium, and tin. Preferably, wet sublayers 171b, 171c comprise titanium or stainless steel. The shielding sublayer is used to block external interference, such as electromagnetic interference from the environment or other electronic devices. Preferably, the shielding sublayers 172b, 172c include copper. Aspects of the present application are not limited thereto, and it will be appreciated that other electronic components may be mounted on the substrate, and encapsulants and shielding may be needed on the electronic components on both sides of the substrate. Additionally, it can be seen that the thermal interface layer is selectively shielded and/or selectively formed and/or optionally configured with a metal cover.

1D is a cross-sectional view illustrating a semiconductor device with discrete antenna packages according to an embodiment of the present application. As shown in FIG. 1D , in semiconductor device 100d, the electronic components mounted on one side of substrate 110d opposite the encapsulant and thermal management layers described above may be individual antenna packages 150d. . Discrete antenna packages 150d may be formed within another encapsulant layer 151d. Discrete antenna packages 150d have each antenna conductive pattern electrically connected to specific conductive patterns (not shown) in substrate 110d to further connect to other electronic components on the top side of substrate 110d. can be included inside.

In some embodiments, an encapsulant covering a plurality of electronic components can be configured to expose a top surface of at least one electronic component of the plurality of electronic components, whereby the shielding layer on the encapsulant covers the at least one electronic component. May contact the top surface of the component. FIG. 2A shows a semiconductor device 200 with a thinner encapsulant, according to an embodiment of the present application.

As shown in FIG. 2A , multiple electronic components including two semiconductor dies 220, individual devices 230, 240, and dielectric members 250 may be mounted on either side of substrate 210. there is. Additionally, it can be seen that dielectric members 250 can be replaced with the discrete antenna package configuration shown in FIG. 1D. Similar to the embodiment of Figure 1A, the two semiconductor dies 220 and the individual devices 230 need to be encapsulated, while other electronic components do not need to be encapsulated. However, unlike the embodiment of FIG. 1A , the encapsulant 260 configured to cover the two semiconductor dies 220 and the individual devices 230 may expose the top surfaces of the two semiconductor dies 220 . At the same time, some electronic components within encapsulant 260 may be left unexposed, such as individual devices 230 . A shielding layer 270 is formed on the encapsulant 260. Because the top surfaces of the semiconductor dies 220 are exposed, the shielding layer 270 contacts the top surfaces of the two semiconductor dies 220 . In some preferred embodiments, shielding layer 270 may cover the outer surface of the encapsulant cube formed by encapsulant 260. Thermal interface layer 280 is disposed on shielding layer 270 and conforms to the top surface of shielding layer 270. A metal cover 290 is disposed on the thermal interface layer 280 and conforms to the top surface of the thermal interface layer 280. The materials of encapsulant 260, the aforementioned layers, and metal cover 290 are similar to those described with reference to the embodiment illustrated in FIG. 1A. It will be appreciated that some electronic components may be exposed from the encapsulant while others may not, and this may be configured differently.

With further reference to FIG. 2A , shielding layer 270 may further include sublayers illustratively shown by enlarging portion 201 of semiconductor device 200 in FIGS. 2B and 2C . Portions 201b and 201c shown in FIGS. 2B and 2C are cross-sectional views of layered structures on encapsulant covering electronic components, respectively. In particular, the portion where the right semiconductor die 220 of FIG. 2A contacts the shielding layer 270 is enlarged.

Referring to Figure 2b, the enlarged portion 201b shows that the shielding layer 270b may include three sub-layers according to a preferred embodiment. Of note, enlarged portion 210b shows the top surface of semiconductor die 220b exposed from encapsulant 260 of FIG. 2A, where semiconductor die 220b contacts shielding layer 270b. . Specifically, in the preferred embodiment of FIG. 2B, shielding layer 270b may include, from bottom to top, a wet sublayer 271b, a shielding sublayer 272b, and a protective sublayer 273b. A thermal interface layer 280b is then placed on the protective sublayer 273b, and a metal cover 290b is placed on the thermal interface layer 280b.

In another embodiment, i.e., portion 201c shown in FIG. 2C, the shielding layer 270c is a wet sublayer 271c in contact with the semiconductor die 220c and a shielding sublayer 272c on the wet sublayer 271c, respectively. It can contain only two sublayers. A thermal interface layer 280c is disposed on shielding sublayer 272c, and a metal cover 290c is disposed on thermal interface layer 280c. The material configurations of the above-described layers and metal cover may refer back to the examples of FIGS. 1B and 1C.

In some other embodiments, the electronic component mounted on the substrate may be a semiconductor package that may include one or more semiconductor dies and/or one or more discrete devices. Such embodiments may refer to FIGS. 3A, 3B and 4 which illustrate a situation where layers for encapsulation, shielding and thermal management are constructed on a semiconductor package of multiple electronic components mounted on a substrate.

FIG. 3A shows a semiconductor device 300 according to an embodiment of the present application. Referring to FIG. 3A , in semiconductor device 300, multiple electronic components may be mounted on substrate 310. That is, the semiconductor package 320, individual devices 340, and dielectric members 350 may be mounted on substrate 310 and electrically connected together through conductive structures within substrate 310. Additionally, it can be seen that the dielectric members 350 can be replaced with a discrete antenna package configuration as shown in FIG. 1D. The semiconductor package 320 includes a substrate 321, two semiconductor dies 322 and individual devices 323 mounted on one side of the substrate 321, and one semiconductor die on the other side of the substrate 321. It may include multiple components such as (324). Electronic components mounted on substrate 321 are electrically connected together through conductive structures within substrate 321. Note that a portion of the semiconductor package 320 may have been previously sealed in some embodiments. The substrate 321 of the semiconductor package 320 may be electrically connected to the substrate 310 through solder balls 325 or the like. In this embodiment, the semiconductor package 320 is encapsulated with encapsulant 360 to form an encapsulant cube similar to the embodiment of FIG. 1A. In some embodiments, semiconductor die 324 disposed between substrate 321 and substrate 310 may expose a surface facing from encapsulant 360 toward substrate 310, as illustrated in FIG. 3A. . Shielding layer 370 is formed on encapsulant 360 to cover at least a portion of the outer surface of encapsulant 360. Preferably, shielding layer 370 covers the entire exterior surface of the encapsulant cube. Shielding layer 370 includes a top section covering the top surface of the encapsulant cube, and a side section covering the lateral surfaces of the encapsulant cube. A thermal interface layer 380 is further formed on shielding layer 370. Desirably, thermal interface layer 380 may completely cover the top section of shielding layer 370 and may not cover side sections of shielding layer 370 . That is, thermal interface layer 380 conforms to the top section of the shielding layer. A metal cover 390 is further disposed on the thermal interface layer 380. Desirably, metal cover 390 can completely cover the top surface of thermal interface layer 380. That is, metal cover 390 conforms to the top surface of thermal interface layer 380. It can be seen that the shielding layer 370 of the semiconductor device 300 may be a shielding layer 101b or 101c comprising three or two sub-layers, respectively.

Referring to FIG. 3B, the semiconductor device 300b may be configured similarly to FIG. 3A. That is, the semiconductor package 320 may be mounted on the substrate 310 of the semiconductor device 300b through solder balls 325. In this embodiment, semiconductor package 320 also includes a substrate 321, two semiconductor dies, and individual devices 323a and 323b. Unlike FIG. 3A, the individual devices 323b of the semiconductor package 320 do not need to be encapsulated, and therefore, the encapsulant 360 is not formed on the individual devices 323b. That is, the encapsulant 360 is formed on a portion of the semiconductor package 320.

Figure 4 shows a semiconductor device 400 according to an embodiment of the present application. Referring to FIG. 4 , a semiconductor device 400 equipped with a semiconductor package 420 is shown. Similar to FIG. 2A , the semiconductor package 420 is mounted on a substrate and requires a thermal interface layer and a metal cover, and the encapsulant 460 also covers the top surface of at least one electronic component of the semiconductor package 420. It can be configured to expose. It can be seen that such a configuration can be adapted to a semiconductor package configuration as shown in FIG. 3B. In a preferred embodiment, the top surfaces of the two semiconductor dies 422 are exposed from the encapsulant 460. In this case, the shielding layer 470 formed on the encapsulant 460 contacts the top surfaces of the two semiconductor dies 422. Other electronic components within encapsulant 460 may be left uncovered and not in contact with shielding layer 470 . A thermal interface layer 480 is disposed on shielding layer 470. A metal cover 490 is disposed on the thermal interface layer 480.

The above embodiments show a thermal interface layer and a metal cover being placed on top of the shielding layer. In another aspect, a thermal interface layer and a metal cover may be constructed beneath the shielding layer, as illustrated in the embodiments shown in FIGS. 5A-8.

FIG. 5A shows a semiconductor device 500 according to an embodiment of the present application. As shown in FIG. 5A , thermal interface layer 580 is disposed on the top surface of the encapsulant cube formed by encapsulant 560 and the electronic components covered by encapsulant 560 . Thermal interface layer 580 conforms to the top surface of the encapsulant cube. Metal cover 590 is disposed on thermal interface 580 , which conforms to the top surface of thermal interface 580 . In a preferred embodiment, shielding layer 570 is disposed on metal shroud 590 such that the top surface of metal shroud 590, the lateral surfaces of the encapsulant cube, the lateral surfaces of thermal interface layer 580, and the metal shroud 590 It covers the lateral surfaces of (590).

Shielding layer 570 in semiconductor device 500 shown in Figure 5A further includes sublayers according to two different embodiments shown enlarged portions 501 of semiconductor device 500 in Figures 5B and 5C. can do. Portions 501b, 501c are cross-sectional views of the layered structures on encapsulants 560b, 560c covering the electronic components.

The typical laminate structures shown in FIGS. 5B and 5C both consist of, from bottom to top, encapsulants 560b, 560c, thermal interface layers 580b, 580c, metal caps 590b, 590c, and shielding layers 570b, respectively. , 570c). The difference between the two typical laminate structures shown in FIGS. 5B and 5C lies in the lower layers of the shielding layers 570b and 570c. Referring to Figure 5b, the enlarged portion 501b shows that the shielding layer 570b may include three sub-layers according to a preferred embodiment. Specifically, shielding layer 570b may include, from bottom to top, a wet sublayer 571b, a shielding sublayer 572b, and a protective sublayer 573b. In another embodiment 501c shown in Figure 5C, the shielding layer 570c may include only two sublayers: a shielding sublayer 572c on the metal cover 590c and a protective sublayer 573c on the shielding sublayer 572c. there is.

Figure 6 shows a semiconductor device 600 according to an embodiment of the present application. Similar to the embodiment shown in Figure 5A, a thermal interface layer 680 and a metal cover 690 are also under the shielding layer 670, but where the encapsulant 660 is similar to the embodiment shown in Figure 2A. It is configured to expose a top surface of at least one electronic component within encapsulant 660. 6A, the encapsulant 660 covering the plurality of electronic components can be configured to expose the top surfaces of two semiconductor dies 620, whereby the thermal interface layer 680 is 620). A metal cover 690 is disposed on the thermal interface layer 680, both of which have an area equal to the top surface of the encapsulant cube formed by the encapsulant 660. Shielding layer 670 is formed on metal cover 690. Similar to FIG. 5A , shielding layer 670 covers the top surface of metal shroud 690, the lateral surfaces of metal shroud 690, the lateral surfaces of thermal interface layer 680, and the lateral surfaces of the encapsulant cube. You can see that it can be covered.

Similar to the semiconductor device 500 shown in Figure 5A, the shielding layer 670 within the semiconductor device 600 is shown in two different enlargements of the portion 601 of the semiconductor device 600 in Figures 6B and 6C. It may additionally include lower layers according to the embodiment. Portions 601b and 601c are cross-sectional views of layered structures on encapsulant 660 covering electronic components. In particular, the portion where the right semiconductor die 620 of FIG. 6A contacts the shielding layer 670 is enlarged.

The typical laminate structures of the embodiments shown in FIGS. 6B and 6C both include, from bottom to top, semiconductor dies 620b, 620c, thermal interface layers 680b, 680c, metal covers 690b, 690c, and Shielding layers 670b and 670c. The difference between the two typical laminate structures shown in FIGS. 6B and 6C lies in the lower layers of the shielding layers 670b and 670c. Referring to FIG. 6B , the enlarged portion 601b shows that the shielding layer 670b may include three sublayers from bottom to top: a wetting sublayer 671b, a shielding sublayer 672b, and a protective sublayer 673b. indicates that there is Three sub-layers of shielding layer 670b are formed on metal cover 690b. In another embodiment 601c shown in Figure 6C, shielding layer 670c may include only two sublayers, respectively a shielding sublayer 672c and a protection sublayer 673c on shielding sublayer 672c.

Similar to the embodiments shown in FIGS. 3 and 4 , the electronic component mounted on the substrate may be a semiconductor package that may include one or more semiconductor dies and/or one or more individual devices. In this situation, a thermal interface layer and a metal cover may also be constructed underneath the shielding layer, see FIGS. 7 and 8 .

Figure 7 shows a semiconductor device 700 according to an embodiment of the present application. Referring to FIG. 7 , in a semiconductor device 700, multiple electronic components are mounted on a substrate 710. That is, the semiconductor package 720, individual devices 740, and dielectric members 750 are mounted on the substrate 710 and are electrically connected to each other through the substrate 710. It can also be seen that the dielectric members 750 can be replaced with a discrete antenna package configuration as shown in FIG. 1D. The semiconductor package 720 may include multiple components as shown in FIG. 7 . In this embodiment, semiconductor package 720 is sealed with encapsulant 760 to form an encapsulant cube. On the periphery of the encapsulant 760 is a thermal interface layer 780 and a metal cover 790, both of which have an area equal to the top surface of the encapsulant cube. Shielding layer 770 further covers the top surface of metal shroud 790, the lateral surfaces of metal shroud 790, the lateral surfaces of thermal interface layer 780, and the lateral surfaces of the encapsulant cube. It can be seen that shielding layer 770 may be the same or similar to shielding layer 501b or 501c shown in FIGS. 5B and 5C. It can be seen that such a configuration can be adapted to a semiconductor package configuration as shown in FIG. 3B.

Figure 8 shows a semiconductor device 800 according to an embodiment of the present application. 8, an encapsulant 860 is shown exposing the top surface of at least one electronic component within a semiconductor package 820 mounted on a substrate. Similar to semiconductor device 600 shown in Figure 6A, thermal interface layer 880 contacts the top surfaces of two semiconductor dies 822 exposed from encapsulant 860. Other electronic components of semiconductor package 820 are left covered by encapsulant 860 . A metal cover 890 is disposed on the thermal interface layer 880, both of which have the same area as the top surface of the encapsulant cube formed by the encapsulant 860. Shielding layer 870 further covers the top surface of metal shroud 890, the lateral surfaces of metal shroud 890, the lateral surfaces of thermal interface layer 880, and the lateral surfaces of the encapsulant cube. It can be seen that the shielding layer 870 of the semiconductor device 800 may be the same or similar to the shielding layer 601b or 601c shown in FIGS. 6B and 6C. It can be seen that such a configuration can be adapted to a semiconductor package configuration as shown in FIG. 3B.

9A-10F, the steps for manufacturing the semiconductor device described above are illustrated. Note that the sequential order illustrated below represents only some of the embodiments and may be adapted to specific scenarios.

FIG. 9A is a flow chart illustrating a method 900 for manufacturing a semiconductor device according to an embodiment of the present application. Herein, a substrate is first provided in block 901 and then at least one electronic component is mounted thereon in block 902. An encapsulant is then formed on the substrate at block 903 to at least partially encapsulate the at least one electronic component. A shielding layer is formed in block 904, a thermal interface layer is formed in block 905, and a metal cover is formed in block 906. Of note, as illustrated in the above embodiments, the formation of the shielding layer may occur before the formation of the thermal interface layer in block 904 and the metal cover in block 905, or after these two blocks. There may be. Of note, when a semiconductor package containing multiple electronic components is mounted on a substrate, some or all of the semiconductor package may be sealed in advance.

9B-9E illustrate various steps for fabricating a semiconductor device according to the method shown in FIG. 9A on a provided substrate 910. As shown in Figure 9B, a substrate 910 is provided on which a plurality of electronic components such as two semiconductor dies 920, individual devices 930, 940 and dielectric members 950 are provided, for example. It is first mounted by soldering paste printing and reflow. Then, in Figure 9C, an encapsulant 960 is formed by molding to encapsulate some of the aforementioned electronic components, such as two semiconductor dies 920 and individual devices 930. Next, in Figure 9D, a shielding layer 970 is deposited, preferably by sputtering, for example, completely covering the encapsulant 960 and the encapsulated electronic components. Then, in Figure 9E, thermal interface layer 980 is disposed on shielding layer 970 by dispensing. Next, in Figure 9F, a metal cover 990 is attached on the thermal interface layer 980.

In method 1000, formation of shielding layer 1004 may follow formation of thermal interface layer 1005 and formation of metal cover 1006 as previously mentioned. Of note, when a semiconductor package containing multiple electronic components is mounted on a substrate, a portion of the semiconductor package may be pre-sealed.

Figures 10B-10F illustrate various steps for manufacturing a semiconductor device according to the method shown in Figure 10A. As shown in FIG. 10B, a substrate 1010 is provided on which a plurality of electronic components such as two semiconductor dies 1020, individual devices 1030, 1040 and dielectric members 1050 are provided, for example. It is first mounted by soldering paste printing and reflow. Then, in Figure 10C, an encapsulant 1060 is formed by molding to encapsulate some of the aforementioned electronic components, such as two semiconductor dies 1020 and individual devices 1030. The two steps described above are similar to method 900. Next, in Figure 10D, a thermal interface layer 1080, preferably covering the top surface of the encapsulated electronic components and encapsulant 1060, is disposed, for example by dispensing. Next in Figure 10E, a metal cover 1090 is attached on the thermal interface layer 1080. Finally, a shielding layer 1070 of FIG. 10F is deposited, for example by sputtering, preferably completely covering the thermal interface layer 1080, metal cover 1090, encapsulant 1060 and encapsulated electronic components. .

It can be seen that the steps described above in FIGS. 9B to 9F and 10B to 10F can be adapted to any of the semiconductor devices described above in FIGS. 1A to 8.

From the above examples it can be seen that the present application includes a laminate structure of a shield, a thermal interface layer and a metal cover. These structures introduce thermal management into the semiconductor device without affecting the general structure of the typical semiconductor device. Accordingly, the present application provides a thermally managed semiconductor device and is widely applicable.

The discussion herein has included numerous illustrative drawings illustrating various portions of a semiconductor device and method of manufacturing the same. For clarity of illustration, these drawings do not depict all aspects of each example assembly. Any of the example assemblies and/or methods provided herein may share any or all characteristics with any or all other assemblies and/or methods provided herein.

Various embodiments have been described herein with reference to the accompanying drawings. However, it will be apparent that various modifications and changes may be made to the various embodiments and additional embodiments may be implemented without departing from the broader scope of the invention as set forth in the following claims. will be. Additionally, other embodiments will be apparent to those skilled in the art from consideration of this specification and practice of one or more embodiments of the invention disclosed herein. Accordingly, it is intended that this application and the examples herein are to be regarded as illustrative only, and that the true scope and spirit of the invention is indicated by the following listing of the exemplary claims.

Claims (36)

As a semiconductor device,
Board;
at least one electronic component mounted on the substrate;
a sealant formed on the substrate and at least partially sealing the at least one electronic component;
a shielding layer formed on the encapsulant;
a thermal interface layer formed on the shielding layer; and
A semiconductor device comprising a metal lid formed on the thermal interface layer. According to paragraph 1,
The shielding layer:
wet sublayer; and
A semiconductor device comprising a shielding sublayer formed on the wet sublayer. According to paragraph 2,
The semiconductor device of claim 1, wherein the shielding layer further comprises a protective sublayer formed on the shielding sublayer. According to paragraph 3,
A semiconductor device wherein the protective sublayer comprises stainless steel, an organic solderability preservative, or nickel. According to paragraph 2,
the wet sublayer comprises stainless steel or titanium;
The semiconductor device of claim 1, wherein the shielding sublayer comprises copper. According to paragraph 1,
A semiconductor device wherein the at least one electronic component includes one or more semiconductor die and one or more discrete devices. According to paragraph 1,
The semiconductor device wherein the encapsulant is configured such that a top surface of the at least one electronic component is exposed from the encapsulant and contacts the shielding layer. According to paragraph 1,
The semiconductor device of claim 1, wherein the encapsulant is configured to cover a top surface and lateral surfaces of the at least one electronic component. According to paragraph 1,
A semiconductor device wherein the thermal interface layer includes solder paste. As a semiconductor device,
Board;
at least one electronic component mounted on the substrate;
a sealant formed on the substrate and at least partially sealing the at least one electronic component;
A thermal interface layer formed on the encapsulant;
a metal cover formed on the thermal interface layer; and
A semiconductor device comprising a shielding layer formed on the substrate and covering the metal lid, the thermal interface layer, and the encapsulant. According to clause 10,
The shielding layer:
shielding sublayer; and
A semiconductor device comprising a protective sublayer formed on a wet sublayer. According to clause 11,
The semiconductor device of claim 1, wherein the shielding layer further comprises a wetting sublayer formed beneath the shielding sublayer. According to clause 12,
A semiconductor device wherein the wet sublayer comprises stainless steel or titanium. According to clause 11,
the shielding sublayer comprises copper;
A semiconductor device wherein the protective sublayer comprises stainless steel, an organic solderability preservative, or nickel. According to clause 10,
A semiconductor device wherein the at least one electronic component includes one or more semiconductor die and one or more discrete devices. According to clause 10,
The semiconductor device wherein the encapsulant is configured such that a top surface of the at least one electronic component is exposed from the encapsulant and contacts the shielding layer. According to clause 10,
The semiconductor device of claim 1, wherein the encapsulant is configured to cover a top surface and lateral surfaces of the at least one electronic component. According to clause 10,
A semiconductor device wherein the thermal interface layer includes solder paste. As a method for manufacturing a semiconductor device,
providing a substrate;
mounting at least one electronic component on the substrate;
forming an encapsulant on the substrate and at least partially encapsulating the at least one electronic component;
forming a shielding layer on the encapsulant;
forming a thermal interface layer on the shielding layer; and
A method comprising forming a metal cap over the thermal interface layer. According to clause 19,
The shielding layer:
wet sublayer; and
A method comprising a shielding sublayer formed on said wetting sublayer. According to clause 20,
The method of claim 1, wherein the shielding layer further comprises a protective sublayer formed on the shielding sublayer. According to clause 21,
wherein the protective sublayer comprises stainless steel, an organic solderability preservative, or nickel. According to clause 20,
the wet sublayer comprises stainless steel or titanium;
The method of claim 1, wherein the shielding sublayer comprises copper. According to clause 19,
The method of claim 1, wherein the at least one electronic component includes one or more semiconductor die and one or more discrete devices. According to clause 19,
The method of claim 1 , wherein the encapsulant is configured such that a top surface of the at least one electronic component is exposed from the encapsulant and contacts the shielding layer. According to clause 19,
The method of claim 1, wherein the encapsulant is configured to cover a top surface and lateral surfaces of the at least one electronic component. According to clause 19,
The method of claim 1, wherein the thermal interface layer includes solder paste. As a method for manufacturing a semiconductor device,
providing a substrate;
mounting at least one electronic component on the substrate;
forming an encapsulant on the substrate and at least partially encapsulating the at least one electronic component;
forming a thermal interface layer on the encapsulant;
forming a metal cap over the thermal interface layer; and
A method comprising forming a shielding layer on the substrate and covering the metal lid, the thermal interface layer, and the encapsulant. According to clause 28,
The shielding layer:
shielding sublayer; and
A method comprising a protective sublayer formed on a wet sublayer. According to clause 29,
The method of claim 1, wherein the shielding layer further comprises a wetting sublayer formed beneath the shielding sublayer. According to clause 30,
wherein the wet sublayer comprises stainless steel or titanium. According to clause 29,
the shielding sublayer comprises copper;
wherein the protective sublayer comprises stainless steel, an organic solderability preservative, or nickel. According to clause 28,
The method of claim 1, wherein the at least one electronic component includes one or more semiconductor die and one or more discrete devices. According to clause 28,
The method of claim 1 , wherein the encapsulant is configured such that a top surface of the at least one electronic component is exposed from the encapsulant and contacts the shielding layer. According to clause 28,
The method of claim 1, wherein the encapsulant is configured to cover a top surface and lateral surfaces of the at least one electronic component. According to clause 28,
The method of claim 1, wherein the thermal interface layer includes solder paste.

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