KR20230169885A - Persistent memory and computing system - Google Patents

Abstract

Persistent memory devices and computing systems with improved efficiency are provided. The persistent memory device includes a main controller for receiving and transmitting data through a CXL interface, a buffer memory for receiving and storing data from the main controller and transmitting data to the main controller, a plurality of first non-volatile memories, and a plurality of first non-volatile memories. A first storage device including a first sub-controller for controlling volatile memories, a plurality of second non-volatile memories and a second sub-controller different from the first sub-controller for controlling the plurality of second non-volatile memories. It includes a storage device, wherein the main controller receives information about how to flush data stored in the buffer memory to the first storage device and the second storage device from the host device, and based on this, the first sub-controller and the second sub-controller Controls the operation of

Description

Persistent memory device and computing system {PERSISTENT MEMORY AND COMPUTING SYSTEM}

The present invention relates to persistent memory devices and computing systems.

When a device using NAND flash using the CXL (Compute express link) interface is used as a memory device, high availability (HA) and durability must be guaranteed beyond that of storage devices using conventional NAND flash.

The technical problem to be solved by the present invention is to provide a persistent memory device and computing system with improved efficiency.

The technical problems of the present invention are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the description below.

A persistent memory device according to some embodiments of the present invention for achieving the above technical problem includes a main controller that receives and transmits data through a CXL interface, a buffer that receives and stores data from the main controller, and transmits data to the main controller. A first storage device including a memory, a plurality of first non-volatile memories and a first sub-controller for controlling the plurality of first non-volatile memories, a plurality of second non-volatile memories and a first sub-controller for controlling the plurality of second non-volatile memories. A second storage device including a second sub-controller different from the first sub-controller, wherein the main controller receives information about how to flush data stored in the buffer memory from the host device to the first storage device and the second storage device. It is received, and the operations of the first sub-controller and the second sub-controller are controlled based on this.

A computing system according to some embodiments of the present invention for achieving the above technical problem includes a main controller that receives and transmits data through a host device and a CXL interface, a main controller that receives a GPF command from the host, and a main controller that receives data from the main controller. a persistent memory device including a buffer memory for storing and transmitting data to a main controller, a first storage device, and a second storage device, wherein the host device determines an operation mode of the persistent memory device and issues a GPF command. The main controller controls the operation of the first storage device and the second storage device, and receives a GPF command from the host device to transfer at least part of the data stored in the buffer memory to the first storage device. and flushing to the second storage device.

Specific details of other embodiments are included in the detailed description and drawings.

1 is an exemplary diagram for explaining a computing system to which a persistent memory device is applied according to some embodiments.
2 to 6 are exemplary diagrams for explaining the operation of a persistent memory device according to some embodiments.
FIG. 7 is an exemplary diagram for explaining a server system to which a persistent memory device is applied according to some embodiments.

Hereinafter, embodiments according to the technical idea of the present invention will be described with reference to the attached drawings.

1 is an exemplary diagram for explaining a computing system to which a persistent memory device is applied according to some embodiments.

Referring to FIG. 1 , the computing system 1000 may include a host device 10, a CXL interface 200, and a persistent memory device 100. In some embodiments, computing system 1000 may be used for user devices such as a personal computer, laptop computer, server, media player, digital camera, etc., or for navigation, a black box, or a vehicle. It may be included in automotive devices such as electronic devices. Alternatively, the computing system 1000 may be a mobile device such as a portable communication terminal (mobile phone), a smart phone, a tablet personal computer (PC), a wearable device, a healthcare device, or an IOT (internet of things) device. ) may be a system.

The host device 10 may include a host processor 11, a host memory 12, and a CXL host interface circuit 13. The host processor 11 can control overall operations of the computing system 1000. In some embodiments, the host processor 11 may be one of various processors, such as a central processing unit (CPU), a graphics processing unit (GPU), a neural processing unit (NPU), a data processing unit (DPU), etc. In some embodiments, host processor 11 may each include a single core processor or a multi-core processor. In some embodiments, the host processor 11 may be one of a number of modules included in an application processor (AP), and the application processor may be implemented as a system on chip (SOC). You can.

The host memory 12 is a working memory and can store instructions, programs, or data necessary for the operation of the host processor 11. Alternatively, the host memory 12 may temporarily store data to be transferred to the persistent memory device 100 and/or the CXL storage device (not shown), or data transferred from the persistent memory device 100 and/or the CXL storage device. It can function as a buffer memory for When the host processor 11 is implemented as an AP, the host memory 12 may be an embedded memory provided within the AP, or may be a non-volatile memory or memory module disposed outside the AP. According to some embodiments, the host processor 11 and the host memory 12 may be implemented as separate semiconductor chips. Alternatively, in some embodiments, the host processor 11 and the host memory 12 may be integrated into the same semiconductor chip.

CXL host interface circuit 13 may communicate with persistent memory device 100 and CXL storage device through CXL interface 200.

The persistent memory device 100 may include a main controller 110, a buffer memory 120, a first storage device 130, and a second storage device 140. The persistent memory device 100 may be used as main memory or system memory of the computing system 1000. The persistent memory device 100 may be connected to the host device 10 through the CXL interface 200. The main controller 110 may receive data from or transmit data to the host device 10 through the CXL interface 200. The main controller 110 may receive commands from the host device 10 through the CXL interface 200. The buffer memory 120 can receive data from the main controller 110 and store it. The buffer memory 120 may transmit data to the main controller 110. The first storage device 130 may include a first sub-controller 131 and a plurality of first non-volatile memories 132_1 to 132_3. Although three first non-volatile memories are shown in FIG. 1, the embodiment is not limited thereto. The first sub-controller 131 may manage a plurality of first non-volatile memories 132_1 to 132_3 under the control of the main controller 110. The first sub-controller 131 may flush data stored in the buffer memory 120 to the first non-volatile memories 132_1 to 132_3 under the control of the main controller 110. The second storage device 140 may include a second sub-controller 141 and a plurality of second non-volatile memories 142_1 to 142_3. Although three second non-volatile memories are shown in FIG. 1, the embodiment is not limited thereto. The second sub-controller 141 may manage a plurality of second non-volatile memories 142_1 to 142_3 under the control of the main controller 110. The second sub-controller 141 may flush data stored in the buffer memory 120 to the plurality of second non-volatile memories 142_1 to 142_3 under the control of the main controller 110.

Although not shown, computing system 1000 may further include a CXL storage device. A CXL storage device may include a CXL storage controller and non-volatile memories. The CXL storage controller may store data in each non-volatile memory or transmit data stored in each non-volatile memory to the host device 10 under the control of the host device 10. In some embodiments, the non-volatile memories may be, but are not limited to, NAND flash memory.

In some embodiments, host device 10, persistent memory device 100, and CXL storage device may be configured to share the same interface with each other. For example, the host device 10, persistent memory device 100, and CXL storage device may communicate with each other through a CXL interface 200 (compute express link interface). In some embodiments, the CXL interface 200 supports coherency, memory access, and dynamic protocol muxing of the input/output protocol (IO protocol) to support accelerators, memory It may refer to a low-latency and high-bandwidth link that enables various connections between devices or various electronic devices.

Hereinafter, for convenience of explanation, it is assumed that the host device 10, the persistent memory device 100, and the CXL storage device communicate with each other through the CXL interface 200. However, the embodiment is not limited thereto, and the host device 10, persistent memory device 100, and CXL storage device are connected to each other based on various computing interfaces such as GEN-Z protocol, NVLink protocol, CCIX protocol, Open CAPI protocol, etc. Can communicate.

The CXL interface 200 may include a sub-protocol CXL.io, CXL.cache, and CXL.mem. The CXL.io protocol is a PCIe transaction layer and can be used in the computing system 1000 to discover devices, manage interrupts, provide access by registers, handle initialization, and handle signal errors. The CXL.cache protocol can be used when an accelerator (e.g., a GPU or a field programmable gate array (FPGA)) accesses the host memory 12. The CXL.mem protocol allows the host device 10 to access the accelerator's dedicated memory or It may be used when accessing the buffer memory 120 of the persistent memory device 100.

In some embodiments, host device 10, persistent memory device 100, and CXL storage device may communicate with each other using CXL.io, an input/output protocol. CXL.io may have an inconsistent input/output protocol based on PCIe. The host device 10, persistent memory device 100, and CXL storage device can exchange various information including user data with each other using CXL.io.

FIG. 2 is an example diagram for explaining the operation of a persistent memory device according to some embodiments.

Referring to FIG. 2, a buffer memory 120 and a first storage device 130 are shown. Although only the first storage device 130 is shown in FIG. 2, the description of the first storage device 130 may be equally applied to the second storage device 140.

The first sub-controller 131 of the first storage device 130 includes a first sub-interface circuit 131_1, a first sub-processor 131_2, a first sub-memory 131_3, and a first flash translation layer. ; FTL) (131_4) and a first error correction code (ECC) engine (131_5) (hereinafter referred to as ECC engine). The first sub-controller 131 may be connected to the buffer memory 120 and the main controller 110 through the first sub-interface circuit 131_1. The first sub-controller 131 can receive various commands from the main controller 110 through the first sub-interface circuit 131_1, and the buffer memory 120 can receive various commands through the first sub-interface circuit 131_1. Data may be flushed to the plurality of first non-volatile memories 132_1 to 132_3. The first sub-interface circuit 131_1 may be implemented to comply with standard protocols such as Toggle or Open NAND Flash Interface (ONFI). The first subprocessor 131_2 may be configured to control overall operations of the first subcontroller 131. The first sub-memory 131_3 may store an address mapping table that stores information that can convert a logical block address into a physical address of non-volatile memory. The first sub-memory 131_3 may be a high-speed memory such as DRAM for fast access. The first flash conversion layer 131_4 may perform various management operations to efficiently use the plurality of first non-volatile memories 132_1 to 132_3. For example, the first flash conversion layer 131_4 converts the logical address managed by the host device 10 based on the address mapping table and the physical address used in the plurality of first non-volatile memories 132_1 to 132_3. Address conversion can be performed. The first flash conversion layer 131_4 may perform a bad block management operation on the first non-volatile memories 132_1 to 132_3. The first flash conversion layer 131_4 may perform a wear leveling operation on non-volatile memory (NVM). Additionally, the first flash conversion layer 131_4 may perform a garbage collection operation on the plurality of first non-volatile memories 132_1 to 132_3.

In some embodiments, the first flash conversion layer 131_4 may be implemented based on software, hardware, firmware, or a combination thereof. When the first flash conversion layer 131_4 is implemented in the form of software or firmware, program codes related to the first flash conversion layer 131_4 may be stored in the first sub-memory 131_3, and the first sub-processor 131_2 ) can be driven by. When the first flash conversion layer 131_4 is implemented as hardware, hardware configurations configured to perform the various management operations described above may be implemented in the first storage device 130.

The first ECC engine 131_5 may detect and correct errors on data stored in the plurality of first non-volatile memories 132_1 to 132_3. For example, the first ECC engine 131_5 may generate parity bits for data to be stored in the plurality of first non-volatile memories 132_1 to 132_3, and the generated parity bits may be stored together with the data. It may be stored in a plurality of first non-volatile memories 132_1 to 132_3. When data is read from the plurality of first non-volatile memories 132_1 to 132_3, the first ECC engine 131_5 reads the parity bits read from the plurality of first non-volatile memories 132_1 to 132_3 together with the read data. Using this, you can detect and correct errors in data.

The plurality of first non-volatile memories 132_1 to 132_3 of the first storage device 130 may include flash memory. Flash memory may include a 2D NAND memory array or a 3D (or vertical) NAND (VNAND) memory array. As another example, the plurality of first non-volatile memories may be various types of non-volatile memories. For example, the plurality of first non-volatile memories (132_1 to 132_3) include Magnetic RAM (MRAM), Spin-Transfer Torque MRAM (MRAM), Conductive bridging RAM (CBRAM), Ferroelectric RAM (FeRAM), and PRAM ( It can be Phase RAM, Resistive RAM, and various other types of memory.

FIG. 3 is an example diagram for explaining the operation of a persistent memory device according to some embodiments.

Referring to FIG. 3, a buffer memory 120, a first storage device 130a, and a second storage device 140a are shown. The buffer memory 120 may receive a plurality of data from the main controller 110 and store them. The main controller 110 receives a global persistent flush (GPF) command from the host device 10 and transfers part of the data stored in the buffer memory 120 to a plurality of first non-volatile memories 132a_1 through the first sub-controller 131a. to 132a_3) can be flushed. The main controller 110 receives a global persistent flush (GPF) command from the host device 10 and transfers part of the data stored in the buffer memory 120 to a plurality of second non-volatile memories 142a_1 through the second sub-controller 141a. to 142a_3) can be flushed.

According to some embodiments, the host device 10 may transmit a command (CMD_MODE1) to the main controller 110 of the persistent memory device 100 to operate the persistent memory device 100 in a first operation mode. The main controller 110 receives the CMD_MODE1 command and transfers the first data (DATA_1) among the plurality of data stored in the buffer memory 120 to the plurality of first data through the first sub-controller 131a and the second sub-controller 141a. Flushing may be performed in the non-volatile memories 132a_1 to 132a_3 and the plurality of second non-volatile memories 142a_1 to 142a_3. In an environment where the first storage device or the second storage device operates normally in the first operation mode, data flushed to the plurality of first non-volatile memories 132a_1 to 132a_3 and the plurality of second non-volatile memories 142a_1 to 142a_3 may be the same. Here, the 'normally operating environment' refers to the first sub-controller 131a of the first storage device 130a, the plurality of first non-volatile memories 132a_1 to 132a_3, or other components of the first storage device 130a. This indicates that an error has occurred and a plurality of data stored in the buffer memory 120 cannot be flushed to the first non-volatile memories 132a_1 to 132a_3. The same applies to the second storage device 140a. Hereinafter, description of 'normally operating environment' will be omitted.

FIG. 4 is an example diagram for explaining the operation of a persistent memory device according to some embodiments.

Referring to FIG. 4 , according to some embodiments, the first storage device 130a may not operate normally. For example, if the first sub-controller 131a of the first storage device 130a is damaged or for other reasons, a plurality of data stored in the buffer memory 120 may be flushed to the plurality of first non-volatile memories 132a_1 to 132a_3. memory cells constituting the plurality of first non-volatile memories 132a_1 to 132a_3 may be deteriorated or may not be able to store data for other reasons. If the first storage device 130a does not operate normally while operating in the first mode, the main controller 110 detects this and manages it to the second sub-controller 141a of the second storage device 140a that operates normally. A Management Transfer (MF) command (CMD_MF) can be transmitted. Additionally, the main controller 110 provides the second sub-controller 141a of the normally operating second storage device 140a with an address mapping table stored in the first sub-memory (131_3 in FIG. 2) of the first sub-controller 131a. The physical address of the last mapped data among the existing information can be transmitted to the second sub-controller 141a. Thereafter, the main controller 110 may deactivate the first sub-controller 131a, which does not operate normally. The second sub-controller 141a of the normally operating second storage device 140a receives the CMD_MF command and the physical address of the last mapped data and operates the plurality of first non-volatile memories 132a_1 to 132a_1. The last mapped data from 132a_3) can be loaded. Accordingly, the second sub-controller 141a can manage the plurality of first non-volatile memories 132a_1 to 132a_3 and the plurality of second non-volatile memories 142a_1 to 142a_3.

According to some embodiments, the main controller 110 flushes the same data to two storage devices, so that even if one storage device fails and the data in the failed storage device is lost, the same data is preserved in the other storage device. High availability of the persistent memory device 100 can be guaranteed.

According to some embodiments, the main controller 110 transfers management of a plurality of non-volatile memories of a failed storage device to a normally operating storage device, thereby preventing waste of memory space due to a storage device failure. there is.

FIG. 5 is an example diagram for explaining the operation of a persistent memory device according to some embodiments.

Referring to FIG. 5, a buffer memory 120, a first storage device 130b, and a second storage device 140b are shown. The buffer memory 120 may receive a plurality of data from the main controller 110 and store them. The main controller 110 receives a global persistent flush (GPF) command from the host device 10 and transfers part of the data stored in the buffer memory 120 to a plurality of first non-volatile memories 132b_1 through the first sub-controller 131b. to 132b_3) can be flushed. The main controller 110 receives a global persistent flush (GPF) command from the host device 10 and transfers part of the data stored in the buffer memory 120 to a plurality of second non-volatile memories 142b_1 through the second sub-controller 141b. to 142b_3) can be flushed.

According to some embodiments, the host device 10 may transmit a command (CMD_MODE2) to the main controller 110 of the persistent memory device 100 to operate the persistent memory device 100 in a second operation mode. The main controller 110 receives the CMD_MODE2 command and transfers the second data (DATA_2) among the plurality of data stored in the buffer memory 120 to the plurality of first non-volatile memories 132b_1 to 132b_3 through the first sub-controller 131b. Can be flushed. The main controller 110 receives the CMD_MODE2 command, generates snapshots of the plurality of data stored in the buffer memory 120 at specific cycles, and generates a plurality of second non-volatile memories 142b_1 to 142b_1 through the second sub-controller 141b. Snapshots created in 142b_3) can be flushed. The main controller 110 may receive information about a specific period for creating a snapshot from the host device 10 through the CXL interface 200. While operating in the second operation mode, the first storage device 130b may not operate normally. In this case, the second storage device 140b may operate in the same manner as the first operation mode described above. Since this has been explained previously, detailed explanation will be omitted.

In the case of NAND flash memory, the number of times internal memory cells can be written may be limited due to deterioration of the memory cells. According to some embodiments, data may be flushed to the plurality of second non-volatile memories 142b_1 to 142b_3 of the second storage device 140b at specific cycles rather than in real time. Accordingly, the number of writes of the second storage device 140b can be reduced, and through this, the durability of the second storage device 140b can be increased. As a result, high availability of the persistent memory device 100 can be guaranteed.

According to some embodiments, data may be flushed to the plurality of second non-volatile memories 142b_1 to 142b_3 of the second storage device 140b at specific cycles rather than in real time. Through this, the power usage required for flushing can be reduced compared to flushing in real time.

FIG. 6 is an example diagram for explaining the operation of a persistent memory device according to some embodiments.

Referring to FIG. 6, a buffer memory 120, a first storage device 130c, and a second storage device 140c are shown. The buffer memory 120 may receive a plurality of data from the main controller 110 and store them. The main controller 110 receives a global persistent flush (GPF) command from the host device 10 and transfers part of the data stored in the buffer memory 120 to a plurality of first non-volatile memories 132c_1 through the first sub-controller 131c. to 132c_3) can be flushed. The main controller 110 receives a global persistent flush (GPF) command from the host device 10 and transfers part of the data stored in the buffer memory 120 to a plurality of second non-volatile memories 142c_1 through the second sub-controller 141c. to 142c_3) can be flushed.

According to some embodiments, the host device 10 may transmit a command (CMD_MODE3) to the main controller 110 of the persistent memory device 100 to operate the persistent memory device 100 in a third operation mode. The main controller 110 receives the CMD_MODE3 command and transfers the third data (DATA_3) among the plurality of data stored in the buffer memory 120 to the plurality of first non-volatile memories 132c_1 to 132c_3 through the first sub-controller 131c. Can be flushed. The main controller 110 receives the CMD_MODE3 command and transfers the third data (DATA_3) and the fourth data (DATA_4), which are different from the plurality of data stored in the buffer memory 120, to the plurality of second data through the second sub-controller 141c. Flushing may be performed to non-volatile memory (142c_1 to 142c_3).

According to some embodiments, as described above, the first storage device 130c may not operate normally. In this case, the second storage device 140c may operate in the same manner as the first operation mode described above. Since this has been explained previously, detailed explanation will be omitted.

It is well known that non-volatile memories such as NAND flash generally have slower read/write speeds than volatile memories such as DRAM. According to some embodiments, since each storage device flushes different data, the write speed of flushing data from the buffer memory 120 to the storage device and the read speed of loading data from the storage device to the buffer memory 120 are theoretically can be doubled. In conclusion, it is possible to prevent speed reduction due to the difference in bandwidth between the buffer memory 120 and the storage device.

According to some embodiments, the main controller 110 transfers management of a plurality of non-volatile memories of a failed storage device to a normally operating storage device, thereby preventing waste of memory space due to a storage device failure. there is.

FIG. 7 is an exemplary diagram for explaining a server system to which a persistent memory device is applied according to some embodiments.

Referring to FIG. 7, the server system 3000 is a system that collects various data and provides services. The server system 3000 may be a system for operating a search engine and database, or may be a computing system used in companies such as banks or government agencies. Server system 3000 may include application servers 3100 to 3100n and data storage servers 3200 to 3200m. The number of application servers 3100 to 3100n and the number of data storage servers 3200 to 3200m can be selected in various ways depending on the embodiment, and the number of application servers 3100 to 3100n and the data storage servers ( 3200 to 3200 m) may be different.

The application server 3100 or the data storage server 3200 may include at least one of processors 3110 and 3210 and memories 3120 and 3220. Taking the data storage server 3200 as an example, the processor 3210 can control the overall operation of the data storage server 3200, accesses the memory 3220, and executes instructions and/or instructions loaded into the memory 3220. Data can be run. The processor 3210 may be, for example, the host device (10 in FIG. 1) described above. The memory 3220 may include, for example, the previously described persistent memory device (100 in FIG. 1), Double Data Rate Synchronous DRAM (DDR SDRAM), High Bandwidth Memory (HBM), Hybrid Memory Cube (HMC), and Dual In-Memory (DIMM). line Memory Module), Optane DIMM, or Non-Volatile DIMM (NVMDIMM). Depending on the embodiment, the number of processors 3210 and memories 3220 included in the data storage server 3200 may be selected in various ways.

In some embodiments, processor 3210 and memory 3220 may provide a processor-memory pair. In some embodiments, the number of processors 3210 and memories 3220 may be different. Processor 3210 may include a single core processor or a multi-core processor. The above description of the data storage server 3200 can be similarly applied to the application server 3100. Depending on the embodiment, the application server 3100 may not include the server data storage device 3150. The data storage server 3200 may include at least one server data storage device 3250. The number of server data storage devices 3250 included in the data storage server 3200 may be selected in various ways depending on the embodiment.

Application servers 3100 to 3100n and data storage servers 3200 to 3200m may communicate with each other through a network 3300. The network 3300 may be implemented using Fiber Channel (FC) or Ethernet. At this time, FC is a medium used for relatively high-speed data transmission, and an optical switch that provides high performance/high availability can be used. Depending on the access method of the network 3300, the data storage servers 3200 to 3200m may be provided as file storage, block storage, or object storage.

In some embodiments, network 3300 may be a storage-only network, such as a storage area network (SAN). For example, the SAN may be an FC-SAN that uses an FC network and is implemented according to the FC Protocol (FCP). As another example, the SAN may be an IP-SAN that uses a TCP/IP network and is implemented according to the iSCSI (SCSI over TCP/IP or Internet SCSI) protocol. In other embodiments, network 3300 may be a general network, such as a TCP/IP network. For example, the network 3300 may be implemented according to protocols such as FC over Ethernet (FCoE), Network Attached Storage (NAS), and NVMe over Fabrics (NVMe-oF).

Hereinafter, the description will focus on the application server 3100 and the data storage server 3200. The description of the application server 3100 may also be applied to other application servers 3100n, and the description of the data storage server 3200 may also be applied to other data storage servers 3200m.

The application server 3100 may store data requested by a user or client to be stored in one of the data storage servers 3200 to 3200m through the network 3300. Additionally, the application server 3100 may obtain data requested to be read by a user or client from one of the data storage servers 3200 to 3200m through the network 3300. For example, the application server 3100 may be implemented as a web server or a database management system (DBMS).

The application server 3100 may access a memory 3120n or a server data storage device 3150n included in another application server 3100n through the network 3300, or a data storage server (3150n) through the network 3300. You can access embedded memory (3220-3220m) or server data storage (3250-3250m). Accordingly, the application server 3100 can perform various operations on data stored in the application servers 3100-3100n and/or the data storage servers 3200-3200m. For example, the application server 3100 may execute a command to move or copy data between the application servers 3100-3100n and/or the data storage servers 3200-3200m. At this time, the data passes from the server data storage devices (3250-3250m) of the data storage servers (3200-3200m) through the memories (3220-3220m) of the data storage servers (3200-3200m), or directly to the application servers. (3100-3100n) can be moved to memory (3120-3120n). Data moving through the network 3300 may be encrypted data for security or privacy.

Taking the data storage server 3200 as an example, the interface 3254 may provide a physical connection between the processor 3210 and the controller 3251 and a physical connection between the NIC 3240 and the controller 3251. For example, the interface 3254 may be implemented in a Direct Attached Storage (DAS) method that directly connects the server data storage device 3250 with a dedicated cable. Additionally, for example, the interface 3254 may include Advanced Technology Attachment (ATA), Serial ATA (SATA), external SATA (e-SATA), Small Computer Small Interface (SCSI), Serial Attached SCSI (SAS), and Peripheral ATA (PCI). Component Interconnection), PCIe (PCI express), NVMe (NVM express), IEEE 1394, USB (universal serial bus), SD (secure digital) card, MMC (multi-media card), eMMC (embedded multi-media card), It can be implemented in various interface methods such as Universal Flash Storage (UFS), embedded Universal Flash Storage (eUFS), and compact flash (CF) card interface.

The data storage server 3200 may further include a switch 3230 and a NIC 3240. The switch 3230 can selectively connect the processor 3210 and the server data storage device 3250, or selectively connect the NIC 3240 and the server data storage device 3250, under the control of the processor 3210. there is.

In some embodiments, NIC 3240 may include a network interface card, network adapter, etc. The NIC 3240 may be connected to the network 3300 by a wired interface, a wireless interface, a Bluetooth interface, an optical interface, etc. The NIC 3240 may include internal memory, DSP, a host bus interface, etc., and may be connected to the processor 3210 and/or the switch 3230 through the host bus interface. The host bus interface may be implemented as one of the examples of interface 3254 described above. In one embodiment, the NIC 3240 may be integrated with at least one of the processor 3210, the switch 3230, and the server data storage device 3250.

In the data storage server (3200-3200m) or application server (3100-3100n), the processor sends a command to the server data storage device (3130-3130n, 3250-3250m) or memory (3120-3120n, 3220-3220m) to store data. It can be programmed or led. At this time, the data may be error-corrected data through an ECC (Error Correction Code) engine. The data is data that has been processed through Data Bus Inversion (DBI) or Data Masking (DM), and may include Cyclic Redundancy Code (CRC) information. The data may be encrypted for security or privacy.

The server data storage devices 3150-3150m and 3250-3250m may transmit control signals and command/address signals to the NAND flash memory devices 3252-3252m in response to read commands received from the processor. Accordingly, when reading data from the NAND flash memory device (3252-3252m), the RE (Read Enable) signal is input as a data output control signal and can serve to output data to the DQ bus. DQS (Data Strobe) can be generated using the RE signal. Command and address signals can be latched in the page buffer depending on the rising edge or falling edge of the WE (Write Enable) signal.

The controller 3251 can generally control the operation of the server data storage device 3250. In one embodiment, the controller 3251 may include Static Random Access Memory (SRAM). The controller 3251 may write data to the NAND flash 3252 in response to a write command, or may read data from the NAND flash 3252 in response to a read command. For example, the write command and/or read command may be transmitted to processor 3210 in data storage server 3200, processor 3210m in another data storage server 3200m, or processor 3110, 3110n in application server 3100, 3100n. ) can be provided from. The DRAM 3253 may temporarily store (buffer) data to be written to the NAND flash 3252 or data read from the NAND flash 3252. Additionally, the DRAM 3253 can store metadata. Here, metadata is data generated by the controller 3251 to manage user data or NAND flash 3252. The server data storage device 3250 may include a Secure Element (SE) for security or privacy.

In some embodiments, memories 3120 to 3120n may be used as main memory or system memory of the application server 3100. The memories 3220 to 3220n may be used as main memory or system memory of the data storage server 3200. Taking the application server 3100 as an example, the memory 3120 may be connected to the processor 3110 through a CXL interface (200 in FIG. 1). The memory 3120 may receive data from or transmit data to the processor 3110 through the CXL interface (200 in FIG. 1). The memory 3120 may receive commands from the processor 3110 through the CXL interface 200.

Memory 3120 may include non-volatile memory cells, such as NAND flash memory. The processor 3110 may determine the operation mode of the memory 3120. For example, the processor 3110 may control the memory 3120 to operate in any one of the first to third operation modes described above. The memory 3120 may flush data into non-volatile memory cells according to a mode determined by the processor 3110.

Although embodiments of the present invention have been described above with reference to the attached drawings, the present invention is not limited to the above embodiments and can be manufactured in various different forms, and can be manufactured in various different forms by those skilled in the art. It will be understood by those who understand that the present invention can be implemented in other specific forms without changing its technical spirit or essential features. Therefore, the embodiments described above should be understood in all respects as illustrative and not restrictive.

Host devices: 10 Persistent memory devices: 100
CXL interface: 200 Compute system: 1000
Server systems: 3000

Claims (10)

A main controller that receives and transmits data through the CXL interface;
a buffer memory that receives and stores data from the main controller and transmits data to the main controller;
a first storage device including a plurality of first non-volatile memories and a first sub-controller that controls the plurality of first non-volatile memories; and
A second storage device including a plurality of second non-volatile memories and a second sub-controller that is different from the first sub-controller that controls the plurality of second non-volatile memories,
The main controller is,
Receiving information on how to flush data stored in the buffer memory to the first storage device and the second storage device from a host device, and controlling the operations of the first sub-controller and the second sub-controller based on this information Permanent memory device. According to claim 1,
The first sub-controller and the second sub-controller are:
Includes a first sub-memory and a second sub-memory each storing an address mapping table,
The main controller is,
If the operation of the first sub-controller is impossible, a management transfer command is transmitted to the second sub-controller, and the physical address of the last mapped data stored in the first sub-memory of the first sub-controller is transferred to the second sub-controller. Permanent memory transfer to a device. According to clause 2,
The main controller is,
A persistent memory device wherein the second sub-controller, which has received the management transfer command, controls the plurality of first non-volatile memories and the plurality of second non-volatile memories. According to claim 1,
The buffer memory is,
Receiving and storing a plurality of data including first data from the main controller,
The main controller is,
A persistent memory device for flushing the first data to the plurality of first non-volatile memories. According to clause 4,
The main controller is,
A persistent memory device for flushing the first data to the plurality of second non-volatile memories. According to clause 4,
The main controller is,
Create a snapshot of a plurality of data stored in the buffer memory,
A persistent memory device for flushing snapshots of the plurality of data to the plurality of second non-volatile memories. According to clause 6,
The main controller is,
A persistent memory device that receives information about a cycle for generating snapshots of a plurality of data stored in the buffer memory from a host device. According to claim 1,
The buffer memory is,
Receiving and storing a plurality of data including second data and third data from the main controller,
The main controller is,
Flushing the second data into the plurality of first non-volatile memories,
A persistent memory device for flushing the third data that is different from the second data into the plurality of second non-volatile memories. host device; and
A main controller that receives and transmits data through the CXL interface and receives GPF commands from the host,
A buffer memory that receives and stores data from the main controller and transmits data to the main controller,
a persistent memory device including a first storage device and a second storage device;
The host device is,
Determining an operation mode of the persistent memory device and controlling a flushing operation of the persistent memory device through the GPF command,
The main controller is,
Controlling operations of the first storage device and the second storage device, receiving the GPF command from the host device and flushing at least a portion of data stored in the buffer memory to the first storage device and the second storage device A computing system that does. According to clause 9,
The host device is,
A computing system that determines a period for generating a snapshot of data stored in the buffer memory when the persistent memory device operates in a second operation mode among the operation modes.

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