KR20230166622A - Display Device For High-Speed Driving And Driving Method Therefor - Google Patents

Abstract

A display device according to an embodiment of the present specification includes a display panel provided with a plurality of pixels; a timing controller that generates current control information based on a transition degree of image data to be written to the pixels; and a plurality of output buffers for outputting a target data voltage corresponding to the image data to data output channels connected to the pixels, each of the output buffers having a preset rising voltage for output of the target data voltage. an amplifier output unit that applies current or polling current to an output node connected to one of the data output channels; and a slew rate adjuster that selects an additional rising current or an additional falling current according to the current control information to adjust the time at which the additional rising current or an additional falling current is applied to the output node in order to increase the output slew rate of the target data voltage. Includes.

Description

Display device for high-speed driving and driving method therefor {Display Device For High-Speed Driving And Driving Method Therefor}

This specification relates to a high-speed driving display device and a driving method thereof.

Recently, display devices for high-speed driving have been proposed to be suitable for high-resolution and high-speed driving.

The power consumption characteristics and data charging/discharging characteristics required for high-speed display devices are in a trade-off relationship. In the case of existing high-speed display devices, it is difficult to satisfy both power consumption characteristics and data charging and discharging characteristics.

Accordingly, this specification provides a display device and a driving method thereof that can improve both power consumption characteristics and data charging/discharging characteristics.

A display device according to an embodiment of the present specification includes a display panel provided with a plurality of pixels; a timing controller that generates current control information based on a transition degree of image data to be written to the pixels; and a plurality of output buffers for outputting a target data voltage corresponding to the image data to data output channels connected to the pixels, each of the output buffers having a preset rising voltage for output of the target data voltage. an amplifier output unit that applies current or polling current to an output node connected to one of the data output channels; and a slew rate adjuster that selects an additional rising current or an additional falling current according to the current control information to adjust the time at which the additional rising current or an additional falling current is applied to the output node in order to increase the output slew rate of the target data voltage. Includes.

A method of driving a display device according to an embodiment of the present specification includes generating current control information based on the transition degree of image data to be written to pixels; and outputting a target data voltage corresponding to the image data to data output channels connected to the pixels, wherein outputting the target data voltage to data output channels connected to the pixels includes: Applying a preset rising current or falling current to output a data voltage to an output node connected to one of the data output channels; And selecting an additional rising current or an additional falling current according to the current control information to increase the output slew rate of the target data voltage and adjusting the time at which the additional rising current or additional falling current is applied to the output node. do.

The embodiments of this specification have the following effects.

The embodiment of the present specification improves both power consumption characteristics and data charge/discharge characteristics by setting the amplifier bias current (Isum) according to normal transition conditions and selectively enabling additional current sources for output channels with a large degree of data transition. You can do it.

The embodiment of the present specification selectively enables an additional current source for rising or an additional current source for falling according to the direction of data transition for each pixel, and adjusts the enable time of the additional current source according to the degree of data transition. By doing so, power consumption characteristics and data charging/discharging characteristics can be efficiently improved.

In the embodiment of the present specification, since the additional current source of the individual output buffer can be controlled using the EPI protocol, the operation of the additional current source can be controlled without adding a separate controller.

The effects according to the present specification are not limited to the contents exemplified above, and further various effects are included in the present specification.

1 is a diagram showing a display device according to an embodiment of the present specification.
FIG. 2 is a diagram showing the connection relationship between a source driver integrated circuit and data lines in a display device according to an embodiment of the present specification.
Figure 3 is a diagram showing a source driver integrated circuit in a display device according to an embodiment of the present specification.
FIG. 4 is a diagram showing an output circuit included in a source driver integrated circuit in a display device according to an embodiment of the present specification.
FIG. 5 is a diagram showing the relationship between a power control signal and an amplifier bias current in the main bias unit included in the output circuit of FIG. 4.
Figure 6 is a diagram showing the relationship between amplifier bias current and transition time.
Figures 7 to 9 are diagrams for explaining changes in output of data voltage according to the operation of an additional current source for rising.
10 to 12 are diagrams for explaining changes in the output of data voltage according to the operation of an additional current source for polling.
Figure 13 is a flowchart of a method of driving a display device according to an embodiment of the present specification.
FIG. 14 is a flowchart showing a method of setting the first control information determined in step S30 of FIG. 13 and transmitting it to the EPI formatter.
FIG. 15 is a flowchart showing a method of setting the second control information determined in step S40 of FIG. 13 and transmitting it to the EPI formatter.
FIG. 16 is a diagram illustrating an EPI transmission data format including current control information according to the first embodiment of the present specification.
FIG. 17 is a diagram illustrating the structure of first current control information and second current control information included in the EPI transmission data format of FIG. 16.
FIG. 18 is a diagram showing an example of setting the first current control information included in the EPI transmission data format of FIG. 16.
FIG. 19 is a diagram showing an example of setting the second current control information included in the EPI transmission data format of FIG. 16.
Figure 20 is a diagram showing the EPI transmission data format including current control information according to the second embodiment of the present specification.
Figures 21 and 22 are diagrams illustrating the structure of third current control information included in the EPI transmission data format of Figure 20.
FIG. 23 is a diagram showing an example of setting third current control information included in the EPI transmission data format of FIG. 20.
Figures 24 and 25 are diagrams showing the transition time reduction rate before and after application of the present invention in each of a plurality of power control modes.

The advantages and features of the present specification and methods for achieving them will become clear by referring to the embodiments described in detail below along with the accompanying drawings. However, the present specification is not limited to the embodiments disclosed below and will be implemented in various different forms, but the present embodiments only serve to ensure that the disclosure of the present specification is complete, and that common knowledge in the technical field to which this specification pertains is provided. It is provided to fully inform those who have the scope of the invention, and this specification is only defined by the scope of the claims.

The shape, size, ratio, angle, number, etc. disclosed in the drawings for explaining the embodiments of the present specification are illustrative, and the present specification is not limited to the matters shown. Like reference numerals refer to like elements throughout the specification. When 'includes', 'has', 'consists of', etc. mentioned in the specification are used, other parts may be added unless '~ only' is used. When a component is expressed in the singular, the plural is included unless specifically stated otherwise.

When interpreting a component, it is interpreted to include the margin of error even if there is no separate explicit description.

In the case of a description of a positional relationship, for example, if the positional relationship between two parts is described as 'on top', 'on top', 'at the bottom', 'next to ~', 'right next to' Alternatively, there may be one or more other parts placed between the two parts, unless 'directly' is used.

First, second, etc. may be used to describe various components, but these components are not limited by these terms. These terms are merely used to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the technical idea of the present specification.

Like reference numerals refer to substantially like elements throughout the specification. Hereinafter, embodiments of the present specification will be described in detail with reference to the attached drawings. In the following description, if it is determined that a detailed description of a known function or configuration related to the present specification may unnecessarily obscure the gist of the present specification, the detailed description will be omitted.

1 is a diagram showing a display device according to an embodiment of the present specification. And, Figure 2 is a diagram showing the connection relationship between the source driver integrated circuit and data lines in the display device according to an embodiment of the present specification.

1 and 2, a display device according to an embodiment of the present specification includes an electroluminescent display panel (PNL), a timing controller (CONT), a data driving circuit (DDRV), and a gate driving circuit (GDRV). It can be implemented as a display device or liquid crystal display device.

The display panel (PNL) is provided with a plurality of data lines (DL) and a plurality of gate lines (GL), and pixels (PIX) can be arranged in the intersection area of these signal lines (GL, DL). there is. A pixel array may be formed in the display area of the display panel PNL by pixels PIX arranged in a matrix form.

In a pixel array, pixels (PIX) are adjacent to each other in the horizontal direction to form a horizontal line. The number of horizontal lines becomes the vertical resolution of the display panel (PNL). Pixels (PIX) constituting the same horizontal line are connected to the same gate line (GL) and are connected to different data lines (DL). Each pixel (PIX) may be implemented as a light-emitting cell including a light-emitting diode, or as a liquid crystal cell including a liquid crystal layer.

The timing controller (CONT) operates a data driving circuit (DDRV) based on timing signals such as the vertical synchronization signal (Vsync), horizontal synchronization signal (Hsync), and data enable signal (DE) input from the host system (not shown). A data timing control signal (DDC) for controlling the operation timing of and a gate timing control signal (GDC) for controlling the operation timing of the gate driving circuit (GDRV) can be generated. The gate timing control signal (GDC) may include a gate start signal, gate shift clocks, etc. The data timing control signal (DDC) includes a source start pulse, a source sampling clock, and a source output enable signal.

The timing controller (CONT) transmits image data (DATA) input from the host system to the data driving circuit (DDRV) through an internal interface circuit. The image data (DATA) is for image display in the pixels (PIX), and is converted to a data voltage in the data driving circuit (DDRV) and then written to the pixels (PIX). The internal interface circuit may be an Embedded Panel Interface (EPI) circuit.

The timing controller (CONT) compares the image data (DATA) in units of horizontal lines to derive the transition degree of the image data (DATA) in pixel units, and then generates current control information based on the transition degree of the image data (DATA). do. The timing controller (CONT) configures the data timing control signal (DDC), current control information, and video data (DATA) in EPI transmission format and then transmits them to the data driving circuit (DDRV).

The gate driving circuit (GDRV) generates a scan signal (SCAN) based on the gate timing control signal (GDC) from the timing controller (CONT) and supplies this scan signal (SCAN) to the gate lines (GL). The horizontal line on which the data voltage will be written is selected by the scan signal (SCAN). The gate driving circuit (GDRV) may be built into the non-display area of the display panel (PNL) according to the gate-in-panel (GIP) method. The non-display area may be located outside the panel array in the display panel (PNL).

The data driving circuit (DDRV) may include at least one source driver integrated circuit (SD-IC). The source driver integrated circuit (SD-IC) separates the data timing control signal (DDC), current control information, and image data (DATA) in the EPI transmission format received from the timing controller (CONT). The source driver integrated circuit (SD-IC) converts image data (DATA) into data voltage based on the data timing control signal (DDC), and then converts this data voltage to the data line through the data output channels (CH1 to CHn). It is supplied to fields (DL1~DLn). At this time, the source driver integrated circuit (SD-IC) selectively additionally controls the output slew rate of the data voltage in the data output channels (CH1 to CHn) according to the current control information, thereby improving both power consumption characteristics and data charge/discharge characteristics. It can be improved.

FIG. 3 is a diagram showing a source driver integrated circuit (SD-IC) in a display device according to an embodiment of the present specification.

Referring to FIG. 3, the source driver integrated circuit (SD-IC) may include a control logic circuit 300, a latch circuit 310, a D/A conversion circuit 320, and an output circuit 330.

The control logic circuit 300 samples bits of control data from signals received through the EPI transmission format according to the internal clock timing, and controls the operation of the source driver integrated circuit (SD-IC) from the sampled control data. Restore the data timing control signal (DDC) to do this.

The control logic circuit 300 samples image data from a signal received through a serial-type EPI transmission format according to the internal clock timing. The control logic circuit 300 samples and restores current control information (CON1 to CONn) from signals received through the EPI transmission format according to the internal clock timing. Current control information (CON1~CONn) is set and restored independently for each data output channel. Current control information (CON1 to CONn) includes transition direction information for selecting additional rising current or additional falling current within the output circuit 330, and on time ( On time) information.

The transition direction information refers to the transition direction of the data voltage and may include a first logic value indicating an upward transition and a second logic value indicating a downward transition. The transition direction information serves as a standard for selecting an enabled additional current from among the additional rising current or the additional falling current within the output circuit 330. When a first logic value indicating an upward transition is input to the output circuit 330, additional rising current is enabled, and when a second logic value indicating a downward transition is input, an additional falling current is enabled and additional current is supplied. . If additional rising current is enabled in the output circuit 330, the upward transition time of the data voltage may be reduced, and if additional falling current is enabled, the downward transition time of the data voltage may be reduced.

On time information serves as a standard for setting the enable maintenance time of the additional current selected by the transition direction information. The on-time information may be set so that the enable maintenance time of the additional current increases as the transition amount of the data voltage increases. For example, when a first logic value indicating an upward transition is input to the output circuit 330, additional rising current is enabled, and the enable maintenance time of the additional rising current is determined according to on-time information. As the upward transition amount of the data voltage increases, the transition time can be reduced by increasing the enable maintenance time of the additional rising current. In the same way, when a second logic value indicating a downward transition is input to the output circuit 330, the additional polling current is enabled, and the enable maintenance time of the additional polling current is determined according to the on-time information. As the downward transition amount of the data voltage increases, the downward transition time can be reduced by increasing the enable maintenance time of the additional polling current. Meanwhile, when the transition amount of the data voltage is small within the reference range, the on-time information is set to disable both the additional rising current and the additional falling current.

In the case of a liquid crystal display, transition direction information may include a vertical polarity control signal. The polarity of the data voltage is inverted for each horizontal line by the vertical polarity control signal. If the polarity of the data voltage is higher than the common voltage, it becomes positive polarity. Conversely, if it is lower than the common voltage, it becomes negative polarity. The vertical polarity control signal serves as a standard for selecting whether to enable an additional rising current or an additional falling current within the output circuit 330. When a first logic value indicating an upward transition is input to the output circuit 330, additional rising current is enabled, and when a second logic value indicating a downward transition is input, an additional falling current is enabled and additional current is supplied. . If additional rising current is enabled in the output circuit 330, the upward transition time of the data voltage may be reduced, and if additional falling current is enabled, the downward transition time of the data voltage may be reduced.

On-time information can be set according to the degree of transition of the data voltage. The larger the transition amount of the data voltage, the longer the enable state of the additional current can be maintained, thereby reducing the transition time. However, if the transition amount of the data voltage is small within the standard range, both the additional rising current and the additional falling current are disabled regardless of the transition direction.

The latch circuit 310 converts the bits of image data sampled by the control logic circuit 300 into a parallel type data system. The latch circuit 310 is synchronized according to the internal clock output from the control logic circuit 300.

The D/A conversion circuit 320 generates a data voltage by converting image data converted into a parallel type data system into a gamma compensation voltage.

The output circuit 330 includes a plurality of output buffers 330-1 to 330-n and outputs target data voltages corresponding to image data to data output channels CH1 to CHn. The output circuit 330 further includes a main bias unit (MBB) commonly connected to the output buffers 330-1 to 330-n. The output slew rate of each of the output buffers 330-1 to 330-n may be controlled according to current control information (CON1 to CONn) individually input from the control logic circuit 300.

FIG. 4 is a diagram showing an output circuit included in a source driver integrated circuit in a display device according to an embodiment of the present specification. FIG. 5 is a diagram showing the relationship between a power control signal and an amplifier bias current in the main bias unit included in the output circuit of FIG. 4. Figure 6 is a diagram showing the relationship between amplifier bias current and transition time.

Referring to FIG. 4, the output circuit 330 includes output buffers 330-1 to 330-n commonly connected to the main bias unit MBB.

The main bias unit MBB determines the size of the amplifier bias current Isum according to the preset power control signals LLL and HHH and commonly applies it to the output buffers 330-1 to 330-n.

The main bias unit (MBB) is connected between the high-potential voltage source (NH) and the low-potential voltage source (NL) to generate a reference current (Iref) and an amplifier bias current (Isum) based on the reference current (Iref). It includes a bias circuit unit that outputs. The bias circuit unit includes mirror units (M1, M2) that mirror the reference current (Iref) and current adjustment units (A1 to Ak) that determine the size of the bias current (Isum) according to the power control signal (PWRC). The channel capacitance of the transistors (A1 to Ak) constituting the current adjustment unit may be different, and for example, the channel capacitance of the kth transistor (Ak) may be larger than that of the first transistor (A1).

As an example, the power control signal (PWRC) may be composed of eight control signals (LLL to HHH) as shown in FIG. 5. These control signals (LLL to HHH) correspond to each of the eight power control modes and can turn on any one of the transistors (A1 to A8). In the first power control mode, the first transistor A1 is turned on according to the control signal LLL and the amplifier bias current Isum becomes the reference current Iref. In the fifth power control mode, the fifth transistor (A5) is turned on according to the control signal (HLL), and the amplifier bias current (Isum) becomes 5*reference current (Iref). Likewise, in the eighth power control mode, the eighth transistor (A8) is turned on according to the control signal (HHH) and the amplifier bias current (Isum) becomes 8*reference current (Iref).

The power control signal PWRC determines the transition time at which the amplifier outputs of the output buffers 330-1 to 330-n change to the target voltage level TL, as shown in FIG. 6. The larger the amplifier bias current (Isum), the shorter the transition time. For example, the transition time is t1 in the control signal (HHH), t2 (t2>t1) in the control signal (HLL), and t3 (t3>t2) in the control signal (LLL).

Each of the output buffers 330-1 to 330-n includes an amplifier (AMP) having an input stage (ISTG) and an amplifier output section, and a slew rate adjustment section that generates an additional rising current (Iadd_R) and an additional falling current (Iadd_F). (Rising current source, falling current source, SA, SB). Here, TA is any one of TA1 to TAn, TB is any one of TB1 to TBn, and AMP is any one of AMP1 to AMPn. And, Iadd_R is any one of Iadd_R1 to Iadd_Rn, Iadd_F is any one of Iadd_F1 to Iadd_Fn, SA is any one of SA1 to SAn, and SB is any one of SB1 to SBn.

The input stage (ISTG) sinks the bias current (Isum). The input stage (ISTG) may be implemented as a Single ended Differential Amp, but is not limited thereto. The amplifier output unit applies a rising current or falling current corresponding to the bias current (Isum) to the output node (NO) connected to one of the data output channels (CH1 to CHn) according to the transition direction information or the vertical polarity control signal. Here, NO is any one of NO1 to NOn.

The amplifier output unit includes a pull-up transistor (TA) for sourcing the rising current from the high-potential voltage source (NH) to the output node (NO), and a falling current from the output node (NO) to the low-potential voltage source (NL). Includes a pull-down transistor (TB) for sinking.

The pull-up transistor (TA) is turned on for the upward transition of the data voltage and sources the rising current to the output node (NO), and the pull-down transistor (TB) is turned on for the upward transition of the data voltage. Sinking the polling current with the potential voltage source (NL).

The slew rate adjustment unit receives current control information (CON) from the control logic circuit 300. Here, CON is any one of CON1 to CONn. The slew rate adjuster increases the output slew rate of the target data voltage by selectively applying additional rising current (Iadd_R) or additional falling current (Iadd_F) to the output node (NO) according to the current control information (CON).

The slew rate adjustment unit includes a first additional current source that generates an additional rising current (Iadd_R), and a first additional current source that is turned on or off according to the current control information (CON) to control the current flow between the first additional current source and the output node (NO). A switch (SA), a second additional current source that generates an additional polling current (Iadd_F), and a second additional current source that is turned on or off according to the current control information (CON) to control the current flow between the second additional current source and the output node (NO) 2 Includes additional switch (SB).

The first additional switch (SA) and the second additional switch (SB) are selected according to the transition direction information of the current control information (CON) and remain in the on state according to the on-time information. However, even if the first additional switch (SA) or the second additional switch (SB) is selected according to the transition direction information, if the on-time information is set to disable all additional current, the first additional switch (SA) and the second additional switch All switches (SB) are turned off.

Figure 7 is a diagram for explaining the circuit operation when operating the additional current source for rising, Figure 8 is a diagram for explaining the output change of the data voltage according to the supply of additional rising current, and Figure 9 is the supply maintenance time of the additional rising current. This is a diagram to explain the change in output of data voltage according to .

As shown in FIG. 7, while the first additional switch (SA) is turned on, the first additional current source and the first additional switch (SA) are connected in series with each other between the high potential voltage source (NH) and the output node (NO). At this time, the first additional current source and the pull-up transistor (TA) are connected in parallel with each other between the high-potential voltage source (NH) and the output node (NO), and as a result, the rising current (IR) by the pull-up transistor (TA) ) and the total rising current (IR+Iadd_R) obtained by adding the additional rising current (Iadd_R) by the first additional current source is applied to the output node (NO). Compared to the rising current (IR), the total rising current (IR+Iadd_R) advances the transition time for the amplifier output to change to the target voltage level (TL_R) by △T, as shown in Figure 8, and as a result, the output slew rate of the data voltage is It can be improved. Additionally, by adjusting the time during which the additional rising current (Iadd_R) is enabled, as shown in FIG. 9, the size of the total rising current (IR+Iadd_R) can be adjusted according to the size of the output voltage (Vout) of the amplifier. For example, when the first additional switch (SA) is turned on and the time for enabling the additional rising current (Iadd_R) increases to 100%, 120%, and 150%, the size of the total rising current (IR+Iadd_R) also increases to the rising current ( It may increase depending on the time when Iadd_R) is enabled. As the size of the output voltage (Vout) of the amplifier increases, the size of the total rising current (IR+Iadd_R) also increases. By adjusting the enable time of the rising current (Iadd_R), TL1 (Iadd_R 100%), TL2 (Iadd_R 120%) , can be increased to TL3 (Iadd_R 150%). The larger the amplifier's output voltage (Vout), the shorter the transition time for the amplifier's output to change to the target voltage level. Therefore, the larger the transition amount between the previous data voltage and the current data voltage, the more the enable time of the additional rising current (Iadd_R) increases. Transition time can be shortened. On the other hand, if the amount of transition between the previous data voltage and the current data voltage is relatively small, and the size of the total rising current (IR+Iadd_R) is too large, the amplifier's output voltage (Vout) will be lower than the target voltage level due to overcharging. An overshoot phenomenon that outputs at a higher voltage may occur. Therefore, by adjusting the time when the additional rising current (Iadd_R) is enabled according to the amount of transition between previous data and current data, the slew rate can be improved while ensuring output stability, and power efficiency can be improved. there is.

FIG. 10 is a diagram for explaining the circuit operation during operation of the additional polling current source, FIG. 11 is a diagram for explaining the change in output of the data voltage according to the supply of additional polling current, and FIG. 12 is the supply maintenance time of the additional polling current. This is a diagram to explain the change in output of data voltage according to .

As shown in FIG. 10, while the second additional switch SB is turned on, the second additional current source and the second additional switch SB are connected in series between the low-potential voltage source NL and the output node NO. At this time, the second additional current source and the pull-down transistor (TB) are connected in parallel with each other between the low-potential voltage source (NL) and the output node (NO), and as a result, the falling current (IF) by the pull-down transistor (TB) ) and the total polling current (IF+(Iadd_F)) obtained by adding the additional polling current (Iadd_F) by the second additional current source is applied to the output node (NO). Compared to the polling current (IF), the total polling current (IF+(Iadd_F)) advances the transition time for the amplifier output to change to the target voltage level (TL_F) by △T, as shown in Figure 11, and as a result, the output slew rate of the data voltage This can be improved. In addition, by adjusting the time when the additional polling current (Iadd_R) is enabled as shown in FIG. 12, the size of the total polling current (IR+Iadd_F) can be adjusted according to the size of the output voltage (Vout) of the amplifier. For example, when the second additional switch (SB) is turned on and the time for enabling the additional polling current (Iadd_F) increases to 100%, 120%, and 150%, the size of the total polling current (IR+Iadd_F) may also increase. there is. As the size of the output voltage (Vout) of the amplifier increases, the size of the total polling current (IR+Iadd_F) also adjusts the enable time of the additional polling current (Iadd_F) to IF1 (Iadd_F 100%) and IF2 (Iadd_F 120%). , the decline may increase with TF3 (Iadd_F 150%). Therefore, by adjusting the time at which the additional polling current (Iadd_F) is enabled according to the amount of transition between previous data and current data, the output slew rate can be improved while ensuring output stability, and power efficiency can be improved.

As such, since this embodiment includes a slew rate adjuster, the amplifier bias current (Isum) is set to match the normal transition condition, and the enable time of the additional current source is adjusted according to the transition condition to improve power consumption characteristics and data charging/discharging. Stability of output can be guaranteed while improving characteristics.

FIG. 13 is a flowchart of a method of driving a display device according to an embodiment of the present specification, and is a diagram showing the operation of a timing controller that generates current control information based on the transition degree of image data.

Referring to FIG. 13, when R (Red), G (Green), and B (Blue) image data are input (S10), the timing controller outputs the N-1 (N is a natural number) line image data and the N-th line image data. is compared for each R, G, and B subpixel of each output channel to calculate the data transition amount (DATA_△) for each R, G, and B subpixel (S20).

The timing controller sets the first current control information to select the additional rising current (Iadd_R) or the additional falling current (Iadd_F) according to the plus (+)/minus (-) sign of the data transition amount (DATA_△) ( S30). If the data transition amount (DATA_△) is positive (+) (DATA_△>0), the transition direction of the output data of the corresponding subpixel can be determined to be the rising direction, and the data transition amount (DATA_△) is In case of minus (-) (DATA_△<0), the transition direction of the output data of the corresponding subpixel can be determined to be a falling direction. Accordingly, the timing controller can set the first current control information indicating the transition direction of the output data, and the first current control information can be a standard for selecting the additional rising current (Iadd_R) or the additional falling current (Iadd_F). .

Once the transition direction of the output data is determined, the timing controller sets second current control information that determines the on time of the additional current according to the size of the data transition amount (DATA_△) (S40). The larger the data transition amount (DATA_△), the longer the on time can be set to improve charge/discharge characteristics. Accordingly, the timing controller sets the second current control information so that the on time of the additional current is set according to the data transition amount (DATA_△), and when the data transition amount (DATA_△) is within the standard range, the additional current is disabled. Second current control information can be set.

The timing controller may format current control information (CON) including the first and second current control information of RGB data for each subpixel into EPI transmission data and then transmit it to the source driver integrated circuit (S50).

FIG. 14 is a flowchart showing a method of setting the first current control information determined in step S30 of FIG. 13 and transmitting it to the EPI formatter.

Referring to FIG. 14, after calculating the data transition amount (DATA_△) for each R, G, and B subpixel of the N-1 (N is a natural number) line image data and the N-th line image data (S20), the data transition Determine the plus (+)/minus (-) sign of the quantity (DATA_△) (S300).

If the data transition amount (DATA_△) is positive (+) (DATA_△>0), the first current control information (CTR_1) can be set to '01' or '1' (S310).

When the data transition amount (DATA_△) is negative (-) (DATA_△<0), the first current control information (CTR_1) can be set to '10' or '0' (S320).

The first current control information (CTR_1) may be output to the EPI formatter and reflected in the EPI transmission data (S50).

As described above, the first current control information (CTR_1) includes transition direction information of output data and can be a standard for selecting an additional rising current source or an additional falling current source. The above-described embodiment illustrates the case where the first current control information (CTR_1) is displayed as a 1-bit ('1' or '0') or 2-bit ('01' or '10') logical value. It is not limited.

FIG. 15 is a flowchart showing a method of setting the second current control information (CTR_2) determined in step S40 of FIG. 13 and transmitting it to the EPI formatter.

The timing controller may set second current control information (CTR_2) indicating the on time of the additional current source according to the data transition amount (DATA_△). The second current control information (CTR_2) according to the data transition amount (DATA_△) may be stored in the internal memory of the timing controller or may be stored in an external memory. In the memory for setting the second current control information (CTR_2), the data transition amount (DATA_△) may be divided into a plurality of sections and logical values corresponding to the sections may be stored. The flowchart of FIG. 15 divides the data transition amount (DATA_△) into four sections based on the first to third reference values (V _TH 1 to V _TH 3), and displays each section as a 2-bit logical value. The case is exemplified, but is not limited to this.

Referring to FIG. 15, after calculating the data transition amount (DATA_△) for each R, G, and B subpixel of the N-1 (N is a natural number) line image data and the N-th line image data (S20), the data transition Depending on the size of the amount (DATA_△), the on time of the additional current can be determined (S400~S420).

The timing controller determines whether the data transition amount (DATA_△) is less than the first reference value (V _TH 1) (S400). The first reference value (V _TH 1) is a gray scale value expressed in 3 bits and can be set in the 16 to 96 Gray scale range.

If the data transition amount (DATA_△) is less than the first reference value (V _TH 1) (DATA_△<V _TH 1), the second current control information (CTR_2) can be set to '00' (CTR_2=00)( S405).

If the data transition amount (DATA_△) is greater than the first reference value (V _TH 1), it is determined whether the data transition amount (DATA_△) is less than the second reference value (V _TH 2) (S410). The second reference value (V _TH 2) is a gray scale value expressed in 3 bits and can be set in the 104 to 160 Gray scale range.

If the data transition amount (DATA_△) is less than the second reference value (V _TH 2) (V _TH 1<DATA_△<V _TH 2), the second current control information (CTR_2) can be set to '01' (CTR_2 =01)(S415).

If the data transition amount (DATA_△) is greater than the second reference value (V _TH 2), it is determined whether the data transition amount (DATA_△) is less than the third reference value (V _TH 3) (S420). The third reference value (V _TH 2) is a gray scale value expressed in 3 bits and can be set in the 168 to 224 Gray scale range.

If the data transition amount (DATA_△) is smaller than the third reference value (V _TH 3) (V _TH 2<DATA_△<V _TH 3), the second current control information (CTR_2) can be set to '10' (CTR_2 =10)(S425).

If the data transition amount (DATA_△) is greater than the third reference value (V _TH 3), the second current control information (CTR_2) can be set to '11' (CTR_2 = 11) (S430).

The second current control information (CTR_2) may be output to the EPI formatter and reflected in the EPI transmission data (S50).

The timing controller may format the current control information (CON) including the first current control information (CTR_1) and the second current control information (CTR_2) into EPI transmission data and then transmit it to the source driver integrated circuit.

As described above, according to this embodiment, the transition amount (DATA_△) of image data for each R, G, and B subpixel is calculated, and a current including additional rising current or additional falling current and on-time information of the corresponding current is calculated. After setting the control information, it can be transmitted in EPI transmission data format.

Figures 16 to 19 are diagrams for explaining the EPI transmission data format including current control information according to the first embodiment. FIG. 16 is a diagram illustrating a schematic data structure of the EPI transmission data format according to the first embodiment, and FIG. 17 is a diagram illustrating the structures of the first current control information and the second current control information in FIG. 16. 18 is a diagram showing an example of setting the first current control information, and FIG. 19 is a diagram showing an example of setting the second current control information.

Referring to FIG. 16, in the EPI transmission data format according to the first embodiment of the present invention, 1 packet data includes image data of 1 pixel and first current control information (CTR_1) and second current control information (CTR_2) of the pixel data. ) can be composed of.

For example, 1 packet of R video data includes R video data (R), first current control information (R_CTR_1) indicating the transition direction of output data when supplying R video data (R), and It may include second current control information (R_CTR_2) indicating time (Iadd on time). The 2-bit first current control information (R_CTR_1) is allocated to the clock edge (CLK) (R_CTR_1, Bit[0:1]), and is placed 2 after the 8-bit R video data (R, Bit[2:9]). The second current control information (R_CTR_2, Bit[10:11]) of the bit can be set.

Following 1 packet of R video data, 1 packet of G video data is transmitted, and 1 packet of G video data is also assigned to the first current control information (G_CTR_1) to the clock edge (CLK) (G_CTR_1, Bit[0 :1]), 2 bits of second current control information (G_CTR_2, Bit[10:11]) can be set after 8 bits of G video data (G, Bit[2:9]).

Following 1 packet of G video data, 1 packet of B video data is transmitted, and 1 packet of B video data is also allocated to the clock edge (CLK) with first current control information (B_CTR_1) (B_CTR_1, Bit[0 :1]), 2 bits of second current control information (B_CTR_2, Bit[10:11]) can be set after 8 bits of B video data (B, Bit[2:9]).

FIG. 17 is a diagram illustrating the structures of first current control information and second current control information, FIG. 18 is a diagram showing an example of setting the first current control information, and FIG. 19 is a diagram showing an example of setting the second current control information. This is a drawing that shows.

As shown in FIG. 17, the first current control information (R_CTR_1) indicating the transition direction of the R video data is set to “01” at the clock edge (CLK) for output of the R video data, and as shown in FIG. 18 As shown, the additional rising current (Iadd_R) is turned on and the additional falling current (Iadd_F) is turned off. As the second current control information (R_CTR_2) is set to “01” after the R video data (R), as shown in FIG. 19, when the R video data (R) is output, the additional rising current (Iadd_R) is 100%. It is enabled during the on-time period of .

As shown in FIG. 17, the first current control information (G_CTR_1) indicating the transition direction of the G video data is set to “10” at the clock edge (CLK) for output of the G video data, and as shown in FIG. 18 As shown, the additional falling current (Iadd_F) is turned on and the additional rising current (Iadd_R) is turned off. As the second current control information (G_CTR_2) is set to “10” after the G video data (G), as shown in FIG. 19, the additional polling current (Iadd_F) when outputting the G video data (G) is 120%. It is enabled during the on-time period of .

The EPI transmission data according to the first embodiment is transmitted to the source driver integrated circuit, and the source driver integrated circuit receives the EPI transmission data and restores the first current control information (CTR_1) and the second current control information (CTR_2). The source driver integrated circuit can selectively turn on the additional switch selected according to the first current control information (CTR_1) and maintain the on state of the switch according to the on time set in the second current control information (CTR_2).

Meanwhile, as shown in the table of FIG. 19, when the data transition amount (DATA_Δ) is smaller than the first reference value (V _TH 1), the second current control information (CTR_2) is set to “00”. Accordingly, the source driver integrated circuit disables both the additional rising current (Iadd_R) and the additional falling current (Iadd_F) regardless of the additional current selected by the first current control information (CTR_1) (Iadd = 'Off'). maintain Accordingly, when the second current control information (CTR_2) is set to “00”, all additional switches in the output buffer are kept in the off state. Accordingly, it is possible to prevent an overshoot phenomenon from occurring due to additional current in a channel with a small data transition amount.

Figures 20 to 23 are diagrams for explaining the EPI transmission data format including current control information according to the second embodiment. Figure 20 is a diagram showing a schematic data structure of the EPI transmission data format according to the second embodiment, Figures 21 and 22 are diagrams illustrating the structure of third current control information, and Figure 23 is a diagram showing the third current control This diagram shows an example of information settings.

In the EPI transmission data format according to the above-described first embodiment, transition direction information is set at the clock edge and additional 2 bits are allocated after the image data to set on-time information of an additional current source. On the other hand, the EPI transmission data format according to the second embodiment is different in that 3 bits are additionally allocated after the video data to set additional transition direction information and current source on-time information.

Referring to FIG. 20, the EPI transmission data format according to the second embodiment of the present invention may consist of 1 packet data, a clock edge (CLK), 1 pixel image data, and third current control information (CTR_3). there is. The third current control information (R_CTR_3) may include the transition direction of output data and on-time information of the additional current source.

For example, 1 packet of R video data includes a clock edge (CLK), R video data (R), the transition direction of the output data when supplying the R video data (R), and the on time of the additional current source (Iadd on). It may include third current control information (R_CTR_3) meaning time). 2 bits are allocated to the clock edge (CLK) (CLK, Bit[0:1]), and 3 bits of third current control information (R_CTR_3) are assigned after 8 bits of R image data (R, Bit[2:9]). , Bit[10:12]) can be set. In the 3-bit third current control information (R_CTR_3), the first bit (Bit[10]) is a bit that sets the transition direction of the output data and can be set to '0' or '1'. Afterwards, 2 bits of information may be set, meaning the on time (Iadd on time) of the additional current source. The on-time information (Iadd on time) of the additional current source included in the third current control information (R_CTR_3) may be set in the same manner as the second current control information (CTR_2) illustrated in FIG. 19.

Following 1 packet of R video data, 1 packet of G video data is transmitted, and 1 packet of G video data also includes 2 bits of clock edge (CLK, Bit[0:1]) and 8 bits of G video data. (G, Bit[2:9]) and 3 bits of third current control information (G_CTR_3, Bit[10:12]).

Following 1 packet of G video data, 1 packet of B video data is transmitted, and 1 packet of B video data is also transmitted, along with 2 bits of clock edge (CLK, Bit[0:1]) and 8 bits of B video data. (B, Bit[2:9]) and 3 bits of third current control information (B_CTR_3, Bit[10:12]).

Figures 21 and 22 are diagrams illustrating the structure of the third current control information, and Figure 23 shows the transition direction of the output data set in the first bit (Bit[10]) in the third current control information (R_CTR_3). This is a drawing illustrating information.

As shown in FIG. 21, after the clock edge (CLK) and the R image data, third current control information (R_CTR_3), which indicates the transition direction of the output data and the on time (Iadd on time) of the additional current source, is added. You can. As the first bit (Bit[10]) of the third current control information (R_CTR_3) is set to '1', as shown in FIG. 23, the additional rising current (Iadd_R) is turned on, and the additional falling current (Iadd_F) is turned off. Afterwards, as '01', meaning the on time (Iadd on time) of the additional current source, is set, as illustrated in FIG. 19, when R image data (R) is output, the additional rising current (Iadd_R) is 100% on time period. Enabled for a while.

As shown in FIG. 22, after the clock edge (CLK) and the G image data, the first bit (Bit[10]) of the third current control information (R_CTR_3) is set to '1', As shown in 23, the additional rising current (Iadd_R) is turned on and the additional falling current (Iadd_F) is turned off. Afterwards, as '11', meaning the on time (Iadd on time) of the additional current source, is set, as illustrated in FIG. 19, when R video data (R) is output, the additional rising current (Iadd_R) is 150% of the on time period. Enabled for a while.

Figures 24 and 25 are diagrams showing the transition time reduction rate before and after application of the present invention in each of a plurality of power control modes.

Referring to Figures 24 and 25, this embodiment selects additional rising current or additional falling current according to the direction of data transition and adjusts the on time of the additional current according to the amount of data transition, thereby adjusting the transition time of the corresponding output channel. By shortening it, the output slew rate of the target data voltage can be increased while the current consumption can be reduced.

Through the above-described content, those skilled in the art will be able to see that various changes and modifications can be made without departing from the technical idea of the present specification. Therefore, the technical scope of the present specification is not limited to the content described in the detailed description of the specification, but should be determined by the scope of the patent claims.

PNL: Display panel CONT: Timing controller
DDRV: Data driving circuit GDRV: Gate driving circuit
SD-IC: Source driver integrated circuit 300: Control logic circuit
310: Latch circuit 320: D/A conversion circuit
330: output circuit

Claims (14)

A display panel provided with a plurality of pixels;
a timing controller that generates current control information based on a transition degree of image data to be written to the pixels; and
A plurality of output buffers for outputting a target data voltage corresponding to the image data to data output channels connected to the pixels,
Each of the output buffers is:
an amplifier output unit that applies a preset rising current or falling current to an output node connected to one of the data output channels to output the target data voltage; and
In order to increase the output slew rate of the target data voltage, a slew rate adjuster selects an additional rising current or an additional falling current according to the current control information and adjusts the time at which the additional rising current or additional falling current is applied to the output node. Including display device. According to claim 1,
The amplifier output unit,
a pull-up transistor for sourcing the rising current from a high potential voltage source to the output node; and
A display device including a pull-down transistor for sinking the polling current from the output node to a low-potential voltage source. According to claim 2,
The slew rate adjustment unit,
a first additional current source generating the additional rising current;
a first additional switch that is turned on or off according to the current control information to control current flow between the first additional current source and the output node;
a second additional current source generating the additional polling current; and
A display device including a second additional switch that is turned on or off according to the current control information to control current flow between the second additional current source and the output node. According to claim 3,
The first additional current source and the first additional switch are connected in series with each other between the high potential voltage source and the output node,
The second additional current source and the second additional switch are connected in series between the output node and the low-potential voltage source. According to claim 3,
While the first additional switch is turned on,
The pull-up transistor and the first additional current source are connected in parallel between the high potential voltage source and the output node,
A display device in which a total rising current obtained by adding the rising current and the additional rising current is applied to the output node. According to claim 3,
While the second additional switch is turned on,
The pull-down transistor and the second additional current source are connected in parallel between the output node and the low-potential voltage source,
A display device in which a total polling current obtained by adding the polling current and the additional polling current is applied to the output node. According to claim 3,
The first additional switch and the second additional switch are:
Selectively turned on under a first condition in which the transition degree of the image data exceeds a preset threshold,
A display device that is turned off in a second condition where the transition degree of the image data is less than or equal to the threshold value. According to claim 7,
The first additional switch and the second additional switch are:
A display device in which the turn-on time increases as the transition degree of the image data increases. According to claim 3,
The timing controller is,
N-1 (N is a natural number) line image data and N-th line image data are compared pixel by data output channel, and transition is performed depending on whether the degree of data transition for each pixel according to the comparison exceeds a preset threshold. Generate first current control information indicating direction information, and generate second current control information indicating the time for keeping the first additional switch or the second additional switch in the on state according to the degree of data transition,
The first additional switch and the second additional switch are selectively turned on according to the first current control information and remain on for a time set according to the second current control information. According to clause 9,
The transition direction information includes first state information indicating an upward transition and second state information indicating a downward transition,
In response to the first state information, the first additional switch is turned on and the second additional switch is turned off,
A display device in which the first additional switch is turned off and the second additional switch is turned on in response to the second status information. According to clause 9,
Further comprising a source driver integrated circuit having the plurality of output buffers,
The timing controller transmits the current control information to the source driver integrated circuit through EPI transmission data format,
The EPI transmission data format is,
A display device comprising a clock edge including the first current control information, an image data bit, and an additional bit including the second current control information. According to clause 9,
Further comprising a source driver integrated circuit having the plurality of output buffers,
The timing controller transmits the current control information to the source driver integrated circuit through EPI transmission data format,
The EPI transmission data format is,
A display device comprising a clock edge, an image data bit, and additional bits including the first current control information and the second current control information. According to claim 1,
It further includes a main bias unit that determines the size of the amplifier bias current according to a preset power control signal,
A display device in which the magnitude of the rising current and the falling current is proportional to the magnitude of the amplifier bias current. generating current control information based on the transition degree of image data to be written to pixels; and
A step of outputting a target data voltage corresponding to the image data to data output channels connected to the pixels,
The step of outputting the target data voltage to data output channels connected to the pixels includes:
applying a preset rising current or falling current to an output node connected to one of the data output channels to output the target data voltage; and
Display including the step of selecting an additional rising current or an additional falling current according to the current control information in order to increase the output slew rate of the target data voltage and adjusting the time at which the additional rising current or additional falling current is applied to the output node. How to operate the device.