KR20230161320A - Display apparatus - Google Patents

Abstract

One embodiment of the present invention includes a sub-pixel circuit disposed in a display area and including a plurality of transistors, electrically connected to one of the plurality of transistors of the sub-pixel circuit, and extending along a first direction in the display area. A light emitting diode including a data line, a voltage layer having a width greater than the width of the data line and overlapping the data line, a first electrode overlapping the voltage layer, a light emitting layer on the first electrode, and a second electrode on the light emitting layer. Disclosed is a display device including:

Description

Display apparatus {Display apparatus}

Embodiments of the present invention relate to display devices.

In a display panel such as an organic light emitting display panel, thin film transistors are disposed in the display area to control the brightness of light emitting diodes. Thin film transistors control the corresponding light emitting diode to emit light of a predetermined color using the transmitted data signal, driving voltage, and common voltage.

In order to provide data signals, driving voltages, common voltages, etc., data driving circuits, driving voltage supply lines, common voltage supply lines, etc. are located in the non-display area outside the display area.

One embodiment of the present invention can provide a display device capable of providing high quality images. The purpose of the present invention is not limited thereto.

One embodiment of the present invention includes a sub-pixel circuit disposed in a display area and including a plurality of transistors; a data line electrically connected to one of the plurality of transistors of the subpixel circuit and extending along a first direction in the display area; a voltage layer having a width greater than the width of the data line and overlapping the data line; and a light emitting diode including a first electrode overlapping the voltage layer, a light emitting layer on the first electrode, and a second electrode on the light emitting layer.

The voltage layer may include a transparent conductive material.

It may further include a common voltage line disposed in the display area and electrically connected to the second electrode of the light emitting diode, and the voltage layer may have the same voltage level as the common voltage line.

The common voltage line includes a first common voltage line and a second common voltage line extending to intersect each other in the display area, and the voltage layer may correspond to a portion of the first common voltage line.

It further includes an insulating layer interposed between the voltage layer and one selected from a first common voltage line and a second common voltage line, wherein the voltage layer is electrically connected to the selected one through a contact hole defined in the insulating layer. You can.

It may further include a driving voltage line disposed in the display area and electrically connected to the sub-pixel circuit, and the voltage layer may have the same voltage level as the driving voltage line.

The driving voltage line includes a first driving voltage line and a second driving voltage line extending to intersect each other in the display area, and the voltage layer is a contact hole defined in an insulating layer interposed between the first common voltage line and the voltage layer. It can be electrically connected to the first common voltage line through.

The voltage layer may overlap the light emitting area of the light emitting diode.

One embodiment of the present invention includes a first light emitting diode electrically connected to a first subpixel circuit arranged in a first display area; a second light emitting diode located in a second display area inside the first display area and electrically connected to a second subpixel circuit disposed in an area different from the second display area; a conductive bus line electrically connecting the second sub-pixel circuit and the second light-emitting diode; a data line electrically connected to one of the plurality of transistors of the first sub-pixel circuit and extending along a first direction in the first display area; and a voltage layer interposed between the data line and the first electrode of the first light emitting diode and overlapping the data line and the first electrode, wherein the voltage layer has a width greater than the width of the data line. , a display device is initiated.

The voltage layer may include the same material as the conductive bus line.

The voltage layer and the conductive bus line may include transparent conductive oxide.

It may further include a common voltage line disposed in the first display area and electrically connected to a second electrode of the first light emitting diode, and the voltage layer may have the same voltage level as the common voltage line.

The common voltage line may include a first common voltage line and a second common voltage line extending to intersect each other in the first display area.

The first common voltage line may overlap the first electrode of the first light emitting diode.

The voltage layer may correspond to a portion of the first common voltage line.

It further includes an insulating layer interposed between the voltage layer and one selected from a first common voltage line and a second common voltage line, wherein the voltage layer is electrically connected to the selected one through a contact hole defined in the insulating layer. You can.

It may further include a driving voltage line disposed in the first display area and electrically connected to the first subpixel circuit, and the voltage layer may have the same voltage level as the driving voltage line.

The driving voltage line includes a first driving voltage line and a second driving voltage line extending to intersect each other in the first display area, and the voltage layer is defined in an insulating layer interposed between the first common voltage line and the voltage layer. It can be electrically connected to the first common voltage line through the contact hole.

The voltage layer may overlap the light emitting area of the first light emitting diode.

It overlaps the second display area and may further include a component including a sensor or camera.

According to an embodiment of the present invention as described above, it is possible to prevent quality degradation caused by a light emitting diode and a data line disposed below it by using a voltage layer, and thus a display device capable of displaying a high quality image. can be provided. Of course, the scope of the present invention is not limited by this effect.

1 is a perspective view schematically showing a display device according to an embodiment of the present invention.
Figure 2 is a cross-sectional view schematically showing a display device according to an embodiment of the present invention.
Figure 3 is a plan view schematically showing a display panel according to an embodiment of the present invention.
Figure 4 is an equivalent circuit diagram schematically showing a subpixel circuit electrically connected to a light emitting diode of a display panel according to an embodiment of the present invention.
Figure 5 is a plan view showing a horizontal common voltage line and a vertical common voltage line of a display panel according to an embodiment of the present invention.
Figure 6 is a plan view showing the horizontal driving voltage line and vertical driving voltage line of the display panel according to an embodiment of the present invention.
7A and 7B are plan views showing a portion of a display panel according to an embodiment of the present invention, respectively.
8A and 8B correspond to cross-sectional views showing a portion of a display panel according to an embodiment of the present invention.
Figure 9 is a plan view showing a portion of a display panel according to another embodiment of the present invention.
Figure 10 corresponds to a cross-sectional view showing a portion of a display panel according to an embodiment of the present invention.
Figure 11 is a plan view showing a portion of a display panel according to an embodiment of the present invention, showing second light emitting diodes and second subpixel circuits being electrically connected through conductive bus lines.
FIG. 12 is a cross-sectional view taken along line XII-XII' of FIG. 11.

Since the present invention can be modified in various ways and can have various embodiments, specific embodiments will be illustrated in the drawings and described in detail in the detailed description. The effects and features of the present invention and methods for achieving them will become clear by referring to the embodiments described in detail below along with the drawings. However, the present invention is not limited to the embodiments disclosed below and may be implemented in various forms.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. When describing with reference to the drawings, identical or corresponding components will be assigned the same reference numerals and redundant description thereof will be omitted. .

In the following embodiments, when various components such as layers, membranes, regions, and plates are said to be “on” other components, this does not only mean that they are “right on” the other components, but also when other components are interposed between them. Also includes cases where Additionally, for convenience of explanation, the sizes of components may be exaggerated or reduced in the drawings. For example, the size and thickness of each component shown in the drawings are shown arbitrarily for convenience of explanation, so the present invention is not necessarily limited to what is shown.

In the following embodiments, the x-axis, y-axis, and z-axis are not limited to the three axes in the Cartesian coordinate system, but can be interpreted in a broad sense including these. For example, the x-axis, y-axis, and z-axis may be orthogonal to each other, but may also refer to different directions that are not orthogonal to each other.

1 is a perspective view schematically showing a display device according to an embodiment of the present invention.

Referring to FIG. 1 , the display device 1 may include a display area DA and a peripheral area PA located outside the display area DA. The display area (DA) can display an image through subpixels. The peripheral area (PA) is a non-display area that is disposed outside the display area (DA) and does not display an image, and may entirely surround the display area (DA). Drivers for providing electrical signals or power to the display area (DA) may be placed in the peripheral area (PA). A pad, which is an area where electronic devices, printed circuit boards, etc. can be electrically connected, may be disposed in the peripheral area (PA).

Hereinafter, for convenience of explanation, the case where the display device 1 is a smart phone will be described, but the display device 1 of the present invention is not limited to this. The display device 1 is a mobile phone, a smart phone, a tablet PC (tablet personal computer), a mobile communication terminal, an electronic notebook, an e-book, a portable multimedia player (PMP), a navigation device, and a UMPC (Ultra). It can be applied to not only portable electronic devices such as mobile PCs, but also various products such as televisions, laptops, monitors, billboards, and the Internet of Things (IOT). In addition, the display device 1 according to one embodiment is mounted on a wearable device such as a smart watch, a watch phone, a glasses-type display, and a head mounted display (HMD). It can be applied. In addition, the display device 1 according to one embodiment includes a dashboard of a car, a center information display (CID) disposed on the center fascia or dashboard of a car, and a room mirror display (a room mirror display instead of a side mirror of a car). room mirror display), entertainment for the rear seats of a car, can be applied to the display screen placed on the back of the front seat.

In some embodiments, the display area DA may include a first display area DA1, a second display area DA2, and a third display area DA3. In another embodiment, the display area DA may not include the second display area DA2 and the third display area DA3, but hereinafter, for convenience of explanation, the display area DA is used as the first display area DA2. It is described as including an area DA1, a second display area DA2, and a third display area DA3.

The display area (DA) can display an image using two-dimensionally arranged subpixels. The subpixels include first subpixels P1 arranged in the first display area DA1, second subpixels P2 arranged in the second display area DA2, and third display area DA3. It may include arranged third subpixels (P3).

The first display area DA1 may occupy most of the display area DA. Occupying most of the area may mean that the area of the first display area DA1 is approximately 50% or more of the area of the display area DA. The second display area DA2 may be disposed inside the display area DA. For example, the second display area DA2 may be entirely surrounded by the first display area DA1. The third display area DA3 may be arranged between the first display area DA1 and the second display area DA2. The third display area DA3 may entirely surround the second display area DA2 and may be entirely surrounded by the first display area DA1.

The second display area DA2 and the third display area DA3 may each have a smaller area than the first display area DA1. In one embodiment, Figure 1 shows that the second display area DA2 and the third display area DA3 each have a circular shape. As another example, the second display area DA2 and the third display area DA3 may each have a substantially rectangular shape.

1 shows a second display area DA2 and a third display area at the center of the upper side (+y direction) of the display area DA, which has a substantially rectangular shape when viewed from a direction approximately perpendicular to the top surface of the display device 1. (DA3) is shown as being arranged, but the present invention is not limited thereto. The second display area DA2 and the third display area DA3 may be arranged, for example, at the upper right or upper left side of the display area DA.

The second display area DA2 can implement an image through the second subpixels P2, and can transmit light or sound through the area between the second subpixels P2. Hereinafter, the area through which light or sound can pass is referred to as the transmission area (TA). In other words, the second display area DA2 may include a transmission area TA between the second subpixels P2.

Figure 2 is a cross-sectional view schematically showing a display device according to an embodiment of the present invention.

Referring to FIG. 2 , the display device 1 may include a display panel 10 and a component 20 disposed to overlap the display panel 10 . The component 20 may be placed in the second display area DA2.

Component 20 may be an electronic element that uses light or sound. For example, electronic elements may be sensors that measure distance such as proximity sensors, sensors that recognize parts of the user's body (e.g., fingerprint, iris, face, etc.), small lamps that output light, or image sensors that capture images ( For example, a camera), etc. Electronic elements that use light can use light in various wavelength bands, such as visible light, infrared light, and ultraviolet light. Electronic elements that use sound may use ultrasonic waves or sounds in other frequency bands.

The second display area DA2 may include a transmission area TA through which light and/or sound output from the component 20 or traveling from the outside toward the component 20 can pass through. In one embodiment, the transmission area TA is an area through which light can pass, and may correspond to an area between the second subpixels P2. In the case of the display device 1 according to an embodiment of the present invention, when light is transmitted through the second display area DA2 including the transmission area TA, the light transmittance is about 10% or more and about 25%. It may be greater than or equal to about 40%, greater than or equal to about 50%, greater than or equal to about 85%, or greater than or equal to about 90%.

Each of the first sub-pixel (P1), the second sub-pixel (P2), and the third sub-pixel (P3) previously described with reference to FIG. 1 can emit light using a light-emitting diode, and each light-emitting diode is connected to the display panel. It can be placed in the display area (DA) of (10). In this regard, in this specification, the light emitting diode corresponding to the first subpixel (P1) of the first display area (DA1) is referred to as the first light emitting diode (ED1), and the second subpixel of the second display area (DA2) is referred to as the first light emitting diode (ED1). The light emitting diode corresponding to (P2) is called the second light emitting diode (ED2), and the light emitting diode corresponding to the third subpixel (P3) of the third display area (DA3) is called the third light emitting diode (ED3). The first to third light emitting diodes ED1, ED2, and ED3 may be disposed on the substrate 100.

The substrate 100 may include an insulating material such as glass or polymer resin, and a protective film (PB) may be disposed on the back of the substrate 100. The substrate 100 may be a rigid substrate or a flexible substrate capable of bending, folding, rolling, etc. The protective film (PB) may include an opening (PB-OP) located in the second display area (DA2) to improve the transmittance of the transmission area (TA).

The first light emitting diode ED1 is disposed in the first display area DA1 and is electrically connected to the first subpixel circuit PC1 disposed in the first display area DA1. The first subpixel circuit PC1 may include transistors and a storage capacitor electrically connected to the transistors.

The second light emitting diode ED2 is disposed in the second display area DA2. The second light emitting diode (ED2) is electrically connected to the second subpixel circuit (PC2), and is connected to the second subpixel circuit (PC2) to improve the transmittance and transmission area of the transmission area (TA) provided in the second display area (DA2). The row PC2 is not arranged in the second display area DA2. The second sub-pixel circuit (PC2) is disposed in the third display area (DA3), and the second light-emitting diode (ED2) can be electrically connected to the second sub-pixel circuit (PC2) through a conductive bus line (CBL). .

The conductive bus line (CBL) may electrically connect the second subpixel circuit (PC2) of the third display area (DA3) and the second light emitting diode (ED2) of the second display area (DA2). The conductive bus line (CBL) may include a conductive material with light transparency, such as transparent conductive oxide (TCO). Transparent conductive oxide (TCO) is indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), and indium gallium oxide. (IGO; indium gallium oxide) and/or aluminum zinc oxide (AZO; aluminum zinc oxide).

The third light emitting diode ED3 is disposed in the third display area DA3 and is electrically connected to the third sub-pixel circuit PC3 disposed in the third display area DA3. The third sub-pixel circuit PC3 may include transistors and a storage capacitor electrically connected to the transistors.

The first to third light emitting diodes (ED1, ED2, and ED3) are light emitting elements that emit light of a predetermined color and may include organic light emitting diodes (Organic Light Emitting Diodes). In another embodiment, the first to third light emitting diodes ED1, ED2, and ED3 may include inorganic light emitting diodes or may be light emitting diodes including quantum dots.

The first to third light emitting diodes ED1, ED2, and ED3 may be covered with the encapsulation layer 300. The encapsulation layer 300 may be a thin film encapsulation layer including an inorganic encapsulation layer containing an inorganic insulating material and an organic encapsulating layer containing an organic insulating material. In one embodiment, the encapsulation layer 300 may include first and second inorganic encapsulation layers and an organic encapsulation layer between them.

In another embodiment, the encapsulation layer 300 may be an encapsulation substrate such as glass. A sealant containing a frit or the like may be disposed between the substrate 100 and the encapsulation substrate. The sealant is located in the peripheral area (PA) but extends to surround the outer edge of the display area (DA) to prevent moisture from penetrating into the first to third light emitting diodes (ED1, ED2, and ED3) through the side. You can. .

The input sensing layer 400 may be formed on the encapsulation layer 300. The input sensing layer 400 can acquire coordinate information according to an external input, for example, a touch event of an object such as a finger or a stylus pen. The input sensing layer 400 may include a touch electrode and trace lines connected to the touch electrode. The input sensing layer 400 can detect external inputs using a mutual cap method or a self-cap method.

The optical functional layer 500 may include an anti-reflection layer. The anti-reflection layer can reduce the reflectance of light (external light) incident on the display panel 10 from the outside through the cover window 600. The anti-reflection layer may include a retarder and a polarizer. When the optical functional layer 500 includes a polarizer, the optical functional layer 500 may include an opening 510 located in the second display area DA2 and thus improve the transmittance of the transmission area TA2. You can.

In another embodiment, the anti-reflection layer may include a black matrix and color filters. The color filters may be arranged considering the color of light emitted from each of the first to third light emitting diodes ED1, ED2, and ED3. When the optical functional layer 500 includes a black matrix and color filters, a light-transmitting material may be disposed at a position corresponding to the transmission area (TA).

In another embodiment, the anti-reflection layer may include a destructive interference structure. The destructive interference structure may include a first reflective layer and a second reflective layer disposed on different layers. The first reflected light and the second reflected light reflected from the first reflective layer and the second reflective layer, respectively, may interfere destructively, and thus the external light reflectance may be reduced.

The cover window 600 may be disposed on the optical functional layer 500. The cover window 600 may be coupled to the optical function layer 500 through an adhesive layer such as a transparent optically transparent adhesive interposed between the cover window 600 and the optical function layer 500 . The cover window 600 may include glass or plastic. Plastic materials may include polyethersulfone, polyacrylate, polyether imide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate.

The cover window 600 may include a flexible cover window. For example, the cover window 600 may include polyimide and/or ultra-thin glass.

Figure 3 is a plan view schematically showing a display panel according to an embodiment of the present invention.

Referring to FIG. 3 , the display panel 10 may include a display area (DA) and a peripheral area (PA). The shape of the display panel 10 may be substantially the same as the shape of the substrate 100. For example, it can be said that the substrate 100 includes a display area (DA) and a peripheral area (PA).

In some embodiments, the display area DA may include first to third display areas DA1, DA2, and DA3. The display area DA, for example, the first to third display areas DA1, DA2, and DA3, may correspond to the image plane of the display panel 10. The second display area DA2 may be surrounded by the third display area DA3, and the third display area DA3 may be surrounded by the first display area DA1. The second display area DA2 may include a transparent area TA as previously described with reference to FIG. 2 .

The display area (DA) is a part that displays an image, and the display area (DA) may have various shapes, such as a circle, an oval, a polygon, or a specific shape. Although FIG. 1 shows that the display area DA has a substantially square shape, in another embodiment, the display area DA may have a roughly square shape with rounded corners.

Light emitting diodes may be disposed in the display area (DA). The light emitting diodes may be electrically connected to each of the subpixel circuits arranged in the display area (DA). In some embodiments, light emitting diodes are disposed in the first to third display areas DA1, DA2, and DA3, and subpixel circuits electrically connected to the light emitting diodes respectively display the first display area DA1 and the third display area DA1. It may be placed in the area DA3, but may not be placed in the second display area DA2.

For example, the first subpixel circuit (PC1) electrically connected to the first light emitting diode (ED1) disposed in the first display area (DA1) is disposed in the first display area (DA1) and the second display area (DA2) And the second and third subpixel circuits (PC2, PC3) electrically connected to the second and third light emitting diodes (ED2, ED3) respectively disposed in the third display area (DA3) are in the third display area (DA3). can be placed. In other words, some of the subpixel circuits disposed in the third display area DA3 (e.g., the second subpixel circuit, PC2) are connected to the second light emitting diodes ED2 disposed in the second display area DA2. Among the sub-pixel circuits that are electrically connected and disposed in the third display area (DA3), another part (e.g., the third sub-pixel circuit, PC3) is connected to the third light emitting diode (ED3) disposed in the third display area (DA3). ) can be electrically connected to the Hereinafter, for convenience of explanation, among the subpixel circuits arranged in the third display area DA3, the subpixel circuits electrically connected to the second light emitting diodes ED2 are referred to as second subpixel circuits PC2. Among the subpixel circuits arranged in the third display area DA3, the subpixel circuits electrically connected to the third light emitting diodes ED3 are called third subpixel circuits PC3.

Figure 3 shows that the second sub-pixel circuits PC2 are arranged in the third display area DA3, but the present invention is not limited to this. In another embodiment, the second subpixel circuits PC2 may be disposed in the peripheral area PA.

The first to third subpixel circuits (PC1, PC2, PC3) are transistors connected to signal lines or voltage lines for controlling the on/off and brightness of the corresponding first to third light emitting diodes (ED1, ED2, ED3), respectively. may include. In this regard, Figure 3 shows a scan line (SL) and a data line (DL) as signal lines electrically connected to the transistors, and a driving voltage line (VDDL) and a common voltage line (VSSL) as voltage lines.

The peripheral area (PA) may entirely surround the display area (DA). A portion of the peripheral area PA (hereinafter referred to as the protruding peripheral area) may extend in a direction away from the display area DA. In other words, the display panel 10 extends along one direction from the main area (MR) and the main area (MA) including the display area (DA) and a portion of the peripheral area (PA) surrounding the display area (DA). It may include an extended sub-region (SR), and the sub-region (SR) may correspond to the protruding peripheral region described above. The width (e.g., width in the x-direction) of the sub-region (SR) may be smaller than the width (e.g., width in the x-direction) of the main region (MR), and a portion of the sub-region (SR) may be formed on the substrate 100. It can be bent toward the back of.

Voltage supply lines and driving circuits may be disposed in the peripheral area (PA). In this regard, Figure 3 shows the common voltage supply line 1000, the driving voltage supply line 2000, the first driving circuit 3031, the second driving circuit 3032, and the data driving circuit 4000 in the peripheral area (PA). It shows what is placed in .

The common voltage supply line 1000 may have a loop shape that partially surrounds the display area DA and has one side open. The common voltage supply line 1000 includes a first common voltage input unit 1011, a second common voltage input unit 1012, and a third common voltage input unit 1014 disposed adjacent to the first edge E1 of the display area DA. ) may include. In one embodiment, the first common voltage input unit 1011 and the second common voltage input unit 1012 may be disposed adjacent to the first edge E1 of the display area DA but spaced apart from each other. The third common voltage input unit 1014 is adjacent to the first edge E1 of the display area DA and may be located between the first common voltage input unit 1011 and the second common voltage input unit 1012.

The first common voltage input unit 1011 and the second common voltage input unit 1012 are bodies extending along the second edge (E2), third edge (E3), and fourth edge (E4) of the display area (DA). It can be connected by unit 1013. In other words, the first common voltage input unit 1011, the second common voltage input unit 1012, and the body unit 1013 may be formed as one body. The common voltage supply line 1000 has a loop shape with one side open, and both ends of the common voltage supply line 1000 correspond to the first common voltage input unit 1011 and the second common voltage input unit 1012, respectively. The area between the voltage input unit 1011 and the second common voltage input unit 1012 may correspond to the body unit 1013.

The first auxiliary common voltage supply line 1021 and the second auxiliary common voltage supply line 1022 may be disposed in the peripheral area (PA). The first auxiliary common voltage supply line 1021 and the second auxiliary common voltage supply line 1022 may each be a type of branch line extending from the common voltage supply line 1000.

The first auxiliary common voltage supply line 1021 is electrically connected to the common voltage supply line 1000 and may extend along the second edge E2 of the display area DA. The first auxiliary common voltage supply line 1021 may be located between the first driving circuit 3031, which will be described later, and the second edge E2 of the display area DA.

The second auxiliary common voltage supply line 1022 is electrically connected to the common voltage supply line 1000 and may extend along the fourth edge E4 of the display area DA. The second auxiliary common voltage supply line 1022 may be located between the second driving circuit 3032, which will be described later, and the fourth edge E4 of the display area DA. The common voltage supply line 1000, the first auxiliary common voltage supply line 1021, and the second auxiliary common voltage supply line 1022 may be electrically connected to common voltage lines (VSSL) passing through the display area (DA).

The common voltage lines (VSSL) may include a first common voltage line and a second common voltage line extending to cross each other. For example, the common voltage line (VSSL) may include a first common voltage line extending in the y-direction and a second common voltage line extending in the x-direction. Hereinafter, for convenience of explanation, the 'first common voltage line extending in the y direction' is referred to as the vertical common voltage line (VSL), and the 'second common voltage line extending in the x direction' is referred to as the horizontal common voltage line (HSL).

The vertical common voltage line (VSL) and the horizontal common voltage line (HSL) may pass through the display area (DA) to intersect each other. The vertical common voltage line (VSL) and horizontal common voltage line (HSL) may be located on different floors.

The vertical common voltage line (VSL) may be electrically connected to the common voltage supply line (1000). One end of each of the vertical common voltage lines (VSLs) may be connected to the body portion 1013, and the other end of each of the vertical common voltage lines (VSLs) may be connected to a first common voltage input unit 1011 and a second common voltage input unit 1012. ), or may be connected to the third common voltage input unit 1014.

The horizontal common voltage line (HSL) may be electrically connected to the first auxiliary common voltage supply line 1021 and the second auxiliary common voltage supply line 1022. One end of each of the horizontal common voltage lines (HSL) is electrically connected to the first auxiliary common voltage supply line 1021, and the other end of each of the horizontal common voltage lines (HSL) is electrically connected to the second auxiliary common voltage supply line 1022. It can be connected to .

In some embodiments, the vertical common voltage line (VSL) and the horizontal common voltage line (HSL) may be electrically connected to each other through a first contact hole (CNT1) defined in at least one insulating layer interposed between them. The first contact hole (CNT1) for connecting the vertical common voltage line (VSL) and the horizontal common voltage line (HSL) may be located in the display area (DA). For example, the vertical common voltage line (VSL) and the horizontal common voltage line (HSL) are connected on a portion of the display area (DA) located between the first edge (E1) of the display area (DA) and the transmission area (TA). A first contact hole (CNT1) may be disposed for.

The driving voltage supply line 2000 may include a first driving voltage input unit 2021 and a second driving voltage input unit 2022 spaced apart from each other with the display area DA in between. The first driving voltage input unit 2021 and the second driving voltage input unit 2022 may extend substantially in parallel with the display area DA interposed therebetween. The first driving voltage input unit 2021 is disposed adjacent to the first edge E1 of the display area DA, and the second driving voltage input unit 2022 is adjacent to the third edge E3 of the display area DA. It can be placed like this.

The driving voltage supply line 2000 may be electrically connected to driving voltage lines VDDL passing through the display area DA. The driving voltage line VDDL may include a first driving low voltage line and a second driving voltage line extending to intersect each other. For example, the driving voltage line VDDL may include a first driving voltage line extending in the y-direction and a second driving voltage line extending in the x-direction. Hereinafter, for convenience of explanation, the 'first driving voltage line extending in the y direction' is referred to as the vertical driving voltage line (VDL), and the 'second driving voltage line extending in the x direction' is referred to as the horizontal driving voltage line (HDL).

The vertical driving voltage line (VDL) and the horizontal driving voltage line (HDL) may pass through the display area (DA) so as to intersect each other. The vertical driving voltage line (VDL) and the horizontal driving voltage line (HDL) are located on different layers and can be connected through a second contact hole (CNT2) formed in at least one insulating layer located between them. A second contact hole (CNT2) for connection between the vertical driving voltage line (VDL) and the horizontal driving voltage line (HDL) may be located in the display area (DA).

The first driving circuit 3031 and the second driving circuit 3032 are disposed in the peripheral area (PA) and may be electrically connected to the scan line (SL). In one embodiment, some of the scan lines SL may be electrically connected to the first driving circuit 3031, and the remaining scan lines may be connected to the second driving circuit 3032. The first driving circuit 3031 and the second driving circuit 3032 include a scan driving unit that generates a scan signal, and the generated scan signal is transmitted to any one transistor of the sub-pixel circuit (PC) through the scan line (SL). can be passed on.

The data driving circuit 4000 transmits a data signal through a data line DL passing through the display area DA to a subpixel circuit, for example, any one included in each of the first to third subpixel circuits PC1, PC2, and PC3. can be transmitted to the transistor.

A first terminal portion TD1 may be located on one side of the substrate 100. A printed circuit board 5000 may be attached to the first terminal portion TD1. The printed circuit board 5000 includes a second terminal portion (TD2) electrically connected to the first terminal portion (TD1), and the control unit 6000 may be disposed on the printed circuit board 5000. Control signals of the control unit 6000 are transmitted through the first and second terminal units TD1 and TD2 to the first and second driving circuits 3031 and 3032, the data driving circuit 4000, the driving voltage supply line 2000, and the common Each may be provided to the voltage supply line 1000.

Figure 4 is an equivalent circuit diagram schematically showing a subpixel circuit electrically connected to a light emitting diode of a display panel according to an embodiment of the present invention. The light emitting diode (ED) of FIG. 4 may correspond to each of the first to third light emitting diodes (ED1, ED2, and ED3) previously described with reference to FIG. 3, and the subpixel circuit (PC) of FIG. 4 is similar to that of FIG. 3. It may correspond to each of the first to third subpixel circuits (PC1, PC2, and PC3) described with reference to. In other words, the equivalent circuit diagram of the first light-emitting diode (ED1, Figure 3) and the first sub-pixel circuit (PC1), the equivalent circuit diagram of the second light-emitting diode (ED2, Figure 3) and the second sub-pixel circuit (PC2), and The equivalent circuit diagrams of the third light emitting diode (ED3, FIG. 3) and the third subpixel circuit (PC3) may be the same. As previously described, the light emitting diode (ED) may be an organic light emitting diode, an inorganic light emitting diode, or may include a quantum dot light emitting diode.

Referring to FIG. 4, the first electrode (e.g., anode) of the light emitting diode (ED) is electrically connected to the subpixel circuit (PC), and the second electrode (e.g., cathode) of the light emitting diode (ED) is electrically connected to the subpixel circuit (PC). ) may be electrically connected to a common voltage line (VSSL, for example, a vertical common voltage line (VSL)) that provides a common voltage (ELVSS). The light emitting diode (ED) can emit light with a luminance corresponding to the amount of current supplied from the subpixel circuit (PC).

The sub-pixel circuit (PC) can control the amount of current flowing from the driving voltage line (VDDL) to the common voltage (ELVSS) via the light emitting diode (ED) in response to the data signal. The subpixel circuit (PC) may include a first transistor (M1), a second transistor (M2), and a storage capacitor (Cst).

Each of the first transistor M1 and the second transistor M2 may be an oxide semiconductor transistor including a semiconductor layer made of an oxide semiconductor, or a silicon semiconductor transistor including a semiconductor layer made of polysilicon. Depending on the type of transistor, the first electrode may be one of the source electrode and the drain electrode, and the second electrode may be the other of the source electrode and the drain electrode.

The first electrode of the first transistor (M1) is connected to the driving voltage line (VDDL, for example, vertical driving voltage line (VDL)) that supplies the driving voltage (ELVDD), and the second electrode is connected to the first electrode of the light emitting diode (ED). can be connected The gate electrode of the first transistor (M1) may be connected to the first node (N1). The first transistor M1 may control the amount of current flowing through the light emitting diode ED from the driving voltage line VDDL, for example, the vertical driving voltage line VDL, in response to the voltage of the first node N1.

The second transistor M2 may be a switching transistor. The first electrode of the second transistor M2 may be connected to the data line DL, and the second electrode may be connected to the first node N1. The gate electrode of the second transistor M2 may be connected to the scan line SL. The second transistor (M2) is turned on when a scan signal is supplied to the scan line (SL) and can electrically connect the data line (DL) and the first node (N1).

The storage capacitor Cst may be connected to the first node N1. For example, the first capacitor electrode of the storage capacitor (Cst) is connected to the gate electrode of the first transistor (M1), and the second capacitor electrode of the storage capacitor (Cst) is connected to the driving voltage line (VDDL), for example, the vertical driving voltage line (VDL). can be electrically connected to. In some embodiments, the second capacitor electrode of the storage capacitor Cst may be a part of the driving voltage line VDDL, for example, a part of the horizontal driving voltage line HDL described above with reference to FIG. 3.

Figure 4 shows two transistors, but the present invention is not limited thereto. The sub-pixel circuit (PC) may include three or more transistors.

Figure 5 is a plan view showing a horizontal common voltage line and a vertical common voltage line of a display panel according to an embodiment of the present invention.

Referring to FIG. 5, a common voltage supply line 1000 and a first auxiliary common voltage supply line 1021 and a second auxiliary common voltage supply line 1033 electrically connected to the common voltage supply line 1000 are disposed in the peripheral area (PA). It can be.

A common voltage line (VSSL) electrically connected to the common voltage supply line 1000 is disposed in the display area (DA). The common voltage line (VSSL) may be electrically connected to the second electrode (eg, cathode) of the light emitting diode. The common voltage line (VSSL) may include vertical common voltage lines (VSL) and horizontal common voltage lines (HSL) that intersect each other. Vertical common voltage lines (VSL) extending in a first direction (e.g., y-direction) and horizontal common voltage lines (HSL) extending in a second direction (e.g., x-direction) to intersect the vertical common voltage lines (VSL) are displayed. It can be placed in the area (DA). Some of the vertical common voltage lines (VSL) are electrically connected to the first common voltage input unit 1011 and the body unit 1013, and other parts are electrically connected to the second common voltage input unit 1012 and the body unit 1013. And another part may be electrically connected to the third common voltage input unit 1014 and the body unit 1013.

Vertical common voltage lines (VSL) and horizontal common voltage lines (HSL) that intersect each other may have a mesh structure on a plane. A vertical common voltage line (VSL) and a horizontal common voltage line (HSL) arranged on different floors may be electrically connected in the display area (DA). For example, the vertical common voltage line (VSL) and the horizontal common voltage line (HSL) are connected through the first contact hole (CNT1) defined in at least one insulating layer interposed between the vertical common voltage line (VSL) and the horizontal common voltage line (HSL). can be electrically connected.

In some embodiments, when the display area (DA) includes the second display area (DA2), a vertical common voltage line ( VSL) and the horizontal common voltage line (HSL) may not pass through the second display area (DA2).

Figure 6 is a plan view showing the horizontal driving voltage line and vertical driving voltage line of the display panel according to an embodiment of the present invention.

Referring to FIG. 6, a driving voltage supply line 2000 is disposed in the peripheral area (PA) as previously described with reference to FIG. 3, and the driving voltage supply lines 2000 are spaced apart from each other with the display area DA in between. It may include a first driving voltage input unit 2021 and a second driving voltage input unit 2022.

A driving voltage line (VDDL) electrically connected to the driving voltage supply line (2000) is disposed in the display area (DA). The driving voltage line (VDDL) may include a vertical driving voltage line (VDL) and a horizontal driving voltage line (HDL) that intersect each other. Vertical driving voltage lines (VDL) extending in a first direction (e.g., y-direction) and horizontal driving voltage lines (HDL) extending in a second direction (e.g., x-direction) to intersect the vertical driving voltage lines (VDL) are displayed. It can be placed in the area (DA). Vertical driving voltage lines (VDL) and horizontal driving voltage lines (HDL) that intersect each other may have a mesh structure on a plane.

The horizontal driving voltage line (HDL) may include the second capacitor electrode of the storage capacitor described above with reference to FIG. 4. In other words, a portion of the horizontal driving voltage line (HDL) may correspond to the second capacitor electrode of the storage capacitor.

The vertical driving voltage line (VDL) and the horizontal driving voltage line (HDL) arranged on different floors may be electrically connected in the display area (DA). For example, the vertical driving voltage line (VDL) and the horizontal driving voltage line (HDL) are connected through the second contact hole (CNT2) defined in at least one insulating layer interposed between the vertical driving voltage line (VDL) and the horizontal driving voltage line (HDL). can be electrically connected.

In some embodiments, when the display area DA includes the second display area DA2, a vertical driving voltage line (FIG. 3) is used to sufficiently secure the transmission area TA included in the second display area DA2. VDL) and horizontal driving voltage line (HDL) may not pass through the second display area (DA2).

7A and 7B are plan views each showing a portion of a display panel according to an embodiment of the present invention. 7A and 7B show a portion of the display area of the display panel, for example, the first display area DA1.

Referring to FIGS. 7A and 7B , the data line DL may extend along a first direction (eg, y direction). The vertical driving voltage line (VDL) is disposed adjacent to the data line (DL) and may extend along a first direction (eg, y-direction). The data line (DL) and vertical driving voltage line (VDL) arranged adjacent to each other are electrically connected to one subpixel circuit and can supply a data signal or driving voltage.

As some embodiments, in FIGS. 7A and 7B, two data lines (DL) are arranged adjacent to each other, and two vertical driving voltage lines (VDL) are arranged on both sides with the two data lines (DL) in between. shows that In other words, FIGS. 7A and 7B show two data lines DL and two vertical driving voltage lines VDL, respectively, along a first direction (e.g., y direction) between the two data lines DL. It shows that they are arranged symmetrically on the left and right with respect to an extended virtual vertical line.

As another embodiment, the two data lines (DL) and the two vertical driving voltage lines (VDL) may not be left-right symmetrical with respect to the above-described virtual vertical line. For example, vertical driving voltage lines (VDL) and data lines (DL) may be alternately arranged along the second direction (eg, x-direction). In other words, the two data lines (DL) may be spaced apart from each other with a vertical driving voltage line (VDL) between them.

The voltage layer 240 may overlap the data line DL. For example, the voltage layer 240 may extend along the first direction (eg, y-direction) like the data line DL. The voltage layer 240 may have a constant voltage level. For example, the voltage layer 240 may have the same voltage level as the common voltage line (VSSL) described with reference to FIG. 5 . In some embodiments, the voltage layer 240 is electrically connected to a sublayer of the common voltage line (VSSL, Figure 5), for example, one selected from the vertical and horizontal common voltage lines (VSL, HSL) corresponding to the first and second common voltage lines. It can be connected to .

As an example, the voltage layer 240 may be a portion of a vertical common voltage line (VSL) having a voltage level of the common voltage as shown in FIG. 7A. The vertical common voltage line (VSL) may overlap the data line (DL) and the first electrode 221 of the first light emitting diode (ED1).

As another example, the voltage layer 240 may be disposed on a layer different from the vertical common voltage line (VSL) having a voltage level of the common voltage, as shown in FIG. 7B. The vertical common voltage line (VSL) and the voltage layer 240 disposed on different layers may be electrically connected through a contact hole 213CNT defined in the insulating layer interposed between them. The voltage layer 240 shown in FIG. 7B may be disposed on a vertical common voltage line (VSL) with an insulating layer interposed therebetween.

The voltage layer 240 may include a conductive material. The voltage layer 240 is made of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In ₂ O ₃ ), and indium. It may include a transparent conductive oxide such as gallium oxide (IGO; indium gallium oxide) and/or aluminum zinc oxide (AZO).

The first width W1 of the voltage layer 240 may be larger than the second width W2 of the data line DL. In some embodiments, as shown in FIGS. 7A and 7B, the first width W1 of the voltage layer 240 may be greater than the sum of the second widths W2 of the two data lines DL. The first width W1 of the voltage layer 240 may be smaller than the width of the first electrode 221 of the first light emitting diode ED1, as shown in FIG. 7A. In another embodiment, the first width W1 of the voltage layer 240 is relatively large enough to overlap most of the first electrode 221 of the first light emitting diode ED1, as shown in FIG. 7B. You can have

The voltage layer 240 may overlap the light emitting diode, for example, the light emitting area EA of the first light emitting diode ED1. The voltage layer 240 overlaps a portion of the light-emitting area EA of the first light-emitting diode ED1 as shown in FIG. 7A, or overlaps the light-emitting area EA of the first light-emitting diode ED1 as shown in FIG. 7B. It can overlap with the entire EA).

Referring to FIGS. 7A and 7B , light emitting diodes, for example, the first light emitting diode ED1, may be arranged to be spaced apart from each other. One of the first light emitting diodes ED1 may be disposed to overlap the voltage layer 240 and the data line DL, and the other first light emitting diode ED1 may be disposed to overlap the voltage layer 240 and the data line DL. It can be placed overlapping with the vertical driving voltage line (VDL).

The first electrode 221 of one of the first light emitting diodes ED1 may overlap the data line DL below the voltage layer 240. As a comparative example of the present invention, when there is no voltage layer 240, the first light emitting diode (ED1) overlapping the data line (DL) is affected by the parasitic capacitance between the data line (DL) and the first electrode 221. Accordingly, light may be emitted with a different luminance than the other first light emitting diode (ED1), and in this case, display quality may deteriorate. However, when the voltage layer 240 is disposed as in the embodiment of the present application, the above-described problem can be prevented.

Another first light emitting diode (ED1) may be arranged to overlap the vertical driving voltage line (VDL). As an embodiment, the vertical driving voltage line (VDL) may include a narrow portion with a relatively small width and a wide portion with a relatively large width along a second direction (e.g., x-direction), and the other first light emitting diode (ED1) may overlap the wide portion of the vertical driving voltage line (VDL).

FIGS. 8A and 8B correspond to cross-sectional views showing a portion of a display panel according to an embodiment of the present invention.

Referring to FIGS. 8A and 8B, the first subpixel circuit (PC1) is disposed on the substrate 100 in the first display area (DA1), and the first light emitting diode (ED1) is connected to the first subpixel circuit (PC1). ), but may be electrically connected to the first subpixel circuit (PC1). The substrate 100 may include glass or polymer resin.

The buffer layer 201 may be disposed on the upper surface of the substrate 100. The buffer layer 201 can prevent impurities from penetrating into the semiconductor layer of the transistor. The buffer layer 201 may include an inorganic insulating material such as silicon nitride, silicon oxynitride, and silicon oxide, and may be a single layer or multilayer containing the above-described inorganic insulating material.

The first subpixel circuit PC1 may be disposed on the buffer layer 201. The first sub-pixel circuit (PC1) may include a plurality of thin film transistors and a storage capacitor as previously described with reference to FIG. 4, and FIG. 8 shows the first transistor (T1) of the first sub-pixel circuit (PC1). and a storage capacitor (Cst). In some embodiments, the first subpixel circuit PC1 may further include transistors in addition to the transistors described with reference to FIG. 4 . In this regard, Figure 8 shows that the first subpixel circuit (PC1) includes an additional transistor (hereinafter referred to as the sixth transistor) electrically connected between the first transistor (T1) and the first electrode 221 of the first light emitting diode (ED1). (T6)).

The first transistor T1 may include a first semiconductor layer A1 on the buffer layer 201 and a first gate electrode GE1 that overlaps the channel region C1 of the first semiconductor layer A1. The first semiconductor layer A1 may include a silicon-based semiconductor material, such as polysilicon, or an oxide-based semiconductor material. The first semiconductor layer A1 may include a channel region C1 and a first region B1 and a second region D1 disposed on both sides of the channel region C1. The first area (B1) and the second area (D1) are areas with superior conductivity than the channel area (C1), and one of the first area (B1) and the second area (D1) is a source area and the other is a drain area. It may correspond to an area.

The sixth transistor T6 may include a sixth semiconductor layer A6 on the buffer layer 201 and a sixth gate electrode GE6 overlapping the sixth semiconductor layer A6. The sixth semiconductor layer A6 includes the same material as the first semiconductor layer A1 and may be integrally connected to the first semiconductor layer A1. The sixth semiconductor layer A6 may include a channel region and a source region and a drain region located on both sides of the channel region.

The first gate electrode (GE1) and the sixth gate electrode (GE6) may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc. It may have a single-layer or multi-layer structure containing one material. A first gate insulating layer 203 will be disposed below the first gate electrode GE1 and the sixth gate electrode GE6 for electrical insulation from the first semiconductor layer A1 and the sixth semiconductor layer A6. You can. The first gate insulating layer 203 may include an inorganic insulating material such as silicon nitride, silicon oxynitride, and silicon oxide, and may be a single layer or multilayer containing the above-described inorganic insulating material.

The storage capacitor Cst may include a first capacitor electrode CE1 and a second capacitor electrode CE2 that overlap each other. In one embodiment, the first capacitor electrode (CE1) may include a first gate electrode (GE1). In other words, the first gate electrode GE1 may include the first capacitor electrode CE1. For example, the first gate electrode (GE1) and the first capacitor electrode (CE1) may be integrated.

A first interlayer insulating layer 205 may be disposed between the first capacitor electrode (CE1) and the second capacitor electrode (CE2) of the storage capacitor (Cst). The first interlayer insulating layer 205 may include an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride, and may include a single-layer or multi-layer structure including the above-described inorganic insulating material.

In some embodiments, the second capacitor electrode (CE2) may be a part of the horizontal common voltage line (HSL). The portion of the horizontal common voltage line (HSL) that overlaps the first capacitor electrode (CE1) may correspond to the second capacitor electrode (CE2).

The horizontal common voltage line (HSL) and the second capacitor electrode (CE2) may include a low-resistance conductive material such as molybdenum (Mo), aluminum (Al), copper (Cu), and/or titanium (Ti). , may include a single-layer or multi-layer structure made of the above-described materials.

A second inter-layer insulating layer 207, a third inter-layer insulating layer 209, and a fourth inter-layer insulating layer 210 may be disposed on the storage capacitor Cst. The second interlayer insulating layer 207, the third interlayer insulating layer 209, and the fourth interlayer insulating layer 210 may each include an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride, and may include the above-described inorganic insulating material. It may have a single-layer or multi-layer structure including an insulating material.

The first insulating layer 211 may be disposed on the fourth interlayer insulating layer 210. The first insulating layer 211 may include an inorganic insulating material or an organic insulating material. In one embodiment, the first insulating layer 211 may include an organic insulating material such as acrylic, benzocyclobutene (BCB), polyimide, or hexamethyldisiloxane (HMDSO).

The data line DL and the vertical driving voltage line VDL may be disposed on the first insulating layer 211 and may include the same material. The data line (DL) and vertical driving voltage line (VDL) may contain aluminum (Al), copper (Cu), and/or titanium (Ti), and may be made of a single layer or multiple layers containing the above-mentioned materials. For example, the data line (DL) and the vertical driving voltage line (VDL) may have a three-layer structure of titanium layer/aluminum layer/titanium layer.

As an embodiment, as previously described with reference to FIG. 7A, when the voltage layer 240 corresponds to a portion of the vertical common voltage line (VSL), as shown in FIG. 8A, the voltage layer 240 is the second insulation It may be disposed on the data line DL with the layer 212 interposed therebetween. The voltage layer 240 may overlap the data line DL with a width greater than the width of the data line DL. The voltage layer 240 may include transparent conductive oxide.

In another embodiment, as previously described with reference to FIG. 7B, the voltage layer 240 may be disposed on a different layer from the vertical common voltage line (VSL). In this regard, FIG. 8a shows the vertical common voltage line (VSL). It is shown that the second insulating layer 212 is disposed, and the voltage layer 240 is disposed on the third insulating layer 213. Although not shown in FIG. 8B, the voltage layer 240 may be electrically connected to the vertical common voltage line (VSL) through the contact hole 213CNT (FIG. 7B) defined in the third insulating layer 213. In another embodiment, the voltage layer 240 may be electrically connected to a horizontal common voltage line. The voltage layer 240 may overlap the data line DL with a width greater than the width of the data line DL. The voltage layer 240 may include transparent conductive oxide.

Referring to FIGS. 8A and 8B , the voltage layer 240 may overlap the first electrode 221 of the first light emitting diode ED1 with the insulating layer(s) therebetween. 8A shows the voltage layer 240 disposed on the second insulating layer 212 and FIG. 8B shows the voltage layer 9240 disposed on the third insulating layer 213, but the present invention is not limited thereto. No. As another example, the voltage layer 240 may be disposed on the fourth insulating layer 214.

The second insulating layer 212, third insulating layer 213, fourth insulating layer 214, and fifth insulating layer 215 are each made of acrylic, Benzocyclobutene (BCB), polyimide, or Hexamethyldisiloxane (HMDSO). It may include organic insulating materials such as.

The first electrode 221 of the first light emitting diode ED1 may be disposed on the fifth insulating layer 215. The first electrode 221 may be electrically connected to the sixth transistor T6 through the first to fifth connection metals (CM1, CM2, CM3, CM4, and CM5). The first connection metal (CM1) and/or the second connection metal (CM2) may include a metal material. For example, the first connection metal (CM1) and/or the second connection metal (CM2) may include the same material as the data line (DL) and/or the driving voltage line (PL). The third connection metal (CM3), the fourth connection metal (CM4), and the fifth connection metal (CM5) may include a transparent conductive material. The third connection metal (CM3) may include the same material as the voltage layer 240.

The first electrode 221 is made of silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), and iridium (Ir). ), chromium (Cr), or a reflective film containing compounds thereof. In another embodiment, the first electrode 221 may further include a conductive oxide layer above and/or below the above-described reflective film. The conductive oxide layer is made of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In ₂ O ₃ ), and indium gallium oxide. (IGO; indium gallium oxide) and/or aluminum zinc oxide (AZO; aluminum zinc oxide). In one embodiment, the first electrode 221 may include a plurality of sub-layers. For example, the first electrode 221 may have a three-layer structure of an ITO layer, an Ag layer, and an ITO layer.

The bank layer 216 may be disposed on the first electrode 221. The bank layer 216 may include an opening overlapping the first electrode 221, and the width of the opening of the bank layer 216 may correspond to the width of the light emitting area of the first light emitting diode ED1.

The bank layer 216 may cover the edge of the first electrode 221. The bank layer 216 may overlap the contact hole 215CNT of the fifth insulating layer 215 formed for electrical connection between the first subpixel circuit PC1 and the first electrode 221. The bank layer 216 may include an organic insulating material such as polyimide. Alternatively, the bank layer 216 may include a light-blocking material. In one embodiment, the bank layer 216 may include an organic insulating material containing a light-blocking dye.

A spacer 217 may be formed on the bank layer 216. The spacer 217 may be formed together with the bank layer 216 in the same process, or may be formed individually in a separate process. In one embodiment, the spacer 217 may include an organic insulating material such as polyimide. In another embodiment, the bank layer 216 may include an organic insulating material containing a light-blocking dye, and the spacer 217 may include an organic insulating material such as polyimide.

The middle layer 222 includes a light emitting layer 222b. The middle layer 222 may include a first functional layer 222a disposed below the light-emitting layer 222b and/or a second functional layer 222c disposed above the light-emitting layer 222b. The light-emitting layer 222b may include a high-molecular or low-molecular organic material that emits light of a predetermined color (red, green, or blue). As another example, the light emitting layer 222b may include an inorganic material or quantum dots.

The second functional layer 222c may include an electron transport layer (ETL) and/or an electron injection layer (EIL). The first functional layer 222a and the second functional layer 222c may include organic materials.

The light emitting layer 222b may be formed in the first display area DA1 to overlap the first electrode 221 through the opening of the bank layer 216. On the other hand, the organic material layer included in the middle layer, for example, the first functional layer 222a and the second functional layer 222c, may entirely cover the display area DA (FIG. 3).

The middle layer 222 may have a single stack structure including a single light-emitting layer, or a tandem structure that is a multi-stack structure including a plurality of light-emitting layers. When having a tandem structure, a charge generation layer (CGL) may be disposed between the plurality of stacks.

The second electrode 223 may be made of a conductive material with a low work function. For example, the second electrode 223 is made of silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), and iridium. It may include a (semi) transparent layer containing (Ir), chromium (Cr), lithium (Li), calcium (Ca), or an alloy thereof. Alternatively, the second electrode 223 may further include a layer such as ITO, IZO, ZnO, or In2O3 on the (semi) transparent layer containing the above-mentioned material. The second electrode 223 may entirely cover the display area DA (FIG. 3).

The capping layer 225 may be disposed on the second electrode 223. The capping layer 225 may include an inorganic material or an organic material. The capping layer 225 may include LiF, an inorganic insulating material, and/or an organic insulating material. The capping layer 225 may entirely cover the display area DA.

The first light emitting diode ED1 may be covered with the encapsulation layer 300. The encapsulation layer 300 may include at least one organic encapsulation layer and at least one inorganic encapsulation layer. In one embodiment, FIGS. 8A and 8B illustrate that the encapsulation layer 300 includes first and second inorganic encapsulation layers 310 and 330 and an organic encapsulation layer 320 sandwiched between them. The encapsulation layer 300 may be disposed on the capping layer 225 .

The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may include one or more inorganic materials selected from the group consisting of aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride. there is. The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may be a single layer or a multilayer containing the above-mentioned materials. The organic encapsulation layer 320 may include a polymer-based material. Polymer-based materials may include acrylic resin, epoxy resin, polyimide, and polyethylene. In one embodiment, the organic encapsulation layer 320 may include acrylate.

9 is a plan view showing a portion of a display panel according to another embodiment of the present invention. FIG. 9 shows a portion of the display area of the display panel, for example, the first display area DA1.

Referring to FIG. 9, the data line DL may extend along a first direction (eg, y-direction). The vertical driving voltage line (VDL) is disposed adjacent to the data line (DL) and may extend along a first direction (eg, y-direction). The data line (DL) and vertical driving voltage line (VDL) arranged adjacent to each other are electrically connected to one subpixel circuit and can supply a data signal or driving voltage.

In some embodiments, Figure 9 shows two data lines (DL) arranged adjacent to each other, as previously described with reference to Figures 7a and 7b, and two vertical driving voltage lines (VDL) are connected to two data lines (DL). It shows that they are placed on both sides with the cells in between. As another embodiment, the two data lines (DL) and the two vertical driving voltage lines (VDL) may not be left-right symmetrical with respect to the above-described virtual vertical line. For example, vertical driving voltage lines (VDL) and data lines (DL) may be alternately arranged along the second direction (eg, x-direction).

Light emitting diodes, for example, the first light emitting diode ED1, may be arranged to be spaced apart from each other. One of the first light emitting diodes ED1 may be disposed to overlap the data line DL. In some embodiments, when a plurality of data lines DL are arranged adjacently as shown in FIG. 9, the first light emitting diode ED1 and/or the first electrode 221 of the first light emitting diode ED1 may be arranged to overlap each of the data lines DL. As another embodiment, when the data lines DL are arranged to be spaced apart from each other with a vertical driving voltage line VDL between them, the first light emitting diode ED1 may overlap one data line DL.

The voltage layer 240' may overlap the data line DL. For example, the voltage layer 240' may have a shape similar to the first electrode 221 of the first light emitting diode ED1 that overlaps the data line DL. For example, the voltage layer 240' may have an isolated shape on a plane. The edge of the voltage layer 240' may be disposed farther from the center of the first electrode 221 of the first light emitting diode ED1 than the edge of the first electrode 221 of the first light emitting diode ED1.

The voltage layer 240' may have a constant voltage level. As an example, the voltage layer 240' may have a voltage level of the driving voltage.

In some embodiments, the voltage layer 240' is a sublayer of the driving voltage line VDDL (FIG. 6), for example, one selected from the vertical and horizontal driving voltage lines VDL and HDL corresponding to the first and second driving voltage lines. Can be electrically connected. For example, as shown in FIG. 9, the voltage layer 240' is connected to the vertical driving voltage line (VDL) through the contact hole 212CNT defined in the insulating layer interposed between the voltage layer 240' and the vertical driving voltage line (VDL). ) can be electrically connected to.

The voltage layer 240' may include a conductive material. The voltage layer 240' is made of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In ₂ O ₃ ), It may include a transparent conductive oxide such as indium gallium oxide (IGO) and/or aluminum zinc oxide (AZO).

The first width W1' of the voltage layer 240' may be larger than the second width W2 of the data line DL. In some embodiments, as shown in FIG. 9, the first width W1' of the voltage layer 240' may be greater than the sum of the second widths W2 of the two data lines DL.

Light emitting diodes, for example, the first light emitting diode ED1, may be arranged to be spaced apart from each other. One of the first light emitting diodes ED1 may be disposed to overlap the voltage layer 240' and the data line DL, and the other first light emitting diode ED1 may be disposed to overlap the voltage layer 240' and the data line DL. Can be placed overlapping with the vertical driving voltage line (VDL). Another first light emitting diode (ED1) may be arranged to overlap the vertical driving voltage line (VDL). As an embodiment, the vertical driving voltage line (VDL) may include a narrow portion with a relatively small width and a wide portion with a relatively large width along a second direction (e.g., x-direction), and the other first light emitting diode (ED1) may overlap the wide portion of the vertical driving voltage line (VDL).

Figure 10 corresponds to a cross-sectional view showing a portion of a display panel according to an embodiment of the present invention.

The display panel 10 according to the embodiment of FIG. 10 is substantially the same as the structure of the display panel 10 previously described with reference to FIG. 8A or 8B except for the voltage layer 240'. For example, a first sub-pixel circuit (PC1) is disposed on the substrate 100 in the first display area (DA1), and the first light-emitting diode (ED1) may be electrically connected to the first sub-pixel circuit (PC1). It can be sealed with an encapsulation layer 300. Among the configurations of the display panel 10 of FIG. 10, the same structure as the display panel 10 described with reference to FIGS. 8A and 8B is replaced with the content described above, and the following will focus on the differences.

The voltage layer 240' may be disposed on the second insulating layer 212. The voltage layer 240' may be disposed on a different layer from the vertical driving voltage line (VDL) with the second insulating layer 212 interposed therebetween. The voltage layer 240' may be electrically connected to the vertical driving voltage line (VDL) through the contact hole 212CNT of the second insulating layer 212, and may have the same voltage level as the vertical driving voltage line (VDL).

Although the vertical driving voltage line (VDL) is not shown in FIG. 10, it can be electrically connected to the horizontal driving voltage line (HDL) as previously described with reference to FIG. 6. In some embodiments, the vertical driving voltage line (VDL) and the horizontal driving voltage line (HDL) have an insulating layer interposed therebetween (e.g., a second inter-layer insulating layer 207, a third inter-layer insulating layer 209, and a fourth inter-layer insulating layer). They may be electrically connected through a second contact hole penetrating the insulating layer 210 and the first insulating layer 211.

The voltage layer 240' may be disposed on the data line DL. As described with reference to FIG. 8, the voltage layer 240' may overlap the data line DL with a width greater than the width of the data line DL. The voltage layer 240' may include transparent conductive oxide. The voltage layer 240 is an insulating layer, for example, the first electrode 221 of the first light emitting diode ED1 with the third insulating layer 213, fourth insulating layer 214, and fifth insulating layer 215 interposed therebetween. ) can be nested.

Figure 10 shows that the voltage layer 240' is disposed on the second insulating layer 212, but the present invention is not limited thereto. As another example, the voltage layer 240' may be disposed on the third insulating layer 213 or the fourth insulating layer 214.

FIG. 11 shows a portion of a display panel according to an embodiment of the present invention, and is a plan view showing second light-emitting diodes and second subpixel circuits electrically connected through conductive bus lines, and FIG. 12 is FIG. This is a cross-sectional view along line ‘-XII’.

Each second subpixel circuit PC2 disposed in the third display area DA3 may be electrically connected to a plurality of second light emitting diodes that emit light of the same color. In this regard, Figure 11 shows one second sub-pixel circuit (PC2) electrically connected to two second red light-emitting diodes (ED2r) through a first conductive bus line (CBL1), and the other second sub-pixel circuit (PC2). The subpixel circuit (PC2) is electrically connected to the four second green light emitting diodes (ED2g) through the second conductive bus line (CBL2), and the other second subpixel circuit (PC2) is connected to the third conductive bus line. It is shown electrically connected to two second blue light emitting diodes (ED2b) through a line (CBL3).

The first conductive bus line (CBL1) may extend from the third display area (DA3) toward the second display area (DA2). One part of the first conductive bus line (CBL1) is electrically connected to the second sub-pixel circuit (PC2), and the other part of the first conductive bus line (CBL1) is connected to one of the two second red light emitting diodes (ED2r). Can be electrically connected to one. Among the two second red light emitting diodes (ED2r), one second red light emitting diode (ED2r) connected to the first conductive bus line (CBL1) is connected to the other second red light emitting diode (ED2r) through the first connection line (PWL1). ED2r) can be connected.

The second conductive bus line (CBL2) may extend from the third display area (DA3) toward the second display area (DA2). One part of the second conductive bus line (CBL2) is electrically connected to the second sub-pixel circuit (PC2), and the other part of the second conductive bus line (CBL2) is connected to one of the four second green light emitting diodes (ED2g). Can be electrically connected to one. Among the four second green light emitting diodes (ED2g), one second green light emitting diode (ED2g) connected to the second conductive bus line (CBL2) is connected to the other second green light emitting diode (ED2g) through the second connection line (PWL2). ) can be connected to.

The third conductive bus line CBL3 may extend from the third display area DA3 toward the second display area DA2. One part of the third conductive bus line (CBL3) is electrically connected to the second sub-pixel circuit (PC2), and the other part of the third conductive bus line (CBL3) is connected to one of the two second blue light emitting diodes (ED2b). Can be electrically connected to one. Among the second blue light emitting diodes (ED2b), one second blue light emitting diode (ED2b) connected to the third conductive bus line (CBL3) is connected to the other second blue light emitting diode (ED2b) through the third connection line (PWL3). can be connected with

Referring to FIGS. 11 and 12, at least one of the first to third conductive bus lines (CBL1, CBL2, CBL3) has the voltage layer (240, 240') previously described with reference to FIGS. 8A, 8B, and 10. and can be formed together in the same process. At least one of the first to third conductive bus lines CBL1, CBL2, and CBL3 may be disposed on the same layer as the voltage layers 240 and 240'. In one embodiment, Figure 12 shows the first to third conductive bus lines (CBL1, CBL2, CBL3) on the fourth insulating layer 214, the third insulating layer 213, and the second insulating layer 212, respectively. It shows what is placed in .

At least one of the first to third conductive bus lines CBL1, CBL2, and CBL3 may include the same material as the voltage layers 240 and 240', for example, a translucent conductive material. For example, the first to third conductive bus lines (CBL1, CBL2, CBL3) may include transparent conducting oxide (TCO). Transparent conductive oxides include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In ₂ O ₃ ), and indium gallium oxide. It may include a conductive oxide such as indium gallium oxide (IGO), indium zinc gallium oxide (IZGO), or aluminum zinc oxide (AZO).

The first to third connection lines (PWL1, PWL2, and PWL3) may be transparent. For example, the first to third connection lines (PWL1, PWL2, and PWL3) may include transparent conductive oxide. In some embodiments, the first to third connection lines (PWL1, PWL2, and PWL3) may include the same material as that included in the first electrode 221 of the light emitting diode (FIGS. 8A, 8B, and 10). In some embodiments, when the first electrode 221 includes a sub-layer containing ITO and a sub-layer containing Ag, the first to third connection lines (PWL1, PWL2, PWL3) are connected to the first electrode 221. It can be formed integrally with the sublayer containing ITO.

As such, the present invention has been described with reference to an embodiment shown in the drawings, but this is merely an example, and those skilled in the art will understand that various modifications and variations of the embodiment are possible therefrom. Therefore, the true scope of technical protection of the present invention should be determined by the technical spirit of the attached patent claims.

DL: data line
VSSL: Common voltage line
VDDL: driving voltage line
240, 240': voltage layer

Claims (20)

a subpixel circuit disposed in the display area and including a plurality of transistors;
a data line electrically connected to one of the plurality of transistors of the subpixel circuit and extending along a first direction in the display area;
a voltage layer having a width greater than the width of the data line and overlapping the data line; and
A light emitting diode including a first electrode overlapping the voltage layer, a light emitting layer on the first electrode, and a second electrode on the light emitting layer. According to paragraph 1,
A display device wherein the voltage layer includes a transparent conductive material. According to paragraph 1,
Further comprising a common voltage line disposed in the display area and electrically connected to the second electrode of the light emitting diode,
The display device wherein the voltage layer has the same voltage level as the common voltage line. According to paragraph 3,
The common voltage line is,
A first common voltage line and a second common voltage line extending to intersect each other in the display area,
The voltage layer corresponds to a portion of the first common voltage line. According to paragraph 3,
It further includes an insulating layer interposed between any one selected from a first common voltage line and a second common voltage line and the voltage layer,
The voltage layer is electrically connected to the selected one through a contact hole defined in the insulating layer. According to paragraph 1,
Further comprising a driving voltage line disposed in the display area and electrically connected to the subpixel circuit,
The display device wherein the voltage layer has the same voltage level as the driving voltage line. According to clause 6,
The driving voltage line is,
Includes a first driving voltage line and a second driving voltage line extending to intersect each other in the display area,
The voltage layer is,
A display device electrically connected to a first common voltage line through a contact hole defined in an insulating layer interposed between the first common voltage line and the voltage layer. According to paragraph 1,
The voltage layer overlaps the light emitting area of the light emitting diode. a first light emitting diode electrically connected to a first subpixel circuit arranged in the first display area;
a second light emitting diode located in a second display area inside the first display area and electrically connected to a second subpixel circuit disposed in an area different from the second display area;
a conductive bus line electrically connecting the second sub-pixel circuit and the second light-emitting diode;
a data line electrically connected to one of the plurality of transistors of the first sub-pixel circuit and extending along a first direction in the first display area; and
A voltage layer interposed between the data line and the first electrode of the first light emitting diode and overlapping the data line and the first electrode,
A display device in which the voltage layer has a width greater than the width of the data line. According to clause 9,
The display device wherein the voltage layer includes the same material as the conductive bus line. According to claim 10,
The display device wherein the voltage layer and the conductive bus line include a transparent conductive oxide. According to clause 9,
Further comprising a common voltage line disposed in the first display area and electrically connected to a second electrode of the first light emitting diode,
The display device wherein the voltage layer has the same voltage level as the common voltage line. According to claim 12,
The common voltage line is,
A display device comprising a first common voltage line and a second common voltage line extending to intersect each other in the first display area. According to claim 13,
The display device wherein the first common voltage line overlaps the first electrode of the first light emitting diode. According to claim 14,
The voltage layer corresponds to a portion of the first common voltage line. According to claim 13,
It further includes an insulating layer interposed between any one selected from a first common voltage line and a second common voltage line and the voltage layer,
The voltage layer is electrically connected to the selected one through a contact hole defined in the insulating layer. According to clause 9,
Further comprising a driving voltage line disposed in the first display area and electrically connected to the first subpixel circuit,
The display device wherein the voltage layer has the same voltage level as the driving voltage line. According to claim 17,
The driving voltage line is,
A first driving voltage line and a second driving voltage line extending to intersect each other in the first display area,
The voltage layer is,
A display device electrically connected to a first common voltage line through a contact hole defined in an insulating layer interposed between the first common voltage line and the voltage layer. According to clause 9,
The voltage layer overlaps the light emitting area of the first light emitting diode. According to clause 9,
The display device further includes a component that overlaps the second display area and includes a sensor or camera.

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