KR20230160679A - Display apparatus - Google Patents

Abstract

The present invention provides a high-resolution display device that is robust and flexible against external shocks. The present invention provides a first region including a plurality of first pixel regions arranged at a first pitch along a first direction, and the first pixel regions along the first direction. a substrate having a defined second region including a plurality of second pixel regions arranged at a second pitch smaller than the pitch; A plurality of first trenches disposed on the substrate and each corresponding to a boundary of adjacent first pixel areas in the first direction among the plurality of first pixel areas, and a plurality of second pixel areas a first insulating layer having a plurality of second trenches respectively corresponding to boundaries of second pixel areas adjacent to each other in the first direction; a plurality of first pixel isolation layers each buried in the plurality of first trenches and including a material different from the first insulating layer; and a plurality of second pixel isolation layers each buried in the plurality of second trenches and including a material different from the first insulating layer.

Description

Display apparatus {Display apparatus}

The present invention relates to a display device.

Recently, the uses of display devices have become more diverse. In addition, the thickness of display devices is becoming thinner and lighter, and the scope of their use is expanding.

As display devices are utilized in various ways, there may be various methods for designing the form of the display device. Additionally, as the area occupied by the display area of a display device is expanded, various functions that are incorporated or linked to the display device are being added.

The problem to be solved by the present invention is to provide a high-resolution display device that is flexible and robust against external shocks.

The technical problems to be achieved by the present invention are not limited to the technical problems mentioned above, and other technical problems not mentioned can be clearly understood by those skilled in the art from the description of the present invention. .

According to one aspect of the present invention, a first area including a plurality of first pixel areas arranged at a first pitch along a first direction, and arranged at a second pitch smaller than the first pitch along the first direction. a substrate having a defined second area including a plurality of second pixel areas; A plurality of first trenches disposed on the substrate and each corresponding to a boundary of adjacent first pixel areas in the first direction among the plurality of first pixel areas, and a plurality of second pixel areas a first insulating layer having a plurality of second trenches respectively corresponding to boundaries of second pixel areas adjacent to each other in the first direction; a plurality of first pixel isolation layers each buried in the plurality of first trenches and including a material different from the first insulating layer; and a plurality of second pixel isolation layers each buried in the plurality of second trenches and including a material different from that of the first insulating layer.

According to one example, the first thickness of each of the plurality of first pixel separators along the thickness direction of the substrate may be greater than the second thickness of each of the plurality of second pixel separators along the thickness direction of the substrate. there is.

According to one example, there are a plurality of first areas and a plurality of second areas, and the plurality of first areas and the plurality of second areas may be alternately arranged along the first direction.

According to one example, the display device includes a plurality of first pixel circuits each disposed on some second pixel areas of the plurality of second pixel areas; a plurality of second pixel circuits each disposed on some other second pixel areas among the plurality of second pixel areas; a plurality of first display elements disposed on the first area and each electrically connected to the plurality of first pixel circuits; and a plurality of second display elements disposed on the second area and electrically connected to each of the plurality of second pixel circuits.

According to one example, the first spacing between first display elements that are adjacent to each other in the first direction among the plurality of first display elements is defined by the distance between first display elements that are adjacent to each other in the first direction among the plurality of second display elements. It may be substantially equal to the second spacing between the second display elements.

According to one example, the display device may further include a plurality of conductive patterns interposed between the substrate and the plurality of first pixel separators and each in contact with the plurality of first pixel separators.

According to one example, the display device may further include a plurality of semiconductor patterns interposed between the substrate and the plurality of first pixel isolation films and each in contact with the plurality of first pixel isolation films.

According to one example, the first thickness of each of the plurality of first pixel separators along the thickness direction of the substrate is substantially equal to the second thickness of each of the plurality of second pixel separators along the thickness direction of the substrate. may be the same.

According to one example, the display device includes a plurality of first pixel circuits each disposed on the plurality of first pixel areas; a plurality of second pixel circuits respectively disposed on the plurality of second pixel areas; a plurality of first display elements disposed on the first area and each electrically connected to the plurality of first pixel circuits; and a plurality of second display elements disposed on the second area and electrically connected to each of the plurality of second pixel circuits, wherein among the plurality of first display elements, the plurality of first display elements are aligned with each other in the first direction. A first spacing between neighboring first display elements may be substantially equal to a second spacing between second display elements neighboring each other in the first direction among the plurality of second display elements.

According to one example, a folding area including the first area and the second area and a non-folding area are further defined on the substrate, the display device is disposed below the substrate, and the first area in the folding area is further defined. It may further include a support layer including a first support portion including a slit corresponding to the region and a spoke corresponding to the second region of the folding region, and a second support portion corresponding to the non-folding region.

According to one example, the non-folding area includes a plurality of third pixel areas arranged at a third pitch substantially the same as the first pitch along the first direction, and the first insulating layer includes the plurality of third pixel areas. It further has a plurality of third trenches, each corresponding to a boundary of third pixel regions that are adjacent to each other in the first direction among the three pixel regions, and the display device is respectively buried in the plurality of third trenches, and the display device It may further include a plurality of third pixel separators containing a material different from the first insulating layer.

According to one example, the first thickness of each of the plurality of first pixel separators along the thickness direction of the substrate is the second thickness of each of the plurality of second pixel separators along the thickness direction of the substrate, and the substrate may be greater than the third thickness of each of the plurality of third pixel separators along the thickness direction.

According to one example, the display device includes a plurality of first pixel circuits each disposed on some second pixel areas of the plurality of second pixel areas; a plurality of second pixel circuits each disposed on some other second pixel areas among the plurality of second pixel areas; a plurality of third pixel circuits respectively disposed on the plurality of third pixel areas; a plurality of first display elements disposed on the first area of the folding area and each electrically connected to the plurality of first pixel circuits; a plurality of second display elements disposed on the second area of the folding area and each electrically connected to the plurality of second pixel circuits; and a plurality of third display elements disposed on the non-folding area and electrically connected to each of the plurality of third pixel circuits, wherein among the plurality of first display elements, the plurality of first display elements are disposed on the non-folding area and are electrically connected to each other in the first direction. The first spacing between neighboring first display elements is the second spacing between second display elements neighboring each other in the first direction among the plurality of second display elements and the second spacing between the second display elements neighboring each other in the first direction among the plurality of third display elements. It may be substantially equal to the third spacing between third display elements adjacent to each other in the first direction.

According to one example, the first gap between first pixel separators of the plurality of first pixel separators that are adjacent to each other in the first direction is the distance between first pixel separators of the plurality of second pixel separators that are adjacent to each other in the first direction. It may be larger than the second gap between the second pixel separators.

According to one example, the first insulating layer may include an inorganic material, and the plurality of first pixel separators and the plurality of second pixel separators may include an organic material.

According to one example, the display device includes a conductive layer disposed on the first insulating layer; and a second insulating layer disposed on the conductive layer and integral with the plurality of first pixel isolation films and the plurality of second pixel isolation films.

According to one example, the plurality of first pixel areas are arranged at a third pitch along a second direction intersecting the first direction, and the plurality of second pixel areas are arranged at the third pitch along the second direction. It may be arranged at a fourth pitch that is substantially the same as.

According to another aspect of the present invention, there is provided a substrate comprising: a substrate having a defined first region including a plurality of first pixel regions and a second region including a plurality of second pixel regions; An insulating layer disposed on the substrate and having a plurality of first trenches each at least partially surrounding the plurality of first pixel regions, and a plurality of second trenches each at least partially surrounding the plurality of second pixel regions. ; a plurality of first pixel isolation layers each buried in the plurality of first trenches and including a material different from the insulating layer; and a plurality of second pixel isolation films each buried in the plurality of second trenches and including a material different from the insulating layer, and each of the plurality of first pixel isolation films along the thickness direction of the substrate. A display device is provided in which one depth is greater than a second depth of each of the plurality of second pixel separators along the thickness direction of the substrate.

According to one example, a display device includes a plurality of first pixel circuits each disposed on some second pixel areas of the plurality of second pixel areas; a plurality of second pixel circuits each disposed on some other second pixel areas among the plurality of second pixel areas; a plurality of first display elements disposed on the first area and each electrically connected to the plurality of first pixel circuits; and a plurality of second display elements disposed on the second area and electrically connected to each of the plurality of second pixel circuits.

According to one example, the first spacing between neighboring first display elements among the plurality of first display elements is the second spacing between neighboring second display elements among the plurality of second display elements. may be substantially the same as

According to one example, the display device is interposed between the substrate and the plurality of first pixel isolation films and further includes a plurality of conductive patterns or a plurality of semiconductor patterns respectively contacting the plurality of first pixel isolation films. can do.

According to one example, there are a plurality of first areas and a plurality of second areas, and the plurality of first areas and the plurality of second areas may be alternately arranged along one direction.

According to one example, a folding area including the first area and the second area and a non-folding area are further defined on the substrate, the display device is disposed below the substrate, and the first area in the folding area is further defined. It may further include a support layer including a first support portion including a slit corresponding to the region and a spoke corresponding to the second region of the folding region, and a second support portion corresponding to the non-folding region.

According to one example, the non-folding area includes a plurality of third pixel regions, the insulating layer further has a plurality of third trenches each at least partially surrounding the plurality of third pixel regions, and the display device further comprising a plurality of third pixel isolation films each buried in the plurality of third trenches and including a material different from the insulating layer, wherein the first depth of each of the plurality of first pixel isolation films is defined by the thickness of the substrate. It may be greater than the third depth of each of the plurality of third pixel separators along the thickness direction.

According to one example, the insulating layer may include an inorganic material, and the plurality of first pixel separators and the plurality of second pixel separators may include an organic material.

Other aspects, features and advantages other than those described above will become apparent from the detailed description, claims and drawings for carrying out the invention below.

These general and specific aspects may be practiced using any system, method, computer program, or combination of any system, method, or computer program.

According to an embodiment of the present invention as described above, a high-resolution display device that is robust and flexible against external shock can be implemented. Of course, the scope of the present invention is not limited by this effect.

1 is a plan view schematically showing a display device according to an embodiment.
FIG. 2 is an enlarged plan view illustrating parts I and II of FIG. 1 by way of example.
FIG. 3 is an exemplary cross-sectional view of a portion of the display device of FIG. 2 taken along lines III-III' and lines IV-IV'.
FIG. 4 is an exemplary cross-sectional view of a portion of the display device of FIG. 2 taken along lines III-III' and lines IV-IV'.
FIG. 5 is an exemplary cross-sectional view of a portion of the display device of FIG. 2 taken along lines III-III' and lines IV-IV'.
FIG. 6 is an exemplary cross-sectional view of a portion of the display device of FIG. 2 taken along lines III-III' and lines IV-IV'.
FIG. 7 is an enlarged plan view illustrating parts I and II of FIG. 1 by way of example.
Figure 8 is a perspective view schematically showing a display device according to an embodiment.
FIG. 9 is a perspective view schematically showing a folded form of a display device according to an exemplary embodiment.
FIG. 10 is a diagram schematically showing the structure of the display device of FIG. 8 according to an embodiment.
FIG. 11A is an enlarged plan view illustrating portion VII of the support layer of FIG. 10.
FIG. 11B is an exemplary cross-sectional view of a portion of the support layer of FIG. 11A taken along line VIII-VIII'.
FIG. 12 is an enlarged plan view illustrating portion VII of the support layer of FIG. 10.
FIG. 13 is an exemplary cross-sectional view of a portion of the display device of FIG. 8 taken along line V-V'.
Figure 14 is a cross-sectional view schematically showing a portion of a display device according to an embodiment.
FIG. 15 is an equivalent circuit diagram of one pixel included in the display device of FIG. 8.
FIG. 16 is a diagram illustrating a schematic arrangement of light emitting areas of a plurality of pixels arranged in a display area according to an embodiment.
FIG. 17 is an enlarged plan view illustrating part VI of FIG. 8 by way of example.
FIG. 18 is an enlarged plan view illustrating part VI of FIG. 8 by way of example.
FIG. 19 is an exemplary cross-sectional view of a portion of the display device of FIG. 18 taken along line IX-IX'.
FIG. 20 is an exemplary cross-sectional view of a portion of the display device of FIG. 18 taken along line IX-IX'.
FIG. 21 is an exemplary cross-sectional view of a portion of the display device of FIG. 18 taken along line IX-IX'.
FIG. 22 is an exemplary cross-sectional view of a portion of the display device of FIG. 18 taken along line IX-IX'.
FIG. 23 is an exemplary cross-sectional view of a portion of the display device of FIG. 18 taken along line IX-IX'.

Since the present invention can be modified in various ways and can have various embodiments, specific embodiments will be illustrated in the drawings and described in detail in the detailed description. The effects and features of the present invention and methods for achieving them will become clear by referring to the embodiments described in detail below along with the drawings. However, the present invention is not limited to the embodiments disclosed below and may be implemented in various forms.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. When describing with reference to the drawings, identical or corresponding components will be assigned the same reference numerals and redundant description thereof will be omitted. .

In the following embodiments, terms such as first and second are used not in a limiting sense but for the purpose of distinguishing one component from another component.

In the following embodiments, singular terms include plural terms unless the context clearly dictates otherwise.

In the following embodiments, terms such as include or have mean the presence of features or components described in the specification, and do not preclude the possibility of adding one or more other features or components. .

In the following embodiments, when a part of a film, region, component, etc. is said to be on or on another part, it is not only the case that it is directly on top of the other part, but also when another film, region, component, etc. is interposed between them. Also includes cases where it is.

In the drawings, the sizes of components may be exaggerated or reduced for convenience of explanation. For example, the size and thickness of each component shown in the drawings are shown arbitrarily for convenience of explanation, so the present invention is not necessarily limited to what is shown.

In cases where an embodiment can be implemented differently, a specific process sequence may be performed differently from the described sequence. For example, two processes described in succession may be performed substantially at the same time, or may be performed in an order opposite to that in which they are described.

In this specification, “A and/or B” refers to A, B, or A and B. And, “at least one of A and B” indicates the case of A, B, or A and B.

In the following embodiments, when membranes, regions, components, etc. are said to be connected, if the membranes, regions, and components are directly connected, or/and other membranes, regions, and components are in the middle of the membranes, regions, and components. This also includes cases where they are interposed and indirectly connected. For example, in this specification, when membranes, regions, components, etc. are said to be electrically connected, when the membranes, regions, components, etc. are directly electrically connected, and/or other membranes, regions, components, etc. are interposed. indicates a case of indirect electrical connection.

The x-axis, y-axis, and z-axis are not limited to the three axes in the Cartesian coordinate system and can be interpreted in a broad sense including these. For example, the x-axis, y-axis, and z-axis may be orthogonal to each other, but may also refer to different directions that are not orthogonal to each other.

1 is a plan view schematically showing a display device according to an embodiment.

Referring to FIG. 1 , the display device 1 includes a display area DA that displays an image and a peripheral area PA surrounding at least a portion of the display area DA. The display device 1 may provide an image to the outside using light emitted from the display area DA. Of course, since the display device 1 includes the substrate 100, it may be said that the substrate 100 has a display area DA and a peripheral area PA. In other words, it may be said that the display area DA and the peripheral area PA are defined on the substrate 100.

The substrate 100 may be made of various materials such as glass, metal, or plastic. According to one embodiment, the substrate 100 may include a flexible material. Here, flexible material refers to a material that bends, bends, and can be folded or rolled. The substrate 100 made of such a flexible material may be made of ultra-thin glass, metal, or plastic.

The display area DA may be provided in a rectangular shape as shown in FIG. 1 . In another embodiment, the display area DA may have a polygonal shape such as a triangle, pentagon, or hexagon, or a circular, oval, or irregular shape.

Pixels PX including various display elements such as organic light-emitting diodes (OLEDs) may be disposed in the display area DA of the substrate 100. The pixels (PX) are composed of a plurality, and the plurality of pixels (PX) can be arranged in various forms such as a stripe arrangement, a pentile arrangement, or a mosaic arrangement to create an image. Hereinafter, in this specification, each pixel (PX) refers to a sub-pixel that emits different colors, and each pixel (PX) is, for example, one of a red sub-pixel, a green sub-pixel, and a blue sub-pixel. It can be.

As a display device according to an embodiment of the present invention, an organic light emitting display device will be described as an example, but the display device of the present invention is not limited thereto. As another example, the display device of the present invention may be an inorganic light emitting display (Inorganic Light Emitting Display) or a display device such as a quantum dot light emitting display (Quantum Dot Light Emitting Display). For example, the light emitting layer of the display element provided in the display device contains an organic material, an inorganic material, quantum dots, an organic material and a quantum dot, an inorganic material and a quantum dot, or an organic material, an inorganic material, and a quantum dot. It may also include .

Meanwhile, the display area DA may include a first area AR1 and a second area AR2. As will be described later in FIG. 2, the first area AR1 includes first pixel areas PXAR1 arranged at a first pitch pt1 along a first direction (eg, ±y direction), and Area 2 AR2 may include second pixel areas PXAR2 arranged at a second pitch pt2 that is different from the first pitch pt1 along the first direction (eg, ±y direction).

In FIG. 1, the area of the first area AR1 and the area of the second area AR2 are shown to be the same. However, in another embodiment, the area of the first area AR1 and the area of the second area AR2 are may be different from each other. Additionally, in one embodiment, there may be a plurality of first and second areas AR1 and AR2, respectively. The first areas AR1 and the second areas AR2 may be arranged alternately along one direction.

The peripheral area PA of the substrate 100 is an area disposed around the display area DA and may be an area where an image is not displayed. In the peripheral area PA, various wires that transmit electrical signals to be applied to the display area DA and pads to which a printed circuit board or driver IC chip are attached may be located.

FIG. 2 is an enlarged plan view illustrating parts I and II of FIG. 1 by way of example.

Referring to FIG. 2 , the display device 1 (see FIG. 1 ) includes a first area AR1 and a second area AR2 (or the first area AR1 and the second area AR2 are defined). ) may include a substrate 100 (see FIG. 1), a first insulating layer IL1, and first to fourth pixel separators PSL1, PSL2, PSL3, and PSL4.

The first area AR1 may include first pixel areas PXAR1 arranged along a first direction (eg, ±y direction) and a second direction (eg, ±x direction). The second area AR2 may include second pixel areas PXAR2 arranged along a first direction (eg, ±y direction) and a second direction (eg, ±x direction).

In one embodiment, the first pixel areas PXAR1 are arranged at a first pitch pt1 along the first direction (eg, ±y direction), and the second pixel areas PXAR2 are arranged in the first direction (eg, ±y direction). For example, it may be arranged at a second pitch (pt2) along the ±y direction. The first pitch (pt1) and the second pitch (pt2) may be different from each other. For example, the second pitch (pt2) may be smaller than the first pitch (pt1).

In one embodiment, the first pixel areas PXAR1 are arranged at a third pitch pt3 along the second direction (eg, ±x direction), and the second pixel areas PXAR2 are arranged in the second direction (eg, ±x direction). For example, it may be arranged at a fourth pitch (pt4) along the ±x direction. The third pitch (pt3) and the fourth pitch (pt4) may be substantially the same.

The first insulating layer IL1 may be disposed on the substrate 100 . The first insulating layer IL1 may have first to fourth trenches tr1, tr2, tr3, and tr4. The first trenches tr1 respectively correspond to the boundaries of the first pixel areas PXAR1 that are adjacent to each other in the first direction (eg, ±y direction) among the plurality of first pixel areas PXAR1, and the second trenches tr1 The trenches tr2 may respectively correspond to boundaries of second pixel areas PXAR2 that are adjacent to each other in the first direction (eg, ±y direction) among the plurality of second pixel areas PXAR2. The third trenches tr3 respectively correspond to the boundaries of the first pixel areas PXAR1 that are adjacent to each other in the second direction (eg, ±x direction) among the plurality of first pixel areas PXAR1, and the fourth trenches tr3 The trenches tr4 may each correspond to boundaries of second pixel areas PXAR2 that are adjacent to each other in the second direction (eg, ±x direction) among the plurality of second pixel areas PXAR2.

The first pixel separators PSL1 are respectively buried in the first trenches tr1, the second pixel separators PSL2 are respectively buried in the second trenches tr2, and the third pixel separators PSL3 are respectively buried in the third trenches tr1. Each of the trenches tr3 may be buried, and the fourth pixel isolation layers PSL4 may be each buried in the fourth trenches tr4. The first pixel separators PSL1 and the third pixel separators PSL3 may have a grid shape (or mesh structure). The second pixel separators PSL2 and the fourth pixel separators PSL4 may have a grid shape (or mesh structure).

Meanwhile, in FIG. 2, the first pixel area (PXAR1) is shown as being entirely surrounded by the first pixel separators (PSL1) and the third pixel separators (PSL3). However, in another embodiment, the first pixel area (PXAR1) PXAR1) may be partially surrounded by the first pixel separators (PSL1) and third pixel separators (PSL3). Although the description is based on the first pixel area (PXAR1), the second pixel area (PXAR2) can also be applied in the same way. For example, in FIG. 2, the second pixel area PXAR2 is shown as being entirely surrounded by the second pixel isolation films PSL2 and the fourth pixel isolation films PSL4. However, in another embodiment, the second pixel area PXAR2 is entirely surrounded by the second pixel isolation films PSL2 and the fourth pixel isolation films PSL4. The area PXAR2 may be partially surrounded by the second pixel separators PSL2 and the fourth pixel separators PSL4.

In one embodiment, the first gap gp1 between the first pixel separators PSL1 adjacent to each other in the first direction (eg, ±y direction) among the plurality of first pixel separators PSL1 is The second gap gp2 may be different from the second gap gp2 between the second pixel separators PSL2 adjacent to each other in the first direction (eg, ±y direction) among the plurality of second pixel separators PSL2. For example, the first gap (gp1) may be larger than the second gap (gp2).

In one embodiment, the third gap gp3 between the third pixel separators PSL3 adjacent to each other in the second direction (eg, ±x direction) among the plurality of third pixel separators PSL3 is It may be substantially equal to the fourth gap gp4 between adjacent fourth pixel separators PSL4 in the second direction (for example, ±x direction) among the plurality of fourth pixel separators PSL4. .

In one embodiment, the first to fourth pixel separators PSL1, PSL2, PSL3, and PSL4 may include a material different from the first insulating layer IL1. For example, the first insulating layer IL1 may include an inorganic material, and the first to fourth pixel separators PSL1, PSL2, PSL3, and PSL4 may include an organic material. Since the first to fourth pixel separators (PSL1, PSL2, PSL3, and PSL4) contain organic materials, cracks formed in the first insulating layer (IL1) containing inorganic materials in one pixel due to an impact from the outside may spread into adjacent pixels. Growth can be more effectively prevented or minimized.

FIG. 3 is an exemplary cross-sectional view of a portion of the display device of FIG. 2 taken along lines III-III' and lines IV-IV'.

Referring to FIG. 3, the display device 1 (see FIG. 1) includes a substrate 100, a barrier layer 110, a first insulating layer (IL1), a second insulating layer (IL2), and first and second pixel separators. (PSL1, PSL2), and a conductive layer (CL).

The substrate 100 may include glass or polymer resin. Polymer resins include polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, It may include polyarylate, polyimide, polycarbonate, or cellulose acetate propionate. The substrate 100 containing polymer resin may have flexible, rollable, or bendable characteristics. The substrate 100 may have a multilayer structure including a layer containing the above-described polymer resin and an inorganic layer.

The barrier layer 110 may be disposed on the substrate 100 . The barrier layer 110 may serve to prevent or minimize impurities from the substrate 100 or the like from penetrating into the display device 1 . The barrier layer 110 may include an inorganic material such as oxide or nitride, an organic material, or an organic-inorganic composite, and may have a single-layer or multi-layer structure of an inorganic material and an organic material.

The first insulating layer IL1 may be disposed on the barrier layer 110 . The first insulating layer IL1 is made of silicon oxide (SiO ₂ ), silicon nitride (SiN _x ), silicon oxynitride (SiON), aluminum oxide (Al ₂ O ₃ ), titanium oxide (TiO ₂ ), and tantalum oxide (Ta _{2 )} . O ₅ ), hafnium oxide (HfO ₂ ), or zinc oxide (ZnO ₂ ) may be included. The first insulating layer IL1 may have a first trench (tr1) and a second trench (tr2). As described above in FIG. 2 , the first trench tr1 may correspond to the boundary of the first pixel areas PXAR1, and the second trench tr2 may correspond to the boundary of the second pixel areas PXAR2.

In one embodiment, the first depth dp1 of the first trench tr1 along the thickness direction (e.g., ±z direction) of the substrate 100 is the thickness direction (e.g., ±z direction) of the substrate 100. It may be different from the second depth (dp2) of the second trench (tr2) along the ±z direction. For example, the first depth dp1 may be greater than the second depth dp2. Although the description has been made based on the first trench (tr1) and the second trench (tr2), the third trench (tr3) and the fourth trench (tr4) shown in FIG. 2 described above can be equally applied. The depth of the third trench (tr3) along the thickness direction (eg, ±z direction) of the substrate 100 is the depth of the fourth trench (tr4) along the thickness direction (eg, ±z direction) of the substrate 100. ) can be greater than the depth of.

The first pixel separator PSL1 may be disposed in the first trench tr1, and the second pixel separator PSL2 may be disposed in the second trench tr2. In other words, the first pixel separator PSL1 may be buried in the first trench tr1, and the second pixel separator PSL2 may be buried in the second trench tr2. As the first and second pixel separators (PSL1 and PSL2) are disposed in the first and second trenches (tr1 and tr2), respectively, a first insulating layer (IL1) is formed by the first and second trenches (tr1 and tr2). ) can be eliminated or minimized. The first and second pixel separators PSL1 and PSL2 may be formed as a single or multi-layered film made of an organic material. For example, the first and second pixel separators (PSL1, PSL2) are made of general-purpose polymers such as BCB (Benzocyclobutene), polyimide, HMDSO (Hexamethyldisiloxane), Polymethylmethacrylate (PMMA), Polystyrene (PS), and phenol. It may include polymer derivatives having a group, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorine polymers, p-xylene polymers, vinyl alcohol polymers, and blends thereof.

In one embodiment, the first gap gp1 between the first pixel separators PSL1 adjacent to each other in the first direction (eg, ±y direction) among the plurality of first pixel separators PSL1 is The second gap gp2 may be different from the second gap gp2 between the second pixel separators PSL2 adjacent to each other in the first direction (eg, ±y direction) among the plurality of second pixel separators PSL2. For example, the first gap (gp1) may be larger than the second gap (gp2).

In one embodiment, the first thickness th1 of the first pixel separator PSL1 along the thickness direction (e.g., ±z direction) of the substrate 100 is in the thickness direction (e.g., ±z direction) of the substrate 100. , ±z direction) may be different from the second thickness (th2) of the second pixel separator (PSL2). For example, the first thickness th1 may be greater than the second thickness th2. Although the description has been made based on the first pixel separator PSL1 and the second pixel separator PSL2, the third pixel separator PSL3 and fourth pixel separator PSL4 shown in FIG. 2 described above can be equally applied. The thickness of the third pixel separator PSL3 along the thickness direction (eg, ±z direction) of the substrate 100 is the fourth pixel separator film along the thickness direction (eg, ±z direction) of the substrate 100. It may be larger than the thickness of (PSL4).

The conductive layer CL may be disposed on the first insulating layer IL1. The conductive layer (CL) may contain a conductive material containing molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may be formed as a multilayer or single layer containing the above materials. there is. For example, the conductive layer CL may have a multilayer structure of Ti/Al/Ti.

The second insulating layer IL2 may be disposed on the first insulating layer IL1 to cover the conductive layer CL. The second insulating layer IL2 may be formed as a single or multi-layered film made of an organic material, and provides a flat top surface. This second insulating layer (IL2) is made of a general-purpose polymer such as Benzocyclobutene (BCB), polyimide, Hexamethyldisiloxane (HMDSO), Polymethylmethacrylate (PMMA), or Polystyrene (PS), a polymer derivative having a phenolic group, It may include acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorine polymers, p-xylene polymers, vinyl alcohol polymers, and blends thereof.

In one embodiment, the second insulating layer IL2 may be integrated with the first and second pixel separators PSL1 and PSL2.

FIG. 4 is an exemplary cross-sectional view of a portion of the display device of FIG. 2 taken along lines III-III' and lines IV-IV'. Figure 4 is a modified example of Figure 3, with differences in the structures of the trench and pixel isolation film. In the following, overlapping content will be replaced with the description of FIG. 3 and the differences will be mainly explained.

Referring to FIG. 4, in one embodiment, the first depth dp1' of the first trench tr1 along the thickness direction (eg, ±z direction) of the substrate 100 is the thickness of the substrate 100. It may be substantially equal to the second depth dp2' of the second trench tr2 along the thickness direction (eg, ±z direction). Although the description has been made based on the first trench (tr1) and the second trench (tr2), the third trench (tr3) and the fourth trench (tr4) shown in FIG. 2 described above can be equally applied. The depth of the third trench (tr3) along the thickness direction (eg, ±z direction) of the substrate 100 is the depth of the fourth trench (tr4) along the thickness direction (eg, ±z direction) of the substrate 100. ) may be substantially the same as the depth of.

In one embodiment, the first thickness (th1') of the first pixel separator PSL1 along the thickness direction (e.g., ±z direction) of the substrate 100 is in the thickness direction (e.g., ±z direction) of the substrate 100. For example, it may be substantially equal to the second thickness (th2') of the second pixel separator (PSL2) along the ±z direction. Although the description has been made based on the first pixel separator PSL1 and the second pixel separator PSL2, the third pixel separator PSL3 and fourth pixel separator PSL4 shown in FIG. 2 described above can be equally applied. The thickness of the third pixel separator PSL3 along the thickness direction (eg, ±z direction) of the substrate 100 is the fourth pixel separator film along the thickness direction (eg, ±z direction) of the substrate 100. It may be substantially the same as the thickness of (PSL4).

FIG. 5 is an exemplary cross-sectional view of a portion of the display device of FIG. 2 taken along lines III-III' and lines IV-IV'. Figure 5 is a modified example of Figure 3, with a difference in the structure of the conductive pattern. In the following, overlapping content will be replaced with the description of FIG. 3 and the differences will be mainly explained.

Referring to FIG. 5 , the display device 1 (see FIG. 1 ) may include conductive patterns CP. The conductive patterns CP are interposed between the substrate 100 and the first pixel separators PSL1 and may contact each of the first pixel separators PSL1. Conductive patterns (CP) may contain conductive materials including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may be formed as a multilayer or single layer including the above materials. there is. As an example, the conductive patterns CP may be a single layer of Mo.

The conductive patterns CP may serve to help ensure a uniform etching depth when etching the first insulating layer IL1 to form the first trench tr1. By disposing the conductive patterns CP between the substrate 100 and the first pixel isolation layers PSL1, first trenches tr1 with uniform depth can be formed in the first insulating layer IL1.

FIG. 6 is an exemplary cross-sectional view of a portion of the display device of FIG. 2 taken along lines III-III' and lines IV-IV'. Figure 6 is a modified example of Figure 3, with a difference in the structure of the semiconductor pattern. In the following, overlapping content will be replaced with the description of FIG. 3 and the differences will be mainly explained.

Referring to FIG. 6 , the display device 1 (see FIG. 1 ) may include semiconductor patterns (SCPs). The semiconductor patterns SCP are interposed between the substrate 100 and the first pixel separators PSL1 and may contact each of the first pixel separators PSL1. Semiconductor patterns (SCPs) may include amorphous silicon or polysilicon. In another embodiment, the semiconductor patterns (SCP) include indium (In), gallium (Ga), stanium (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), and germanium (Ge). ), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce), and zinc (Zn).

The semiconductor patterns (SCP) may serve to help ensure a uniform etching depth when etching the first insulating layer (IL1) to form the first trench (tr1). By disposing the semiconductor patterns SCP between the substrate 100 and the first pixel isolation layers PSL1, first trenches tr1 with uniform depth can be formed in the first insulating layer IL1.

FIG. 7 is an enlarged plan view illustrating parts I and II of FIG. 1 by way of example. In FIG. 7, the same reference numerals as in FIG. 2 refer to the same members, and duplicate description thereof will be omitted.

Referring to FIG. 7 , the display device 1 (see FIG. 1 ) may include first display elements DE1 and second display elements DE2. The first display elements DE1 may be arranged in the first area AR1 along a first direction (eg, ±y direction) and a second direction (eg, ±x direction). The second display elements DE2 may be arranged in the second area AR2 along a first direction (eg, ±y direction) and a second direction (eg, ±x direction).

In one embodiment, the first gap gg1 between the first display elements DE1 that are adjacent to each other in the first direction (eg, ±y direction) among the plurality of first display elements DE1 is Among the plurality of second display elements DE2, the second spacing gg2 between neighboring second display elements DE2 in the first direction (eg, ±y direction) may be substantially equal to the same. . A first pitch pt1 along the first direction (for example, ±y direction) of the first pixel areas PXAR1 arranged in the first area AR1 and a second pixel arranged in the second area AR2 The second pitch pt2 along the first direction (eg, ±y direction) of the areas PXAR2 may be different, but the first gap gg1 and the second gap gg2 may be substantially the same.

Figure 8 is a perspective view schematically showing a display device according to an embodiment. FIG. 9 is a perspective view schematically showing a folded form of a display device according to an exemplary embodiment. FIG. 8 is a perspective view showing the display device in an unfolded state, and FIG. 9 is a perspective view showing the display device in a folded state.

The display device 11 is a device that displays moving images or still images, and may be used in a mobile phone, a smart phone, a tablet personal computer, a mobile communication terminal, an electronic notebook, an e-book, or a PMP ( It can be used as a display screen for various products such as televisions, laptops, monitors, billboards, and the Internet of Things (IOT), as well as portable electronic devices such as portable multimedia players, navigation, and UMPC (Ultra Mobile PC). Additionally, the display device 11 may be used in wearable devices such as smart watches, watch phones, glasses-type displays, and head mounted displays (HMDs). In addition, the display device 11 may include a CID (Center Information Display) placed on the dashboard of a car, a center fascia or dashboard of a car, a room mirror display instead of a side mirror of a car, It can be used as entertainment for the backseat of a car and as a display placed on the back of the front seat.

As shown in FIG. 8, the display device 11 can be spread out flat as a whole. The display device 11 may be folded or curved, as shown in FIG. 9 .

In one embodiment, the display device 11 can be folded so that the display surfaces face each other. In another embodiment, the display device 11 may be folded so that the display surface faces outward. Here, the “display surface” is the surface on which the image is displayed. The display surface includes a display area (DDA) and a peripheral area (PPA), and an image can be provided to the user through the display area (DDA). Here, the term "folded" means that the shape is not fixed, but can be transformed from the original shape to another shape, such as being folded, curved, or rolled along one or more specific lines, that is, the folding axis. It may include being rolled in a certain way.

Referring to FIGS. 8 and 9 , the display device 11 may have a display area DDA and a peripheral area PPA located outside the display area DDA. The display area DDA may be an area where a plurality of pixels P are arranged to display an image. The peripheral area PPA may be a non-display area surrounding the display area DDA and in which pixels P are not arranged.

The display area DDA may include a first display area DDA1 and a second display area DDA2. The first display area DDA1 may be a flexible folding area, and there may be one or more folding areas. The second display area DDA2 may be a non-folding area. Here, in one embodiment of the present invention, the region that is not folded is referred to as the non-folding region, but this is for convenience of explanation. The expression "non-folding" is used not only for the case where it is rigid due to lack of flexibility, but also for the case where it is flexible. This may include a case where it has flexibility smaller than the folding area, and a case where it has flexibility but does not fold. The display device 11 can display images in the first display area (DDA1) and the second display area (DDA2).

The first display area DDA1 may include a first folding area FA1 and a second folding area FA2. The first folding area FA1 can be folded based on the first folding axis FAX1, and the second folding area FA2 can be folded based on the second folding axis FAX2. In one embodiment, the first folding area FA1 and the second folding area FA2 may have similar areas. In another embodiment, the first folding area FA1 and the second folding area FA2 may have different areas.

The second display area DDA2 may include a first non-folding area NFA1, a second non-folding area NFA2, and a third non-folding area NFA3. A first folded area (FA1) is interposed between the first unfolded area (NFA1) and the second unfolded area (NFA2), and a second unfolded area (FA1) is disposed between the second unfolded area (NFA2) and the third unfolded area (NFA3). 2 A folding area (FA2) may be present.

In the peripheral area PA, various electronic devices or printed circuit boards may be electrically attached, and voltage lines that supply power to drive display elements may be located. For example, in the peripheral area (PA), there is a scan driver that provides a scan signal to each pixel (P), a data driver that provides a data signal to each pixel (P), and a supply line for signals input to the scan driver and data driver ( clock signal line, carry signal line, driving voltage line, etc.), and main power line, etc. may be disposed.

FIG. 10 is a diagram schematically showing the structure of the display device of FIG. 8 according to an embodiment. FIG. 11A is an enlarged plan view exemplarily showing a portion VII of the support layer of FIG. 10, and FIG. 11B is an exemplary cross-sectional view of a portion of the support layer of FIG. 11A taken along the line VIII-VIII'. FIG. 12 is an enlarged plan view illustrating portion VII of the support layer of FIG. 10. FIG. 13 is an exemplary cross-sectional view of a portion of the display device of FIG. 8 taken along line V-V'.

Referring to FIG. 10 , the display device 11 may include a display panel 10, a support layer 50, and a lower cover 90.

The display panel 10 may include a display area (DDA) and a peripheral area (PPA). The display area DDA may include a first display area DDA1 and a second display area DDA2. At least one folding area and at least one non-folding area may be defined in the display panel 10 . At least one folding area may correspond to the first display area DDA1, and at least one non-folding area may correspond to the second display area DDA2.

The first display area DDA1 may include a first folding area FA1 and a second folding area FA2. The second display area DDA2 may include a first non-folding area NFA1, a second non-folding area NFA2, and a third non-folding area NFA3. The first display area DDA1 and the second display area DDA2 may be surrounded by a peripheral area PPA.

As shown in FIG. 13 , the support layer 50 may be disposed below the display panel 10 to support the display panel 10 . The support layer 50 may include a plurality of first support parts 50A and a plurality of second support parts 50B. The first support portions 50A and the second support portions 50B may be formed integrally. Each of the first support parts 50A may correspond to (or overlap) the first folding area FA1 and the second folding area FA2 of the display panel 10 . Each of the second support parts 50B corresponds to (or overlaps) the first non-folding area NFA1, the second non-folding area NFA2, and the third non-folding area NFA3 of the display panel 10. can do. The first support portion 50A may be located between the second support portions 50B.

Each of the first folding area FA1 and the second folding area FA2 of the display panel 10 may include first areas AAR1 and second areas AAR2. The first areas AAR1 of the first folding area FA1 and the second folding area FA2 each correspond to (or overlap) the slits 50S of the first support 50A, and the first folding area ( The second areas (AAR2) of the second folding area (FA1) and FA2 may correspond to (or overlap) the spokes 50P of the first support part 50A, respectively. The first areas AAR1 and the second areas AAR2 may be alternately arranged along the first direction (eg, ±x direction).

Meanwhile, as will be described later in FIG. 17, the first area (AAR1) of the first folding area (FA1) is a first area (AAR1) arranged at a first pitch (CI1) along the first direction (eg, ±x direction). It includes pixel areas PPXAR1, and the second area AAR2 of the first folding area FA1 has a second pitch different from the first pitch CI1 along the first direction (eg, ±x direction). It may include second pixel areas (PPXAR2) arranged as CI2). The first non-folding area NFA1 may include third pixel areas PPXAR3 arranged at a third pitch CI3 along a first direction (eg, ±x direction). The first pitch CI1 and the third pitch CI3 may be substantially the same. Although the description is based on the first folded area (FA1) and the first unfolded area (NFA1), the second folded area (FA2), the second unfolded area (NFA2), and the third unfolded area (NFA3) are also described in the same way. It can be applied.

The support layer 50 may have various structures depending on whether the display device 11 is folded and the folding shape. For example, when the display device 11 is not folded, the support layer 50 does not have a variable shape and may have a flat top surface. When the display device 11 is folded, the support layer 50 may be folded together with the display panel 10. Each of the first supports 50A may be folded based on the first folding axis FAX1 and the second folding axis FAX2.

Each of the first supports 50A may include a plurality of slits 50S and have a certain pattern. The plurality of slits 50S may be arranged along the ±y direction (longitudinal direction, second direction) and the ±x direction perpendicular to the ±y direction (width direction, first direction). The plurality of slits 50S may have a length (ℓ) along the ±y direction parallel to the folding axis of the folding area. For example, the plurality of slits 50S may have a long oval shape along the ±y direction.

In one embodiment, as shown in FIGS. 11A and 11B, each of the first supports 50A has a grid pattern in which a plurality of slits 50S of the same length are spaced apart along the ±y direction and ±x direction. You can have it. The width (lw) of the bars (or grid lines) 50P of the grid pattern may be determined by the first spacing (d1) in the ±x direction and the second spacing (d2) in the ±y direction between the slits (50S). there is. The plurality of slits 50S may be arranged at regular or irregular intervals along the ±y direction and/or ±x direction. The plurality of slits 50S may have the same shape or different shapes. The degree of flexibility of the first support portion 50A is determined by at least one of the length l and width sw of the slits 50S, the first spacing d1 and the second spacing d2 between the slits 50S. can be decided. In another embodiment, as shown in FIG. 12, each of the first supports 50A may have a slit pattern in which a plurality of slits 50S of the same length are arranged in parallel and spaced apart along the ±x direction. The spokes (50P) and slits (50S) of the slit pattern can alternate in the ±x direction.

The support layer 50 may include at least one of glass, plastic, and metal. In one embodiment, the support layer 50 may include polyurethane or carbon fiber reinforced plastic (Carbon). In one embodiment, the support layer 50 may include at least one of stainless steel, invar, nickel (Ni), cobalt (Co), nickel alloy, and nickel-cobalt alloy. In one embodiment, the support layer 50 may include austenitic stainless steels.

As shown in FIG. 13, the cushion layer 70 may be disposed below the support layer 50. The cushion layer 70 can prevent or minimize damage to the support layer 50 and the display panel 10 disposed on the cushion layer 70 due to external impact. In one embodiment, the cushion layer 70 may have an opening 70OP based on the folding axis.

The lower cover 90 may form the lower surface of the display device 11 . The lower cover 90 may include plastic, metal, or both plastic and metal. The lower cover 90 includes first display areas DDA1, which are folding areas of the display panel 10, hinge areas 90A overlapping the first support parts 50A of the support layer 50, and other flat parts. (90B) may include. The flat portion 90B may overlap the second display areas DDA2, which are non-folding areas of the display panel 10, and the second support portions 50B of the support layer 50. Each of the hinge areas 90A of the lower cover 90 may be folded based on the first folding axis FAX1 and the second folding axis FAX2.

Figure 14 is a cross-sectional view schematically showing a portion of a display device according to an embodiment.

Referring to FIG. 14 , the display device 11 may include a display panel 10 and a support layer 50 disposed to overlap the display panel 10 . A cover window (not shown) may be further disposed on the display panel 10 to protect the display panel 10.

The display panel 10 may include a substrate 100, a display layer (DISL), a touch sensor layer (TSL), and an optical function layer (OFL) on the substrate 100. The display panel 10 may include a first display area (DDA1) and a second display area (DDA2). The first display area DDA1 may be a folding area, and there may be one or more folding areas. The second display area DDA2 may be a non-folding area.

The substrate 100 may be made of an insulating material such as glass, quartz, or polymer resin. The substrate 100 may be a flexible substrate capable of bending, folding, rolling, etc.

The display layer (DISL) may include a circuit layer (PCL), display elements disposed on the circuit layer (PCL), and an encapsulation layer such as a thin film encapsulation layer (TFEL) or a sealing substrate (not shown). Insulating layers IL and IL' may be disposed between the substrate 100 and the display layer DISL and within the display layer DISL. In one embodiment, the display element may be an organic light emitting diode that includes an organic light emitting layer. Alternatively, the display element may be a light emitting diode (LED). The size of a light emitting diode (LED) may be micro scale or nano scale. For example, the light emitting diode may be a micro light emitting diode. Alternatively, the light emitting diode may be a nanorod light emitting diode. The nanorod light emitting diode may include gallium nitride (GaN). In one embodiment, a color conversion layer may be disposed on the nanorod light emitting diode. The color conversion layer may include quantum dots. Alternatively, the display element may be a quantum dot light emitting diode (Quantum dot light emitting diode) including a quantum dot light emitting layer. Alternatively, the display element may be an inorganic light emitting diode containing an inorganic semiconductor.

The first display area DDA1 of the display panel 10 corresponds to the first support portion 50A of the support layer 50, and the second display area DDA2 of the display panel 10 corresponds to the second support portion 50A of the support layer 50. It can correspond to the support portion 50B.

A first pixel (P1) and a second pixel (P2) may be disposed in the first display area (DDA1). The first pixel P1 is connected to the first pixel circuit PC1 disposed to correspond to (or overlap) the spoke 50P of the first support 50A and correspond to (or overlap) the slit 50S. It may include a first display element (DDE1) arranged in a similar manner. That is, the first pixel circuit PC1 may not be disposed in the area corresponding to the slit 50S of the first display area DDA1. The first pixel circuit PC1 includes at least one thin film transistor and can control light emission of the first display element DDE1. The first pixel circuit PC1 may be connected to the first display element DDE1 through a connection line CWL. The connection line (CWL) may overlap the rib (50P) and the slit (50S) of the first support portion (50A). The second pixel P2 may include a second pixel circuit PC2 disposed to correspond to (or overlap) the stem 50P of the first support 50A and a second display element DDE2 connected thereto. . The second pixel circuit PC2 includes at least one thin film transistor and can control light emission of the second display element DDE2.

A third pixel P3 may be disposed in the second display area DDA2 of the display panel 10 . The third pixel P3 may include a third pixel circuit PC3 and a third display element DDE3 connected thereto. The third pixel circuit PC3 includes at least one thin film transistor and can control light emission of the third display element DDE3.

The encapsulation layer can be disposed on the display elements. The display elements may be covered with a thin film encapsulation layer (TFEL) or may be covered with a sealing substrate.

In one embodiment, the thin film encapsulation layer (TFEL) may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. In one embodiment, the thin film encapsulation layer (TFEL) may include a first inorganic encapsulation layer 131, an organic encapsulation layer 132, and a second inorganic encapsulation layer 133 that are sequentially stacked. The first inorganic encapsulation layer 131 and the second inorganic encapsulation layer 133 are silicon oxide (SiO ₂ ), silicon nitride (SiN _x ), silicon oxynitride (SiO _x N _y ), and aluminum oxide (Al ₂ O ₃ ). , titanium oxide (TiO ₂ ), tantalum oxide (Ta ₂ O ₅ ), and hafnium oxide (HfO ₂ ). The organic encapsulation layer 132 may include a polymer-based material. Polymer-based materials may include silicone-based resin, acrylic resin, epoxy-based resin, polyimide, and polyethylene.

In another embodiment, the sealing substrate may be disposed to face the substrate 100 with the display elements interposed therebetween. The substrate 100 and the sealing substrate may be combined with a sealing member to seal the internal space between the substrate 100 and the sealing substrate. The sealing substrate may be a flexible substrate. The sealing member may be a sealant, and in other embodiments, the sealing member may include a material that is cured by a laser. For example, the sealing member may be a frit.

The touch sensor layer (TSL) can acquire coordinate information according to an external input, for example, a touch event. The touch sensor layer (TSL) may include a touch electrode and sensing lines connected to the touch electrode. The touch sensor layer (TSL) can detect external input using a self-capacitance method or a mutual capacitance method. The touch sensor layer (TSL) may be formed on the thin film encapsulation layer (TFEL). Alternatively, the touch sensor layer (TSL) may be formed separately on the touch substrate and then bonded to the thin film encapsulation layer (TFEL) through an adhesive layer such as optically clear adhesive (OCA). As an example, the touch sensor layer (TSL) may be formed directly on the thin film encapsulation layer (TFEL), in which case the adhesive layer may not be interposed between the touch sensor layer (TSL) and the thin film encapsulation layer (TFEL). there is.

The optical functional layer (OFL) may include an anti-reflection layer. The anti-reflection layer can reduce the reflectance of light (external light) incident toward the display device 11 from the outside. In some embodiments, the optical functional layer (OFL) may be a polarizing film. In some embodiments, the optical functional layer (OFL) may be a filter support layer including a black matrix and color filters.

FIG. 15 is an equivalent circuit diagram of one pixel included in the display device of FIG. 8.

Referring to FIG. 15 , the pixel circuit PC may include first to seventh transistors T1 to T7. Depending on the type of transistor (N-type or P-type) and/or operating conditions, the first terminal of the transistor may be a source electrode or a drain electrode, and the second terminal may be an electrode different from the first terminal. For example, when the first terminal is a source electrode, the second terminal may be a drain electrode.

The pixel circuit (PC) includes a first scan line (SL1) transmitting the first scan signal (GW), a second scan line (SL2) transmitting the second scan signal (GI), and a third scan signal (GB). A third scan line (SL3) transmitting the emission control signal (EM), an emission control line (EL) transmitting the data signal (DATA), a data line (DL) transmitting the data signal (DATA), and a driving voltage line transmitting the driving voltage (ELVDD) (PL), can be connected to the initialization voltage line (VIL) that transmits the initialization voltage (VINT). The pixel circuit (PC) may be connected to an organic light emitting diode (OLED) as a display element.

The first transistor T1 may be connected between the driving voltage line PL and the organic light emitting diode (OLED). The first transistor T1 may be connected between the first node N1 and the third node N3. The first transistor T1 may be electrically connected to the driving voltage line PL via the fifth transistor T5, and may be electrically connected to the organic light emitting diode (OLED) via the sixth transistor T6. The first transistor T1 may include a gate electrode connected to the second node N2, a first terminal connected to the first node N1, and a second terminal connected to the third node N3. The driving voltage line PL may transmit the driving voltage ELVDD to the first transistor T1. The first transistor (T1) serves as a driving transistor and can receive the data signal (DATA) according to the switching operation of the second transistor (T2) and supply a driving current (Ioled) to the organic light emitting diode (OLED).

The second transistor (or data writing transistor) T2 may be connected between the data line DL and the first node N1. The second transistor T2 may be connected to the driving voltage line PL via the fifth transistor T5. The second transistor T2 may include a gate electrode connected to the first scan line SL1, a first terminal connected to the data line DL, and a second terminal connected to the first node N1. The second transistor T2 is turned on according to the first scan signal GW received through the first scan line SL1 and transmits the data signal DATA transmitted through the data line DL to the first node N1. A switching operation can be performed.

The third transistor (or compensation transistor) T3 may be connected between the second node N2 and the third node N3. The third transistor T3 may be connected to the organic light emitting diode (OLED) via the sixth transistor T6. The third transistor T3 may include a gate electrode connected to the first scan line SL1, a first terminal connected to the second node N2, and a second terminal connected to the third node N3. The third transistor (T3) is turned on according to the first scan signal (GW) received through the first scan line (SL1) and connects the first transistor (T1) with a diode to compensate for the threshold voltage of the first transistor (T1). can do.

The fourth transistor (or first initialization transistor) T4 may be connected between the second node N2 and the initialization voltage line VIL. The fourth transistor T4 may include a gate electrode connected to the second scan line SL2, a first terminal connected to the second node N2, and a second terminal connected to the initialization voltage line VIL. The fourth transistor (T4) is turned on according to the second scan signal (GI) received through the second scan line (SL2) and transfers the initialization voltage (VINT) to the gate electrode of the first transistor (T1). The gate electrode of (T1) can be initialized.

The fifth transistor (or first light emission control transistor) T5 may be connected between the driving voltage line PL and the first node N1. The sixth transistor (or second light emission control transistor) T6 may be connected between the third node N3 and the organic light emitting diode (OLED). The fifth transistor T5 may include a gate electrode connected to the emission control line EL, a first terminal connected to the driving voltage line PL, and a second terminal connected to the first node N1. The sixth transistor T6 may include a gate electrode connected to the emission control line EL, a first terminal connected to the third node N3, and a second terminal connected to the pixel electrode of the organic light emitting diode (OLED). The fifth transistor (T5) and the sixth transistor (T6) are simultaneously turned on according to the light emission control signal (EM) received through the light emission control line (EL), so that the driving current (Ioled) flows to the organic light emitting diode (OLED). .

The seventh transistor (or second initialization transistor) T7 may be connected between the organic light emitting diode (OLED) and the initialization voltage line (VIL). The seventh transistor T7 has a gate electrode connected to the third scan line SL3, a first terminal connected to the second terminal of the sixth transistor T6 and the pixel electrode of the organic light emitting diode (OLED), and an initialization voltage line VIL. It may include a second terminal connected to . The seventh transistor T7 is turned on according to the third scan signal GB received through the third scan line SL3 and transfers the initialization voltage VINT to the pixel electrode of the organic light emitting diode (OLED). The pixel electrode of (OLED) can be initialized.

The capacitor Cst may include a first electrode connected to the gate electrode of the first transistor T1 and a second electrode connected to the driving voltage line PL. The capacitor Cst can maintain the voltage applied to the gate electrode of the first transistor T1 by storing and maintaining a voltage corresponding to the difference between the voltage between the driving voltage line PL and the gate electrode of the first transistor T1. there is.

An organic light emitting diode (OLED) includes a pixel electrode (first electrode, anode) and an opposing electrode (second electrode, cathode), and the opposing electrode can be applied with a common voltage (ELVSS). The organic light emitting diode (OLED) displays an image by receiving a driving current (Ioled) from the first transistor (T1) and emitting light.

In Figure 15, the first to seventh transistors T1 to T7 are shown as P-type transistors. Embodiments of the present invention are not limited thereto. For example, the first to seventh transistors (T1 to T7) may be N-type transistors, or some of the first to seventh transistors (T1 to T7) may be N-type transistors and the remainder may be P-type transistors. there is. For example, among the first to seventh transistors T1 to T7, the third transistor T3 and the fourth transistor T4 may be N-type transistors, and the others may be P-type transistors. Here, the third transistor T3 and the fourth transistor T4 may include a semiconductor layer containing oxide, and the remaining transistors may include a semiconductor layer containing silicon.

Meanwhile, in this embodiment, an organic light-emitting diode is used as a display element, but in another embodiment, an inorganic light-emitting device or a quantum dot light-emitting device may be used as a display element.

FIG. 16 is a diagram illustrating a schematic arrangement of light emitting areas of a plurality of pixels arranged in a display area according to an embodiment.

Referring to FIG. 16, the plurality of pixels arranged in the display area DDA include a first sub-pixel (Pr) that emits light in the first color, a second sub-pixel (Pg) that emits light in the second color, and a third color. It may include a third subpixel (Pb) that emits light. In one embodiment, the first subpixel (Pr) is a red pixel that emits red light, the second subpixel (Pg) is a green pixel that emits green light, and the third subpixel (Pb) is a blue pixel that emits blue light. It could be a pixel.

In the first display area (DDA1) and the second display area (DDA2), the first subpixel (Pr), the second subpixel (Pg), and the third subpixel (Pb) are predetermined in the ±x direction and ±y direction. It can be placed repeatedly according to the pattern. The first subpixel (Pr), the second subpixel (Pg), and the third subpixel (Pb) may include a pixel circuit and a display element electrically connected to the pixel circuit, respectively. In one embodiment, the display element may be an organic light emitting diode (OLED).

The light emitting area of each of the first subpixel (Pr), the second subpixel (Pg), and the third subpixel (Pb) is an area where the light emitting layer of the organic light emitting diode (OLED) is disposed. The light emitting area may be defined by the opening of the pixel defining layer.

In the first column M1, the first emission area EA1 of the first subpixel Pr and the third emission area EA3 of the third subpixel Pb may be alternately arranged in the ±y direction. In the second column M2, the second light emitting area EA2 of the second subpixel Pg may be repeatedly arranged in the ±y direction. The first column M1 and the second column M2 alternate in the ±x direction, and the first emission area EA1 and the third subpixel of the first subpixels Pr of the adjacent first columns M1 ( The arrangement of the third light emitting area EA3 of Pb) may be reversed.

In the first sub-row SN1 of each row N, there is a first emission area EA1 of the first sub-pixel Pr and a third emission area EA1 of the third sub-pixel Pb along the first virtual line ℓℓ1. The areas EA3 are alternately arranged in the ±x direction, and in the second sub-row SN2, the second emission areas EA2 of the second subpixel PX2 are aligned in the ±x direction along the second virtual line ℓℓ2. It can be arranged repeatedly. That is, in each row N, there is a first emission area EA1 of the first subpixel Pr, a second emission area EA2 of the second subpixel Pg, and a third emission area EA2 of the third subpixel Pb. The light emitting area EA3 and the second light emitting area EA2 of the second subpixel Pg may be repeatedly arranged in a zigzag pattern.

The first emission area EA1 of the first subpixel Pr, the second emission area EA2 of the second subpixel Pg, and the third emission area EA3 of the third subpixel Pb are different from each other. It can have an area. In one embodiment, the third emission area EA3 of the third subpixel Pb may have a larger area than the first emission area EA1 of the first subpixel Pr. Additionally, the third emission area EA3 of the third subpixel Pb may have a larger area than the second emission area EA2 of the second subpixel Pg. The first emission area EA1 of the first subpixel Pr may have a larger area than the second emission area EA2 of the second subpixel Pg. In another embodiment, the third emission area EA3 of the third subpixel Pb may have the same area as the first emission area EA1 of the first subpixel Pr. The present invention is not limited to this. For example, the first emission area EA1 of the first subpixel Pr is larger than the second emission area EA2 of the second subpixel Pg and the third emission area EA3 of the third subpixel Pb. Several embodiments are possible, such as large.

The first to third light emitting areas EA1, EA2, and EA3 may have a polygonal shape such as a square or an octagon, a circle, or an oval, and the polygon may also include a shape with rounded corners (or vertices). .

FIG. 17 is an enlarged plan view illustrating part VI of FIG. 8 by way of example. FIG. 17 is a diagram illustrating the connection of a pixel circuit and a display element in a folding area and a non-folding area according to an embodiment. In FIG. 17, the description is based on the first folded area (FA1) and the first unfolded area (NFA1), but the second folded area (FA2), the second unfolded area (NFA2), and the third unfolded area (NFA3) can also be applied equally.

Referring to FIG. 17 , the display area DDA of the display panel 10 may include a first folded area FA1 and a first non-folded area NFA1. The first folding area FA1 may correspond to (or overlap) the first support portion 50A of the support layer 50. The first non-folding area NFA1 may correspond to (or overlap) the second support portion 50B of the support layer 50. The first folding area FA1 may include a first area AAR1 and a second area AAR2. The first area AAR1 may correspond to (or overlap) the slit 50S of the first support portion 50A of the support layer 50. The second area AAR2 may correspond to (or overlap) the rib 50P of the first support portion 50A of the support layer 50. The first area AAR1 has a size corresponding to the width sw of the slit 50S of the support layer 50, and the second area AAR2 has a size corresponding to the width lw of the slit 50P of the support layer 50. It can have a corresponding size. For example, the length of the first area AAR1 in the first direction (eg, ±x direction) corresponds to the width sw of the slit 50S of the support layer 50, and the length of the second area AAR2 corresponds to the width sw of the slit 50S of the support layer 50. The length in the first direction (eg, ±x direction) may correspond to the width (lw) of the abutment 50P of the support layer 50.

The display area DDA of the display panel 10 may include a plurality of pixel areas. For example, the first area AAR1 of the first folding area FA1 may include first pixel areas PPXAR1. The second area AAR2 of the first folding area FA1 may include second pixel areas PPXAR2. The first non-folding area NFA1 may include third pixel areas PPXAR3. Pixel areas may be repeated in a first direction (eg, ±x direction) and a second direction (eg, ±y direction).

In one embodiment, the first pixel areas PPXAR1 may be arranged at a first pitch CI1 along a first direction (eg, ±x direction). The second pixel areas PPXAR2 may be arranged along the first direction (eg, ±x direction) at a second pitch CI2 that is different from the first pitch CI1. For example, the second pitch CI2 may be smaller than the first pitch CI1.

In one embodiment, the third pixel areas PPXAR3 may be arranged at a third pitch CI3 along the first direction (eg, ±x direction). The third pitch CI3 may be substantially the same as the first pitch CI1.

In one embodiment, the first pixel areas PPXAR1 may be arranged at a fourth pitch CI4 along the second direction (eg, ±y direction). The second pixel areas PPXAR2 may be arranged at a fifth pitch CI5 along the second direction (eg, ±y direction). The third pixel areas PPXAR3 may be arranged at a sixth pitch CI6 along the second direction (eg, ±y direction). The fourth pitch (CI4), the fifth pitch (CI5), and the sixth pitch (CI6) may be substantially the same.

A pixel circuit of a pixel may be disposed in some pixel areas. For example, the first pixel circuits PC1 may be respectively disposed on some of the second pixel areas PPAR2 among the plurality of second pixel areas PPAR2. The second pixel circuits PC2 may be disposed on some of the second pixel areas PPAR2 among the plurality of second pixel areas PPAR2. The third pixel circuits PC3 may be respectively disposed on the third pixel areas PPAR3. Pixel circuits may not be disposed in the first area AAR1 of the first folding area FA1 corresponding to the slit 50S of the support layer 50.

As a comparative example, a pixel circuit may be disposed on a substrate corresponding to a slit in the support layer. In this case, when an external force is applied to the display device, the impact from the outside may pass through the slit in the support layer and directly reach the pixel circuit on the substrate. The pixel circuit may be damaged due to external shock, and the display element connected to the pixel circuit may not operate normally.

According to one embodiment of the present invention, pixel circuits may not be disposed in the first area AAR1 of the first folding area FA1 corresponding to the slit 50S of the support layer 50. In this case, even if an external shock passes through the slit 50S of the support layer 50 and reaches the display panel 10, there is no pixel circuit overlapping the slit 50S of the support layer 50, so the pixel caused by the external shock Circuit defects can be prevented or minimized.

In one embodiment, the first direction (eg, ±x direction) pitch between adjacent first pixel circuits (PC1) and the first direction (eg, ±x direction) pitch between adjacent second pixel circuits (PC2) The direction) pitch may be smaller than the first direction (eg, ±x direction) pitch between the third pixel circuits PC3. The arrangement of the first pixel circuits PC1 and the second pixel circuits PC2 in the first direction (eg, ±x direction) and/or the second direction (eg, ±y direction) is used to form a third pixel. The arrangement of the circuits PC3 in the first direction (eg, ±x direction) and/or the second direction (eg, ±y direction) may be different. Accordingly, the size of the first pixel circuit PC1 and the second pixel circuit PC2 in the first direction (eg, ±x direction) is changed to the size of the third pixel circuit PC3 in the first direction (eg, ±x direction). direction) may be smaller than the size.

Signal lines connected to the pixel circuit may be disposed in the pixel area. For example, the pixel area includes the first scan line (SL1), second scan line (SL2), third scan line (SL3), emission control line (EL), data line (DL), and driving voltage line ( PL), initialization voltage line (VIL), etc. may be disposed.

The display element may be placed in the upper layer of the pixel circuit. The display element may be disposed directly on top to overlap a connected pixel circuit, or may be offset from the pixel circuit and partially overlap the pixel circuit of another pixel disposed in an adjacent row and/or column. Alternatively, the display element may be arranged to non-overlap with the connected pixel circuit. For example, first display elements DDE1 are disposed in the first area AAR1 of the first folding area FA1, and second display elements DDE1 are disposed in the second area AAR2 of the first folding area FA1. DDE2) may be disposed, and third display elements DDE3 may be disposed in the first non-folding area NFA1. The first display elements DDE1 may be electrically connected to the first pixel circuits PC1 disposed in the second area AAR2 of the first folding area FA1 through connection lines CWL, respectively. The first display elements DDE1 may not overlap with the first pixel circuits PC1. The second display elements DDE2 may each be electrically connected to the second pixel circuits PC2 disposed in the second area AAR2 of the first folding area FA1. The second display element DDE2 may be disposed directly above the connected second pixel circuit PC2, or may be disposed in an adjacent row and/or column offset from the connected second pixel circuit PC2. It may be arranged to at least partially overlap the pixel circuit PC2 or the first pixel circuit PC1. The third display elements DDE3 may each be electrically connected to the third pixel circuits PC3 disposed in the first non-folding area NFA1. The third display element DDE3 may be disposed directly above the connected third pixel circuit PC3, or may be disposed in an adjacent row and/or column offset from the connected third pixel circuit PC3. It may be arranged to overlap at least part of the pixel circuit PC3.

In one embodiment, the number of first display elements DDE1 disposed in the first area AAR1 of the first folding area FA1 along the first direction (eg, ±x direction) is determined by the support layer 50 ) is determined according to the width sw of the slit 50S, and is disposed in the second area AAR2 of the first folding area FA1 along the first direction (eg, ±x direction). The number of elements DDE2 may be determined according to the width lw of the rib 50P of the support layer 50.

In one embodiment, the first interval PI1 between the first display elements DDE1 that are adjacent to each other in the first direction (eg, ±x direction) among the plurality of first display elements DDE1 is The second interval PI2 between the second display elements DDE2 adjacent to each other in the first direction (eg, ±x direction) among the plurality of second display elements DDE2 may be substantially equal to the second interval PI2. . Among the plurality of first display elements DDE1, the first interval PI1 between adjacent first display elements DDE1 in the first direction (for example, ±x direction) is defined by the plurality of third display elements DDE1. It may be substantially equal to the third interval PI3 between the third display elements DDE3 that are adjacent to each other in the first direction (eg, ±x direction) among the DDE3s.

FIG. 18 is an enlarged plan view illustrating part VI of FIG. 8 by way of example. Figure 18 is a diagram showing an insulating layer and a pixel separator in a folding area and a non-folding area according to an embodiment. In FIG. 18, the description is based on the first folded area (FA1) and the first unfolded area (NFA1), but the second folded area (FA2), the second unfolded area (NFA2), and the third unfolded area (NFA3) can also be applied equally. In FIG. 18, the same reference numerals as in FIG. 17 refer to the same members, and duplicate description thereof will be omitted.

Referring to FIG. 18 , the display panel 10 may include a first insulating layer (IIL1) and first to third pixel separators (PPSL1, PPSL2, and PPSL3).

The first insulating layer IIL1 may have first to third trenches ttr1, ttr2, and ttr3. The first trenches (ttr1) each correspond to the boundaries of the first pixel areas (PPXAR1) that are adjacent to each other in the first direction (eg, ±x direction) among the plurality of first pixel areas (PPXAR1), and the second The trenches (ttr2) each correspond to the boundaries of the second pixel areas (PPXAR2) that are adjacent to each other in the first direction (e.g., ±x direction) among the plurality of second pixel areas (PPXAR2), and the third trench ( ttr3) may respectively correspond to boundaries of third pixel areas PPXAR3 that are adjacent to each other in the first direction (eg, ±x direction) among the plurality of third pixel areas PPXAR3.

The first pixel separators PPSL1 are respectively buried in the first trenches ttr1, the second pixel separators PPSL2 are respectively buried in the second trenches ttr2, and the third pixel separators PPSL3 are respectively buried in the third trenches ttr2. They can be buried in each of the trenches (ttr3).

Meanwhile, in FIG. 18 , the trenches corresponding to the boundaries of pixel regions neighboring each other in the first direction (e.g., ±x direction) and the pixel isolation layers respectively buried in the trenches were described, but in FIG. 2 As described above, the first insulating layer IIL1 may have trenches respectively corresponding to the boundaries of pixel areas neighboring each other in the second direction (eg, ±y direction). Pixel isolation films may be buried in each of the trenches. As shown in FIG. 18, the pixel area may be entirely surrounded by pixel isolation films. In another example, the pixel area may be partially surrounded by pixel isolation films.

In one embodiment, the first gap dd1 between the first pixel separators PPSL1 adjacent to each other in the first direction (eg, ±x direction) among the plurality of first pixel separators PPSL1 is The second spacing dd2 between adjacent second pixel separators PPSL2 in the first direction (eg, ±x direction) among the plurality of second pixel separators PPSL2 may be different. For example, the first interval dd1 may be larger than the second interval dd2.

In one embodiment, the first gap dd1 between the first pixel separators PPSL1 adjacent to each other in the first direction (eg, ±x direction) among the plurality of first pixel separators PPSL1 is It may be substantially equal to the third spacing dd3 between the third pixel separators PPSL3 that are adjacent to each other in the first direction (eg, ±x direction) among the plurality of third pixel separators PPSL3. .

In one embodiment, the first to third pixel separators PPSL1, PPSL2, and PPSL3 may include a material different from that of the first insulating layer IIL1. For example, the first insulating layer (IIL1) may include an inorganic material, and the first to third pixel separators (PPSL1, PPSL2, and PPSL3) may include an organic material. Since the first to third pixel separators (PPSL1, PPSL2, PPSL3) contain organic materials, cracks formed in the first insulating layer (IIL1) containing inorganic materials in one pixel due to external impact may grow into adjacent pixels. can be prevented or minimized more effectively.

FIG. 19 is an exemplary cross-sectional view of a portion of the display device of FIG. 18 taken along line IX-IX'. In FIG. 19, the description is based on the first folded area (FA1) and the first non-folded area (NFA1), but the second folded area (FA2), the second non-folded area (NFA2), and the third non-folded area (NFA3) can also be applied equally.

Referring to FIG. 19 , the display device 11 may include a display panel 10 and a support layer 50. The display panel 10 has a first folded area FA1 corresponding to the first support part 50A of the support layer 50, and a first non-folding area NFA1 corresponding to the second support part 50B of the support layer 50. ) may include. The first folding area FA1 is a first area AAR1 corresponding to the slit 50S of the first support part 50A of the support layer 50, and the rib 50P of the first support part 50A of the support layer 50. ) may include a second area (AAR2) corresponding to.

The first area AAR1 of the first folding area FA1 includes first pixel areas PPXAR1, and the second area AAR2 of the first folding area FA1 includes second pixel areas PPXAR2. And the first non-folding area NFA1 may include third pixel areas PPXAR3. As described above in FIG. 17 , first pixel circuits PC1 or second pixel circuits PC2 may be disposed in the second pixel areas PPXAR2, respectively. Third pixel circuits PC3 may be disposed in each of the third pixel areas PPXAR3. First display elements DDE1 electrically connected to the first pixel circuits PC1 are disposed in the first area AAR1 of the first folding area FA1, and the second area of the first folding area FA1 Second display elements DDE2 are disposed in (AAR2) electrically connected to the second pixel circuits PC2, respectively, and in the first non-folding area NFA1 are electrically connected to the third pixel circuits PC3, respectively. Third display elements DDE3 may be arranged.

Meanwhile, a pixel circuit may not be disposed in the first pixel areas PPXAR1, and signal lines connected to the pixel circuit may be disposed. For example, third electrodes E3 may be disposed in each of the first pixel areas PPXAR1, and the third electrodes E3 may be connected through fourth electrodes E4. The third and fourth electrodes (E3, E4) are the first scan line (SL1), second scan line (SL2), third scan line (SL3), emission control line (EL), and data line (DL) in FIG. 15. ), driving voltage line (PL), initialization voltage line (VIL), etc.

Each of the first to third pixel circuits PC3 may include a semiconductor layer, a gate electrode, and an electrode. For example, the first pixel circuit PC1 includes a second semiconductor layer Act2, a second gate electrode GE2, a fourth gate electrode GE4, and a second electrode E2, and the third pixel The circuit PC3 may include a first semiconductor layer (Act1), a first gate electrode (GE1), a third gate electrode (GE3), and a first electrode (E1). Although the description has been made based on the first pixel circuit (PC1) and the third pixel circuit (PC3), the second pixel circuit (PC2) can also be applied in the same way.

In one embodiment, adjacent pixel circuits may share gate electrodes with each other. For example, adjacent first pixel circuits PC1 may share the second gate electrode GE2, and adjacent third pixel circuits PC3 may share the first gate electrode GE1. Although the description has been made based on the first pixel circuit (PC1) and the third pixel circuit (PC3), the second pixel circuit (PC2) can also be applied in the same way.

The display panel 10 may include a first insulating layer (IIL1). The first insulating layer IIL1 may include a buffer layer 111, a first gate insulating layer 113, a second gate insulating layer 115, and an interlayer insulating layer 117. The first insulating layer (IIL1) includes a first trench (ttr1) corresponding to the boundary between adjacent first pixel areas (PPXAR1), a second trench (ttr2) corresponding to the boundary between adjacent second pixel areas (PPXAR2), and a third trench (ttr3) corresponding to the boundary between adjacent third pixel areas (PPXAR3).

In one embodiment, the first depth ddp1 of the first trench ttr1 along the thickness direction (e.g., ±z direction) of the substrate 100 is determined by the thickness direction (e.g., ±z direction) of the substrate 100. It may be different from the second depth (ddp2) of the second trench (ttr2) along the ±z direction. For example, the first depth (ddp1) may be greater than the second depth (ddp2). The first depth ddp1 of the first trench ttr1 along the thickness direction (eg, ±z direction) of the substrate 100 is along the thickness direction (eg, ±z direction) of the substrate 100. It may be different from the third depth (ddp3) of the third trench (ttr3). For example, the first depth (ddp1) may be greater than the third depth (ddp3). The second depth ddp2 of the second trench ttr2 along the thickness direction (eg, ±z direction) of the substrate 100 is along the thickness direction (eg, ±z direction) of the substrate 100. It may be substantially equal to the third depth ddp3 of the third trench ttr3.

The first trench (ttr1) is formed in the buffer layer 111, the first gate insulating layer 113, the second gate insulating layer 115, and the interlayer insulating layer 117, and the second trench (ttr2) and the third The trench ttr3 may be formed in the second gate insulating layer 115 and the interlayer insulating layer 117.

First to third pixel separators PPSL1, PPSL2, and PPSL3 may be disposed in the first to third trenches ttr1, ttr2, and ttr3, respectively. In other words, first to third pixel isolation layers PPSL1, PPSL2, and PPSL3 may be buried in the first to third trenches ttr1, ttr2, and ttr3, respectively. As the first to third pixel separators PPSL1, PPSL2, and PPSL3 are disposed in the first to third trenches ttr1, ttr2, and ttr3, respectively, the The step of the first insulating layer (IIL1) can be removed or minimized.

In one embodiment, the first gap dd1 between adjacent first pixel separators PPSL1 may be different from the second gap dd2 between adjacent second pixel separators PSL2. For example, the first interval dd1 may be larger than the second interval dd2. The third spacing dd3 between adjacent third pixel separators PPSL3 may be different from the second spacing dd2 between adjacent second pixel separators PSL2. For example, the third interval dd3 may be larger than the second interval dd2. The first spacing dd1 between adjacent first pixel separators PPSL1 may be substantially equal to the third spacing dd3 between adjacent third pixel separators PPSL3.

In one embodiment, the first thickness tth1 of the first pixel separator PPSL1 along the thickness direction (e.g., ±z direction) of the substrate 100 is the thickness direction (e.g., ±z direction) of the substrate 100. , ±z direction) may be different from the second thickness (tth2) of the second pixel separator (PPSL2). For example, the first thickness (tth1) may be greater than the second thickness (tth2). The first thickness tth1 of the first pixel separator PPSL1 along the thickness direction (eg, ±z direction) of the substrate 100 is in the thickness direction (eg, ±z direction) of the substrate 100. It may be different from the third thickness (tth3) of the third pixel separator (PPSL3). For example, the first thickness (tth1) may be greater than the third thickness (tth3). The second thickness tth2 of the second pixel separator PPSL2 along the thickness direction (eg, ±z direction) of the substrate 100 is in the thickness direction (eg, ±z direction) of the substrate 100. It may be substantially the same as the third thickness (tth3) of the third pixel separator (PPSL3).

Hereinafter, with reference to FIG. 19 , the components included in the display device 11 will be described in more detail according to the stacked structure.

The support layer 50 may include at least one of glass, plastic, and metal. In one embodiment, the support layer 50 may include polyurethane or carbon fiber reinforced plastic (Carbon). In one embodiment, the support layer 50 may include at least one of stainless steel, invar, nickel (Ni), cobalt (Co), nickel alloy, and nickel-cobalt alloy. In one embodiment, the support layer 50 may include austenitic stainless steels.

The substrate 100 on the support layer 50 may include glass or polymer resin. Polymer resins include polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, It may include polyarylate, polyimide, polycarbonate, or cellulose acetate propionate. The substrate 100 containing polymer resin may have flexible, rollable, or bendable characteristics. The substrate 100 may have a multilayer structure including a layer containing the above-described polymer resin and an inorganic layer (not shown).

A barrier layer 110 may be disposed on the substrate 100. The barrier layer 110 may serve to prevent or minimize impurities from the substrate 100 or the like from penetrating into the first and second semiconductor layers (Act1 and Act2). The barrier layer 110 may include an inorganic material such as oxide or nitride, an organic material, or an organic-inorganic composite, and may have a single-layer or multi-layer structure of an inorganic material and an organic material.

A first insulating layer (IIL1) may be disposed on the barrier layer 110. The first insulating layer (IIL1) is made of silicon oxide (SiO ₂ ), silicon nitride (SiN _x ), silicon oxynitride (SiON), aluminum oxide (Al ₂ O ₃ ), titanium oxide (TiO ₂ ), and tantalum oxide (Ta _{2 )} . O ₅ ), hafnium oxide (HfO ₂ ), or zinc oxide (ZnO ₂ ) may be included.

The first to third pixel isolation films (PPSL1, PPSL2, PPSL3) respectively disposed in the first to third trenches (ttr1, ttr2, ttr3) of the first insulating layer (IIL1) are formed as a single or multi-layer film made of an organic material. It can be. For example, the first to third pixel separators (PPSL1, PPSL2, PPSL3) are made of general-purpose polymers such as BCB (Benzocyclobutene), polyimide, HMDSO (Hexamethyldisiloxane), Polymethylmethacrylate (PMMA), Polystyrene (PS), and phenol. It may include polymer derivatives having a group, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorine polymers, p-xylene polymers, vinyl alcohol polymers, and blends thereof.

First and second semiconductor layers (Act1 and Act2) may be disposed on the buffer layer 111. The first and second semiconductor layers (Act1 and Act2) may include amorphous silicon or polysilicon. In another embodiment, the first and second semiconductor layers (Act1, Act2) are indium (In), gallium (Ga), stanium (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), and cadmium. (Cd), germanium (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce), and zinc (Zn). may include.

The first and second semiconductor layers (Act1 and Act2) may include a channel region and a source region and a drain region disposed on both sides of the channel region. The first and second semiconductor layers (Act1 and Act2) may be composed of a single layer or multiple layers.

A first gate insulating layer 113 may be disposed on the buffer layer 111 to cover the first and second semiconductor layers (Act1 and Act2). First and second gate electrodes GE1 and GE2 may be disposed on the first gate insulating layer 113. The first and second gate electrodes (GE1, GE2) may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may include the above materials. It can be formed as a multi-layer or single layer. For example, the first and second gate electrodes GE1 and GE2 may be a single layer of Mo.

A second gate insulating layer 115 may be disposed on the first gate insulating layer 113 to cover the first and second gate electrodes GE1 and GE2. Third and fourth gate electrodes GE3 and GE4 may be disposed on the second gate insulating layer 115. The third and fourth gate electrodes (GE3, GE4) may contain a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may include the above materials. It can be formed as a multi-layer or single layer. For example, the third and fourth gate electrodes GE3 and GE4 may be a single layer of Mo.

An interlayer insulating layer 117 may be disposed on the second gate insulating layer 115 to cover the third and fourth gate electrodes GE3 and GE4. First to third electrodes E1, E2, and E3 may be disposed on the interlayer insulating layer 117. The first and second electrodes E1 and E2 may be connected to the gate electrode through at least one contact hole formed in the interlayer insulating layer 117. The first to third electrodes (E1, E2, E3) may contain a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and include the above materials. It can be formed as a multi-layer or single layer. For example, the first to third electrodes E1, E2, and E3 may have a multilayer structure of Ti/Al/Ti.

A second insulating layer (IIL2) may be disposed on the interlayer insulating layer 117 to cover the first to third electrodes (E1, E2, and E3). The second insulating layer IIL2 may be formed as a single or multi-layered film made of an organic material, and provides a flat top surface. This second insulating layer (IIL2) is made of a general-purpose polymer such as Benzocyclobutene (BCB), polyimide, Hexamethyldisiloxane (HMDSO), Polymethylmethacrylate (PMMA), or Polystyrene (PS), a polymer derivative with a phenolic group, It may include acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorine polymers, p-xylene polymers, vinyl alcohol polymers, and blends thereof.

The fourth electrode E4 may be disposed on the second insulating layer IIL2. Some of the fourth electrodes E4 may be connected to the third electrode E3 through contact holes formed in the second insulating layer IIL2. The fourth electrode (E4) may contain a conductive material containing molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may be formed as a multilayer or single layer containing the above materials. You can. For example, the fourth electrode E4 may have a multilayer structure of Ti/Al/Ti.

A third insulating layer 119 may be disposed on the second insulating layer IIL2 to cover the fourth electrode E4. The third insulating layer 119 may be formed of a single layer or multiple layers of an organic material, and provides a flat top surface. The third insulating layer 119 is made of a general-purpose polymer such as Benzocyclobutene (BCB), polyimide, Hexamethyldisiloxane (HMDSO), Polymethylmethacrylate (PMMA), or Polystyrene (PS), a polymer derivative having a phenolic group, It may include acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorine polymers, p-xylene polymers, vinyl alcohol polymers, and blends thereof.

A fifth electrode E5 may be disposed on the third insulating layer 119. Although not shown in FIG. 19 , the fifth electrode E5 may be connected to the fourth electrode E4 through at least one contact hole formed in the third insulating layer 119 . The fifth electrode (E5) may contain a conductive material containing molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may be formed as a multilayer or single layer containing the above materials. You can. For example, the fifth electrode E5 may have a multilayer structure of Ti/Al/Ti.

A fourth insulating layer 121 may be disposed on the third insulating layer 119 to cover the fifth electrode E5. The fourth insulating layer 121 may be formed as a single or multi-layered film made of an organic material, and provides a flat top surface. The fourth insulating layer 121 is made of a general-purpose polymer such as Benzocyclobutene (BCB), polyimide, Hexamethyldisiloxane (HMDSO), Polymethylmethacrylate (PMMA), or Polystyrene (PS), a polymer derivative having a phenolic group, It may include acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorine polymers, p-xylene polymers, vinyl alcohol polymers, and blends thereof.

First to third display elements DDE1, DDE2, and DDE3 may be disposed on the fourth insulating layer 121. The first to third display elements DDE1, DDE2, and DDE3 may be organic light emitting diodes (OLEDs). Each of the first to third display elements DDE1, DDE2, and DDE3 may include a pixel electrode 210, an intermediate layer 220 including an organic light emitting layer, and an opposing electrode 230. Although not shown in FIG. 19, the first to third display elements DDE1, DDE2, and DDE3 may be connected to the fifth electrode E5 through at least one contact hole formed in the fourth insulating layer 121.

The pixel electrode 210 may be a (semi-)transmissive electrode or a reflective electrode. In some embodiments, the pixel electrode 210 includes a reflective layer formed of Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, and compounds thereof, and a transparent or translucent electrode layer formed on the reflective layer. can do. The transparent or translucent electrode layer is made of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In ₂ O ₃ ), and indium gallium. It may include at least one selected from the group including indium gallium oxide (IGO) and aluminum zinc oxide (AZO). In some embodiments, the pixel electrode 210 may be made of ITO/Ag/ITO.

In the display area of the substrate 100, a pixel defining layer 123 may be disposed on the fourth insulating layer 121. The pixel defining film 123 covers the edges of the pixel electrode 210 and may have an opening exposing the central portion of the pixel electrode 210. The light emitting area of each of the first to third display elements DDE1, DDE2, and DDE3 may be defined by the opening.

The pixel defining film 123 prevents arcs, etc. from occurring at the edges of the pixel electrode 210 by increasing the distance between the edge of the pixel electrode 210 and the opposing electrode 230 on top of the pixel electrode 210. can play a role.

The pixel defining layer 123 is made of one or more organic insulating materials selected from the group consisting of polyimide, polyamide, acrylic resin, benzocyclobutene, and phenol resin, and may be formed by a method such as spin coating. The pixel defining layer 123 may include an organic insulating material. Alternatively, the pixel defining layer 123 may include an inorganic insulating material such as silicon nitride, silicon oxynitride, or silicon oxide. Alternatively, the pixel defining layer 123 may include an organic insulating material and an inorganic insulating material. In some embodiments, the pixel defining layer 123 includes a light blocking material and may be black. The light blocking material may be carbon black, carbon nanotubes, a resin or paste containing black dye, metal particles such as nickel, aluminum, molybdenum and alloys thereof, metal oxide particles (e.g. chromium oxide), or metal nitride particles ( For example, chromium nitride) and the like. When the pixel defining layer 123 includes a light blocking material, reflection of external light by metal structures disposed below the pixel defining layer 123 can be reduced.

The intermediate layer 220 is disposed within the opening formed by the pixel defining layer 123 and may include an organic light emitting layer. The organic light-emitting layer may include an organic material containing a fluorescent or phosphorescent material that emits red, green, blue, or white light. The organic light-emitting layer may be a low-molecular organic material or a high-molecular organic material, and below and above the organic light-emitting layer are a hole transport layer (HTL), a hole injection layer (HIL), an electron transport layer (ETL), Alternatively, a functional layer such as an electron injection layer (EIL) may be further selectively disposed.

The counter electrode 230 may be a translucent electrode or a reflective electrode. In some embodiments, the counter electrode 230 may be a transparent or translucent electrode, and may be a metal thin film with a low work function containing Li, Ca, LiF/Ca, LiF/Al, Al, Ag, Mg, and compounds thereof. can be formed. Additionally, a TCO (transparent conductive oxide) film such as ITO, IZO, ZnO, or In ₂ O ₃ may be further disposed on the metal thin film. The counter electrode 230 is disposed across the display area and may be disposed on top of the middle layer 220 and the pixel defining layer 123. The counter electrode 230 may be formed integrally with the first to third display elements DDE1, DDE2, and DDE3 and may correspond to the pixel electrodes 210.

Since the display elements 200 can be easily damaged by moisture or oxygen from the outside, an encapsulation layer (not shown) can cover the display elements 200 to protect them. The encapsulation layer covers the display area and may extend to at least a portion of the surrounding area. This encapsulation layer may include a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer.

FIG. 20 is an exemplary cross-sectional view of a portion of the display device of FIG. 18 taken along line IX-IX'. Figure 20 is a modified example of Figure 19, with a difference in the structure of the trench. In the following, overlapping content will be replaced with the description of FIG. 19 and the differences will be mainly explained.

Referring to FIG. 20 , unlike the above-described FIG. 19 , the second and third trenches (ttr2 and ttr3) may be formed in the interlayer insulating layer 117. Adjacent first pixel circuits PC1 may share the fourth gate electrode GE4, and adjacent third pixel circuits PC3 may share the third gate electrode GE3. Although the description has been made based on the first pixel circuit (PC1) and the third pixel circuit (PC3), the second pixel circuit (PC2) can also be applied in the same way.

In one embodiment, as shown in FIG. 20, the sidewall of the first insulating layer IIL1 defining the first to third trenches ttr1, ttr2, and ttr3 is substantially adjacent to the edge of the third electrode E3. can match.

FIG. 21 is an exemplary cross-sectional view of a portion of the display device of FIG. 18 taken along line IX-IX'. Figure 21 is a modified example of Figure 19, with a difference in the structure of the trench. In the following, overlapping content will be replaced with the description of FIG. 19 and the differences will be mainly explained.

Referring to FIG. 21, unlike the above-described FIG. 19, the depth of each of the first to third trenches (ttr1, ttr2, and ttr3) along the thickness direction (e.g., ±z direction) of the substrate 100 is substantially the same. can do. The first depth (ddp1') of the first trench (ttr1), the second depth (ddp2') of the second trench (ttr2), and the third depth (ddp3') of the third trench (ttr3) may be substantially the same. You can. The first to third trenches (ttr1, ttr2, and ttr3) may be formed in the buffer layer 111, the first gate insulating layer 113, the second gate insulating layer 115, and the interlayer insulating layer 117.

Additionally, the thickness of each of the first to third pixel separators PPSL1, PPSL2, and PPSL3 along the thickness direction (eg, ±z direction) of the substrate 100 may be substantially the same. The first thickness (tth1') of the first pixel separator (PPSL1), the second thickness (tth2') of the second pixel separator (PPSL2), and the third thickness (tth3') of the third pixel separator (PPSL3) are substantially can be the same.

The 4-1 electrode E41 disposed on the second insulating layer IIL2 connects the adjacent third electrodes E3, and the 4-2 electrode E42 connects the adjacent first electrodes E1. , the 4-3rd electrode (E43) can connect the adjacent second electrodes (E2).

FIG. 22 is an exemplary cross-sectional view of a portion of the display device of FIG. 18 taken along line IX-IX'. Figure 22 is a modified example of Figure 19, with a difference in the structure of the conductive pattern. In the following, overlapping content will be replaced with the description of FIG. 19 and the differences will be mainly explained.

Referring to FIG. 22 , the display panel 10 may include conductive patterns (CCPs). The conductive patterns CCP are interposed between the substrate 100 and the first pixel separators PPSL1 and may contact each of the first pixel separators PPSL1. Conductive patterns (CCPs) may contain conductive materials containing molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may be formed as a multilayer or single layer containing the above materials. there is. As an example, the conductive patterns (CCPs) may be a single layer of Mo.

The conductive patterns (CCP) may serve to help ensure a uniform etching depth when etching the first insulating layer (IIL1) to form the first trench (ttr1). By disposing the conductive patterns CCP between the substrate 100 and the first pixel isolation layers PPSL1, first trenches ttr1 with uniform depth can be formed in the first insulating layer IIL1.

FIG. 23 is an exemplary cross-sectional view of a portion of the display device of FIG. 18 taken along line IX-IX'. Figure 23 is a modified example of Figure 19, with a difference in the structure of the conductive pattern. In the following, overlapping content will be replaced with the description of FIG. 19 and the differences will be mainly explained.

Referring to FIG. 23, unlike the above-described FIG. 19, the first insulating layer (IIL1') may include a first gate insulating layer 113, a second gate insulating layer 115, and an interlayer insulating layer 117. there is. The first trench ttr1 may be formed in the first gate insulating layer 113, the second gate insulating layer 115, and the interlayer insulating layer 117.

The display panel 10 may include semiconductor patterns (SSCP). The semiconductor patterns SSCP are interposed between the substrate 100 and the first pixel separators PPSL1 and may contact each of the first pixel separators PPSL1. Semiconductor patterns (SSCP) may include amorphous silicon or polysilicon. In another embodiment, the semiconductor patterns (SSCP) include indium (In), gallium (Ga), stanium (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), and germanium (Ge). ), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce), and zinc (Zn).

The semiconductor patterns (SSCP) may serve to help ensure a uniform etching depth when etching the first insulating layer (IIL1') to form the first trench (ttr1). By disposing the semiconductor patterns SSCP between the substrate 100 and the first pixel isolation layers PPSL1, first trenches ttr1 with uniform depth can be formed in the first insulating layer IIL1'.

So far, only the display device has been mainly described, but the present invention is not limited thereto. For example, a display device manufacturing method for manufacturing such a display device may also be said to fall within the scope of the present invention.

The present invention has been described with reference to the embodiments shown in the drawings, but these are merely exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true scope of technical protection of the present invention should be determined by the technical spirit of the attached patent claims.

1, 11: display device
10: Display panel
100: substrate
pt1, pt2: 1st and 2nd pitch
PXAR1, PXAR2: first and second pixel areas
tr1, tr2: first and second trenches
IL1, IL2: first and second insulating layers
PSL1, PSL2: first and second pixel separators

Claims (25)

A first area including a plurality of first pixel areas arranged at a first pitch along a first direction, and a plurality of second pixel areas arranged at a second pitch smaller than the first pitch along the first direction. a substrate having a defined second region including;
A plurality of first trenches disposed on the substrate and each corresponding to a boundary of adjacent first pixel areas in the first direction among the plurality of first pixel areas, and a plurality of second pixel areas a first insulating layer having a plurality of second trenches respectively corresponding to boundaries of second pixel areas adjacent to each other in the first direction;
a plurality of first pixel isolation layers each buried in the plurality of first trenches and including a material different from the first insulating layer; and
A display device comprising a plurality of second pixel isolation layers each buried in the plurality of second trenches and including a material different from the first insulating layer. According to claim 1,
A first thickness of each of the plurality of first pixel separators along the thickness direction of the substrate is greater than a second thickness of each of the plurality of second pixel separators along the thickness direction of the substrate. According to claim 1,
The first area and the second area are each plural,
The display device wherein the plurality of first areas and the plurality of second areas are alternately arranged along the first direction. According to claim 1,
a plurality of first pixel circuits each disposed on some second pixel areas among the plurality of second pixel areas;
a plurality of second pixel circuits each disposed on some other second pixel areas among the plurality of second pixel areas;
a plurality of first display elements disposed on the first area and each electrically connected to the plurality of first pixel circuits; and
The display device further includes a plurality of second display elements disposed on the second area and each electrically connected to the plurality of second pixel circuits. According to clause 4,
A first spacing between first display elements that are adjacent to each other in the first direction among the plurality of first display elements is determined by dividing second display elements that are adjacent to each other in the first direction among the plurality of second display elements. A display device substantially equal to the second interval therebetween. According to claim 1,
The display device further includes a plurality of conductive patterns interposed between the substrate and the plurality of first pixel separators and in contact with each of the plurality of first pixel separators. According to claim 1,
The display device further includes a plurality of semiconductor patterns interposed between the substrate and the plurality of first pixel isolation films and each in contact with the plurality of first pixel isolation films. According to claim 1,
A display panel wherein a first thickness of each of the plurality of first pixel separators along the thickness direction of the substrate is substantially equal to a second thickness of each of the plurality of second pixel separators along the thickness direction of the substrate. According to claim 1,
a plurality of first pixel circuits respectively disposed on the plurality of first pixel areas;
a plurality of second pixel circuits respectively disposed on the plurality of second pixel areas;
a plurality of first display elements disposed on the first area and each electrically connected to the plurality of first pixel circuits; and
further comprising a plurality of second display elements disposed on the second area and each electrically connected to the plurality of second pixel circuits;
A first gap between first display elements that are adjacent to each other in the first direction among the plurality of first display elements is determined by dividing second display elements that are adjacent to each other in the first direction among the plurality of second display elements. A display device substantially equal to the second interval therebetween. According to claim 1,
A folding region including the first region and the second region and a non-folding region are further defined on the substrate,
The display device is disposed below the substrate, and includes a first support portion including a slit corresponding to the first region of the folding region and a spoke corresponding to the second region of the folding region, and a first support portion corresponding to the non-folding region. A display device further comprising a support layer including a second support portion. According to claim 10,
The non-folding area includes a plurality of third pixel areas arranged at a third pitch substantially the same as the first pitch along the first direction,
The first insulating layer further has a plurality of third trenches respectively corresponding to boundaries of third pixel regions that are adjacent to each other in the first direction among the plurality of third pixel regions,
The display device further includes a plurality of third pixel separators each buried in the plurality of third trenches and including a material different from the first insulating layer. According to claim 11,
The first thickness of each of the plurality of first pixel separators along the thickness direction of the substrate is the second thickness of each of the plurality of second pixel separators along the thickness direction of the substrate and the thickness direction of the substrate. A display device greater than a third thickness of each of the plurality of third pixel separators. According to claim 11,
a plurality of first pixel circuits each disposed on some second pixel areas among the plurality of second pixel areas;
a plurality of second pixel circuits each disposed on some other second pixel areas among the plurality of second pixel areas;
a plurality of third pixel circuits respectively disposed on the plurality of third pixel areas;
a plurality of first display elements disposed on the first area of the folding area and each electrically connected to the plurality of first pixel circuits;
a plurality of second display elements disposed on the second area of the folding area and each electrically connected to the plurality of second pixel circuits; and
further comprising a plurality of third display elements disposed on the non-folding area and each electrically connected to the plurality of third pixel circuits;
A first spacing between first display elements that are adjacent to each other in the first direction among the plurality of first display elements is determined by dividing second display elements that are adjacent to each other in the first direction among the plurality of second display elements. The display device is substantially equal to the second interval between the plurality of third display elements and the third interval between third display elements that are adjacent to each other in the first direction among the plurality of third display elements. According to claim 1,
A first gap between first pixel isolators that are adjacent to each other in the first direction among the plurality of first pixel separators is defined by second pixel separators that are adjacent to each other in the first direction among the plurality of second pixel separators. A display panel that is larger than the second gap between. According to claim 1,
The display device wherein the first insulating layer includes an inorganic material, and the plurality of first pixel separators and the plurality of second pixel separators include an organic material. According to claim 1,
A conductive layer disposed on the first insulating layer; and
The display device further includes a second insulating layer disposed on the conductive layer and integral with the plurality of first pixel isolation films and the plurality of second pixel isolation films. According to claim 1,
The plurality of first pixel areas are arranged at a third pitch along a second direction intersecting the first direction,
The display device wherein the plurality of second pixel areas are arranged at a fourth pitch that is substantially the same as the third pitch along the second direction. A substrate having a first region defined including a plurality of first pixel regions and a second region including a plurality of second pixel regions;
An insulating layer disposed on the substrate and having a plurality of first trenches each at least partially surrounding the plurality of first pixel regions, and a plurality of second trenches each at least partially surrounding the plurality of second pixel regions. ;
a plurality of first pixel isolation layers each buried in the plurality of first trenches and including a material different from the insulating layer; and
a plurality of second pixel isolation layers each buried in the plurality of second trenches and including a material different from the insulating layer;
A first depth of each of the plurality of first pixel separators along the thickness direction of the substrate is greater than a second depth of each of the plurality of second pixel separators along the thickness direction of the substrate. According to clause 18,
a plurality of first pixel circuits each disposed on some second pixel areas among the plurality of second pixel areas;
a plurality of second pixel circuits each disposed on some other second pixel areas among the plurality of second pixel areas;
a plurality of first display elements disposed on the first area and each electrically connected to the plurality of first pixel circuits; and
The display device further includes a plurality of second display elements disposed on the second area and each electrically connected to the plurality of second pixel circuits. According to clause 19,
The first spacing between neighboring first display elements among the plurality of first display elements is substantially the same as the second spacing between neighboring second display elements among the plurality of second display elements. Device. According to clause 18,
The display device further includes a plurality of conductive patterns or a plurality of semiconductor patterns interposed between the substrate and the plurality of first pixel isolation films and in contact with the plurality of first pixel isolation films, respectively. According to clause 18,
The first area and the second area are each plural,
A display device in which the plurality of first areas and the plurality of second areas are alternately arranged along one direction. According to clause 18,
A folding region including the first region and the second region and a non-folding region are further defined on the substrate,
The display device is disposed below the substrate, and includes a first support portion including a slit corresponding to the first region of the folding region and a spoke corresponding to the second region of the folding region, and a first support portion corresponding to the non-folding region. A display device further comprising a support layer including a second support portion. According to clause 23,
The non-folding area includes a plurality of third pixel areas,
The insulating layer further has a plurality of third trenches each surrounding at least a portion of the plurality of third pixel regions,
The display device further includes a plurality of third pixel isolation layers each buried in the plurality of third trenches and including a material different from the insulating layer,
The first depth of each of the plurality of first pixel separators is greater than the third depth of each of the plurality of third pixel separators along the thickness direction of the substrate. According to clause 18,
The display device wherein the insulating layer includes an inorganic material, and the plurality of first pixel separators and the plurality of second pixel separators include an organic material.

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