KR20230155760A - Quantum Circuit Simulation Hardware - Google Patents

Abstract

Quantum circuit simulation hardware is provided. The quantum circuit simulator according to an embodiment of the present invention includes a grouping unit that groups the states that make up the state vector into a plurality of sets based on the target qubit of the gate that makes up the quantum circuit simulated on the computer, and a gate operation that is performed. It includes a decision unit that determines the set and an operation unit that performs a gate operation on the determined set. As a result, when simulating a quantum circuit model on a classical computer rather than a quantum computer, the state vector generated at the quantum output, which is the result of the calculation of the quantum circuit, can be calculated with less complexity and memory.

Description

Quantum Circuit Simulation Hardware

The present invention relates to a simulator of a quantum circuit model, and more specifically, to a technology related to quantum circuit simulation hardware for efficiently calculating state vectors in quantum circuit operations on a classical computer.

A quantum computer is a computer that can solve existing NP-complete problems within polynomial time using several new algorithms such as the Shor algorithm and Groover algorithm, and is a technology that can collapse the RSA encryption system that currently utilizes the characteristics of prime numbers. However, there are resource limitations in actually conducting research with quantum computers, so simulations on classical computers are essential for algorithmic research using quantum circuits.

A quantum circuit can be expressed as a two-dimensional matrix composed of complex numbers, and a quantum circuit using N qubits is expressed as a 2 ^N × 2 ^N matrix. Therefore, in a 50-qubit system that enjoys quantum supremacy, ^a complex matrix of ^{2 50}

Therefore, to solve this problem, a method is needed to reduce the amount of calculations and memory required when calculating quantum circuits.

The present invention was created to solve the above problems, and the purpose of the present invention is to simulate the quantum circuit model on a classical computer, and to use the state vector generated at the quantum output, which is the result of the calculation of the quantum circuit. The goal is to provide quantum circuit simulation hardware that can operate with small complexity and memory.

A quantum circuit simulator according to an embodiment of the present invention to achieve the above object groups the states constituting the state vector into a plurality of sets based on the target qubit of the gate constituting the quantum circuit simulated on the computer. Grouping Department; a decision unit that determines a set to perform a gate operation; and an operation unit that performs a gate operation on the determined set.

The grouping unit may group states in which the target qubit is the same and the remaining qubits are different into the same set.

The decision unit may decide to perform a gate operation on a set in which all grouped states are not 0.

The decision unit may decide not to perform the gate operation on a set in which all grouped states are 0.

The decision unit may determine whether to perform a gate operation based on non-zero states and gates for a set in which some of the grouped states are 0.

The decision unit may determine not to perform the gate operation if the gate is a control gate and the 0 state is a control qubit.

The calculation unit can perform calculations by sequentially updating the quantum state vector on a gate-by-gate basis for the gates constituting the quantum circuit.

In order to determine that the value of the state of the set for decision is 0, the decision unit can check whether the state is 0 with low delay by using internal memory instead of using external memory.

The decision unit may determine not to access the internal memory and not perform the gate operation if the gate is a control gate and the 0 state is a control qubit.

A quantum circuit simulation method according to another embodiment of the present invention includes grouping states constituting a state vector into a plurality of sets based on the target qubit of a gate constituting a quantum circuit simulated on a computer; determining a set to perform a gate operation on; and performing a gate operation on the determined set.

As described above, according to embodiments of the present invention, when simulating a quantum circuit model on a classical computer rather than a quantum computer, the state vector generated at the quantum output, which is the result of the calculation of the quantum circuit, can be calculated with less complexity and memory. It becomes possible. As a result ^{, the} 2 ^N

1 is a diagram showing the configuration of a quantum circuit simulation system according to an embodiment of the present invention;
Figure 2 is a diagram showing the detailed structure of a quantum circuit simulation accelerator;
3 is a diagram showing the detailed structure of a quantum circuit simulator;
4 is a diagram illustrating a gate of a quantum circuit;
5 is a diagram illustrating the state grouping results;
6 is a diagram illustrating a 2-qubit single gate;
7 is a diagram illustrating a 2-qubit control gate;
Figures 8 and 9 are drawings provided to explain the existing quantum circuit calculation method,
10 and 11 are diagrams provided to explain the quantum circuit calculation method according to an embodiment of the present invention.

Hereinafter, the present invention will be described in more detail with reference to the drawings.

An embodiment of the present invention presents simulation hardware for a quantum circuit simulator running on a classical computer to efficiently calculate state vectors in quantum circuit operations using limited memory.

Here, a classical computer is a currently commonly used computer that performs bit (0 or 1)-based operations, and is a concept corresponding to a quantum computer that performs qubit-based operations.

In order to efficiently calculate the state vector in the quantum circuit, in the embodiment of the present invention, the determinant that combines the matrices of the quantum gates constituting the quantum circuit into one by Kronecker product is not calculated, but the quantum circuit is Quantum state vectors are sequentially calculated for each gate unit.

That is, in the embodiment of the present invention, the part consisting of a number of gates in the quantum circuit is divided into gate units and the state vector is updated each time it passes through each gate, thereby requiring a large amount of calculation and memory usage. By excluding the Kerr product operation, the amount of computation and memory usage are dramatically reduced.

Figure 1 is a diagram showing the configuration of a quantum circuit simulation system according to an embodiment of the present invention. As shown, the quantum circuit simulation system according to an embodiment of the present invention includes a host system 100 and a quantum circuit simulation accelerator 200.

The quantum circuit simulation accelerator 200 is simulation hardware that simulates a quantum circuit and can be implemented using an FPGA (Field Programmable Gate Array). The host system 100 is a system for developing a quantum circuit simulator of the quantum circuit simulation accelerator 200.

Figure 2 shows the detailed structure of the quantum circuit simulation accelerator 200. As shown, the quantum circuit simulation accelerator 200 includes a Micro Controller Unit (MCU) 210, a memory 220, a BUS 230, and a quantum circuit simulator 240.

The MCU 210 is equipped with firmware developed and compiled in the host system 100. The MCU 210 equipped with firmware receives quantum circuit data and initial quantum state data to be simulated by the quantum circuit simulator 240 from the host system 100 and stores them in the memory 220.

Quantum circuits are constructed by connecting various gates. Gates include single-qubit gates such as identity gates, Pauli gates, and Clifford gates, controlled Pauli gates, controlled Hadamard gates, controlled rotation gates, and Toffoli gates. There are multi-qubit gates, etc.

Gates that make up a quantum circuit are expressed as matrices. When the host system 100 transfers these matrices to the MCU 210, the MCU 210 stores the matrices in the memory 220. The quantum circuit simulator 240 performs quantum operations using matrices stored in the memory 220 under the control of the MCU 210.

The quantum operation results and final quantum state by the quantum circuit simulator 240 are transmitted to the host system 100 through the MCU 210. BUS 240 provides a communication interface between components of quantum circuit simulation accelerator 200.

Figure 3 shows the detailed structure of the quantum circuit simulator 240. As shown, the quantum circuit simulator 240 includes a state grouping unit 241, an operation skip decision unit 242, an operation unit 243, and a Zero Flag (ZF) SRAM 244.

The state grouping unit 241 groups and outputs the states constituting the state vector based on the target qubit of the gate constituting the quantum circuit. Specifically, the state grouping unit 242 groups two states in which the target qubit is the same and the remaining qubits are different into one set.

In a quantum circuit with N qubits, the state vector can be expressed as a 2 ^N × 1 matrix, and each item of the matrix represents the probability of measuring the corresponding state (|000>, |001>, ...). And the target qubit refers to the qubit to which the gate is applied.

As illustrated in Figure 4, when there is a gate at q0 in a quantum circuit with three qubits (q0, q1, q2), the target qubit is q0 and the eight states constituting the state vector are as shown in Figure 5. Grouped into four sets.

The set grouped and output from the state grouping unit 241 consists of two states (s1, s2) as shown in FIG. 5, and is named using two indices (v1, v2). When performing an operation while passing through one gate, the states (s1, s2) in the same set are related to each other, but are independent from the states in other sets.

The operation skip decision unit 242 determines sets to be skipped without performing the gate operation and sets to perform the gate operation among the sets grouped and output from the state grouping unit 241.

Figure 6 shows a 2-qubit single gate. If the set input through the gate is (s1, s2), the output of the gate (s1', s2') can be expressed by the following matrix operation.

The cases that can be bypassed without calculating s1' are as follows.

If s1 is 0 and u ₁ is 0 or if s2 is 0 and u ₀ is 0

The cases in which s2' can be bypassed without calculating it are as follows.

If s1 is 0 and u ₃ is 0 or if s2 is 0 and u ₂ is 0

Based on the above, the operation skip decision unit 242 determines to perform the gate operation on the set in which all grouped states are not 0, and does not perform the gate operation on the set in which all grouped states are 0. You can decide to skip it.

Meanwhile, whether the state is 0 is checked in the ZF SRAM 244 rather than the external memory 220, so the state can be checked with less computational cost and lower delay than reading the actual value.

Additionally, the operation skip decision unit 242 determines whether to perform a gate operation based on non-zero states and gates for a set in which some of the grouped states are 0.

Specifically, when the gate is a single gate as illustrated in FIG. 6, the operation skip decision unit 242 determines to perform the operation even if some of the states are set to 0.

On the other hand, if the gate is a control gate as illustrated in FIG. 7, which is a multi-qubit gate that can be bypassed according to the input qubit, and the 0 state is the control qubit (q0), it is skipped without accessing the ZF SRAM 244 and performing the gate operation. Decide to do it.

The operation unit 243 sequentially reads the set of states determined to perform the gate operation by the operation skip decision unit 242 from the memory 220 and uses them as inputs to the gate to perform the operation, and the state updated by the operation. These are recorded in memory 220.

The calculation by the calculation unit 243 is repeated for each of all gates constituting the quantum circuit simulated by the quantum circuit simulator 240 until the calculation is completed. As a result, the final updated quantum state vector remains in the memory 120.

Hereinafter, assuming an arbitrary quantum circuit, the quantum circuit calculation method according to an embodiment of the present invention will be described by comparing it with the existing quantum circuit calculation method.

FIG. 8 is a diagram showing the concept of an existing quantum circuit calculation method for an arbitrary quantum circuit, and FIG. 9 is a flowchart showing the existing quantum circuit calculation method.

As shown in Figures 8 and 9, in the existing method, when a state vector |A> of 8 Calculate (unitary matrix). Next, calculate |B> by multiplying the state vector |A> and the unitary matrix.

After calculating the unitary matrix ( By multiplying C> and updating it to |D>, the final state vector is output.

FIG. 10 is a diagram showing the concept of a quantum circuit calculation method according to an embodiment of the present invention for an arbitrary quantum circuit, and FIG. 11 is a flowchart showing a quantum circuit calculation method according to an embodiment of the present invention.

As shown in Figures 10 and 11, in the method according to the embodiment of the present invention, calculation is performed on a quantum gate basis, that is, calculation is performed on only one quantum gate at a time. Accordingly, instead of Kronecker multiplying (ⓧ) the three H gates, they are separated by Hani and operated individually.

Accordingly, when a state vector of size 8×1 |A> is input, it is multiplied by the matrix of the first quantum gate and updated to |B>, then multiplied by the matrix of the second quantum gate and updated to |C>, and the third quantum gate It is multiplied by the gate matrix and updated to |D>.

Afterwards, it is multiplied with the matrix of the fourth quantum gate and updated to |E>, and multiplied by the matrix of the fifth quantum gate and updated to |F> to output the final state vector.

As a result, the number of gate operations (number of state vector updates) increases compared to the existing method, but since Kronecker multiplication is not performed, the amount of calculations and required memory are dramatically reduced. ^Specifically , ^the existing method requires 2 ^N

On the other hand, in the case of the method according to the embodiment of the present invention, since one quantum gate is processed at a time, the same space for storing the input state vector and the output state vector is required as the existing method, but the space for storing the intermediate value required for quantum operation is required. The space required is only 2×2 regardless of the qubit size. In addition, when performing state vector operations, only multiplication and addition operations corresponding to the number of states of the output state vector are performed rather than matrix multiplication, which is advantageous in terms of computational complexity.

So far, a quantum circuit simulation device that efficiently calculates state vectors has been described in detail using preferred embodiments.

In an embodiment of the present invention, when simulating a quantum circuit model on a classical computer, a hardware structure that can calculate the state vector generated at the quantum output, which is the result of the calculation of the quantum circuit, with a small memory is presented.

In an embodiment of the present invention, the final state vector is not calculated using an intermediate unitary matrix with a size of 2 ^N × 2 ^N in a quantum circuit composed of several quantum gates, but is repeatedly divided into 2 × 2 unitary operations of a single quantum gate. Memory consumption was reduced by using intermediate results in units of state vectors with a size of 2N ⁺¹ .

Additionally, in an embodiment of the present invention, states that are related to each other are grouped into a set based on the target qubit of the gate, and if the gate operation can be bypassed depending on the state value and type of gate, the operation is skipped to increase latency and power. Consumption was reduced.

Meanwhile, of course, the technical idea of the present invention can be applied to a computer-readable recording medium containing a computer program that performs the functions of the device and method according to this embodiment. Additionally, the technical ideas according to various embodiments of the present invention may be implemented in the form of computer-readable code recorded on a computer-readable recording medium. A computer-readable recording medium can be any data storage device that can be read by a computer and store data. For example, of course, computer-readable recording media can be ROM, RAM, CD-ROM, magnetic tape, floppy disk, optical disk, hard disk drive, etc. Additionally, computer-readable codes or programs stored on a computer-readable recording medium may be transmitted through a network connected between computers.

In addition, although preferred embodiments of the present invention have been shown and described above, the present invention is not limited to the specific embodiments described above, and can be used in the technical field to which the invention pertains without departing from the gist of the present invention as claimed in the claims. Of course, various modifications can be made by those skilled in the art, and these modifications should not be understood individually from the technical idea or perspective of the present invention.

100: host computer
200: Quantum circuit simulation accelerator
240: Quantum circuit simulator
241: Status grouping unit
242: Operation skip decision unit
243: Calculation unit
244: ZF SRAM

Claims (10)

A grouping unit that groups the states constituting the state vector into a plurality of sets based on the target qubit of the gate constituting the quantum circuit simulated on the computer;
a decision unit that determines a set to perform a gate operation; and
A quantum circuit simulator comprising a calculation unit that performs a gate operation on the determined set.
In claim 1,
Grouping department,
A quantum circuit simulator characterized by grouping states in which the target qubit is the same and the remaining qubits are different into the same set.
In claim 2,
The decision department,
A quantum circuit simulator characterized in that it determines to perform a gate operation for a set in which all grouped states are not 0.
In claim 3,
The decision department,
A quantum circuit simulator characterized in that for a set in which all grouped states are 0, a gate operation is not performed.
In claim 4,
The decision department,
For a set in which some of the grouped states are 0, a quantum circuit simulator characterized in that it determines whether to perform a gate operation based on the non-zero state and the gate.
In claim 5,
The decision department,
A quantum circuit simulator characterized in that if the gate is a control gate and the 0 state is a control qubit, it is decided not to perform the gate operation.
In claim 2,
The decision department,
A quantum circuit simulator characterized by checking whether the state is 0 with low delay using internal memory rather than using external memory to determine that the value of the state of the set is 0.
In claim 7,
The decision department,
A quantum circuit simulator characterized in that, if the gate is a control gate and the 0 state is a control qubit, it is determined not to access the internal memory and not perform the gate operation.
In claim 1,
The calculation department,
A quantum circuit simulator that operates by sequentially updating the quantum state vector on a gate-by-gate basis for the gates that make up the quantum circuit.
Grouping states constituting a state vector into a plurality of sets based on target qubits of gates constituting a quantum circuit simulated on a computer;
determining a set to perform a gate operation on; and
A quantum circuit simulation method comprising: performing a gate operation on the determined set.