KR20230144782A - Hybrid Integrated Circuit - Google Patents

Abstract

The present invention relates to hybrid integrated circuits. According to the present invention, an integrated circuit including at least one passive element is formed through a Complementary Metal-Oxide Semiconductor (CMOS) process, a first semiconductor having a groove for inserting an active element in a portion of the upper surface, and the first semiconductor. It is mounted on the groove portion of the , is formed through a Group 3-5 compound semiconductor process, and includes a second semiconductor, which is an active element connected to the passive element, and the passive element of the first semiconductor is connected to the second semiconductor and the metal line. It provides hybrid integrated circuits connected to each other through.
According to the present invention, in order to improve the performance of existing CMOS-based single integrated circuits, specific transistors requiring high performance in CMOS-based integrated circuits are replaced with III-V compound semiconductor-based transistors, thereby maintaining high integration of the transmitting and receiving integrated circuits. However, it has the advantage of improving transmission and reception performance.

Description

Hybrid Integrated Circuit

The present invention relates to a hybrid integrated circuit, and more specifically, to a hybrid integrated circuit that can improve transmission and reception performance while maintaining a high degree of integration of the transmission and reception integrated circuit.

With the commercialization of 5th generation mobile communication technology, beamforming technology has established itself as one of the core technologies of the transmission and reception system for wireless communication.

This beamforming technology is expected to be applied not only to 5th generation mobile communications but also to 6th generation mobile communications, and is expected to be actively applied in various wireless fields in the future. This beamforming technology consists of antennas implemented in an array and a transmission/reception circuit connected to each antenna.

Figure 1 is a diagram showing the configuration of a transmitting and receiving terminal using a time division method, and Figure 2 is a diagram showing the configuration of a transmitting and receiving terminal using a frequency division method. Figures 1 and 2 illustrate a beamforming system structure consisting of four transmitting and receiving terminals for convenience of explanation, and the number of channels is not necessarily limited thereto.

First, when using the time division method (TDD), one antenna is connected to one transmitting and receiving end as shown in the top picture of FIG. 1, and it operates by selectively connecting the transmitting end and the receiving end using an internal switch. In other words, one antenna is connected to each channel.

When using the frequency division method (FDD), two antennas are connected to one transmitting and receiving end as shown in FIG. 2, and the transmitting end and the receiving end are individually connected to the transmitting antenna and the receiving antenna. That is, two antennas are connected to each channel.

As shown in Figures 1 and 2, there are some differences depending on the TDD and FDD methods, but the number of transmitting and receiving terminals is determined corresponding to the antenna. Compared to other existing mobile communication systems, this beamforming system has the characteristic of requiring multiple transmitting and receiving terminals, and the repeatedly used transmitting and receiving terminals are called channels. Figures 1 and 2 show an example where there are four channels at the transmitting and receiving end.

Unlike mobile communication systems that typically use a single transmitter/receiver, in the case of a beamforming system, the size of the transmitter/receiver is a major factor in determining the feasibility of implementing the entire system. A drawing for explanation of this is shown in Figure 3.

Figure 3 is a conceptual diagram of antenna and wiring according to the transmitter/receiver integration degree. Figure 3(a) represents a high-integration transmitting/receiving terminal, and Figure 3(b) represents a low-integration transmitting/receiving terminal.

In Figure 3, the TDD method is used as an example among the TDD method and the FDD method, but problems depending on the size of the transmitting and receiving terminal are the same or similar in both cases. Figure 3(a) shows high integration as the size of the transmitter and receiver is the same as the size of the antenna array.

However, as shown in (b) of Figure 3, when the size of the transmitting and receiving terminal is formed larger than the size of the antenna array, in addition to the problem of increasing the overall system area, the electrical connection line between each transmitting and receiving terminal channel and the antenna is required for each channel. If they are formed differently, the intended beamforming performance cannot be secured. In addition, as shown in Figure 3 (b), when the connection line between the antenna and the transmitting and receiving terminal is long, there is a problem in that the maximum output power and noise suppression performance are deteriorated due to power leakage due to the connecting line.

Accordingly, in a beamforming system, the size of each channel that makes up the transmitter and receiver is a very important factor. In order to reduce the size of the transmitter and receiver, the beamforming system uses CMOS (Complementary Metal-Oxide Semiconductor), which has the highest integration. It is common to configure the transmitter and receiver based on the process.

This CMOS process has the advantage of being suitable for beamforming systems due to its high integration, but in general, CMOS-based active devices have the disadvantage of showing relatively low performance in terms of linearity, output power, and operating frequency compared to compound semiconductors.

Due to these low-performance CMOS active device characteristics, there is a limitation in that the output power cannot be sufficiently increased in the transmitter and the noise figure is deteriorated in the receiver.

As a result, while the CMOS process has the great advantage of making the implementation of the beamforming system a reality by providing high integration for the beamforming system, it has the disadvantage of deteriorating the transmission and reception signal characteristics due to the performance limitations of the active elements.

Conventional technologies to overcome this include a technology that uses a CMOS process-based integrated circuit and a compound semiconductor-based integrated circuit based on Group 3 and Group 5 elements.

Figure 4 is a diagram illustrating an example of existing research in constructing a power amplifier and a low-noise amplifier using a III-V semiconductor process. Figure 4 shows a structure in which the transmitter and receiver are implemented with four chips rather than a single chip, as indicated by a box.

Generally, the output power characteristics of the transmitting terminal are determined by the power amplifier (PA) that constitutes the transmitting terminal. As shown in Figure 4, the transmitting terminal is configured based on CMOS, but the power amplifier (PA) is composed of a compound semiconductor. This can improve output power.

In addition, the noise suppression performance of the receiving end is determined by the low noise amplifier (LNA) that constitutes the receiving end. As shown in Figure 4, the receiving end is configured based on CMOS, but the low noise amplifier (LNA) has excellent noise suppression performance. Noise suppression performance can be improved by making it a compound semiconductor.

At this time, the power amplifier (PA) and low noise amplifier (LNA) can be composed of different compound semiconductors that each have strengths in output power and noise suppression performance. In this case, three different semiconductor processes are used, so the production The disadvantage is that the unit cost increases and the size of the overall system increases.

Next, there is a method of implementing the power amplifier (PA) and low noise amplifier (LNA) using the same compound semiconductor process. This can be expected to reduce the overall system size compared to using three different semiconductor processes, but still requires two Because different processes are used, there is a problem that the overall system size increases due to connection lines between integrated circuits.

In addition, considering the operating frequency of a general beamforming system, in the case of this prior art, the performance of the entire system is degraded due to parasitic components caused by bonder wires and PCB lines added to connect different integrated circuits, There is a problem that performance differences may occur between each transmitting and receiving end channel.

The technology behind the present invention is disclosed in Korean Patent Publication No. 10-2001-0050332 (published on June 15, 2001).

The present invention replaces specific transistors that require high-performance transistors with III-V compound semiconductor-based transistors in a transmission and reception integrated circuit composed of highly integrated CMOS process technology, thereby improving transmission and reception performance while maintaining a high degree of integration of the transmission and reception integrated circuit. The purpose is to provide a hybrid integrated circuit.

The present invention relates to a first semiconductor in which an integrated circuit including at least one passive element is formed through a Complementary Metal-Oxide Semiconductor (CMOS) process, a groove for inserting an active element is machined in a portion of the upper surface, and the groove of the first semiconductor is provided. It is mounted on, is formed through a Group 3-5 compound semiconductor process, and includes a second semiconductor, which is an active element connected to the passive element, and the passive element of the first semiconductor is connected to the second semiconductor through a metal line. Provides interconnected hybrid integrated circuits.

Additionally, the active element may be a transistor.

In addition, the first semiconductor is a transmitting stage for a beamforming system for mobile communication and is formed as the integrated circuit through a CMOS process, and the active element is the final amplifying stage among the amplifying stages that constitute the power amplifier, which is the final stage of the transmitting stage. It may be a power transistor in a power amplification stage (Power Stage).

In addition, the first semiconductor includes first and second passive elements formed side by side and spaced apart from each other on a semiconductor substrate, and the first and second passive elements are located at the input terminal and the output terminal of the power transistor within the power amplification stage. It may be an input matching network and an output matching network respectively connected to .

In addition, the present invention includes a first semiconductor on which an integrated circuit including at least one passive element is formed through a CMOS (Complementary Metal-Oxide Semiconductor) process, and 3 stacked on top of the first semiconductor, facing each other. -A hybrid integrated circuit formed through a Group 5 compound semiconductor process and comprising a second semiconductor, which is an active element connected to the passive element, and the passive element of the first semiconductor is connected to the second semiconductor and a metal line. provides.

Additionally, the metal line may connect opposing connection terminals of the passive element and the active element during the stacking.

In addition, the first semiconductor includes first and second passive elements formed side by side and spaced apart from each other on a semiconductor substrate, and the second semiconductor is located on both edge portions of the substrate while being spaced apart from the substrate surface of the first semiconductor. These may be stacked to cover the upper surfaces of each edge of the first and second passive elements.

According to the present invention, in order to improve the performance of existing CMOS-based single integrated circuits, specific transistors requiring high performance in CMOS-based integrated circuits are replaced with III-V compound semiconductor-based transistors, thereby maintaining high integration of the transmitting and receiving integrated circuits. However, it has the advantage of improving transmission and reception performance.

Figure 1 is a diagram showing the configuration of a transmitting and receiving terminal using a time division method.
Figure 2 is a diagram showing the configuration of a transmitter and receiver using a frequency division method.
Figure 3 is a conceptual diagram of wiring with an antenna according to the transmitter/receiver integration degree.
Figure 4 is a diagram illustrating an example of existing research in constructing a power amplifier and a low-noise amplifier using a III-V semiconductor process.
Figure 5 is a diagram sequentially showing the structure of a general high-frequency transmission stage, a power amplifier within the transmission stage, and a power amplification stage within the power amplifier.
Figure 6 is a diagram conceptually showing a plan view and a cross-sectional view of a power amplifier semiconductor formed of a CMOS semiconductor.
Figure 7 is a plan view and cross-sectional view of a power amplifier semiconductor for implementing a hybrid integrated circuit according to an embodiment of the present invention.
Figure 8 is a diagram explaining the structure of a hybrid integrated circuit according to the first embodiment of the present invention.
Figure 9 is a diagram explaining the structure of a hybrid integrated circuit according to a second embodiment of the present invention.

Then, with reference to the attached drawings, embodiments of the present invention will be described in detail so that those skilled in the art can easily implement the present invention. However, the present invention may be implemented in many different forms and is not limited to the embodiments described herein. In order to clearly explain the present invention in the drawings, parts that are not related to the description are omitted, and similar parts are given similar reference numerals throughout the specification.

Throughout the specification, when a part is said to be "connected" to another part, this includes not only the case where it is "directly connected," but also the case where it is "electrically connected" with another element in between. . Additionally, when a part "includes" a certain component, this means that it may further include other components rather than excluding other components, unless specifically stated to the contrary.

The hybrid integrated circuit according to the present invention can maximize its effect in a beamforming system using an array antenna, but in the embodiment, the present invention is explained using a general high-frequency transmitting and receiving stage to which the present invention can be applied.

Hereinafter, the configuration of a high-frequency transmitter to which a hybrid integrated circuit according to an embodiment of the present invention is applied will be described with reference to FIG. 5.

Figure 5 is a diagram sequentially showing the structure of a general high-frequency transmission stage, a power amplifier within the transmission stage, and a power amplification stage within the power amplifier.

Generally, the high-frequency transmitting stage includes a variable gain amplifier (VGA), a phase shifter (PS), and a power amplifier (PA) 10, and the power amplifier 10 is again the first drive. It includes an amplifier stage (1st Driver Stage), a second driver stage (2nd Driver Stage), and a power stage (Power Stage) 11. In addition, the power amplification stage 11 includes an input matching network 12, a power transistor 13, and an output matching network 14.

The high-frequency transmitter serves to transmit the modulated signal to the antenna with sufficiently large output power for wireless communication, and the main performance indicators at this time are linearity and output power. What has the greatest influence on these performance indicators is the power amplifier 10, which is the final circuit of the transmitting stage, and the power amplifier stage 11, which is the most final amplifier stage among the amplification stages constituting the power amplifier 10.

As such, the detailed element that has the greatest impact on the performance of the transmitting stage is the power amplification stage 11, which consists of matching circuits 12 and 14 composed of passive elements and active elements 13 between them. It is composed. Among these, the part that has the greatest influence on the performance indicators of the transmitter is the active element 13, indicated as a power transistor in FIG. 5.

In general, when a transmitter is configured with a CMOS process to take advantage of high integration, the linearity and output power characteristics of the transmitter appear lower than those of a compound semiconductor-based transmitter due to the nonlinearity and low breakdown voltage of CMOS-based active devices. .

In an embodiment of the present invention, in order to improve the performance of the transmitter while maintaining the high degree of integration of CMOS, the power transistor 13 constituting the CMOS-based power amplifier 11 of FIG. 5 is replaced with a compound having high linearity and high breakdown voltage. We propose a technology to replace it with a power transistor-based power transistor.

Figure 6 is a diagram conceptually showing a plan view and a cross-sectional view of a power amplifier semiconductor formed of a CMOS semiconductor. As shown in the top view, the passive device region and the active device region (Transistor Region) are formed on the semiconductor substrate without overlapping parts, and the passive devices 21 and 23 and the active device 22 are provided by the semiconductor process. They are connected to each other using metal wires.

Figure 7 is a plan view and cross-sectional view of a power amplifier semiconductor for implementing a hybrid integrated circuit according to an embodiment of the present invention.

In order to implement the hybrid integrated circuit according to the present invention, the CMOS integrated circuit is configured in a form excluding the target active element as shown in FIG. 7. The substrate shown in FIG. 7 corresponds to the first semiconductor based on the CMOS process described later.

And the target active element required to implement the hybrid integrated circuit according to the present invention is replaced with a compound semiconductor-based transistor. A compound semiconductor-based transistor corresponds to the second semiconductor, which will be described later.

As shown in FIG. 7 , a CMOS integrated circuit without an active element portion for replacement with a compound semiconductor is implemented as a hybrid integrated circuit according to the present invention through the same process as FIG. 8 or FIG. 9 .

Figure 8 is a diagram explaining the structure of a hybrid integrated circuit according to the first embodiment of the present invention.

The hybrid integrated circuit 100 according to the first embodiment shown in FIG. 8 can be manufactured through a process of steps 1 to 3, and the bottom figure shows a plan view corresponding to the final completed step 3.

Referring to FIG. 8, the hybrid integrated circuit 100 according to the first embodiment of the present invention includes a first semiconductor 110 based on a CMOS process (CMOS semiconductor) and a second semiconductor 120 based on a compound process (compound semiconductor). ), and the second semiconductor 120 based on a compound with an active element formed in the groove 112 of the first semiconductor 110 is inserted as shown in the figure in step 3, and the metal lines (L1, L2) are connected to each other. It has a structure that is connected (electrically wired).

Through this, a hybrid integrated circuit having a structure in which the first semiconductor 110 and the second semiconductor 120 manufactured through different processes are combined is implemented on a single substrate.

Here, the first semiconductor 110 forms at least one passive element 111 through a CMOS process. This first semiconductor 110 has a groove 112 formed on a portion of its upper surface for inserting active elements. Here, the groove 112 may be processed by an etching or etching process.

In addition, the passive element 111 may correspond to a matching network within the power amplification stage 11 previously described in FIG. 5.

The second semiconductor 120 is formed through a compound semiconductor process and corresponds to an active device (transistor) connected to the passive device 111. These active devices can be manufactured using a group 3-5 (III-V) compound semiconductor process.

Since the second semiconductor 120 manufactured based on a compound as described above itself corresponds to an active device, hereinafter, for convenience of explanation, the second semiconductor 120 will be referred to as an 'active device'.

The active element 120 may correspond to the power transistor 13 element in the power amplification stage 11 previously described in FIG. 5.

This second semiconductor 120 is inserted and mounted into the groove portion 112 of the first semiconductor 110. Here, a separate fixing means, adhesive, etc. may be used at the mounting site.

In this way, the passive elements 111 of the first semiconductor 110 (CMOS semiconductor) manufactured based on CMOS are the active elements 120 and metal lines (L1, L2) of the second semiconductor (compound semiconductor) made by a compound semiconductor process. They can be electrically connected to each other through .

Looking at the manufacturing process, step 1 of FIG. 8 is a step of etching the active element region (groove portion) 112 to be replaced with a compound semiconductor. In the second step, an active element implemented as a compound semiconductor is placed in the etched area 112. Lastly, step 3 is a step of forming metal lines (L1, L2) through a post-process to connect the active element 120 and the passive element 111 located on the hybrid integrated circuit.

In an embodiment of the present invention, an integrated circuit including a passive element 111 may be formed in the first semiconductor 110 based on a CMOS process. Here, the integrated circuit may correspond to a transmitter circuit for a beamforming system for mobile communication as shown in FIG. 5.

At this time, the active element 120 corresponds to the power transistor 13 in the power amplification stage 12, which is the final amplification stage among the amplification stages that constitute the power amplifier 10, which is the final stage of the transmission stage in FIG. 5.

Additionally, in the first semiconductor 110, the passive element 111 includes first and second passive elements 111-1 and 111-2 formed side by side and spaced apart from each other on the semiconductor substrate. At this time, the first and second passive elements 111-1 and 111-2 correspond to the input matching circuit 12 and the output matching circuit 14 respectively connected to the input terminal and output terminal of the power transistor 13 in the power amplifier stage. .

That is, in this case, the target active element in the transmitting circuit, that is, the power transistor 13 of the power amplification stage, is manufactured with the second semiconductor 120 (compound semiconductor) based on the compound semiconductor process, and the first semiconductor 110 ) and is connected to the passive elements 111-1 and 111-2 on the first semiconductor 110 (CMOS semiconductor) by metal lines L1 and L2. In this way, a hybrid integrated circuit for a high-frequency transmitter can be manufactured.

7 and 8 illustrate the hybrid integrated circuit according to the present invention using an example of a transmitting stage structure for mobile communication, and in particular, the power transistor 13 constituting the power amplifying stage 11 of the power amplifier 10 is compound. An example of implementation using a semiconductor-based transistor was shown.

In this case, the active element 120 implemented as a compound semiconductor is gallium nitride (GaN, allium nitride)-based and gallium arsenide (GaAs)-based HEMT (Heterojunction Field-Effect Transistors) or HBT (Heterojunction Bipolar), which have excellent frequency and power characteristics. Transistor), etc.

Similarly, the advantages of the hybrid integrated circuit according to the present invention can be applied to the receiving end structure for mobile communication. In this case, the hybrid implementation process is the same as the method described in Figures 7 and 8. As an example, in the case of a receiving end, noise suppression performance is important, so the performance of the low noise amplifier (LNA), which is the first amplifier of the receiving end, is important. In particular, the performance of the transistor that constitutes the first stage of the low noise amplifier is important. Therefore, in this case, the transistor in the first stage of the low-noise amplifier can be replaced with a compound semiconductor-based active element in the same manner as shown in FIGS. 7 and 8. As an example, the active device implemented with a compound semiconductor may be a gallium arsenide (GaAs)-based mHEMT (Metamorphic HEMT) or InP HEMT (Indium Phosphide HEMT) with excellent frequency and noise characteristics.

Figure 9 is a diagram explaining the structure of a hybrid integrated circuit according to a second embodiment of the present invention.

The hybrid integrated circuit 200 according to the second embodiment shown in FIG. 9 can be manufactured through a process of steps 1 to 3, and the bottom figure shows a plan view corresponding to the final completed step 3.

Referring to FIG. 9, the hybrid integrated circuit 200 according to the second embodiment of the present invention includes a first semiconductor 210 based on a CMOS process and a second semiconductor 220 based on a compound process, and the first semiconductor It has a structure in which the second semiconductor 220 is stacked on top of 210 and connected to each other through metal lines L1 and L2.

Through this, a hybrid integrated circuit is formed in which the first semiconductor 210 and the second semiconductor 220, which are manufactured through different processes, are combined.

The first semiconductor 210 forms at least one passive element 211 through a CMOS process. In the second embodiment as well, the first semiconductor 210 includes first and second passive elements 211-1 and 211-2 formed side by side and spaced apart from each other on a substrate, and these passive elements 211-1 and 211-2 each provide power. It corresponds to the input/output matching circuit of the amplifier stage.

The second semiconductor 220 is formed through a compound semiconductor process and corresponds to an active element (transistor) connected to the passive element 211. The second semiconductor 220 is stacked on top of the first semiconductor 210 to face each other. Active devices can be manufactured using a group 3-5 compound semiconductor process.

Since the second semiconductor 220 manufactured based on a compound like this itself corresponds to an active device, for convenience of explanation, the second semiconductor 220 is referred to as an active device. Additionally, the active element 220 may correspond to the power transistor 13 element in the power amplification stage 11 previously described in FIG. 5.

Here, the second semiconductor 220 is spaced apart from the substrate surface of the first semiconductor 210, as shown in FIG. 9, and both edge portions of the substrate are on the upper surfaces of each edge of the first and second passive elements 211-1 and 211-2. are laminated to cover. At this time, the metal lines (L1, L2) are connected between the opposing connection terminals of the passive element 211 and the second semiconductor 220, which is an active element, during stacking.

Looking at the manufacturing process, as in the embodiment shown in FIGS. 7 and 8, the CMOS integrated circuit is implemented on the CMOS integrated circuit (first semiconductor) 210, excluding the transistor area for replacement with a compound semiconductor. It's a step. In the next second step, metal lines (L1, L2) for connecting the active elements of the compound-based second semiconductor 220 and the passive elements 211 on the CMOS integrated circuit of the first semiconductor 210 are formed using a subsequent process. do. Afterwards, in step 3, a compound semiconductor-based transistor (active element) 220 is connected to the metal lines (L1, L2) formed in step 2 as shown in FIG. 9 to complete the hybrid integrated circuit according to the present invention.

In the case of the first embodiment shown in FIG. 8, the hybrid integrated circuit is implemented in the form of a compound semiconductor being inserted into the substrate of the CMOS integrated circuit, and in the case of the second embodiment shown in FIG. 9, the compound semiconductor is inserted into the CMOS integrated circuit. It is a stacked form, implementing a hybrid integrated circuit in which two semiconductors face each other.

The hybrid integrated circuit according to the present invention as described above is one in which only the active elements for replacement in a high-integration CMOS integrated circuit are selectively replaced with compound semiconductor-based active elements, without lowering the integration of the entire integrated circuit. By being able to utilize active elements, it is possible to improve the performance of the entire integrated circuit.

As a result, according to the present invention, in order to improve the performance of the existing CMOS-based single integrated circuit, a transmitter and receiver are not configured using a plurality of different types of integrated circuits, but a specific CMOS-based integrated circuit requiring high performance is provided. By replacing transistors with III-V compound semiconductor-based transistors, there is an advantage in improving transmission and reception performance while maintaining high integration of the transmission and reception integrated circuit.

The present invention has been described with reference to the embodiments shown in the drawings, but these are merely illustrative, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true scope of technical protection of the present invention should be determined by the technical spirit of the attached patent claims.

10: power amplifier 11: power amplifier stage
12: input matching circuit 13: power transistor
14: output matching circuit 100, 200: hybrid integrated circuit
110, 210: first semiconductor 111, 211: passive element
112: Groove 120, 220: Second semiconductor
L1, L2: metal track

Claims (8)

A first semiconductor in which an integrated circuit including at least one passive element is formed through a CMOS (Complementary Metal-Oxide Semiconductor) process and a groove for inserting an active element is machined in a portion of the upper surface; and
A second semiconductor is inserted into the groove of the first semiconductor, is formed through a group 3-5 compound semiconductor process, and is an active element connected to the passive element,
The passive element of the first semiconductor is,
A hybrid integrated circuit connected to the second semiconductor and a metal line. In claim 1
A hybrid integrated circuit in which the active element is a transistor. In claim 2,
The first semiconductor is a transmitting terminal for a beamforming system for mobile communication and is formed as the integrated circuit through a CMOS process,
The active element is,
A hybrid integrated circuit that is a power transistor in the power stage, which is the final amplification stage among the amplification stages that constitute the power amplifier, which is the final stage of the transmitting stage. In claim 3,
The first semiconductor is,
It includes first and second passive elements formed side by side and spaced apart from each other on a semiconductor substrate,
The first and second passive elements are:
A hybrid integrated circuit comprising an input matching network and an output matching network respectively connected to the input terminal and output terminal of the power transistor within the power amplifier stage. A first semiconductor on which an integrated circuit including at least one passive element is formed through a Complementary Metal-Oxide Semiconductor (CMOS) process; and
A second semiconductor is arranged in a stack facing the upper side of the first semiconductor, is formed through a group 3-5 compound semiconductor process, and is an active element connected to the passive element,
The passive element of the first semiconductor is,
A hybrid integrated circuit connected to the second semiconductor and a metal line. In claim 5,
The metal line is,
A hybrid integrated circuit that connects opposing connection terminals of the passive element and the active element during the stacking. In claim 6,
The first semiconductor is,
It includes first and second passive elements formed side by side and spaced apart from each other on a semiconductor substrate,
The second semiconductor is,
A hybrid integrated circuit in which the edge portions of both sides of the substrate are stacked so that the upper surfaces of each edge of the first and second passive elements are spaced apart from the substrate surface of the first semiconductor. In claim 5,
The first semiconductor is a transmitting terminal for a beamforming system for mobile communication and is formed as the integrated circuit through a CMOS process,
The active element is,
A hybrid integrated circuit that is a power transistor in the power stage, which is the final amplification stage among the amplification stages that constitute the power amplifier, which is the final stage of the transmitting stage.