KR20230140070A - Semiconductor devices - Google Patents

Abstract

A semiconductor device is provided with a metal interconnection structure including intermetallic insulating films and metal interconnections on a substrate. A first upper capping film is provided to cover the upper surface of the metal wiring structure. An abrasive-stopping film is provided on the first upper capping film. A through via contact is provided that extends in a vertical direction from the polishing stop layer and penetrates the polishing stop layer, the first upper capping layer, the metal wiring structure, and the substrate. An upper etch stop film is provided on the polishing stop film and the through via contact. An upper metal interconnection structure is provided on the upper etch stop layer and includes an upper intermetallic insulating layer and an upper metal interconnection. The upper metal interconnection includes a first upper metal interconnection electrically connected to the metal interconnection and a second upper metal interconnection electrically connected to the through via contact.

Description

Semiconductor devices {SEMICONDUCTOR DEVICES}

The present invention relates to semiconductor devices. More specifically, the present invention relates to a semiconductor device including a through via contact.

A through via contact penetrating the substrate may be included to electrically connect the semiconductor device to another semiconductor device or a printed circuit board. The through via contact is typically referred to as a through silicon via (TSV). The through via contact may be formed to have low resistance and reduce damage to the intermetallic insulating layer.

The object of the present invention is to provide a semiconductor device with improved characteristics.

A semiconductor device according to embodiments of the present invention for achieving the above-described problem is provided with a metal interconnection structure including intermetallic insulating films and metal interconnections on a substrate. A first upper capping film is provided to cover the upper surface of the metal wiring structure. An abrasive-stopping film is provided on the first upper capping film. A through via contact is provided that extends in a vertical direction from the polishing stop layer and penetrates the polishing stop layer, the first upper capping layer, the metal wiring structure, and the substrate. An upper etch stop film is provided on the polishing stop film and the through via contact. An upper metal interconnection structure is provided on the upper etch stop layer and includes an upper intermetallic insulating layer and an upper metal interconnection. The upper metal interconnection includes a first upper metal interconnection electrically connected to the metal interconnection and a second upper metal interconnection electrically connected to the through via contact.

Semiconductor devices according to example embodiments may include a first upper capping layer, a polishing stop layer, and an upper etch stop layer, respectively, on a metal wiring structure. Accordingly, diffusion of the metal material included in the metal wiring structure is suppressed, and the through via contact can be formed at an accurate location.

1 to 10 are cross-sectional views for explaining a method of manufacturing a semiconductor device according to example embodiments.
11 is an enlarged cross-sectional view of the upper part of a through-via contact of a semiconductor device according to an exemplary embodiment.

Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the attached drawings.

1 to 9 are cross-sectional views for explaining a method of manufacturing a semiconductor device according to example embodiments.

Referring to FIG. 1, a shallow trench device isolation process is performed on the substrate 100 to form a device isolation pattern 102. Circuit patterns 104 are formed on the device isolation pattern 102 and the substrate 100. The circuit patterns 104 may include a memory circuit or a logic circuit. The circuit patterns 104 may include, for example, N-type MOS transistors and P-type MOS transistors.

Forming first and second interlayer insulating films 110 and 112 covering the circuit patterns 104, and forming a lower wiring including a contact plug and a conductive line within the first and second interlayer insulating films 110 and 112. It forms (114). The first and second interlayer insulating films 110 and 112 may include silicon oxide and silicon nitride.

Referring to FIG. 2, a metal interconnection including intermetallic insulating films 120, metal interconnections 130, and lower capping films 122 on the second interlayer insulating film 112 and the lower interconnection 114. Form the structure 140. The metal wires 130 may be electrically connected to the lower wires 114 .

The intermetallic insulating film 120 may be formed in multiple layers. The lower capping film 122 may be formed between the intermetallic insulating films 120 of each layer.

The intermetallic insulating film 120 may include a low-k or ultra-low-k dielectric that has a lower dielectric constant than silicon oxide (SiO2). In an exemplary embodiment, the intermetallic insulating film 120 is made of fluorine-doped silicon dioxide (SiO2), carbon-doped silicon dioxide (SiO2), porous silicon dioxide (SiO2), hydrogen silsesquioxane (HSG), or Silicone based polymeric dielectric such as MSG (methylsilsesquioxane), organic polymeric dielectric such as polyimide, SiCOH, SiLKTM available from Dow Chemical, ASM. It may include available AURORATM and the like. Since the dielectric constant of the intermetallic insulating film 120 is low, parasitic capacitance generated between the metal wires 130 can be reduced.

The metal wiring 130 may be disposed within the intermetallic insulating film 120 of each layer. Accordingly, the metal wiring 130 may be formed in multiple layers. The metal wiring 130 formed in each layer may penetrate the lower capping film 122 located in the lower layer and contact the metal wiring 130 located in the lower layer. Accordingly, the metal wires 130 of each layer may be electrically connected to each other.

As an example, the metal wiring 130 may have a multi-layer structure in which first to eighth metal wirings 130a, 130b, 130c, 130d, 130e, 130f, 130g, and 130h electrically connected to circuit patterns are vertically stacked. You can. The metal wiring 130 of each layer may include via contacts and line patterns. Hereinafter, the metal wiring 130 will be described as being stacked in eight layers, but the number of stacks of the metal wiring 130 is not limited to this.

In an exemplary embodiment, the via contact and wiring line may include a first barrier metal pattern 132 and a first metal pattern 134. The first barrier metal pattern 132 may include, for example, titanium, titanium nitride, tantalum, or tantalum nitride. The first metal pattern 134 may include copper.

The lower capping film 122 may cover the upper surface of the metal wiring 130 of each layer, excluding the contact area between the upper and lower metal wirings 130.

The lower capping film 122 may be provided to prevent metal components (eg, copper) constituting the metal wiring 130 from diffusing into the intermetallic insulating film 120 . The lower capping film 122 may be an insulating material. Additionally, the lower capping layer may be used as an etch stop layer in the process for forming the metal wire 130.

Meanwhile, since the lower capping film 122 is located between the metal wires 130, it is desirable to have a low dielectric constant in order to reduce parasitic capacitance between the metal wires 130. The lower capping film 122 may have a lower dielectric constant than silicon nitride. In an exemplary embodiment, the lower capping film 122 may include SiCN.

The process for forming the metal wiring 130 of each layer may include a dual damascene process or a single damascene process. To briefly explain the process of forming the metal wiring of each layer through the dual damascene process, the intermetallic insulating film and the lower capping film below it are etched to form an opening in the area where the via contact and wiring line are to be formed. Afterwards, a first barrier metal film is conformally formed on the surface of the opening and the upper surface of the intermetallic insulating film, and a first metal film is formed on the first barrier metal film to fill the opening. Afterwards, a planarization process is performed to expose the upper surface of the intermetallic insulating film. The planarization process may include a chemical mechanical polishing process. Accordingly, the metal wiring 130 including the first barrier metal pattern 132 and the first metal pattern 134 may be formed. As the planarization process is performed, the metal wiring and intermetallic insulating film of each layer are flat and can be positioned on the same plane.

The upper surface of the metal wiring structure 140 may be flat. The upper surfaces of the intermetallic insulating film 120 and the metal wiring 130 disposed at the top may be exposed on the upper surface of the metal wiring structure 140. The upper surfaces of the intermetallic insulating film 120 and the metal wiring 130 disposed on the top of the metal wiring structure 140 may be located on the same plane.

Referring to FIG. 3 , a first upper capping layer 142 is formed on the metal wiring structure 140 to cover the upper surface of the metal wiring structure 140 . A polishing prevention layer 144 is formed on the first upper capping layer 142.

The first upper capping film 142 may be provided to suppress diffusion of metal components constituting the metal wiring 130 disposed at the top of the metal wiring structure 140. The first upper capping layer 142 may include an insulating material. The first upper capping layer 142 may have a lower dielectric constant than silicon nitride. In an exemplary embodiment, the first upper capping layer 142 may include SiCN.

If the first upper capping layer 142 is formed thinner than 100 Å, it is difficult to suppress diffusion of metal components in the metal wiring. If the first upper capping film 142 is formed thicker than 300 Å, the overall thickness of the metal interconnection structure 140 may increase and parasitic capacitance may increase. Accordingly, in an exemplary embodiment, the first upper capping layer 142 may be formed to have a thickness of 100Å to 300Å.

The polishing-stop film 144 may include a material that can be used as a polishing-stop film in a subsequent planarization process of a metal material. The polishing-stop film 144 may include an insulating material different from that of the first upper capping film 142. The polishing prevention film 144 may include SiN, for example.

If the polishing-stop film 144 is formed thinner than 300Å, it may be difficult to stop the polishing process due to wear during the polishing process. If the polishing stop film is formed thicker than 800 Å, parasitic capacitance may increase. Accordingly, in an exemplary embodiment, the polishing-stop film 144 may be formed to have a thickness of 300Å to 800Å. That is, the polishing prevention film 144 may be formed thicker than the first upper capping film 142.

Referring to FIG. 4, a mask pattern (not shown) is formed on the polishing stop layer 144, and the mask pattern is used as an etch mask to form the polishing stop layer 144 and the first upper capping layer 142. , the metal wiring structure 140, the first and second interlayer insulating films 110 and 112, and the upper part of the substrate 100 may be etched to form a through-via hole 150.

The etching process may include a dry etching process. The sidewall of the through via hole 150 formed through the etching process preferably has a vertical slope. However, when an actual etching process is performed, it is difficult for the sidewall of the through via hole 150 to have a vertical inclination, and the sidewall may be inclined so that the width becomes narrower toward the bottom.

When performing the etching process, the intermetallic insulating films 120 and lower capping films 122 of the metal interconnection structure 140 may be etched, and the metal interconnections 130 may not be etched. . Additionally, when performing the etching process, the device isolation pattern 102 of the substrate 100 may be etched.

Referring to FIG. 5, a via insulating film 152 is conformally formed on the upper surface of the polishing stop film 144 and the inner surface of the through via hole 150. The via insulating film 152 may be made of a different material from the polishing insulating film 144. The via insulating film 152 may include, for example, silicon oxide.

A second barrier metal film 154 is conformally formed on the via insulating film 152. The second barrier metal film 154 may be provided to prevent diffusion of metal formed later. The second barrier metal film 154 may include, for example, titanium, titanium nitride, tantalum, or tantalum nitride.

A second metal film 156 is formed on the second barrier metal film 154 to completely fill the inside of the through-via hole 150. The second metal film 156 may be formed of copper, and the copper may be formed through a plating process. For example, the second metal film 156 can be formed by forming a seed film containing copper or copper manganese through a physical vapor deposition or chemical vapor deposition process and then electroplating a copper film on the seed film. there is.

Referring to FIG. 6, the upper portions of the second metal film 156, the second barrier metal film 154, and the via insulating film 152 are removed through a planarization process so that the upper surface of the polishing stop film 144 is exposed. do. The planarization process may include a chemical mechanical polishing process.

When the planarization process is performed, all films formed on the upper surface of the polishing prevention film 144 can be removed. In addition, a portion of the upper portion of the polishing stop film 144 may be consumed, thereby reducing the thickness of the polishing stop film 144.

Accordingly, a through via contact 158 including a via insulating film pattern 152a, a second barrier metal pattern 154a, and a second metal pattern 156a may be formed inside the through via hole 150. The top surface of the through via contact 158 may be located on the same plane as the top surface of the polishing stop film 144. The top surface of the through via contact 158 and the top surface of the polishing stop film 144 may be flat.

Referring to FIG. 7 , an upper etch stop layer 146 is formed on the polishing stop layer 144 and the through via contact 158 to cover the polishing stop layer 144 and the through via contact 158. The upper etch stop layer 146 may include an insulating material having an etch selectivity with the polishing stop layer 144. The upper etch stop layer 146 may include, for example, silicon oxide.

As shown, a first upper capping layer 142, a polishing stop layer 144, and an upper etch stop layer are formed on the metal interconnection 130 and the intermetallic insulating layer 120 disposed at the top of the metal interconnection structure 140. (146) may be covered. Additionally, only the upper etch stop layer 146 may be covered on the through via contact 158.

Although not shown, a mask pattern is formed on the upper etch stop layer 146 to cover the metal wiring 130 and the through via contact 158 disposed at the top of the metal wiring structure 140, and the mask pattern The upper etch stop layer 146, the polishing stop layer 144, and the first upper capping layer 142 are sequentially removed using as an etch mask. Therefore, as the upper etch stop layer 146 is provided, a first upper capping layer covers the metal interconnection 130 and the through via contact 158 disposed on the uppermost part of the metal interconnection structure 140 during the etching process. (142) and the polishing prevention film 144 can be prevented from being etched.

If the upper etch stop layer 146 is formed thinner than 100 Å, it is difficult to serve as an etch stop layer due to consumption during the etching process, and if the upper etch stop layer 146 is formed thicker than 800 Å, parasitic capacitance may increase. Accordingly, in an exemplary embodiment, the upper etch stop layer 146 may be formed to have a thickness of 100Å to 300Å.

Referring to FIG. 8, an upper intermetallic insulating layer 160 is formed on the upper etch stop layer 146. The upper intermetallic insulating film 160 may include a low-k or ultra low-k dielectric that has a lower dielectric constant than silicon oxide (SiO2).

An upper metal interconnection 162 is formed in the upper intermetallic insulating layer 160, which is electrically connected to the metal interconnection 130 and the through via contact 158 disposed at the top of the metal interconnection structure 140, respectively.

Specifically, an upper mask pattern (not shown) is formed on the upper intermetallic insulating layer 160, and this is used as an etch mask to form the upper intermetallic insulating layer 160, the upper etch stop layer 146, and the polishing stop layer. 144 and the first upper capping film 142 are etched to form openings including a trench and an upper via hole for forming the upper metal wiring. The metal wiring 130 or the through via contact 158 disposed at the top of the metal wiring structure 140 may be exposed on the bottom of the openings.

An upper metal wire 162 is formed inside the opening.

To form the upper metal pattern 162, a third barrier metal film is conformally formed on the inner surface of the opening and the upper intermetallic insulating film. A third metal film is formed on the third barrier metal film to completely fill the opening. The third barrier metal film may include, for example, titanium, titanium nitride, tantalum, or tantalum nitride. The third metal film may be formed of copper, and the copper may be formed through a plating process.

Afterwards, the upper portions of the third metal film and the third barrier metal film are removed through a planarization process to expose the upper intermetallic insulating film 160. The planarization process may include a chemical mechanical polishing process. Accordingly, the upper metal wiring 162 including the third barrier metal pattern 164 and the third metal pattern 166 can be formed inside the opening.

The upper surfaces of the upper intermetallic insulating film 160 and the upper metal pattern 162 are flat, and the upper surfaces of the upper intermetallic insulating film 160 and the upper metal pattern 162 may be located on the same plane.

The upper metal wire 162 includes a first upper metal wire 162a in contact with the metal wires 130 disposed at the top of the metal wire structure 140 and a second upper metal wire 162a in contact with the through via contact 158. It may include a metal wiring 162b.

The first upper metal interconnection 162a penetrates the upper intermetallic insulating layer 160, the upper etch stop layer 146, the polishing stop layer 144, and the first upper capping layer 142 to form the metal interconnection structure ( It may be in contact with the metal wiring 130 disposed at the top of 140). The second upper metal wire 162b may penetrate the upper intermetallic insulating layer 160 and the upper etch stop layer 146 and contact the through via contact 158.

Accordingly, the vertical levels of the lower surfaces of the first upper metal wire 162a and the second upper metal wire 162b may be different from each other. The lower surface of the first upper metal wire 162a may be located lower than the lower surface of the second upper metal wire 162b. Additionally, the vertical heights of the first upper metal wire 162a and the second upper metal wire 162b may be different from each other. The vertical height of the first upper metal wire 162a may be higher than the vertical height of the second upper metal wire 162b.

Referring to FIG. 9, a second upper capping layer 170 is formed on the upper metal wiring 162 and the upper intermetallic insulating layer 160.

The second upper capping film 170 may be provided to suppress diffusion of metal components constituting the upper metal wiring 162. The second upper capping layer 170 may include an insulating material. The second upper capping film 170 may include, for example, SiCN.

Referring to FIG. 10, a protective film 172 and a carrier 180 are formed on the second upper capping film 170. In order to expose the bottom of the second metal pattern 156a of the through via contact 158, a back grinding process is performed on the bottom of the substrate 100. In the process, the lower surfaces of the via insulation film pattern 152a and the third barrier metal pattern 164 are removed, so that the via insulation film pattern 152a and the third barrier metal pattern 164 are formed in the through via hole 150. It may have a cylindrical shape surrounding the side walls.

Accordingly, the thickness of the substrate 100 may become thinner. Additionally, the bottom of the substrate 100 may be recessed so that the lower portion of the through via contact 158 partially protrudes.

A lower insulating film 190 may be formed on the bottom of the substrate 100. The lower insulating layer 190 may be planarized to expose the bottom surface of the through via contact 158. Additionally, a lower terminal 192 electrically connected to the through via contact 158 is formed on the bottom of the lower insulating film 190 and the through via contact 158.

According to the above process, the first upper capping film 142 covering the metal wiring structure 140 is provided, thereby suppressing diffusion of the metal material included in the metal wiring structure 140. Since the polishing stop layer 144 is provided on the first upper capping layer 142, the through via contact 158 can be formed by polishing to an accurate position. In addition, the upper etch stop layer 146 is formed to cover the polishing stop layer 144 and the through via contact 158, so that the polishing stop layer 144 below the upper etch stop layer 146 and the first Removal of the upper capping film 142 can be prevented.

The semiconductor device manufactured through the above-described processes may have the following structural characteristics.

11 is an enlarged cross-sectional view of the upper part of a through-via contact of a semiconductor device according to an exemplary embodiment. Hereinafter, the structural features of the semiconductor device will be described with reference to FIGS. 10 and 11, and content already described in the description of the manufacturing method will be briefly described or omitted.

Referring to FIGS. 10 and 11 , a circuit pattern 104 is provided on the substrate 100. First and second interlayer insulating films 110 and 112 are provided covering the circuit pattern 104, and a lower wiring including a contact plug and a conductive line is provided within the first and second interlayer insulating films 110 and 112. 114) is provided.

A metal interconnection structure 140 including intermetallic insulating films 120, metal interconnections 130 provided in the intermetallic insulating film, and lower capping films 122 is provided on the second interlayer insulating film 112. .

The metal wiring 130 may be electrically connected to the circuit pattern 104 and may be stacked in multiple layers. The metal wiring 130 may include a first barrier metal pattern 132 and a first metal pattern 134. The lower capping film 122 may be disposed between the intermetallic insulating films 120 of each layer.

A first upper capping film 142 is provided on the metal wiring structure 140 to cover the metal wiring structure 140. A polishing-stop film 144 is provided on the first upper capping film 142.

The first upper capping film 142 may include, for example, SiCN. In an exemplary embodiment, the first upper capping film may have a thickness of 100Å to 300Å.

The polishing-stop film 144 may include an insulating material different from that of the first upper capping film 142. The polishing prevention film 144 may include SiN, for example.

A through via hole 150 penetrating the polishing stop film 144, the first upper capping film 142, the metal wiring structure 140, the first and second interlayer insulating films 110 and 112, and the substrate 100 is provided. It can be provided.

A through via contact 158 including a via insulating film pattern 152a, a second barrier metal pattern 154a, and a second metal pattern 156a may be provided inside the through via hole 150. The through via contact 158 may extend downward in a vertical direction from the upper surface of the polishing stop film.

The via insulating film pattern 152a and the second barrier metal pattern 154a may be formed to surround the sidewall of the through via hole 150. The second metal pattern 156a may fill the inside of the through-via hole 150 while contacting the second barrier metal pattern 154a. Bottom surfaces of the via insulation film pattern 152a, the second barrier metal pattern 154a, and the second metal pattern 156a may be exposed by the bottom surface of the substrate 100.

The top surface of the through via contact 158 may be located on the same plane as the top surface of the polishing stop film 144. The top surface of the through via contact 158 and the top surface of the polishing stop film 144 may be flat. Accordingly, the top surface of the metal wiring structure 140 may be lower than the top surface of the through via contact 158. That is, the upper surface of the metal wiring 130 located at the uppermost part of the metal wiring structure 140 is more exposed to the first upper capping film 142 and the polishing stop film 144 than the upper surface of the through via contact 158. It can be positioned as low as the sum of its thickness.

An upper etch stop layer 146 may be provided on the upper surface of the through via contact 158 and the polishing stop layer 144. The upper etch stop layer 146 may include silicon oxide. The upper etch stop layer 146 may have a thickness of 100Å to 300Å.

In an exemplary embodiment, the first upper capping layer 142, the polishing stop layer 144, and the upper etch stop layer 146 may include different insulating materials.

An upper intermetallic insulating layer 160 may be provided on the upper etch stop layer 146. An upper metal interconnection 162 electrically connected to the metal interconnections 130 and the through via contact 158 may be provided within the upper intermetallic insulating layer 160 . The upper metal pattern 162 may include a third barrier metal pattern 164 and a third metal pattern 166. The upper surfaces of the upper intermetallic insulating film 160 and the upper metal wiring 162 are flat, and the upper surfaces of the upper intermetallic insulating film 160 and the upper metal wiring 162 may be located on the same plane.

The upper metal wire 162 includes a first upper metal wire 162a electrically connected to the metal wires 130 located below it, and a second upper metal wire electrically connected to the through via contact 158. (162b).

The first upper metal interconnection 162a penetrates the upper intermetallic insulating layer 160, the upper etch stop layer 146, the polishing stop layer 144, and the first upper capping layer 142 to form a metal interconnection structure 140. ) may be in contact with the metal wiring 130 disposed at the top. The second upper metal wire 162b may penetrate the upper intermetallic insulating layer 160 and the upper etch stop layer 146 and contact the through via contact 158.

Accordingly, the vertical levels of the lower surfaces of the first upper metal pattern 162a and the second upper metal pattern 162b may be different from each other. The lower surface of the first upper metal pattern 162a may be located lower than the lower surface of the second upper metal pattern 162b. Additionally, the vertical heights of the first upper metal pattern 162a and the second upper metal pattern 162b may be different from each other. The vertical height of the first upper metal pattern 162a may be higher than the vertical height of the second upper metal pattern 162b.

A second upper capping layer 170 is provided on the upper metal wiring 162 and the upper intermetallic insulating layer 160. The second upper capping film 170 may include SiCN, for example.

A lower insulating film 190 is provided on the bottom of the substrate 100, and a via insulating film pattern 152a, a second barrier metal pattern 154a, and a second barrier metal pattern 154a of the through via contact 158 are formed between the lower insulating film 190. 2 The bottom of the metal pattern 156a may be exposed. A lower terminal 192 electrically connected to the through via contact 158 may be provided on the bottom of the lower insulating film 190 and the through via contact 158.

Although the present invention has been described above with reference to embodiments, those skilled in the art can make various modifications and changes to the present invention without departing from the spirit and scope of the present invention as set forth in the claims below. You will understand that it is possible.

100: substrate 104: circuit pattern
110, 112: first and second interlayer insulating films
114: lower wiring 120: intermetallic insulating film
130: metal wiring 122: lower capping film
132: first barrier metal pattern 134: first metal pattern
140: metal wiring structure 142: first upper capping film
144: polishing film 150: through via hole
152a: Via insulation film pattern 154a: Second barrier metal pattern
156a: Second metal pattern 158: Through via contact
146: upper etch stop layer 160: upper intermetallic insulating layer
164: Third barrier metal pattern 166: Third metal pattern
162: upper metal wiring 170: second upper capping film

Claims (10)

Board;
a metal interconnection structure provided on the substrate and including intermetallic insulating films and metal interconnections;
a first upper capping film covering the upper surface of the metal wiring structure;
a polishing-stop film provided on the first upper capping film;
a through via contact extending vertically from the polishing stop layer and penetrating the polishing stop layer, the first upper capping layer, the metal interconnection structure, and the substrate;
an upper etch stop layer provided on the polishing stop layer and the through via contact;
An upper metal interconnection structure provided on the upper etch stop layer and including an upper intermetallic insulating layer and an upper metal interconnection,
The upper metal interconnection includes a first upper metal interconnection electrically connected to the metal interconnection and a second upper metal interconnection electrically connected to the through via contact. The semiconductor device of claim 1, wherein a top surface of the through via contact is located on the same plane as a top surface of the polishing stop film. The semiconductor device of claim 1, wherein a top surface of the metal interconnection structure is lower than a top surface of the through via contact. The semiconductor device of claim 1, wherein the vertical height of the first upper metal wiring is higher than the vertical height of the second upper metal wiring. The semiconductor device of claim 1, wherein the first upper capping layer, the polishing stop layer, and the upper etch stop layer include different insulating materials. The semiconductor device of claim 1, wherein the first upper capping layer includes SiCN. The semiconductor device of claim 1, wherein the first upper capping layer has a thickness of 100Å to 300Å. The semiconductor device of claim 1, wherein the polishing-stop film includes SiN. The semiconductor device of claim 1, wherein the upper etch stop layer includes silicon oxide. The semiconductor device of claim 1, wherein the through via contact includes a via insulating layer pattern, a barrier metal pattern, and a metal pattern, and bottom surfaces of the via insulating layer pattern, barrier metal pattern, and metal pattern are exposed by the bottom of the substrate.