KR20230135748A - Data storage device for determining a write address using a neural network - Google Patents

Abstract

A data storage device according to the present technology includes one or more non-volatile memory devices including a plurality of unit storage spaces; It includes a recommendation circuit that recommends one unit storage space among a plurality of unit storage spaces to process a write request, and the recommendation circuit includes request information, a target address corresponding to the write request, and the address of data stored in the plurality of unit storage spaces. The feature data generated from this is applied to a neural network circuit to recommend one unit storage space.

Description

A data storage device that determines the write address using a neural network {DATA STORAGE DEVICE FOR DETERMINING A WRITE ADDRESS USING A NEURAL NETWORK}

This technology relates to a data storage device that determines the write address using a neural network.

Solid state drives (SSDs) store data in semiconductor memories such as NAND flash memory.

NAND flash memory has an input/output bandwidth of up to 320MB/s for reading and 42MB/s for writing on a single plane.

In comparison, the NVMe interface used in SSDs has a bandwidth of up to 7.9 GB/s.

In order to overcome the speed difference between the interface device and the NAND flash memory device, a DRAM buffer is added or a technology that processes data in parallel by dividing it into different channels/chips/die/planes is adopted.

For example, during a write operation, write delay can be hidden by storing data in a DRAM buffer and flushing the data in the buffer to NAND flash memory.

However, during a read operation, the read delay cannot be hidden because the data output from the NAND flash memory must wait until it is output externally through the DRAM buffer.

Read requests provided to data storage devices such as SSDs generally have random address patterns, so it is difficult to improve read performance by prefetching data, so improving performance through parallel read operations is virtually the only way.

Conventional SSDs can perform parallel processing operations such as channel striping, which distributes input/output requests to multiple channels, and way pipelining, which processes input requests in another package while processing input/output requests in one package.

Additionally, one NAND flash memory package includes multiple dies that can operate independently, and each die includes multiple planes. Dai is also referred to as Wei.

Accordingly, parallel processing operations are performed through die interleaving, which alternately sends requests to multiple dies, and multi-plane operation, which operates two or more planes simultaneously.

Conventionally, the write address can be determined through parallel processing operations at the channel, package, die, and plane levels, but this has the problem of not taking full advantage of the parallelism of the data storage device because it fails to consider future read request patterns.

As a result, when multiple read requests for data stored in the same channel or the same die are provided, parallel operations are impossible, making it difficult to improve read performance.

KR 10-2021-0019576 A US 2020/0110536 A1

N. Elyasi, C. Choi, A. Sivasubramaniam, J. Yang and V. Balakrishnan, "Trimming the Tail for Deterministic Read Performance in SSDs," 2019 IEEE International Symposium on Workload Characterization (IISWC), 2019, pp. 49-58, doi: 10.1109/IISWC47752.2019.9042073. N. Elyasi, M. Arjomand, A. Sivasubramaniam, M. T. Kandemir and C. R. Das, "Content Popularity-Based Selective Replication for Read Redirection in SSDs," 2018 IEEE 26th International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems ( MASCOTS), 2018, pp. 1-15, doi: 10.1109/MASCOTS.2018.00009. J. Liang, Y. Xu, D. Sun and S. Wu, "Improving Read Performance of SSDs via Balanced Redirected Read," 2016 IEEE International Conference on Networking, Architecture and Storage (NAS), 2016, pp. 1-10, doi: 10.1109/NAS.2016.7549406. U. Gupta et al., "The architectural implications of facebook's dnn-based personalized recommendation," in 2020 IEEE International Symposium on High Performance Computer Architecture (HPCA), 2020: IEEE, pp. 488-501. https://www.tensorflow.org/text/guide/word_embeddings

This technology relates to a data storage device that uses neural network technology to determine a write address to enable parallel processing operations when processing read requests in the future.

A data storage device according to an embodiment of the present invention includes one or more non-volatile memory devices including a plurality of unit storage spaces; It includes a recommendation circuit that recommends one unit storage space among a plurality of unit storage spaces to process a write request, and the recommendation circuit includes request information, a target address corresponding to the write request, and the address of data stored in the plurality of unit storage spaces. The feature data generated from this is applied to a neural network circuit to recommend one unit storage space.

This technology uses a neural network to determine the write address by considering future read patterns, thereby improving read performance by maximizing the parallelism inside the data storage device.

1 is a block diagram showing a data storage device according to an embodiment of the present invention.
Figure 2 is a block diagram showing a recommendation circuit according to an embodiment of the present invention.
Figure 3 is a diagram showing an embedding table.
4 is an explanatory diagram showing a comparison vector update operation.
Figure 5 is an explanatory diagram showing a method of generating learning data for learning operations.
Figure 6 is a graph showing the effect of the present invention.

Hereinafter, embodiments of the present invention will be disclosed with reference to the attached drawings.

Figure 1 is a block diagram showing a data storage device 1000 according to an embodiment of the present invention.

Hereinafter, the present invention will be described using a solid state drive (SSD) including NAND flash memory as an example of the data storage device 1000.

Accordingly, the data storage device 1000 may be referred to as an SSD or SSD device.

The data storage device 1000 includes a host interface 10, FTL 20, DRAM 30, transaction queue 40, channel 50, and flash memory 60.

The data storage device 1000 further includes a recommendation circuit 100.

The host interface 10 receives a request from the host according to the NVMe standard, for example, and transmits the request processing result to the host. The interface technology supporting the NVMe standard itself is a conventional technology, and detailed disclosure is omitted.

The host interface 10 generates a page-by-page write request. If the write data exceeds one page, multiple page-by-page write requests may be generated and individually provided to the FTL 20 and the recommendation circuit 100.

At this time, multiple page-level write requests may be provided sequentially. Accordingly, the FTL 20 and the recommendation circuit 100 can operate in units of one logical page.

FTL (Flash Translation Layer, 20) is a configuration commonly used in SSDs and controls operations such as address mapping, garbage collection, and wear leveling, and detailed description of this will be omitted.

In this embodiment, the FTL 20 further includes a page allocation circuit 21.

The page allocation circuit 21 allocates a page included in the recommendation address provided by the recommendation circuit 100 in response to a write request.

In this embodiment, the recommendation address provided by the recommendation circuit 100 corresponds to the die address. Hereinafter, the die address may be referred to as a die number or die ID. In flash memory, a die can be referred to as a way, and the die address can therefore be referred to as a way address.

That is, the page allocation circuit 21 provides the physical page included in the die as the actual write address. Accordingly, the allocated page may be referred to as a write address, and the page allocation circuit 21 may be referred to as the write address allocation circuit 21.

The recommended address provided in the present invention is not limited to the die address, and in other embodiments, addresses of other units capable of performing parallel processing may be provided as recommended addresses.

For example, when considering securing channel-level parallelism, a channel address can be provided as a recommended address, and the page allocation circuit 21 allocates a page address within the recommended channel.

In another example, parallelism can be considered in the plane unit, which is a sub-unit of the die. In this case, a plane address can be provided as a recommended address, and the page allocation circuit 21 can allocate a page address within the recommended plane. .

In addition, various design changes are possible, and these can be easily recognized by those skilled in the art from the disclosure of the present invention.

The DRAM 30 is connected between the host and the transaction queue 40 to store data for read or write requests.

The host interface 10 further includes a DMA control circuit 11, through which data stored in the host can be read into the DRAM 50 or data stored in the DRAM 50 can be provided to the host using DMA technology.

Since the technology for transmitting and receiving data between a host and an SSD using DMA technology itself is a conventional technology, detailed disclosure thereof will be omitted.

The FTL 20 can perform an address mapping operation according to the allocated page.

The transaction queue 40 performs an operation of queuing commands and data in response to read and write requests for the flash memory 50 device.

Since the operation of the transaction queue 40 itself is a conventional structure, detailed description is omitted.

The flash memory 60 is connected to the channel 50 to transmit and receive commands and data.

Although four channels 50 are shown in FIG. 1, the number of channels 50 may vary depending on the embodiment.

In Figure 1, one flash memory 60 is connected to one channel 50, but depending on the embodiment, multiple flash memories 60 may be connected to one channel 50.

Each flash memory 60 includes therein a plurality of dies 70 that can operate in parallel.

Although FIG. 1 shows two dies 70 included in one flash memory 60, a larger number of dies 70 may be included in one flash memory 60 depending on the embodiment.

When the recommendation circuit 100 receives a page-by-page write request through the host interface 10, it determines a corresponding recommendation address and provides it to the page allocation circuit 21. As described above, in this embodiment, the recommended address corresponds to the die address.

In this embodiment, the recommendation circuit 100 uses neural network technology to determine recommended addresses.

The recommendation circuit 100 is implemented with hardware, software, or a combination of hardware and software, and can perform a learning operation for a neural network and perform an inference operation using the learned neural network.

The recommendation circuit 100 determines a recommendation address to maximize internal parallelism in the process of processing read requests to be performed in the future.

In this technology, the target page information to be assigned and the page information stored in each die are used to predict the probability that a request will be given to each die at a similar time as the target page, and the target page is assigned to the die with the lowest probability.

The recommendation circuit 100 uses neural network technology to recommend the die address with the lowest probability.

In this embodiment, recommender system technology, a type of neural network technology, is applied. The conventional recommendation system compares an embedding vector representing user information with an embedding vector representing item information and outputs the probability that the user will click on the item.

The configuration and operation of the conventional recommendation system have been described in detail in Non-Patent Document 4, so detailed description is omitted.

Figure 2 is a block diagram showing the recommendation circuit 100.

The recommendation circuit 100 includes an embedding table 110, a comparison vector generation circuit 120, a concatenation circuit 130, a multilayer neural network circuit 140, and a decision circuit 150.

The decision circuit 150 determines a recommended address by referring to the score for each die output from the multilayer neural network circuit 140.

For example, the score for each die may correspond to the probability that a request will be made to that die at a similar time as the target page. In this case, the address of the die with the lowest score for each die can be determined as the recommended address.

The multilayer neural network circuit 140 receives feature vectors and outputs scores for each die. The multi-layer neural network circuit 140 may have the form of a fully connected neural network.

The concatenation circuit 130 concatenates the request vector, target vector, and comparison vector to generate one feature vector.

The request vector provided to the concatenation circuit 130 includes as elements whether the request is sequentially accessed or randomly accessed, and the size of the request.

Additionally, in order to avoid recommending the same Dai for consecutive requests, the Dai address recommended for the previous request is further included.

The embedding table 110 is a table structure with multiple rows, and each row can be accessed using a logical page address, and the rows of the table store embedding vectors corresponding to logical page addresses.

Figure 3 shows the structure of the embedding table 110. For example, the embedding vector corresponding to the logical page address (LPN) p is {e0, e1, ..., e8, e9}.

Since the embedding technology that converts input data into vector form is well known, as in Non-Patent Document 5, a detailed description of the embedding technology itself will be omitted.

The embedding table 110 is determined through a neural network learning operation, which is described in detail below.

In this embodiment, the target page information corresponds to the logical page address (LPN) requested to be written.

The comparison vector generation circuit 120 generates a plurality of comparison vectors corresponding to each of the plurality of dies.

In this embodiment, since there are multiple dies, multiple comparison vectors are also generated correspondingly.

For example, the comparison vector generation circuit 120 receives a plurality of embedding vectors by applying each logical page stored in die No. 1 to the embedding table 110 to generate a comparison vector corresponding to die No. 1, and generates a comparison vector corresponding to die No. 1. By adding the embedding vectors for each element, a comparison vector corresponding to die number 1 can be generated.

In this way, multiple comparison vectors corresponding to multiple dies are generated.

The target vector may be generated in response to the logical address requested to be written each time a page-by-page write request is input.

In contrast, the comparison vector generation circuit 120 may calculate the comparison vector in advance before a write request is performed.

The comparison vector generation circuit 120 may additionally perform a comparison vector update operation after a write request is performed for the die.

Figure 4 is a diagram explaining an update operation of a comparison vector.

Figure 4 shows a case where the logical page (p) is invalidated on die A and the logical page (p) is written on die B.

Hereinafter, the embedding vector corresponding to the logical page (p) is expressed as Vp.

The value obtained by subtracting the embedding vector (Vp) from the existing comparison vector (VA) corresponding to die A is set as the new comparison vector (VA').

Additionally, the value obtained by adding the embedding vector (Vp) to the existing comparison vector (VB) corresponding to die B is set as the new comparison vector (VB').

Since die C is not affected by the above write operation, the comparison vector (VC') after the write operation is the same as the existing comparison vector (VC).

In a burst operation in which input/output requests are given at short time intervals, the input/output performance of the SSD may be degraded due to the inference operation of the recommender circuit 100.

The target vector must be newly created each time a request is entered.

In comparison, the comparison vector does not change unless the logical page stored in each die changes, so performance degradation can be prevented by pre-calculating the comparison vector during times when host requests are not served.

When a request such as write or erase is made to a die, a comparison vector must be newly calculated for the die. Even in this case, the computation time can be reduced by adding or subtracting the embedding vector corresponding to the affected page from the existing comparison vector, as shown in Figure 4.

Additionally, this technology can prevent performance degradation by hiding the inference operation in the input/output operation process of the SSD.

When the host sends an input/output request to the SSD 1000, the host interface 10 interprets the request transmitted by the NVMe protocol to determine the type of request, logical address, data length, and host memory address.

Afterwards, the DMA control circuit 11 reads data from the host using the host memory address and stores it in the DRAM 30, or stores the data in the DRAM 30 in the host.

In this embodiment, the DMA control circuit 11 performs the operation of the recommendation circuit 100 during the DMA operation of storing data in the DRAM 30 to hide the time taken for the operation of the recommendation circuit 100, thereby improving the performance of the SSD. prevent degradation.

The embedding table 110 and the multi-layer neural network circuit 140 of the recommendation circuit 100 each include variables whose values are adjusted through learning.

In this embodiment, the learning operation is performed simultaneously on the embedding table 110 and the multilayer neural network circuit 140, but in other embodiments, the learning operation may be performed sequentially.

In this embodiment, a learning operation for the recommendation circuit 100 is performed by applying a supervised learning method.

In supervised learning, the coefficients are adjusted using the output value corresponding to the input value and the true value corresponding to the input value. Since this supervised learning technology itself is a conventional technology, detailed disclosure is omitted.

For supervised learning, a data set containing input values input to the neural network and corresponding true values must be prepared.

In this embodiment, a data set can be prepared using trace data provided to the SSD 1000 for a certain period of time.

Figure 5(A) shows an example of trace data.

The trace data shown includes a write request (W1) followed by five read requests (R1 to R5). Figure 5 assumes that the fifth read request (R5) and the fifth write request (W1) are requests for the same logical address.

When creating a data set from trace data, the die address of the true value to be assigned to the write request must be determined.

Figure 5(B) explains a method for determining the true die address corresponding to a write request.

First, referring to the trace data, the die addresses corresponding to the four read requests from 1 to 4 are displayed.

In Figure 5(B), read request number 1 (R1) is assigned to die number 1 of channel B, read request number 2 (R2) is assigned to die number 2 of channel B, and read request number 3 (R3) is assigned to die number 2 of channel B. Assume that it is assigned to die number 2 of channel A, and read request number 4 (R4) is assigned to die number 1 of channel B.

In Figure 5(B), "bus" represents the time that data output as a result of a read operation occupies the channel bus.

Referring to Figure 5(B), considering the time at which read request No. 5 (R5) is provided, the processing time may overlap with read requests No. 2, 3, and 4, so it does not overlap with them to improve read performance. It is advisable to select a die that does not

Accordingly, in order to improve parallelism, it is desirable that the 5th read operation is performed on die 1 of channel A.

Accordingly, the true value of the die address corresponding to the write request (W1) is determined to be die number 1 of channel A.

In this way, learning data can be prepared from trace data.

In FIG. 2 , the recommendation circuit 100 may further include a learning control circuit 160.

The learning control circuit 160 may control the supervised learning process using learning data pre-stored in a designated address area of the flash memory 50.

The learning control circuit 160 can store trace data for a certain period of time in the DRAM 30 or another designated address area of the flash memory 50 and generates learning data from the trace data in the designated address area of the flash memory 50. You can save or update learning data.

Accordingly, the supervised learning operation may be performed only during the initialization process of the data storage device 1000, may be performed at predetermined time intervals during use of the data storage device 1000, or may be performed during idle time of the data storage device 1000. .

Figure 6 is a graph showing the effect of the present technology.

The graph in FIG. 6 shows the ratio of read latency when a write operation is performed according to the present technology compared to the read latency when a write operation is performed according to the conventional technology.

In Figure 6, the horizontal axis represents the type of workload and the vertical axis represents the ratio of read latency compared to the prior art.

As shown, when this technology was applied to all workloads, read latency was reduced, with an average reduction rate of 25.4 percent.

In this way, it can be seen that when this technology is applied, the read performance of the data storage device 1000 is improved.

The scope of rights of the present invention is not limited to the above disclosure. The scope of rights of the present invention should be interpreted based on the scope literally stated in the claims and the scope of equivalents thereof.

1000: Data storage device (SSD device) 10: Host interface
11: DMA control circuit 20: FTL
21: Page allocation circuit 30: DRAM
40: transaction queue 50: channel
60: Flash memory 70: Die
100: Recommended circuit
110: Embedding table 120: Comparison vector generation circuit
130: concatenated circuit 140: multilayer neural network circuit
150: decision circuit 160: learning control circuit

Claims (13)

One or more non-volatile memory devices including a plurality of unit storage spaces;
A recommendation circuit that recommends one unit storage space among the plurality of unit storage spaces to process a write request,
The recommendation circuit is a data storage device that recommends one unit storage space by applying feature data generated from request information, a target address corresponding to a write request, and addresses of data stored in a plurality of unit storage spaces to a neural network circuit. The data storage device of claim 1, further comprising a write address allocation circuit that allocates a write address within one unit storage space recommended by the recommendation circuit. The method of claim 1, wherein the recommendation circuit
an embedding table that stores an embedding vector corresponding to a data address and generates a target vector from the target address;
a comparison vector generation circuit that generates a plurality of comparison vectors using the plurality of unit storage space information and the embedding table information;
a multi-layer neural network circuit that generates scores for a plurality of unit storage spaces using a request vector corresponding to the request information, the target vector, and the feature data corresponding to the plurality of comparison vectors;
A decision circuit for determining the unit storage space by referring to the score.
A data storage device containing a. The data storage device of claim 3, further comprising a concatenation circuit for generating the feature data by concatenating the request vector, the target vector, and the plurality of comparison vectors. The method of claim 3, wherein the target address is a logical address, and the comparison vector generation circuit adds a plurality of embedding vectors corresponding to a plurality of logical addresses corresponding to a plurality of data stored in any one unit storage space to A data storage device that generates comparison vectors corresponding to unit storage space. The method of claim 5, wherein when one logical address in a unit storage space is invalidated, the comparison vector generation circuit updates the comparison vector by deleting an embedding vector corresponding to the invalidated logical address from the existing comparison vector, A data storage device that updates a comparison vector by adding an embedding vector corresponding to the added logical address to the existing comparison vector when a logical address is added to a unit storage space. The method of claim 3, wherein the recommendation circuit further includes a learning control circuit,
The one or more non-volatile memory devices store learning data in a pre-stored address,
The learning control circuit is a data storage device that controls learning operations for the embedding table and the multilayer neural network circuit using the learning data. The method of claim 7, wherein the learning data is generated from trace data, which is a set of requests provided to the data storage device,
The learning data includes a pair of write request information and a true value of a unit storage space to be recommended correspondingly,
The true value is determined by considering parallel processing of a read request that has the same logical address as any one of a plurality of read requests provided after any one write request in the trace data. The method of claim 2, wherein the non-volatile memory device is a flash memory device,
The unit storage space corresponds to a die of a flash memory device,
A data storage device wherein the write address is a page address inside the recommended die. The method according to claim 9, further comprising: a host interface for receiving and decoding a request provided from a host;
an FTL that performs address mapping with reference to the write address determined by the write address allocation circuit;
Volatile memory device that stores data to be exchanged with the host
A data storage device further comprising: The data storage device of claim 10, wherein the host interface generates a write request in units of multiple pages according to the length of data requested to be written. The method of claim 10, wherein the information decoded from the host interface includes a memory address of the host,
The host interface further includes a DMA control circuit that transmits and receives data between a memory address of the host and the volatile memory device. The data storage device of claim 12, wherein when a write request is received, the recommendation circuit determines a unit storage space to perform a write operation while the DMA control circuit stores host data in the volatile memory device.

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