KR20230127832A - A power management integrated circuit - Google Patents

Abstract

A power management integrated circuit is provided. A power management integrated circuit of the present invention includes a first regulator providing a first output signal to an intellectual property (IP), a second regulator providing a second output signal to the IP module, and a third output signal to the IP module. A third regulator that tracks the first to third output signals and outputs one of the output signals as a selection signal, generates a reference voltage by adding an offset voltage to the selection signal, and generates a reference voltage and a sub-regulator generating an input voltage corresponding to and supplying the generated input voltage to the plurality of regulators.

Description

Power management integrated circuit {A POWER MANAGEMENT INTEGRATED CIRCUIT}

The present invention relates to a power management integrated circuit.

The electronic device may include a power management integrated circuit (hereinafter referred to as "PMIC"). The PMIC can operate the electronic device by supplying power to each of the components constituting the electronic device. The PMIC can supply the power necessary for the processor to operate. A processor may have a plurality of blocks to perform designated functions. The PMIC may supply power to each of a plurality of blocks constituting a processor of an electronic device. The PMIC may be electrically connected to the processor through an interface to supply a plurality of clock signals having designated voltages to a plurality of blocks. Each of the plurality of clock signals supplied to each of the plurality of blocks may have a designated range.

The PMIC includes a plurality of low dropout regulators (hereinafter referred to as "LDOs") connected to a plurality of switching converters and providing an output voltage of a low noise level to each of the plurality of blocks, each LDO Do not use the battery voltage or the voltage directly input to the PMIC. A large difference between the input voltage and output voltage of the PMIC results in large power loss, so the low-dropout regulator uses the output voltage of a high-efficiency sub-regulator as the input power supply. Accordingly, power loss due to the LDO can be minimized.

An object to be solved by the present invention is to provide a power management integrated circuit with improved operating performance.

An object to be solved by the present invention is to provide a power management integrated circuit with good performance efficiency by minimizing power loss by reducing the difference between input and output of a low voltage drop regulator.

The problems to be solved by the present invention are not limited to the above-mentioned problems, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

In order to solve the above problems, a power management integrated circuit according to some embodiments of the present invention includes a first regulator providing a first output signal to an intellectual property (IP), and a second regulator providing a second output signal to the IP. , a third regulator providing a third output signal to the IP, a power tracker tracking the first to third output signals and outputting one output signal as a selection signal, and adding an offset voltage to the selection signal and a sub-regulator that generates a reference voltage, generates an input voltage corresponding to the reference voltage, and provides the generated input voltage to the plurality of regulators.

A power management integrated circuit according to some embodiments of the present invention for solving the above problems is a first loop circuit outputting a first output signal, a second loop circuit outputting a second output signal, and outputting a third output signal. A third loop circuit that tracks the first to third output signals, and generates a reference voltage by adding an offset voltage to the power tracker and outputting any one output signal as a selection signal, and the reference voltage And a charging circuit that generates an input voltage corresponding to and provides it to the first to third loop circuits.

In order to solve the above problems, a power management integrated circuit according to some embodiments of the present invention includes a first regulator providing a first output voltage and a first output current, and a second regulator providing a second output voltage and a second output current. A third regulator providing a third output voltage and a first output current, tracking the first to third output voltages and the first to third output currents, and outputting any one output signal through a common output node. and a power tracker outputting a selection signal, a sub-regulator generating a reference voltage by adding an offset voltage to the selection signal, generating an input voltage corresponding to the reference voltage, and supplying the generated input voltage to the first to third regulators.

1 is a block diagram illustrating a power management integrated circuit according to some embodiments of the present invention.
FIG. 2 is a voltage graph for explaining the operation of the power management integrated circuit of FIG. 1 .
FIG. 3 is a voltage graph and a current graph for explaining the operation of the power management integrated circuit of FIG. 1 .
4 is a block diagram illustrating a power tracker according to some embodiments.
5 is a block diagram illustrating a power tracker according to some embodiments.
6 is a circuit diagram illustrating a power tracker according to some embodiments.
7 is a circuit diagram illustrating a power tracker according to some embodiments.
8 is a circuit diagram illustrating a power tracker according to some embodiments.
9 is a circuit diagram illustrating a power tracker according to some embodiments.
10 is a block diagram illustrating a power tracker according to some embodiments.
FIG. 11 is a voltage graph for explaining the operation of the power management integrated circuit of FIG. 10 .
12 is a block diagram illustrating a power tracker according to some embodiments.
13 is a circuit diagram illustrating a power tracker according to some embodiments.
14 is a block diagram illustrating a power tracker according to some embodiments.
15 is a circuit diagram illustrating a power tracker according to some embodiments.
16 is a block diagram illustrating a power tracker according to some embodiments.

Hereinafter, power management integrated circuits according to some embodiments of the present invention will be described with reference to FIGS. 1 to 16 .

1 is a block diagram illustrating a power management integrated circuit according to some embodiments of the present invention.

Referring to FIG. 1 , a power management integrated circuit 1 may include a digital logic 30 , low voltage drop regulators 21 , 22 , and 23 , a sub-regulator 10 , and a power tracker 100 .

The power management integrated circuit (1) converts the voltage supplied from the outside or the battery voltage to an internal voltage (eg, VL1 to VL3, IL1 to IL3) suitable for the internal component (eg, Intellectual Property; hereinafter IP module, 2) ) as output. In addition, the power management integrated circuit 1 may adjust the clock frequency or phase delay to correspond to the operation of the IP module and output the power according to various embodiments.

Although only one IP module is shown in the illustrated example, this is for convenience of explanation. According to various embodiments, the power management integrated circuit 1 is connected to a plurality of IP modules, and each IP module has its own low voltage drop regulator. (21,22,23) may be concatenated.

The digital logic 30 may output signals c1, c2, and c3 that control the operation of the low drop-out regulator (LDO) 21, 22, and 23. For example, the signals c1, c2, and c3 may adjust the level of the output voltage of the LDOs 21, 22, and 23 or control their activation or inactivation.

According to some embodiments, the digital logic 30 may receive a control command for output signals of the LDOs 21, 22, and 23 from the IP module. The digital logic 30 may output the control signals c1, c2, and c3 to the LDOs 21, 22, and 23 and output the control signal a to the sub-regulator 10 based on the control command. The control signal can control the operation timing of the output signals output from the LDOs 21, 22, and 23 and the sub-regulator 10.

The LDOs 21, 22, and 23 adjust the level conversion timing of the output signals VL and IL based on the control signals c1, c2, and c3, and the sub-regulator 10 controls the level conversion timing of the output signals VL and IL based on the control signals c1, c2, and c3. The level conversion timing of the input voltage VBK can be adjusted.

The sub-regulator 10 provides an input voltage VBK to each of the LDOs 21, 22, and 23. According to some embodiments, the sub-regulator 10 is a switching converter and may be any one of a buck converter circuit, a boost converter circuit, and a buck-boost converter circuit.

The LDOs 21, 22, and 23 generate output signals provided to the IP module based on the input voltage VBK of the sub-regulator 10. The output signal may be, for example, at least one of output voltages VL1 , VL2 , and VL3 or output currents IL1 , IL2 , and IL3 of the LDOs 21 , 22 , and 23 . The LDOs 21, 22, and 23 generate the internal supply voltage required by the IP module as the output signal. For convenience of explanation, in FIG. 1, three LDOs 21, 22, and 23 are described, but the scope of the present invention is not limited thereto and may be applied to three or more regulators.

The power tracker 100 may track the output signals of the LDOs 21, 22, and 23 to select one output signal and output it as a selection signal Vsel. The power tracker 100 may generate the reference voltage Vref by adding the offset voltage Vk to the selection signal Vsel.

For example, the power tracker 100 may operate as a voltage tracker when output signals of the LDOs 21, 22, and 23 are in the form of voltages (ie, output voltages). For example, the power tracker 100 may operate as a current tracker when the output signals of the LDOs 21, 22, and 23 are in the form of current (ie, output current). The operation will be described later with reference to FIGS. 2 and 3 .

FIG. 2 is a voltage graph for explaining the operation of the power management integrated circuit of FIG. 1 .

An operating state of the power management integrated circuit 1 may be defined according to a system operating scenario. For example, it can operate in a normal mode in which all LDOs 21, 22, and 23 are activated, and in a standby mode in which most of the LDOs are turned off for low-power operation. In the illustrated example, it is assumed that the magnitudes of the output voltage VL1 of the LDO 21, the output voltage VL2 of the LDO 22, and the output voltage VL3 of the LDO 23 are VL1>VL2>VL3.

In the first period (0 to t1), all LDOs are turned on, in the second period (t1 to t2), the LDO 21 is turned off, and in the third period (t2 to t3), the LDO 22 is turned off. . The power tracker 100 selects the smallest voltage among the output voltages as the selected voltage Vsel, and generates input voltages VBK of the LDOs 21, 22, and 23 based on the selected voltage Vsel. The power consumption of LDOs (21,22,23) is , where ΔV is the difference between the input voltage (VBK) and the output voltages (VL1 to VL3), and IL means the sum of the currents in turned-on LDOs.

If the input voltage (VBK) is constantly supplied without considering the variation of the output voltages (VL1 to VL3), the power loss is greater than that of the first section in which all the LDOs 21, 22, and 23 are turned on, only the LDO 23 is turned on. may appear larger in the third section. In order to reduce this power loss, when the input voltage (VBK) is adjusted in response to the output of the turned-on LDOs, that is, the difference between the input voltage and the output voltage of the turned-on LDOs. If it is controlled to maintain constant, power loss due to turn-on/turn-off of the LDOs can be prevented.

Therefore, the power management integrated circuit according to the embodiments of the present invention generates the input voltage VBK provided to the LDO according to the selection signal Vsel tracking the output signals of the LDO. That is, as the input voltage VBK is tracked and varied according to the selection signal Vsel, only a minimum amount of power may be lost.

3 is a block diagram illustrating a power tracker according to some embodiments.

Referring to FIG. 3 , according to some embodiments, a power tracker 100-1 includes a track and select unit 110, a voltage generator 120, and a summing node 130.

The track and select unit 110 tracks the output voltages (VL1, VL2, and VL3) of the plurality of LDOs 21, 22, and 23, and selects the output voltage of one of the turned-on LDOs to be used as a selection signal (Vsel). print out According to some embodiments, the selection signal Vsel may be a selected maximum value, a minimum value, or a middle value among the output voltages VL1 , VL2 , and VL3 of the turned-on LDO. Hereinafter, the embodiments described in this specification will be described as an example of outputting the output voltage having the maximum value among the output voltages VL1, VL2, and VL3 of the turned-on LDO as the selection signal Vsel. It will be said that the embodiments of the invention are not limited thereto.

The voltage generator 120 generates the offset voltage Vk according to the reference control signal Vcnt[k:1]. The reference control signal Vcnt[k:q] may adjust the level of the offset voltage Vk.

The summing node 130 generates a reference voltage Vref by summing the selection signal Vsel and the offset voltage Vk, and provides the reference voltage Vref to the sub-regulator 10 .

The sub-regulator 10 generates an input voltage VBK of the LDOs 21, 22, and 23 corresponding to the reference voltage Vref.

4 is a block diagram illustrating a power tracker according to some embodiments.

Referring to FIG. 4 , a power tracker 100-1 according to some embodiments may include a track and select unit 110.

The track and select unit 110 may continuously track the output signals VL1, VL2, and VL3 of the plurality of LDOs 21, 22, and 23 and detect one of them as the selection signal Vsel. The track and selection unit 110 may include a first tracker 111 , a second tracker 112 , a third tracker 113 , and a discharging unit 117 . The first tracker 111 is connected to the output terminal of the LDO 21 and can track the output signal VL1 of the LDO 21. The second tracker 112 may be connected to the output terminal of the LDO 22 and track the output signal VL2 of the LDO 22 . The third tracker 113 is connected to the output terminal of the LDO 23 and can track the output signal VL3 of the LDO 23. The output signals may be, for example, output voltages VL1, VL2, and VL3. In the illustrated embodiment, the case in which the output signals are the output voltages VL1, VL2, and VL3 is described as an example, but the output signal may be the output currents IL1, IL2, and IL3 according to various embodiments.

The first tracker 111, the second tracker 112, and the third tracker 113 may output the tracked signal to the common output node N1. For example, the first tracker 111 outputs the first output signal to the common output node N1, the second tracker 112 outputs the second output signal to the common output node N1, and the third tracker 112 outputs the second output signal to the common output node N1. 113 may output the third output signal to the common output node N1.

The discharging unit 117 is connected to the common output node N1 and can discharge current according to the voltage direction of the selection signal Vsel. The discharging unit 117 enables continuous tracking of the selection signal Vsel at the common output node N1. According to some embodiments, the discharging unit 117 may be implemented as a resistor or as a current source.

According to some embodiments, the power tracker 100-1 may generate a preset offset voltage and provide it to the summing node 130 (N2).

Alternatively, according to some embodiments, the power tracker 100-1 may further include a voltage generator 120 that generates an offset voltage whose level is adjusted by the reference control signal Vcnt[k:1]. The voltage generator 120 may include, for example, an impedance unit 121 and a current generator 122 . The impedance unit 121 may have a preset impedance according to some embodiments or may have a programmable impedance according to some embodiments. The current generator 122 may generate an offset current according to the reference control signal Vcnt[k:1], and the offset current may be reflected in the impedance unit 121 to generate an offset voltage Vk.

The selection signal Vsel is summed with the offset voltage Vk at the summing node N2 (130 in FIG. 3) and output as the reference voltage Vref.

5 is a circuit diagram illustrating a power tracker according to some embodiments.

4 and 5, the first tracker 111, the second tracker 112, and the third tracker 113 include amplifiers A1, A2, and A3, which are input by adjusting the gain of the amplifier. The selection signal Vsel may be output with a voltage higher or lower than the output signals VL1 , VL2 , and VL3 .

For example, the first tracker 111 may include an amplifier A1 and a transistor MN1. The amplifier (A1) receives the output voltage (VL1) of the LDO (21) and the voltage of the common output node (N1) as inputs, respectively, and outputs the output voltage (VL1) of the LDO (21) and the voltage of the common output node (N1). and may output a first comparison signal. The transistor MN1 is connected between the power supply terminal VDD and the common output node N1, and is gated with a first comparison signal to transmit a first candidate selection signal corresponding to the first comparison signal to the common output node N1. can be output through

For example, the second tracker 112 may include an amplifier A2 and a transistor MN2. The amplifier A2 receives the output voltage VL2 of the LDO 22 and the voltage of the common output node N1 as inputs, respectively, and outputs the output voltage VL2 of the LDO 22 and the voltage of the common output node N1. and may output a second comparison signal. The transistor MN2 is connected between the power supply terminal VDD and the common output node N1, and is gated with the second comparison signal to transmit a second candidate selection signal corresponding to the second comparison signal to the common output node N1. can be output through

For example, the third tracker 113 may include an amplifier A3 and a transistor MN3. The amplifier (A3) receives the output voltage (VL3) of the LDO (23) and the voltage of the common output node (N1) as inputs, respectively, and outputs the output voltage (VL3) of the LDO (23) and the voltage of the common output node (N1). and may output a third comparison signal. The transistor MN3 is connected between the power supply terminal VDD and the common output node N1, and is gated with the third comparison signal to transmit a third candidate selection signal corresponding to the third comparison signal to the common output node N1. can be output through

That is, the first tracker 111, the second tracker 112, and the third tracker 113 track the output signals of the LDOs 21, 22, and 23 in the form of voltage source followers.

As an example of the discharging unit 117, a resistor Rk may be further included in the common output node N1.

The amplifiers A1, A2, and A3 may follow the output of any one of the first candidate selection signal, the second candidate selection signal, and the third candidate selection signal to be detected as the selection signal Vsel according to some embodiments. . For example, in the graph of FIG. 2, when all LDOs are turned on and the output voltage is VL1>VL2 (first period), the track and selector 110 continuously sends the first candidate selection signal along the amplifier A1. is tracked and detected by the selection signal Vsel, and the remaining transistors MN2 and MN3 operate in the direction of turning off. Then, when the LDO 21 is turned off and VL1 < VL2 (second period), the track and select unit 110 continuously tracks only the second candidate selection signal (ie, the second candidate selection signal is the selection signal (Vsel) ))) The remaining transistors MN1 and MN3 may be turned off.

The impedance unit 121 may be an impedance resistor (Rs) in one embodiment. An impedance resistor Rs may be connected between the common output node N1 and the summing node N2.

The current generator 122 may include a reference amplifier A4, a reference resistor Rr, and two reference transistors MP1 and MP2 according to some embodiments.

The reference amplifier A4 compares the control voltage Vr with the output voltage of the comparison node N3 and outputs a reference signal. For example, the reference amplifier A4 may be implemented such that the control voltage Vr is applied to the inverting terminal (-) and the non-inverting terminal (+) is connected to the comparison node N3, but according to another embodiment, the non-inverting terminal And it will be said that the connection of the inverting terminal may be implemented in reverse. According to some embodiments, the control voltage Vr may be a voltage whose level is adjusted according to the reference control signal Vcnt[k:1].

The first reference transistor MP1 is gated by the reference signal and is connected between the power supply terminal VDD and the comparison node N3. A reference resistance Rr is connected between the comparison node and the ground terminal. The second reference transistor MP2 is connected between the power supply terminal VDD and the summing node N2, and is gated with a reference signal to generate an offset current.

The offset current is reflected in the impedance resistor 121 and converted into an offset voltage, and the reference voltage Vref is generated by summing the offset voltage Vk and the selection signal Vsel at the summing node N2.

6 is a circuit diagram illustrating a power tracker according to some embodiments. For convenience of explanation, differences from FIG. 5 will be mainly described, and overlapping descriptions will be omitted.

Unlike FIG. 5 , the power tracker of FIG. 6 may include a current source 119 as a discharging unit. The current source 119 may also discharge current according to the voltage direction of the selection signal Vsel.

In the example shown in FIG. 6, the output voltages VL1, VL2, and VL3 of the LDOs 21, 22, and 23 are applied to the non-inverting terminals of the amplifiers A1, A2, and A3, and the inverting terminals are connected to the common output node N1. ), but is not limited thereto, and according to other embodiments, the connection of the non-inverting terminal and the inverting terminal may be reversed. In the illustrated example, the transistors MN1 , MN2 , and MN3 have been described as N-type transistors, but P-type transistors may also be used according to other embodiments.

7 is a circuit diagram illustrating a power tracker according to some embodiments. For convenience of explanation, differences from FIG. 5 will be mainly described, and overlapping descriptions will be omitted.

Referring to FIG. 7, the voltages input to the non-inverting terminals of the amplifiers A1, A2, and A3 do not directly input the output voltages VL1, VL2, and VL3 of the LDOs 21, 22, and 23, and the voltage level is It can be converted and input.

For example, distribution resistors R1 and R2 and an analog buffer 111b may be further included between the LDO 21 and the non-inverting terminal of the amplifier A1. The output voltage of the LDO 21 may be input to the non-inverting terminal of the amplifier A1 via the analog buffer 111b after being divided according to the ratio of the distribution resistors R1 and R2.

Similarly, the output voltage of the LDO 22 may be input to the non-inverting terminal of the amplifier A2 via the analog buffer 112b after being divided according to the ratio of the distribution resistors R3 and R4. The output voltage of the LDO 23 may be input to the non-inverting terminal of the amplifier A1 via the analog buffer 113b after being divided according to the ratio of the distribution resistors R5 and R6.

According to some embodiments, the distribution resistors R1, R2, R3, R4, R5, and R6 may have the same value or different values in consideration of the characteristics of the LDOs 21, 22, and 23 according to some embodiments. may have

When the level-converted output voltages VL1, VL2, and VL3 are input to the amplifiers A1, A2, and A3, the power tracker can be operated with less power consumption.

8 is a circuit diagram illustrating a power tracker according to some embodiments. For convenience of explanation, differences from FIG. 5 will be mainly described, and overlapping descriptions will be omitted.

Referring to FIG. 8, unlike FIG. 6, in the amplifiers A11, A12, and A13, the output voltages VL1, VL2, and VL3 of the LDOs 21, 22, and 23 are applied to the inverting terminals (-), and the non-inverting terminals (+) may be connected to the common output node N1. In the illustrated example, P-type transistors MP11, MP12, and MP13 may be connected to the transistor.

The first tracker 111' may include an amplifier A11 and a transistor MP11. The amplifier A11 receives the output voltage VL1 of the LDO 21 through the inverting terminal (-) and the voltage of the common output node N1 through the non-inverting terminal (+), and receives the output voltage (VL1) of the LDO 21 ( VL1) and the voltage of the common output node N1 may be compared, and the first comparison signal may be output to the gate of the transistor MP11. The transistor MP11 is connected between the power supply terminal VDD and the common output node N1, is gated with the first comparison signal, and transmits a first candidate selection signal corresponding to the first comparison signal to the common output node N1. can be output through

For example, the second tracker 112' may include an amplifier A12 and a transistor MP12. The amplifier A12 receives the output voltage VL2 of the LDO 22 through an inverting terminal and the voltage of the common output node N1 through a non-inverting terminal, and outputs the output voltage VL2 of the LDO 22 and the common output node. The voltage of (N1) may be compared and the second comparison signal may be output to the gate of the transistor MP12. The transistor MP12 is connected between the power supply terminal VDD and the common output node N1 and is gated with the second comparison signal to transmit a second candidate selection signal corresponding to the second comparison signal to the common output node N1. can be output through

For example, the third tracker 113 may include an amplifier A13 and a transistor MP13. The amplifier A13 receives the output voltage VL3 of the LDO 23 through an inverting terminal and the voltage of the common output node N1 through a non-inverting terminal, and outputs the output voltage VL3 of the LDO 23 and the common output node. The voltage of (N1) can be compared and the third comparison signal can be output to the gate of the transistor MP13. The transistor MP13 is connected between the power supply terminal VDD and the common output node N1 and is gated with the third comparison signal to transmit a third candidate selection signal corresponding to the third comparison signal to the common output node N1. can be output through

For example, the reference amplifier A14 included in the current generator 125 compares the control voltage Vr with the output voltage of the comparison node N3 and outputs a reference signal to the gate of the comparison reference transistor MN31. The reference amplifier A14 may be implemented such that the control voltage Vr is applied to the non-inverting terminal (+) and the inverting terminal (-) is connected to the comparison node N3. The comparison reference transistor MN31 may be connected to the P-type complementary transistor. The source terminals of the first reference complementary transistor MP31 and the second reference complementary transistor MP32 are connected to the power supply terminal VDD, and the drain of the first reference complementary transistor MP31 is the drain of the comparison reference transistor MN31. connected with A drain terminal of the second reference complementary transistor MP32 is connected to the summing node N2. Gate terminals of the first reference complementary transistor MP31 and the second reference complementary transistor MP32 are connected to the drain terminal of the first reference complementary transistor MP31.

That is, the reference signal output from the reference amplifier A14 gates the comparison reference transistor MN31, generates an offset current by the reference complementary transistors MP31 and MP32 forming a current mirror circuit, and the offset current is an impedance unit. An offset voltage can be generated based on (121).

As a result, the offset voltage Vk and the selection voltage Vsel are summed at the summing node N2 to output the reference voltage Vref.

FIG. 9 is a block diagram illustrating a power management integrated circuit according to some embodiments, and FIG. 10 is a voltage graph illustrating an operation of the power management integrated circuit of FIG. 9 . For convenience of description, differences from the embodiment of FIG. 3 will be mainly described, and overlapping descriptions will be omitted.

9 and 10, a power management integrated circuit according to some embodiments includes a plurality of loop circuits 21', 22', and 23', a power tracker 100-2, and a charging circuit 11. do.

For example, the first loop circuit 21' may be a constant voltage loop circuit, the second loop circuit 22' may be a constant current loop circuit, and the third loop circuit ( 23') may be an input voltage loop circuit. The first loop circuit 21' outputs the first output signal VL1, the second loop circuit 22' outputs the second output signal VL2, and the third loop circuit 23' outputs the third output signal VL2. An output signal VL3 is output.

The power tracker 100-2 tracks the first to third output signals VL1, VL2, and VL3, and detects one of the output signals as the selection signal Vsel. The power tracker 100 - 2 generates a reference voltage Vref by adding the offset voltage Vk to the selection signal Vsel and provides the reference voltage Vref to the charging circuit 11 .

The power tracker 100-2 includes a track and selection unit 110' that outputs a selection signal Vsel to a common output node N1.

According to some embodiments, the power tracker 100-2 further includes a voltage generator 120 providing an offset voltage whose level is adjusted by the reference control signal Vcnt[k:1] to the summing node 130. can do. Alternatively, according to some embodiments, the power tracker 100-2 may provide a preset offset voltage to the summing node 130.

The charging circuit 11 generates an input voltage Vo corresponding to the reference voltage Vref, and supplies the input voltage Vo to the first to third loop circuits 21', 22', and 23'.

For example, the magnitudes of the first output signal VL1, the second output signal VL2, and the third output signal VL3 are VL1>VL2>VL3, and the selection signal Vsel has the maximum value among the tracked output signals. Suppose we detect

Referring to FIG. 10, the track and select unit 110' tracks and detects the highest voltage for each section among the first to third output signals VL1, VL2, and VL3. In the illustrated example, the first output signal VL1 is detected in the first section, the second output signal VL2 is detected in the second section, and the third output signal VL3 is detected in the third section and output as a selection signal Vsel. do.

11 is a block diagram illustrating a power tracker according to some embodiments, and FIG. 12 is a circuit diagram illustrating the power tracker of FIG. 11 according to an embodiment.

Referring to FIG. 11 , the power tracker 100-3 may include a first tracker 111″, a second tracker 112″, a third tracker 113″, and a sourcing unit 118 .

According to some embodiments, the power tracker 100 - 3 may further include an impedance unit 121 and a current generator 125 . The impedance unit 121 and the current generator 125 may generate an offset voltage.

According to some embodiments, the first tracker 111" may include an amplifier A1 and a transistor MP1. The amplifier A1 receives the output signal VL1 of the loop circuit through a non-inverting terminal and has a common The first comparison signal may be output by receiving the voltage of the output node N1 through the inverting terminal.The transistor MP1 is connected between the common output node N1 and the ground terminal and has a first comparison signal corresponding to the first comparison signal. 1 candidate selection signal can be output. Since the second tracker 112" and the third tracker 113" have the same structure as the first tracker 111", a description thereof will be omitted.

The sourcing unit 118 is disposed between the power supply terminal VDD and the common output node N1 to discharge current according to the voltage direction of the selection signal Vsel. The sourcing unit 118 may be, for example, a current source Idis.

The impedance unit 121 may be, for example, a simple resistor or, for example, a variable programmable resistor.

Since the current generator 125 may be implemented similarly to the current generator 125 of FIG. 8 according to some embodiments, a description thereof is omitted.

When the sourcing unit 118 and the first to third trackers 111", 112", and 113" are implemented as shown in FIG. 11, the power tracker 100-3 continuously tracks the output voltage of the LDO, unlike FIG. Thus, the minimum value among the output voltages can be detected as the selection signal Vsel.

13 is a block diagram illustrating a power tracker according to some embodiments, and FIG. 14 is a circuit diagram illustrating the power tracker of FIG. 13 according to an embodiment. For convenience of description, descriptions overlapping those of FIG. 3 will be omitted.

Referring to FIG. 13, the power tracker 100-4 outputs voltages VL of LDOs 21, 22, and 23 as shown in FIG. 3 or loop circuits 21', 22', and 23' as shown in FIG. The selection signal Vsel may be generated by tracking the output current IL, and the reference voltage Vref may be generated by adding an offset voltage to the selection signal Vsel.

According to some embodiments, the power tracker 100-4 may include a plurality of trackers 114, 115, and 116 that track the output voltage and output current from each LDO or loop circuit.

For example, the first tracker 114 may include an input resistor Rs, an amplifier A1 and a transistor MN1. The amplifier A1 has a first input terminal connected to a common output node, a second input terminal connected to one end of an input resistor, and generating a comparison signal by comparing signals between the first input terminal and the second input terminal to generate a transistor It can be applied to the gate of (MN1). The output voltage VL of the LDO or loop circuit may be provided to the other end of the input resistance Rs, and the output current IL may be provided to one end of the input resistance. The second tracker 115 and the third tracker 116 may have the same structure as the first tracker 114 .

Since the impedance unit 121 and the current generator 122 overlap with those of FIGS. 4 and 5 described above, descriptions thereof are omitted.

According to some embodiments, when the power tracker 100 - 4 is implemented as shown in FIG. 13 , the selection signal Vsel may be detected by tracking not only the output voltage VL but also the output current IL. Fig. 15 will be described as an example.

FIG. 15 is a voltage graph and a current graph for explaining the operation of the power management integrated circuit of FIG. 13 .

Referring to FIG. 15 , the LDO 21 may output an output current IL1 and an output voltage VL1 based on the input voltage VBK. Assume that the level of the output current IL varies while the output voltage VL1 remains constant. For convenience of description, a case in which only one LDO 21 is turned on and operated will be described.

The output current IL1 maintains a constant value in the period t1, rises in the period t2, remains constant in the period t3, falls in the period t4, and remains constant in the period after t4.

Even if the output voltage VL1 is constant, when the output current IL1 increases in the intervals t2 and t3, the voltage input to the non-inverting terminal of the amplifier A1 increases due to the input resistance Rs. Accordingly, the comparison signal output from the output terminal of the amplifier A1 changes according to the change of the output current IL1, and the selection signal Vsel can also change according to the comparison signal. That is, even if the output voltage VL1 is constant, the selection signal Vsel may vary in proportion to the output current IL1. In addition, since the input voltage VBK generated by the sub-regulator 10 is also generated from the reference voltage Vref based on the selection signal Vsel, the input voltage VBK also affects the output current IL1 like the selection signal Vsel. fluctuates according to

16 is a block diagram illustrating a power tracker according to some embodiments.

Referring to FIG. 16 , a power tracker 200 according to some embodiments includes a plurality of sub-trackers 211, 212, and 213, a sourcing unit 217, a discharging unit 219, an impedance unit 221, and current generation It may be implemented to include all of the parts 222 .

In order to track the output signal of the regulator (for example, the LDO of FIG. 1 or the loop circuit of FIG. 9), the power tracker 200 may use sub-trackers 211, 212, and 213 and a sourcing unit 217 according to an embodiment. Alternatively, the sub trackers 211, 212, and 213 and the discharging unit 219 may be used according to another embodiment.

The power tracker 200 may use the impedance unit 221 and the current generator 222 according to the characteristics of the IP module connected to the power management integrated circuit, or may apply and use a pre-stored offset voltage to the summing node N2. Alternatively, without applying the offset voltage without the impedance unit 221 and the current generator 222, the selection voltage Vsel may be used as the reference voltage Vref.

Although the embodiments of the present invention have been described with reference to the accompanying drawings, those skilled in the art to which the present invention pertains can be implemented in other specific forms without changing the technical spirit or essential features of the present invention. you will be able to understand Therefore, the embodiments described above should be understood as illustrative in all respects and not limiting.

1: power management integrated circuit 2: IP module
10: sub-regulator 21, 22, 23: regulator
30: digital logic
100, 100-1, 100-2, 100-3, 100-4: Power Tracker
110: track and selection unit 120: voltage generation unit
N1: common output node N2, 130: summing node

Claims (20)

A first regulator providing a first output signal to an IP (Intellectual Property) module;
a second regulator providing a second output signal to the IP module;
a third regulator providing a third output signal to the IP module;
a power tracker generating a reference voltage by tracking the first to third output signals and adding an offset voltage to a selection signal obtained by detecting one of the output signals; and
and a sub-regulator generating an input voltage corresponding to the reference voltage and supplying the generated input voltage to the first to third regulators. The method of claim 1, wherein the first output signal, the second output signal and the third output signal are
A power management integrated circuit that is at least one of a first output voltage, a second output voltage, a third output voltage, or a first output current, a second output current, and a third output current. The power management integrated circuit of claim 1 , wherein the level of the input voltage follows the selection signal. The method of claim 1, wherein the power tracker
a current generator generating an offset current according to a reference control signal;
an impedance unit receiving the offset current and outputting the offset voltage;
a first tracker connected to an output terminal of the first regulator and tracking the first output signal;
a second tracker connected to the output terminal of the second regulator and tracking the second output signal;
a third tracker connected to an output terminal of the third regulator and tracking the third output signal; and
and a discharging unit connected to the common output node of the first tracker, the second tracker, and the third tracker to discharge current according to a voltage direction of the selection signal. The method of claim 4, wherein the first tracker
a first amplifier comparing the output signal of the first regulator with the selection signal of the common output node and outputting a comparison signal; and
and a transistor coupled between a power supply terminal and the common output node and generating the selection signal corresponding to the comparison signal. The method of claim 4, wherein the discharging unit
A resistor connected between the common output node and a ground terminal, a power management integrated circuit. The method of claim 4, wherein the discharging unit
A power management integrated circuit, which is a current source connected between the common output node and a ground terminal to emit a preset current. The method of claim 4, wherein the current generator
a reference amplifier for outputting a reference signal by comparing the control voltage with the output voltage of the comparison node;
a first reference transistor coupled between a power supply terminal and the comparison node and gated with the reference signal;
a reference resistance connected between the comparison node and a ground terminal; and
and a second reference transistor connected between the power supply terminal and a summing node and configured to generate the offset current in response to the reference signal. 9. The power management integrated circuit of claim 8, further comprising an impedance resistor connected between the common output node and the summing node. a first loop circuit that outputs a first output signal;
a second loop circuit outputting a second output signal;
a third loop circuit outputting a third output signal;
a power tracker generating a reference voltage by tracking the first to third output signals and adding an offset voltage to a selection signal obtained by detecting one of the output signals; and
and a charging circuit generating an input voltage corresponding to the reference voltage and providing the input voltage to the first to third loop circuits. 11. The power management integrated circuit of claim 10, wherein the level of the input voltage follows the selection signal. 11. The method of claim 10, wherein the power tracker
a first tracker for tracking the first output signal;
a second tracker tracking the second output signal;
a third tracker tracking the third output signal;
a sourcing unit connected to a common output node of the first tracker, the second tracker, and the third tracker; and
and a voltage generator outputting the reference voltage corresponding to the selection signal output from the common output node. The method of claim 12, wherein the voltage generator
an impedance unit having one end connected to the common output node; and
Including a current generator for generating an offset voltage by providing a variable offset current to the impedance unit,
and outputting the reference voltage by adding the offset voltage to the selection signal. 14. The power management integrated circuit of claim 13, wherein the impedance unit is a programmable resistor. The method of claim 13, wherein the current generator
a reference amplifier for outputting a reference signal by comparing the control voltage with the output voltage of the comparison node;
a comparison reference transistor having one terminal connected to the comparison node and gated with the reference signal;
a first reference complementary transistor connected between the other terminal of the comparison reference transistor and a power supply terminal and gated with a signal of the other terminal of the comparison reference transistor;
a second reference complementary transistor gated by a signal of the other terminal of the comparison reference transistor, connected between the power supply terminal and the summing node, and configured to generate the offset current corresponding to the reference signal; and
A power management integrated circuit comprising a reference resistor connected between the comparison node and a ground terminal. 13. The method of claim 12, wherein the sourcing unit
A power management integrated circuit, which is a current source that emits a predetermined discharging current from the common output node. The method of claim 12, wherein the first tracker
a first amplifier comparing the first output signal and the selection signal of the common output node and outputting a comparison signal; and
and a transistor coupled between a power supply terminal and the common output node and generating the selection signal corresponding to the comparison signal. a first regulator providing a first output voltage and a first output current;
a second regulator providing a second output voltage and a second output current;
a third regulator providing a third output voltage and a first output current;
a power tracker generating a reference voltage by tracking the first to third output voltages and the first to third output currents and adding an offset voltage to a selection signal detected through a common output node; and
and a sub-regulator generating an input voltage corresponding to the reference voltage and supplying the generated input voltage to the first to third regulators. 19. The method of claim 18, wherein the power tracker
A first amplifier configured to compare the selection signal of the common output node with the first output voltage and the first output current and output a first comparison signal, and a first transistor connected between a power supply terminal and the common output node. first tracker;
A second amplifier configured to compare the selection signal of the common output node with the second output voltage and the second output current and output a second comparison signal, and a second transistor connected between a power supply terminal and the common output node. a second tracker; and
A third amplifier for outputting a third comparison signal by comparing the selection signal of the common output node with the third output voltage and the third output current, and a third transistor connected between a power supply terminal and the common output node. Including third trackers,
and outputting a smallest value among the output signals of the first transistor, the second transistor, and the third transistor as the selection signal through the common output node. 20. The method of claim 19, wherein the first amplifier
a first input terminal connected to the common output node;
a second input terminal connected to one end of the input resistance; and
An output terminal connected to the gate of the first transistor to output the first comparison signal;
wherein the first output current is provided to one end of the input resistance and the first output voltage is provided to the other end of the input resistance.

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