KR20230127113A - Image sensor - Google Patents

Abstract

The image sensor includes a substrate including a pixel area, a first photoelectric conversion area and a second photoelectric conversion area disposed in the pixel area of the substrate and adjacent to each other in a first direction, and a deep substrate penetrating the substrate and surrounding the pixel area. The device isolation pattern, the deep device isolation pattern includes first extensions extending in a second direction crossing the first direction between the first photoelectric conversion region and the second photoelectric conversion region, wherein the first extension is The parts are spaced apart from each other in the second direction, a plurality of first transfer gate electrodes disposed on the pixel region of the substrate and vertically overlapping the first photoelectric conversion region, and on the pixel region of the substrate. and a plurality of second transfer gate electrodes disposed on and vertically overlapping the second photoelectric conversion region. The first photoelectric conversion region extends under the plurality of first transfer gate electrodes in the second direction.

Description

Image sensor {Image sensor}

The present invention relates to an image sensor, and more particularly to a CMOS image sensor.

An image sensor is a semiconductor device that converts an optical image into an electrical signal. Recently, with the development of computer and communication industries, demand for image sensors with improved performance is increasing in various fields such as digital cameras, camcorders, personal communication systems (PCS), game devices, security cameras, and medical micro cameras. Image sensors may be classified into a charge coupled device (CCD) type and a complementary metal oxide semiconductor (CMOS) type. The CMOS image sensor is abbreviated as CIS (CMOS image sensor). The CIS includes a plurality of pixels two-dimensionally arranged. Each of the pixels includes a photodiode (PD). The photodiode serves to convert incident light into an electrical signal. The plurality of pixels are defined by a deep isolation pattern disposed therebetween.

One technical problem to be achieved by the present invention is to provide an image sensor capable of improving charge transfer characteristics of unit pixels.

Another technical problem to be achieved by the present invention is to provide an image sensor capable of increasing a charge storage capacity (full well capacity) of a unit pixel.

An image sensor according to the present invention includes a substrate including a pixel area; a first photoelectric conversion region and a second photoelectric conversion region disposed in the pixel region of the substrate and adjacent to each other in a first direction; a deep device isolation pattern penetrating the substrate and surrounding the pixel region, the deep device isolation pattern extending in a second direction intersecting the first direction between the first photoelectric conversion region and the second photoelectric conversion region; including first extensions, wherein the first extensions are spaced apart from each other in the second direction; a plurality of first transfer gate electrodes disposed on the pixel region of the substrate and vertically overlapping the first photoelectric conversion region; and a plurality of second transfer gate electrodes disposed on the pixel region of the substrate and vertically overlapping the second photoelectric conversion region. The first photoelectric conversion region may extend in the second direction under the plurality of first transfer gate electrodes.

An image sensor according to the present invention includes a substrate having first and second surfaces facing each other, the substrate including a pixel area; A deep device isolation pattern penetrating the substrate along a direction perpendicular to the first surface, the deep device isolation pattern surrounding the pixel area along first and second directions that are parallel to the first surface and cross each other. that; A first photoelectric conversion region and a second photoelectric conversion region disposed in the pixel region of the substrate and adjacent to each other in the first direction, and the deep device isolation pattern are interposed between the first photoelectric conversion region and the second photoelectric conversion region. including first extensions extending in the second direction, the first extensions being spaced apart from each other in the second direction; a plurality of first transfer gate electrodes disposed on the pixel region of the substrate and on the first photoelectric conversion region; and a plurality of second transfer gate electrodes disposed on the pixel region of the substrate and on the second photoelectric conversion region. The first photoelectric conversion region may extend from one side of one of the first extensions to one side of the other of the first extensions along the second direction, and the second photoelectric conversion region may extend from one side of the first extensions to another side of the first extensions, and It may extend from the other side of the one of the first extensions to the other side of the other of the first extensions along the direction.

According to the concept of the present invention, each pixel area may include a first photoelectric conversion region and a second photoelectric conversion region adjacent to each other, and a deep device isolation pattern extends between the first photoelectric conversion region and the second photoelectric conversion region. It may include first extension parts and second extension parts extending into the first photoelectric conversion region and the second photoelectric conversion region, respectively. In this case, each pixel area may be configured to include a plurality of photodiodes, and thus, the charge storage capacity of each pixel area may be increased. In addition, a plurality of first transfer gate electrodes may be disposed on the first photoelectric conversion region, and a plurality of second transfer gate electrodes may be disposed on the second photoelectric conversion region. Accordingly, charge transfer characteristics of each pixel region may be improved.

Accordingly, an image sensor capable of improving charge transfer characteristics and charge storage capacity of a unit pixel may be provided.

1 is a block diagram schematically illustrating an image sensor according to example embodiments.
2 is a circuit diagram of a unit pixel of an image sensor according to example embodiments.
3 is a plan view of an image sensor according to some embodiments of the present invention.
FIG. 4 is a plan view in which some components of FIG. 3 are omitted.
5A and 5B are cross-sectional views taken along AA' and BB' of FIG. 3, respectively.
6 is a plan view of an image sensor according to some embodiments of the present invention.
FIG. 7 is a plan view in which some components of FIG. 6 are omitted.
8a, 8b, 8c, and 8d are cross-sectional views along lines AA', BB', CC', and DD' of FIG. 3, respectively.
9 is a plan view of an image sensor according to some embodiments of the present invention.
FIG. 10 is a plan view in which some components of FIG. 9 are omitted.
Fig. 11 is a cross-sectional view taken along line C-C' of Fig. 9;
12 and 13 are cross-sectional views corresponding to line C-C' of FIG. 9 illustrating an image sensor according to some embodiments of the present invention.
14 is a plan view of an image sensor according to some embodiments of the present invention.
FIG. 15 is a plan view in which some components of FIG. 14 are omitted.
FIG. 16 is a cross-sectional view taken along line C-C' of FIG. 14;
17 and 18 are cross-sectional views corresponding to line C-C' of FIG. 14 illustrating an image sensor according to some embodiments of the present invention.
19A to 21A are diagrams illustrating a method of manufacturing an image sensor according to some embodiments of the present invention, and are cross-sectional views corresponding to line AA′ of FIG. 3 .
19B to 21B are views illustrating a method of manufacturing an image sensor according to some embodiments of the present invention, and are cross-sectional views corresponding to line BB′ of FIG. 3 .
22 is a plan view of an image sensor according to some embodiments of the present invention.
FIG. 23 is a cross-sectional view taken along the line II' of FIG. 22 .

Hereinafter, the present invention will be described in detail by describing embodiments of the present invention with reference to the accompanying drawings.

1 is a block diagram schematically illustrating an image sensor according to example embodiments.

Referring to FIG. 1, an image sensor includes an active pixel sensor array (1), a row decoder (2), a row driver (3), a column decoder (4), and timing. It may include a timing generator (5), a Correlated Double Sampler (CDS) 6, an Analog to Digital Converter (ADC) 7, and an I/O buffer (8). .

The active pixel sensor array 1 may include a plurality of two-dimensionally arranged pixels, and may convert an optical signal into an electrical signal. The active pixel sensor array 1 may be driven by a plurality of driving signals, such as a pixel selection signal, a reset signal, and a charge transfer signal, provided from the row driver 3 . Also, the electrical signal converted by the active pixel sensor array 1 may be provided to the correlated double sampler 6 .

The row driver 3 may provide a plurality of driving signals for driving the plurality of pixels to the active pixel sensor array 1 according to a result decoded by the row decoder 2 . When the plurality of pixels are arranged in a matrix form, driving signals may be provided for each row.

The timing generator 5 may provide timing signals and control signals to the row decoder 2 and the column decoder 4 .

The correlated double sampler (CDS) 6 may receive, hold, and sample the electric signal generated by the active pixel sensor array 1 . The correlated double sampler 6 double-samples a specific noise level and a signal level caused by an electrical signal, and outputs a difference level corresponding to a difference between the noise level and the signal level.

The analog-to-digital converter (ADC) 7 may convert the analog signal corresponding to the difference level output from the correlated double sampler 6 into a digital signal and output the converted digital signal.

The input/output buffer 8 may latch digital signals and sequentially output the latched signals to an image signal processing unit (not shown) according to decoding results in the column decoder 4 .

2 is a circuit diagram of a unit pixel of an image sensor according to example embodiments.

Referring to FIGS. 1 and 2 , the active pixel sensor array 1 may include a plurality of pixels PX, and the pixels PX may be arranged in a matrix form. Each of the pixels PX includes a first photoelectric conversion device PD1 , a first photoelectric conversion device PD2 , a first transfer transistor TX1 , a second transfer transistor PX2 , and logic transistors RX. , SX, DX). The logic transistors RX, SX, and DX may include a reset transistor RX, a select transistor SX, and a drive transistor DX. The first transfer transistor TX1 , the second transfer transistor PX2 , the reset transistor RX , and the select transistor SX are respectively a first transfer gate TG1 and a second transfer gate TG2 . , a reset gate RG, and a selection gate SG. Each of the pixels PX may further include a floating diffusion region FD.

The first and second photoelectric conversion elements PD1 and PD2 may generate and accumulate photocharges in proportion to the amount of light incident from the outside. The first and second photoelectric conversion elements PD1 and PD2 may be photodiodes including a P-type impurity region and an N-type impurity region. The first transfer transistor TX1 may transfer the charge generated by the first photoelectric conversion device PD1 to the floating diffusion region FD, and the second transfer transistor TX2 may transfer the charge generated by the first photoelectric conversion device PD1. Charges generated in (PD2) may be transferred to the floating diffusion region (FD).

The floating diffusion region FD may receive and accumulate charges generated by the first and second photoelectric conversion elements PD1 and PD2. The drive transistor DX may be controlled according to the amount of photocharges accumulated in the floating diffusion region FD.

The reset transistor RX may periodically reset charges accumulated in the floating diffusion region FD. A drain electrode of the reset transistor RX may be connected to the floating diffusion region FD, and a source electrode of the reset transistor RX may be connected to a power supply voltage VDD. When the reset transistor RX is turned on, a power supply voltage VDD connected to a source electrode of the reset transistor RX may be applied to the floating diffusion region FD. Therefore, when the reset transistor RX is turned on, charges accumulated in the floating diffusion region FD are discharged to reset the floating diffusion region FD.

The drive transistor DX may serve as a source follower buffer amplifier. The drive transistor DX may amplify a potential change in the floating diffusion region FD and output it to an output line Vout.

The selection transistor SX may select pixels PX to be read in units of rows. When the selection transistor SX is turned on, the power supply voltage VDD may be applied to the drain electrode of the drive transistor DX.

Although FIG. 2 illustrates a unit pixel PX including two photoelectric conversion elements PD1 and PD2 and five transistors TX1, TX2, RX, DX, and SX, the image sensor according to the present invention Not limited to this. For example, the reset transistor RX, the drive transistor DX, or the select transistor SX may be shared by neighboring pixels PX. Accordingly, the degree of integration of the image sensor may be improved.

3 is a plan view of an image sensor according to some embodiments of the present invention, and FIG. 4 is a plan view in which some components of FIG. 3 are omitted. 5A and 5B are cross-sectional views along lines A-A' and BB' of FIG. 3, respectively.

Referring to FIGS. 3 , 4 , 5A and 5B , the image sensor may include a photoelectric conversion layer 10 , a wiring layer 20 , and a light transmission layer 30 . The photoelectric conversion layer 10 may be disposed between the wiring layer 20 and the light transmission layer 30 .

The photoelectric conversion layer 10 may include a substrate 100 , and the substrate 100 may include a plurality of pixel regions PXR. The substrate 100 may be a semiconductor substrate (eg, a silicon substrate, a germanium substrate, a silicon-germanium substrate, a II-VI compound semiconductor substrate, or a III-V compound semiconductor substrate) or a silicon on insulator (SOI) substrate. there is. The substrate 100 may have a first surface 100a and a second surface 100b facing each other. The plurality of pixel regions PXR may be two-dimensionally arranged along a first direction D1 and a second direction D2 parallel to the first surface 100a of the substrate 100 . The first direction D1 and the second direction D2 may cross each other.

The photoelectric conversion layer 10 may further include a deep device isolation pattern 150 penetrating the substrate 100 and disposed between the plurality of pixel regions PXR. The deep device isolation pattern 150 may penetrate the substrate 100 along a third direction D3 perpendicular to the first surface 100a of the substrate 100 . The deep device isolation pattern 150 may extend from the first surface 100a of the substrate 100 toward the second surface 100b of the substrate 100 . The first surface 100a of the substrate 100 may expose the top surface 150U of the deep device isolation pattern 150, and the second surface 100b of the substrate 100 may expose the deep device isolation pattern 150. The lower surface 150L of the separation pattern 150 may be exposed. An upper surface 150U of the deep device isolation pattern 150 may be substantially coplanar with the first surface 100a of the substrate 100, and a lower surface 150L of the deep device isolation pattern 150 may be substantially coplanar with the first surface 100a of the substrate 100. It may be substantially coplanar with the second surface 100b of the substrate 100 . The deep device isolation pattern 150 may prevent cross-talk between adjacent pixel regions PXR.

The deep device isolation pattern 150 may surround each of the plurality of pixel regions PXR in a plan view. The deep device isolation pattern 150 may extend to surround each pixel area PXR along the first and second directions D1 and D2 . The deep device isolation pattern 150 may include first extensions 150P1 extending into each pixel region PXR along the second direction D2 . The first extensions 150P1 may be spaced apart from each other in the second direction D2 within each pixel area PXR. A length L1 of each of the first extension parts 150P1 along the second direction D2 is greater than a distance DS1 between the first extension parts 150P1 along the second direction D2. can

The deep device isolation pattern 150 includes the semiconductor patterns 152 and 154 penetrating at least a portion of the substrate 100, the buried insulating pattern 158 on the semiconductor patterns 152 and 154, and the semiconductor pattern 152. , 154) and the side insulating pattern 156 interposed between the substrate 100. The side insulating pattern 156 may extend from the side surface of the semiconductor patterns 152 and 154 to the side surface of the buried insulating pattern 158 . The semiconductor patterns 152 and 154 include a first semiconductor pattern 152 penetrating at least a portion of the substrate 100 and a second semiconductor between the first semiconductor pattern 152 and the side insulating pattern 156 . pattern 154. The first semiconductor pattern 152 may cover an uppermost surface of the second semiconductor pattern 154 and may contact the side insulating pattern 156 . The filling insulating pattern 158 may be disposed on the first semiconductor pattern 152 . The first semiconductor pattern 152 may extend between the filling insulating pattern 158 and the second semiconductor pattern 154 and may contact the side insulating pattern 156 .

Each of the first semiconductor pattern 152 and the second semiconductor pattern 154 may include a semiconductor material doped with an impurity. The impurity may have a P-type or N-type conductivity. For example, each of the first semiconductor pattern 152 and the second semiconductor pattern 154 may include boron-doped polycrystalline silicon. Each of the side insulating pattern 156 and the filling insulating pattern 158 may include, for example, silicon oxide, silicon nitride, and/or silicon oxynitride.

The first photoelectric conversion region 110a and the second photoelectric conversion region 110b may be disposed in each pixel region PXR and may be adjacent to each other in the first direction D1 within each pixel region PXR. there is. The first extensions 150P1 of the deep device isolation pattern 150 may be disposed between the first photoelectric conversion region 110a and the second photoelectric conversion region 110b. The first extension parts 150P1 may extend in the second direction D2 between the first photoelectric conversion region 110a and the second photoelectric conversion region 110b and extend in the second direction D2. may be separated from each other. The first photoelectric conversion region 110a may extend in the second direction D2 from one side of the first extension portions 150P1, and the second photoelectric conversion region 110b may extend along the first extension portions 150P1. It may extend in the second direction D2 from the other side of (150P1). For example, the first photoelectric conversion region 110a extends from one side of one of the first extensions 150P1 to one side of the other of the first extensions 150P1 along the second direction D2. The second photoelectric conversion region 110b may be continuously extended, and the second photoelectric conversion region 110b may extend from one side of the first extension part 150P1 along the second direction D2 to one of the first extension parts 150P1. It may be continuously extended to the other side of the other one.

The substrate 100 may have a first conductivity type, and the first and second photoelectric conversion regions 110a and 110b may be regions doped with impurities of a second conductivity type different from the first conductivity type. there is. For example, the first conductivity type and the second conductivity type may be a P type and an N type, respectively. In this case, the impurity of the second conductivity type may include an N-type impurity such as phosphorus, arsenic, bismuth, and/or antimony. Each of the first and second photoelectric conversion regions 110a and 110b may form a photodiode by forming a PN junction with the substrate 100 . For example, the first photoelectric conversion region 110a may form a first photodiode (PD1 in FIG. 2 ) by forming a PN junction with the substrate 100, and the second photoelectric conversion region 110b may form a PN junction. A second photodiode (PD2 in FIG. 2 ) may be configured by forming a PN junction with the substrate 100 . Each pixel region PXR may correspond to a unit pixel (PX in FIG. 2 ) including the first photodiode (PD1 in FIG. 2 ) and the second photodiode (PD2 in FIG. 2 ). In some embodiments, the semiconductor patterns 152 and 154 of the deep device isolation pattern 150 may include a semiconductor material doped with impurities of the first conductivity type (eg, P-type impurities). .

A shallow device isolation pattern 105 may be disposed adjacent to the first surface 100a of the substrate 100 . Each of the plurality of pixel regions PXR may include active patterns ACT defined by the shallow device isolation pattern 105 . As an example, the shallow device isolation pattern 105 may include at least one of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer. The active patterns ACT may be spaced apart from each other in each pixel area PXR, and the shallow device isolation pattern 105 may be interposed between the active patterns ACT. The deep device isolation pattern 150 may pass through the shallow device isolation pattern 105 and extend into the substrate 100 . Each of the first extensions 150P1 of the deep device isolation pattern 150 may pass through the shallow device isolation pattern 105 and extend into each pixel region PXR. Some of the active patterns ACT may overlap the first photoelectric conversion region 110a vertically (eg, in the third direction D3), and some of the active patterns ACT may overlap with the first photoelectric conversion region 110a. may overlap the second photoelectric conversion region 110b vertically (eg, in the third direction D3). Each of the first extension parts 150P1 may extend between corresponding active patterns ACT among the active patterns ACT.

The buried insulating pattern 158 of the deep device isolation pattern 150 may be disposed within the shallow device isolation pattern 105 . The buried insulating pattern 158 may pass through the shallow device isolation pattern 105 and contact the semiconductor patterns 152 and 154 . The side insulating pattern 156 of the deep device isolation pattern 150 may extend between the shallow device isolation pattern 105 and the filling insulating pattern 158 .

A plurality of first transfer gate electrodes TG1, a first floating diffusion region FD1, a plurality of second transfer gate electrodes TG2, and a second floating diffusion region FD2 are formed on each pixel region PXR. , and may be disposed adjacent to the first surface 100a of the substrate 100 . The first transfer gate electrodes TG1 and the first floating diffusion region FD1 may be disposed on a corresponding active pattern ACT among the active patterns ACT, and the first photoelectric conversion region ( 110a) and vertically (eg, in the third direction D3). The first photoelectric conversion region 110a may continuously extend in the second direction D2 under the first transfer gate electrodes TG1 and the first floating diffusion region FD1. The second transfer gate electrodes TG2 and the second floating diffusion region FD2 may be disposed on a corresponding active pattern ACT among the active patterns ACT, and the second photoelectric conversion region ( 110b) and vertically (eg, in the third direction D3). The second photoelectric conversion region 110b may continuously extend in the second direction D2 under the second transfer gate electrodes TG2 and the second floating diffusion region FD2.

The first floating diffusion region FD1 and the second floating diffusion region FD2 extend in the first direction D1 with one of the first extensions 150P1 of the deep device isolation pattern 150 interposed therebetween. can be spaced apart from each other. The first transfer gate electrodes TG1 may be disposed adjacent to the first floating diffusion region FD1, and the second transfer gate electrodes TG2 may be adjacent to the second floating diffusion region FD2. can be placed appropriately. According to some embodiments, the second transfer gate electrodes TG2 may include the first transfer gate electrodes (TG2) along the first direction D1 with the one of the first extension portions 150P1 interposed therebetween. TG1).

A lower portion of each of the first transfer gate electrodes TG1 may extend into the substrate 100 toward the first photoelectric conversion region 110a, and each of the first transfer gate electrodes TG1 may extend into the substrate 100 . An upper portion of may protrude above the top surface of the corresponding active pattern ACT (ie, the first surface 100a of the substrate 100). Lower portions of each of the second transfer gate electrodes TG2 may extend into the substrate 100 toward the second photoelectric conversion region 110b, and each of the second transfer gate electrodes TG2 may extend into the substrate 100 . An upper portion of may protrude above the top surface of the corresponding active pattern ACT (ie, the first surface 100a of the substrate 100). The first floating diffusion region FD1 and the second floating diffusion region FD2 are doped with impurities of the second conductivity type different from the first conductivity type of the substrate 100 (eg, N-type impurities). areas may be

The first transfer gate electrodes TG1 and the first floating diffusion region FD1 may constitute the first transfer transistor TX1 of FIG. 2 . The second transfer gate electrodes TG2 and the second floating diffusion region FD2 may constitute the second transfer transistor TX2 of FIG. 2 .

A first gate dielectric pattern GI1 may be interposed between each of the first transfer gate electrodes TG1 and the substrate 100 (that is, the corresponding active pattern ACT), and the second gate dielectric pattern ( GI2) may be interposed between each of the second transfer gate electrodes TG2 and the substrate 100 (that is, the corresponding active pattern ACT).

A plurality of gate electrodes GE and source/drain regions SD may be disposed on each pixel region PXR and adjacent to the first surface 100a of the substrate 100 . The gate electrodes GE and the source/drain regions SD may be disposed on corresponding active patterns ACT among the active patterns ACT, and the first photoelectric conversion region 110a Alternatively, it may overlap the second photoelectric conversion region 110b vertically (eg, in the third direction D3). The source/drain regions SD may be, for example, regions doped with impurities (eg, N-type impurities) of the second conductivity type different from the first conductivity type of the substrate 100 . The gate electrodes GE and the source/drain regions SD may configure the drive transistor DX, the selection transistor SX, and the reset transistor RX of FIG. 2 . A gate dielectric pattern GI may be interposed between each of the gate electrodes GE and the substrate 100 (that is, the corresponding active pattern ACT).

The wiring layer 20 may be disposed on the first surface 100a of the substrate 100 . The wiring layer 20 may include a first interlayer insulating film 210 and a second interlayer insulating film 240 sequentially stacked on the first surface 100a of the substrate 100 . The first interlayer insulating film 210 is disposed on the first surface 100a of the substrate 100 to cover the first and second transfer gate electrodes TG1 and TG2 and the gate electrodes GE. can cover The wiring layer 20 includes the first and second transfer gate electrodes TG1 and TG2, the gate electrodes GE, the first and second floating diffusion regions FD1 and FD2, and the source/drain. Contact plugs 220 connected to the regions SD and conductive lines 230 connected to the contact plugs 220 may be further included. The contact plugs 220 pass through the first interlayer insulating layer 210 to form the first and second transfer gate electrodes TG1 and TG2, the gate electrodes GE, and the first and second floating It may be connected to the diffusion regions FD1 and FD2 and the source/drain regions SD. The conductive lines 230 may be disposed in the second interlayer insulating layer 240 . At least some of the contact plugs 220 may extend into the second interlayer insulating layer 240 and be connected to the conductive lines 230 . The first interlayer insulating layer 210 and the second interlayer insulating layer 240 may include an insulating material, and the contact plugs 220 and the conductive lines 230 may include a conductive material.

The light transmission layer 30 may be disposed on the second surface 100b of the substrate 100 . The light transmission layer 30 may include a color filter array 320 and a micro lens array 330 disposed on the second surface 100b of the substrate 100 . The color filter array 320 may be disposed between the second surface 100b of the substrate 100 and the micro lens array 330 . The light transmission layer 30 may condense and filter light incident from the outside, and may provide the light to the photoelectric conversion layer 10 .

The color filter array 320 may include a plurality of color filters 320 respectively disposed on the plurality of pixel regions PXR. Each color filter 320 may be disposed on each pixel area PXR, and is perpendicular to (for example, the first and second photoelectric conversion areas 110a and 110b) of each pixel area PXR. in the third direction D3). The micro lens array 330 may include a plurality of micro lenses 330 respectively disposed on the plurality of color filters 320 . Each microlens 330 may be disposed on each pixel area PXR, and is perpendicular to (for example, the first and second photoelectric conversion areas 110a and 110b) of each pixel area PXR. in the third direction D3).

An anti-reflective layer 310 may be interposed between the second surface 100b of the substrate 100 and the color filter array 320 . The antireflection film 310 prevents reflection of light incident on the second surface 100b of the substrate 100 so that the light can smoothly reach the first and second photoelectric conversion regions 110a and 110b. It can be prevented. A first insulating layer 312 may be interposed between the anti-reflective layer 310 and the color filter array 320, and a second insulating layer 322 may be interposed between the color filter array 320 and the micro lens array 330. may be interposed between them.

According to the concept of the present invention, each pixel region PXR may include the first photoelectric conversion region 110a and the second photoelectric conversion region 110b adjacent to each other in the first direction D1, The deep device isolation pattern 150 may include the first extension portions 150P1 interposed between the first photoelectric conversion region 110a and the second photoelectric conversion region 110b. In this case, each pixel region PXR may include two photodiodes composed of the first photoelectric conversion region 110a and the second photoelectric conversion region 110b, and thus each pixel region PXR The charge storage capacity of can be increased. In addition, the plurality of first transfer gate electrodes TG1 are disposed on the first photoelectric conversion region 110a to electrically connect the first photoelectric conversion region 110a and the first floating diffusion region FD1. and the plurality of second transfer gate electrodes TG2 are disposed on the second photoelectric conversion region 110b to form the second photoelectric conversion region 110b and the second floating diffusion region FD2. can be electrically connected. At least two first transfer gate electrodes TG1 are disposed on the first photoelectric conversion region 110a, and at least two second transfer gate electrodes TG2 are disposed on the second photoelectric conversion region 110b. , charge transfer characteristics of each pixel region PXR may be improved.

Accordingly, an image sensor capable of improving charge transfer characteristics and charge storage capacity of a unit pixel may be provided.

6 is a plan view of an image sensor according to some embodiments of the present invention, and FIG. 7 is a plan view in which some components of FIG. 6 are omitted. 8a, 8b, 8c, and 8d are cross-sectional views along lines AA', BB', CC', and DD' of FIG. 3, respectively. For simplicity of explanation, differences from the image sensor described with reference to FIGS. 3, 4, 5A, and 5B will be mainly described.

6, 7, and 8A to 8D , the deep device isolation pattern 150 includes second extension portions 150P2 extending into each pixel area PXR along the first direction D1. can include more. The second extension parts 150P2 may be spaced apart from each other in the first direction D1 within each pixel area PXR. The length L2 of each of the second extension parts 150P2 along the first direction D1 is greater than the length L1 of each of the first extension parts 150P1 along the second direction D2. can be less than or equal to

One of the second extension portions 150P2 may extend into the first photoelectric conversion region 110a along the first direction D1, and the other of the second extension portions 150P2 may extend into the first photoelectric conversion region 110a. It may extend into the second photoelectric conversion region 110b along a direction opposite to the direction D1 . The one of the second extension parts 150P2 may be disposed between the first part 110a1 and the second part 110a2 of the first photoelectric conversion region 110a, and the second extension part 150P2 The other one may be disposed between the third portion 110b1 and the fourth portion 110b2 of the second photoelectric conversion region 110b. The first photoelectric conversion region 110a may continuously extend along the second direction D2 between the second extension parts 150P2. For example, the first part 110a1 and the second part 110a2 of the first photoelectric conversion region 110a may be continuously connected between the second extension parts 150P2. The second photoelectric conversion region 110b may continuously extend along the second direction D2 between the second extension parts 150P2. For example, the third portion 110b1 and the fourth portion 110b2 of the second photoelectric conversion region 110b may be continuously connected between the second extension portions 150P2.

The active patterns ACT may be spaced apart from each other in each pixel area PXR, and the shallow device isolation pattern 105 may be interposed between the active patterns ACT. The deep device isolation pattern 150 may pass through the shallow device isolation pattern 105 and extend into the substrate 100 . Each of the first extensions 150P1 of the deep device isolation pattern 150 may pass through the shallow device isolation pattern 105 and extend into each pixel region PXR, and the deep device isolation pattern 150 Each of the second extension portions 150P2 of ) may pass through the shallow device isolation pattern 105 and extend into each pixel region PXR. At least one of the active patterns ACT may be disposed between the first extension parts 150P1 and between the second extension parts 150P2. The rest of the active patterns ACT are the first part 110a1 and the second part 110a2 of the first photoelectric conversion region 110a, and the third part of the second photoelectric conversion region 110b. The portion 110b1 and the fourth portion 110b2 may be disposed to overlap each other vertically (eg, in the third direction D3).

A plurality of first transfer gate electrodes TG1, a floating diffusion region FD, and a plurality of second transfer gate electrodes TG2 are provided on each pixel region PXR and on the first transfer gate electrode of the substrate 100. It may be disposed adjacent to one side (100a). The floating diffusion region FD may be disposed in the corresponding active pattern ACT between the first extension portions 150P1 and between the second extension portions 150P2. The first transfer gate electrodes TG1 and the second transfer gate electrodes TG2 may be disposed adjacent to the floating diffusion region FD and may be disposed on the corresponding active pattern ACT. there is.

The first transfer gate electrodes TG1 may overlap the first photoelectric conversion region 110a vertically (eg, in the third direction D3). One of the first transfer gate electrodes TG1 may vertically overlap (eg, in the third direction D3) the first part 110a1 of the first photoelectric conversion region 110a, , The first portion 110a1 of the first photoelectric conversion region 110a and the floating diffusion region FD may be electrically connected. Another one of the first transfer gate electrodes TG1 may vertically overlap (eg, in the third direction D3) the second part 110a2 of the first photoelectric conversion region 110a. The second portion 110a2 of the first photoelectric conversion region 110a and the floating diffusion region FD may be electrically connected. The first transfer gate electrodes TG1 and the floating diffusion region FD may constitute the first transfer transistor TX1 of FIG. 2 . The first part 110a1 and the second part 110a2 of the first photoelectric conversion region 110a may be continuously connected under the first transfer gate electrodes TG1 along the second direction D2. can That is, the first photoelectric conversion region 110a may continuously extend under the first transfer gate electrodes TG1 along the second direction D2.

The second transfer gate electrodes TG2 may overlap the second photoelectric conversion region 110b vertically (eg, in the third direction D3). One of the second transfer gate electrodes TG2 may vertically overlap (eg, in the third direction D3) the third portion 110b1 of the second photoelectric conversion region 110b. , The third portion 110b1 of the second photoelectric conversion region 110b and the floating diffusion region FD may be electrically connected. Another one of the second transfer gate electrodes TG2 may vertically overlap (eg, in the third direction D3) the fourth portion 110b2 of the second photoelectric conversion region 110b. The fourth part 110b2 of the second photoelectric conversion region 110b and the floating diffusion region FD may be electrically connected. The second transfer gate electrodes TG2 and the floating diffusion region FD may configure the second transfer transistor TX2 of FIG. 2 . The third portion 110b1 and the fourth portion 110b2 of the second photoelectric conversion region 110b may be continuously connected under the second transfer gate electrodes TG2 along the second direction D2. can That is, the second photoelectric conversion region 110b may continuously extend under the second transfer gate electrodes TG2 along the second direction D2.

Except for the above-described difference, the image sensor according to the present embodiments is substantially the same as the image sensor described with reference to FIGS. 3, 4, 5A, and 5B.

According to the present embodiments, each pixel region PXR may include the first photoelectric conversion region 110a and the second photoelectric conversion region 110b adjacent to each other in the first direction D1, The deep device isolation pattern 150 includes the first extension portions 150P1 interposed between the first photoelectric conversion region 110a and the second photoelectric conversion region 110b, and the first photoelectric conversion region 110a. ) and the second extension parts 150P2 each extending into the second photoelectric conversion region 110b. In this case, each pixel region PXR includes the first part 110a1 and the second part 110a2 of the first photoelectric conversion region 110a, and the third part 110a2 of the second photoelectric conversion region 110b. Four photodiodes including the portion 110b1 and the fourth portion 110b2 may be included, and thus, the charge storage capacity of each pixel region PXR may be increased. In addition, the plurality of first transfer gate electrodes TG1 may be disposed on the first photoelectric conversion region 110a to electrically connect the first photoelectric conversion region 110a and the floating diffusion region FD. and the plurality of second transfer gate electrodes TG2 are disposed on the second photoelectric conversion region 110b to electrically connect the second photoelectric conversion region 110b and the floating diffusion region FD. there is. At least two first transfer gate electrodes TG1 are disposed on the first photoelectric conversion region 110a, and at least two second transfer gate electrodes TG2 are disposed on the second photoelectric conversion region 110b. , charge transfer characteristics of each pixel region PXR may be improved.

9 is a plan view of an image sensor according to some embodiments of the present invention, and FIG. 10 is a plan view in which some components of FIG. 9 are omitted. Fig. 11 is a cross-sectional view taken along line C-C' of Fig. 9; Sections along AA', BB', and D-D' of FIG. 9 are substantially the same as those of FIGS. 8A, 8B, and 8D, respectively. For simplicity of description, differences from the image sensor described with reference to FIGS. 6, 7, and 8A to 8D will be mainly described.

9, 10, and 11 , the first transfer gate electrodes TG1 may overlap the first photoelectric conversion region 110a vertically (eg, in the third direction D3). can Each of the first transfer gate electrodes TG1 may electrically connect the first photoelectric conversion region 110a and the floating diffusion region FD. According to some embodiments, three first transfer gate electrodes TG1 may be disposed on the first photoelectric conversion region 110a, and the first photoelectric conversion region 110a and the floating diffusion region ( FD) can be electrically connected. The first transfer gate electrodes TG1 and the floating diffusion region FD may constitute the first transfer transistor TX1 of FIG. 2 . The first photoelectric conversion region 110a may continuously extend under the first transfer gate electrodes TG1 along the second direction D2.

The second transfer gate electrodes TG2 may overlap the second photoelectric conversion region 110b vertically (eg, in the third direction D3). Each of the second transfer gate electrodes TG2 may electrically connect the second photoelectric conversion region 110b and the floating diffusion region FD. According to some embodiments, three second transfer gate electrodes TG2 may be disposed on the second photoelectric conversion region 110b, and the second photoelectric conversion region 110b and the floating diffusion region ( FD) can be electrically connected. The second transfer gate electrodes TG2 and the floating diffusion region FD may configure the second transfer transistor TX2 of FIG. 2 . The second photoelectric conversion region 110b may continuously extend under the second transfer gate electrodes TG2 along the second direction D2.

Except for the above-mentioned difference, the image sensor according to the present embodiments is substantially the same as the image sensor described with reference to FIGS. 6, 7, and 8A to 8D.

12 and 13 are cross-sectional views corresponding to line C-C' of FIG. 9 illustrating an image sensor according to some embodiments of the present invention.

Referring to FIGS. 9, 12, and 13 , lower portions of each of the first transfer gate electrodes TG1 may extend into the substrate 100 toward the first photoelectric conversion region 110a, An upper portion of each of the first transfer gate electrodes TG1 may protrude above a corresponding top surface of the active pattern ACT (ie, the first surface 100a of the substrate 100). According to some embodiments, upper portions of neighboring first transfer gate electrodes TG1 among the first transfer gate electrodes TG1 may be connected to each other. For example, as shown in FIG. 12 , an upper portion of one of the first transfer gate electrodes TG1 may be spaced apart from upper portions of the other of the first transfer gate electrodes TG1 , and the first transfer gate electrodes TG1 may be spaced apart from each other. The upper portions of the remaining transfer gate electrodes TG1 may be connected to each other. As another example, as shown in FIG. 13 , upper portions of all of the first transfer gate electrodes TG1 may be connected to each other.

Lower portions of each of the second transfer gate electrodes TG2 may extend into the substrate 100 toward the second photoelectric conversion region 110b, and each of the second transfer gate electrodes TG2 may extend into the substrate 100 . An upper portion of may protrude above the top surface of the corresponding active pattern ACT (ie, the first surface 100a of the substrate 100). According to some embodiments, upper portions of neighboring second transfer gate electrodes TG2 among the second transfer gate electrodes TG2 may be connected to each other. For example, similar to that shown in FIG. 12 , an upper portion of one of the second transfer gate electrodes TG2 may be spaced apart from upper portions of the other of the second transfer gate electrodes TG2 , and The upper portions of the remaining of the two transfer gate electrodes TG2 may be connected to each other. As another example, similar to that shown in FIG. 13 , upper portions of all of the second transfer gate electrodes TG2 may be connected to each other.

14 is a plan view of an image sensor according to some embodiments of the present invention, and FIG. 15 is a plan view in which some components of FIG. 14 are omitted. 16 is a cross-sectional view taken along line C-C' of FIG. 14; Sections along AA', BB', and D-D' of FIG. 14 are substantially the same as those of FIGS. 8A, 8B, and 8D, respectively. For simplicity of description, differences from the image sensor described with reference to FIGS. 6, 7, and 8A to 8D will be mainly described.

14, 15, and 16, the first transfer gate electrodes TG1 may overlap the first photoelectric conversion region 110a vertically (eg, in the third direction D3). can Each of the first transfer gate electrodes TG1 may electrically connect the first photoelectric conversion region 110a and the floating diffusion region FD. According to some embodiments, four first transfer gate electrodes TG1 may be disposed on the first photoelectric conversion region 110a, and the first photoelectric conversion region 110a and the floating diffusion region ( FD) can be electrically connected. The first transfer gate electrodes TG1 and the floating diffusion region FD may constitute the first transfer transistor TX1 of FIG. 2 . The first photoelectric conversion region 110a may continuously extend under the first transfer gate electrodes TG1 along the second direction D2.

The second transfer gate electrodes TG2 may overlap the second photoelectric conversion region 110b vertically (eg, in the third direction D3). Each of the second transfer gate electrodes TG2 may electrically connect the second photoelectric conversion region 110b and the floating diffusion region FD. According to some embodiments, four second transfer gate electrodes TG2 may be disposed on the second photoelectric conversion region 110b, and the second photoelectric conversion region 110b and the floating diffusion region ( FD) can be electrically connected. The second transfer gate electrodes TG2 and the floating diffusion region FD may configure the second transfer transistor TX2 of FIG. 2 . The second photoelectric conversion region 110b may continuously extend under the second transfer gate electrodes TG2 along the second direction D2.

Except for the above-mentioned difference, the image sensor according to the present embodiments is substantially the same as the image sensor described with reference to FIGS. 6, 7, and 8A to 8D.

17 and 18 are cross-sectional views corresponding to line C-C' of FIG. 14 illustrating image sensors according to some embodiments of the present invention.

14, 17, and 18, lower portions of each of the first transfer gate electrodes TG1 may extend into the substrate 100 toward the first photoelectric conversion region 110a, An upper portion of each of the first transfer gate electrodes TG1 may protrude above a corresponding top surface of the active pattern ACT (ie, the first surface 100a of the substrate 100). According to some embodiments, upper portions of neighboring first transfer gate electrodes TG1 among the first transfer gate electrodes TG1 may be connected to each other. For example, as shown in FIG. 17 , upper portions of a pair of first transfer gate electrodes TG1 among the first transfer gate electrodes TG1 may be connected to each other, and the first transfer gate electrodes ( Upper portions of the other pair of first transfer gate electrodes TG1 of TG1) may be connected to each other. Upper portions of the pair of first transfer gate electrodes TG1 may be spaced apart from upper portions of the other pair of first transfer gate electrodes TG1 . As another example, as shown in FIG. 18 , upper portions of all of the first transfer gate electrodes TG1 may be connected to each other.

Lower portions of each of the second transfer gate electrodes TG2 may extend into the substrate 100 toward the second photoelectric conversion region 110b, and each of the second transfer gate electrodes TG2 may extend into the substrate 100 . An upper portion of may protrude above the top surface of the corresponding active pattern ACT (ie, the first surface 100a of the substrate 100). According to some embodiments, upper portions of neighboring second transfer gate electrodes TG2 among the second transfer gate electrodes TG2 may be connected to each other. For example, as shown in FIG. 17 , upper portions of a pair of second transfer gate electrodes TG2 among the second transfer gate electrodes TG2 may be connected to each other, and the second transfer gate electrodes may be connected to each other. Upper portions of the other pair of second transfer gate electrodes TG2 of (TG2) may be connected to each other. Upper portions of the pair of second transfer gate electrodes TG2 may be spaced apart from upper portions of the other pair of second transfer gate electrodes TG2 . As another example, similar to that shown in FIG. 18 , upper portions of all of the second transfer gate electrodes TG2 may be connected to each other.

19A to 21A are views illustrating a method of manufacturing an image sensor according to some embodiments of the present invention, and are cross-sectional views corresponding to line AA′ of FIG. 3 . 19B to 21AB are views illustrating a method of manufacturing an image sensor according to some embodiments of the present invention, and are cross-sectional views corresponding to line BB′ of FIG. 3 . For simplicity of description, descriptions overlapping with those of the image sensor described with reference to FIGS. 3, 4, 5A, and 5B are omitted.

Referring to FIGS. 3, 4, 19a and 19b , a substrate 100 having a first surface 100a and a second surface 100b facing each other may be provided. The substrate 100 may have a first conductivity type (eg, P type). A first trench T1 may be formed adjacent to the first surface 100a of the substrate 100 . Forming the first trench T1 includes forming a first mask pattern 103 on the first surface 100a of the substrate 100, and etching the first mask pattern 103. It may include etching the substrate 100 by using it as a mask. The first trench T1 may define active patterns ACT in the substrate 100 .

An element isolation layer 105L may be formed on the first surface 100a of the substrate 100 . The device isolation layer 105L may cover the first mask pattern 103 and fill the first trench T1. The device isolation layer 105L may include, for example, a silicon oxide layer, a silicon nitride layer, and/or a silicon oxynitride layer.

A second trench T2 may be formed in the substrate 100 . Forming the second trench T2 may include forming a second mask pattern (not shown) defining a region where the second trench T2 is to be formed on the device isolation layer 105L, and 2 may include etching the device isolation layer 105L and the substrate 100 using the mask pattern as an etching mask.

The second trench T2 may define a plurality of pixel regions PXR in the substrate 100 . The plurality of pixel regions PXR may be arranged along the first direction D1 and the second direction D2. The second trench T2 may surround each pixel region PXR in a plan view. The second trench T2 may extend to surround each pixel area PXR along the first and second directions D1 and D2 . Each of the plurality of pixel regions PXR may include the active patterns ACT defined by the first trench T1. The second trench T2 may include first extension trenches ET1 extending into each pixel region PXR. The first extension trenches ET1 may extend in the second direction D2 in each pixel area PXR and may be spaced apart from each other in the second direction D2. According to some embodiments, as described with reference to FIG. 6 , the second trench T2 may further include second extension trenches extending into each pixel region PXR. The second extension trenches may extend in the first direction D1 in each pixel area PXR and may be spaced apart from each other in the first direction D1.

Referring to FIGS. 3, 4, 20A and 20B , a deep device isolation pattern 150 filling the second trench T2 may be formed. The deep device isolation pattern 150 includes a side insulating pattern 156 conformally covering the inner surface of the second trench T2, semiconductor patterns 152 and 154 filling the lower portion of the second trench T2, and A buried insulating pattern 158 filling a remainder of the second trench T2 may be provided on the semiconductor patterns 152 and 154 . The semiconductor patterns 152 and 154 include a first semiconductor pattern 152 filling a portion of the second trench T2 and a second semiconductor between the first semiconductor pattern 152 and the side insulating pattern 156. pattern 154. The deep device isolation pattern 150 may include first extension portions 150P1 filling the first extension trenches ET1. According to some embodiments, the deep device isolation pattern 150 may further include second extension portions 150P2 filling the second extension trenches, as described with reference to FIG. 6 .

Forming the deep device isolation pattern 150 may include, for example, forming a side insulating layer conformally covering the inner surface of the second trench T2 on the device isolation layer 105L, or forming a side insulating layer on the side insulating layer. Forming a second semiconductor layer that partially fills the second trench T2, anisotropically etching the second semiconductor layer to form the second semiconductor pattern 154, and forming the second semiconductor pattern 154 on the second semiconductor pattern 154. Forming a first semiconductor layer filling the second trench T2, forming the first semiconductor pattern 152 by etching-backing the first semiconductor layer, and filling a remainder of the second trench T2. The filling insulating layer may be formed, and the filling insulating layer and the side insulating layer may be planarized to form the filling insulating pattern 158 and the side insulating pattern 156 . Forming the second semiconductor pattern 154 may further include, for example, implanting impurities of the first conductivity type (eg, P-type impurities) into the second semiconductor pattern 154 . The planarization process for forming the buried insulating pattern 158 and the side insulating pattern 156 is performed until the first surface 100a of the substrate 100 is exposed. This may include planarizing the device isolation layer 105L. By the planarization process, the first mask pattern 103 may be removed and a shallow device isolation pattern 105 filling the first trench T1 may be formed.

The first photoelectric conversion region 110a and the second photoelectric conversion region 110b may be formed in each pixel region PXR. The first photoelectric conversion region 110a and the second photoelectric conversion region 110b may be adjacent to each other in the first direction D1 within each pixel region PXR. The first extensions 150P1 of the deep device isolation pattern 150 may be interposed between the first photoelectric conversion region 110a and the second photoelectric conversion region 110b. The first extension parts 150P1 may extend in the second direction D2 between the first photoelectric conversion region 110a and the second photoelectric conversion region 110b, and extend in the second direction D2. can be spaced apart from each other. According to some embodiments, as described with reference to FIGS. 6 and 7 , the second extension portions 150P2 of the deep device isolation pattern 150 may include the first photoelectric conversion region 110a and the second extension portions 150P2 . Each may extend into the photoelectric conversion region 110b. Each of the first photoelectric conversion region 110a and the second photoelectric conversion region 110b may continuously extend in the second direction D2 between the second extension portions 150P2.

Forming the first and second photoelectric conversion regions 110a and 110b is, for example, a second conductivity type (eg, P-type) different from the first conductivity type (eg, P-type) in the substrate 100 . , N-type) impurities may be implanted.

A thinning process may be performed on the second surface 100b of the substrate 100, and portions of the substrate 100 and the deep device isolation pattern 150 may be removed by the thinning process. The thinning process may include, for example, grinding or polishing the second surface 100b of the substrate 100 and/or anisotropic and/or isotropic etching. The lower portion of the deep device isolation pattern 150 may be removed by the thinning process, and the lower surface 150L of the deep device isolation pattern 150 may substantially overlap the second surface 100b of the substrate 100. It is possible to achieve common ground with

Referring to FIGS. 3, 4, 21A and 21B , a plurality of first transfer gate electrodes TG1, a first floating diffusion region FD1, a plurality of second transfer gate electrodes TG2 and a second A floating diffusion region FD2 may be formed on each pixel region PXR and adjacent to the first surface 100a of the substrate 100 . The first transfer gate electrodes TG1 and the first floating diffusion region FD1 may be formed on a corresponding active pattern ACT among the active patterns ACT, and the first photoelectric conversion region ( 110a) and vertically (eg, in the third direction D3). The second transfer gate electrodes TG2 and the second floating diffusion region FD2 may be formed on a corresponding active pattern ACT among the active patterns ACT, and the second photoelectric conversion region ( 110b) and vertically (eg, in the third direction D3). According to some embodiments, as described with reference to FIGS. 6 and 7 , the floating diffusion region FD is between the first extension portions 150P1 of the deep device isolation pattern 150 and the deep device isolation region FD. It may be formed on the corresponding active pattern ACT between the second extension parts 150P2 of the pattern 150, and a plurality of first transfer gate electrodes TG1 may be formed on the first photoelectric conversion region 110a. overlapping with the second photoelectric conversion region 110b vertically (eg, in the third direction D3), and the plurality of second transfer gate electrodes TG2 perpendicularly (eg, in the third direction D3) with the second photoelectric conversion region 110b. in three directions (D3)) may be formed to overlap.

Lower portions of each of the first and second transfer gate electrodes TG1 and TG2 may pass through the corresponding active pattern ACT and extend into the substrate 100 . Upper portions of each of the first and second transfer gate electrodes TG1 and TG2 protrude above the corresponding upper surface of the active pattern ACT (ie, the first surface 100a of the substrate 100). can The first and second floating diffusion regions FD1, FD2, or the floating diffusion region FD have a second conductivity different from the first conductivity type of the substrate 100 within the corresponding active pattern ACT. It may be formed by doping with type impurities (eg, N-type impurities).

A first gate dielectric pattern GI1 may be formed between each of the first transfer gate electrodes TG1 and the substrate 100 (that is, the corresponding active pattern ACT), and a second gate dielectric pattern ( GI2) may be formed between each of the second transfer gate electrodes TG2 and the substrate 100 (that is, the corresponding active pattern ACT).

A plurality of gate electrodes GE and source/drain regions SD may be formed on each pixel region PXR and adjacent to the first surface 100a of the substrate 100 . The gate electrodes GE and the source/drain regions SD may be formed on corresponding active patterns ACT, and the first photoelectric conversion region 110a or the second photoelectric conversion region ( 110b) and vertically (eg, in the third direction D3). The source/drain regions SD may be formed by doping the corresponding active patterns ACT with impurities of the second conductivity type (eg, N-type impurities). A gate dielectric pattern GI may be formed between each of the gate electrodes GE and the substrate 100 (that is, the corresponding active pattern ACT).

A first interlayer insulating film 210 may be formed on the first surface 100a of the substrate 100, and the first and second transfer gate electrodes TG1 and TG2 and the gate electrodes GE ) can be covered. Some of the contact plugs 220 may be formed in the first interlayer insulating layer 210 and pass through the first interlayer insulating layer 210 to form the first and second floating diffusion regions FD1 , FD2 , or It may be connected to the floating diffusion region FD) and the source/drain regions SD. A second interlayer insulating layer 240 may be formed on the first interlayer insulating layer 210 . The rest of the contact plugs 220 and the conductive lines 230 may be formed in the second interlayer insulating layer 240 . The rest of the contact plugs 220 pass through the first interlayer insulating film 210 and the second interlayer insulating film 240 to form the first and second transfer gate electrodes TG1 and TG2 and the gate electrodes. (GE). The conductive lines 230 may be connected to the contact plugs 220 .

Referring again to FIGS. 3, 4, 5A, and 5B , an anti-reflection film 310 and a first insulating film 312 may be sequentially formed on the second surface 100b of the substrate 100. . A color filter array 320 may be formed on the first insulating layer 312 . The color filter array 320 may include a plurality of color filters 320 , and the plurality of color filters 320 may be respectively disposed on the plurality of pixel regions PXR. Each of the plurality of color filters 320 is perpendicular to the first and second photoelectric conversion regions 110a and 110b of each pixel region PXR (eg, in the third direction D3). It can be formed to overlap.

A second insulating layer 322 may be formed on the color filter array 320 , and a micro lens array 330 may be formed on the second insulating layer 322 . The micro lens array 330 may include a plurality of micro lenses 330 respectively disposed on the plurality of color filters 320 . Each of the plurality of micro lenses 330 is perpendicular to the first and second photoelectric conversion regions 110a and 110b of each pixel region PXR (eg, in the third direction D3). It can be formed to overlap.

22 is a plan view of an image sensor according to some embodiments of the present invention, and FIG. 23 is a cross-sectional view taken along the line II′ of FIG. 22 . For simplicity of explanation, differences from the image sensor described with reference to FIGS. 3, 4, 5A, and 5B will be mainly described.

22 and 23 , the image sensor includes a substrate 100 including a pixel array area AR, an optical black area OB, and a pad area PR, and a first surface of the substrate 100 ( The wiring layer 20 on 100a), the base substrate 40 on the wiring layer 20, and the light transmitting layer 30 on the second surface 100b of the substrate 100 may be included. The wiring layer 20 may be disposed between the first surface 100a of the substrate 100 and the base substrate 40 . The wiring layer 20 includes an upper wiring layer 21 adjacent to the first surface 100a of the substrate 100 and a lower wiring layer 23 between the upper wiring layer 21 and the base substrate 40. can include The pixel array region AR may include a plurality of pixel regions PXR and a deep device isolation pattern 150 disposed between them. The pixel array area may be configured substantially the same as the image sensor described with reference to FIGS. 1 to 18 .

A first connection structure 50 , a first contact 81 , and a bulk color filter 90 may be disposed on the optical black area OB of the substrate 100 . The first connection structure 50 may include a first light blocking pattern 51 , a first separation pattern 53 , and a first capping pattern 55 . The first light blocking pattern 51 may be disposed on the second surface 100b of the substrate 100 . The first blocking pattern 51 may cover the first insulating layer 312 and conformally cover inner walls of each of the third trench TR3 and the fourth trench TR4 . The first light blocking pattern 51 may pass through the photoelectric conversion layer 10 and the upper wiring layer 21 . The first light blocking pattern 51 may be connected to the semiconductor patterns 152 and 154 of the deep device isolation pattern 150 of the photoelectric conversion layer 10, and the upper wiring layer 21 and the lower wiring layer ( 23) can be connected to the wires in. Accordingly, the first connection structure 50 may electrically connect the photoelectric conversion layer 10 and the wiring layer 20 . The first light blocking pattern 51 may include a metal material (eg, tungsten). The first light blocking pattern 51 may block light incident into the optical black area OB.

The first contact 81 may fill the remainder of the third trench TR3 . The first contact 81 may include a metal material (eg, aluminum). The first contact 81 may be connected to the semiconductor patterns 152 and 154 of the deep device isolation pattern 150 . A bias may be applied to the semiconductor patterns 152 and 154 through the first contact 81 . The first separation pattern 53 may fill the remainder of the fourth trench TR4 . The first separation pattern 53 may pass through the photoelectric conversion layer 10 and may pass through a portion of the wiring layer 20 . The first separation pattern 53 may include an insulating material. The first capping pattern 55 may be disposed on the first separation pattern 53 . The first capping pattern 55 may include the same material as the buried insulating pattern 158 of the deep device isolation pattern 150 .

The bulk color filter 90 may be disposed on the first connection structure 50 and the first contact 81 . The bulk color filter 90 may cover the first connection structure 50 and the first contact 81 . A first passivation layer 71 may be disposed on the bulk color filter 90 to seal the bulk color filter 90 .

An additional photoelectric conversion region 110 ′ and a dummy region 111 may be provided in corresponding pixel regions PXR of the optical black region OB. The additional photoelectric conversion region 110 ′ may be a region doped with impurities of a second conductivity type different from the first conductivity type of the substrate 100 (eg, N-type impurities). The additional photoelectric conversion region 110 ′ is photoelectric conversion regions 110 in the plurality of pixel regions PXR of the pixel array region AR, for example, the first and second photoelectric conversion regions 110a. , 110b)), but may not perform the same operation as the photoelectric conversion regions 110 (that is, generate an electrical signal by receiving light). The dummy region 111 may not be doped with impurities.

A second connection structure 60 , a second contact 83 , and a second passivation layer 73 may be disposed on the pad region PR of the substrate 100 . The second connection structure 60 may include a second light blocking pattern 61 , a second separation pattern 63 , and a second capping pattern 65 .

The second blocking pattern 61 may be disposed on the second surface 100b of the substrate 100 . The second blocking pattern 61 may cover the first insulating layer 312 and conformally cover inner walls of each of the fifth trench TR5 and the sixth trench TR6 . The second blocking pattern 61 may pass through the photoelectric conversion layer 10 and the upper wiring layer 21 . The second light blocking pattern 61 may be connected to wirings in the lower wiring layer 23 . Accordingly, the second connection structure 60 may electrically connect the photoelectric conversion layer 10 and the wiring layer 20 . The second blocking pattern 61 may include a metal material (eg, tungsten). The second light blocking pattern 61 may block light incident into the pad region PR.

The second contact 83 may fill the remainder of the fifth trench TR5 . The second contact 83 may include a metal material (eg, aluminum). The second contact 83 may serve as an electrical connection path between the image sensor and an external device. The second separation pattern 63 may fill the remainder of the sixth trench TR6 . The second separation pattern 63 may pass through the photoelectric conversion layer 10 and may pass through a portion of the wiring layer 20 . The second separation pattern 63 may include an insulating material. The second capping pattern 65 may be disposed on the second separation pattern 63 . The second capping pattern 65 may include the same material as the buried insulating pattern 158 of the deep device isolation pattern 150 . The second passivation layer 73 may cover the second connection structure 60 .

The current applied through the second contact 83 passes through the second light blocking pattern 61 , wirings in the wiring layer 20 , and the first light blocking pattern 51 to the deep device isolation pattern 150 . may flow to the semiconductor patterns 152 and 154 of. Electrical signals generated from the photoelectric conversion regions 110 (eg, the first and second photoelectric conversion regions 110a and 110b) in the plurality of pixel regions PXR of the pixel array region AR are Light may be transmitted to the outside through the wirings in the wiring layer 20 , the second light blocking pattern 61 , and the second contact 83 .

The above description of embodiments of the present invention provides examples for explaining the present invention. Therefore, the present invention is not limited to the above embodiments, and many modifications and changes, such as combining and implementing the above embodiments, are possible by those skilled in the art within the technical spirit of the present invention. It's obvious.

Claims (20)

a substrate including a pixel area;
a first photoelectric conversion region and a second photoelectric conversion region disposed in the pixel region of the substrate and adjacent to each other in a first direction;
a deep device isolation pattern penetrating the substrate and surrounding the pixel region, the deep device isolation pattern extending in a second direction intersecting the first direction between the first photoelectric conversion region and the second photoelectric conversion region; including first extensions, wherein the first extensions are spaced apart from each other in the second direction;
a plurality of first transfer gate electrodes disposed on the pixel region of the substrate and vertically overlapping the first photoelectric conversion region; and
a plurality of second transfer gate electrodes disposed on the pixel region of the substrate and vertically overlapping the second photoelectric conversion region;
The first photoelectric conversion region extends under the plurality of first transfer gate electrodes in the second direction. The method of claim 1,
The second photoelectric conversion region extends under the plurality of second transfer gate electrodes in the second direction. The method of claim 1,
A length of each of the first extension parts along the second direction is greater than a distance between the first extension parts along the second direction. The method of claim 1,
further comprising a first floating diffusion region and a second floating diffusion region disposed in the pixel region and spaced apart from each other in the first direction with one of the first extensions of the deep device isolation pattern interposed therebetween;
The plurality of first transfer gate electrodes are disposed adjacent to the first floating diffusion region, and the plurality of second transfer gate electrodes are disposed adjacent to the second floating diffusion region. The method of claim 1,
A lower portion of each of the plurality of first transfer gate electrodes extends into the substrate toward the first photoelectric conversion region,
A lower portion of each of the plurality of second transfer gate electrodes extends into the substrate toward the second photoelectric conversion region. The method of claim 1,
The deep device isolation pattern further includes second extensions extending in the first direction;
The second extension parts are spaced apart from each other in the first direction,
One of the second extension parts extends into the first photoelectric conversion area, and the other of the second extension parts extends into the second photoelectric conversion area. The method of claim 6,
A length of each of the second extension parts along the first direction is less than or equal to a length of each of the first extension parts along the second direction. The method of claim 6,
Further comprising a floating diffusion region disposed in the pixel region and disposed between the first extension parts and between the second extension parts,
The plurality of first transfer gate electrodes and the plurality of second transfer gate electrodes are disposed adjacent to the floating diffusion region. The method of claim 8,
one of the plurality of first transfer gate electrodes electrically connects a first portion of the first photoelectric conversion region and the floating diffusion region;
Another one of the plurality of first transfer gate electrodes electrically connects a second portion of the first photoelectric conversion region and the floating diffusion region;
wherein the one of the second extension parts extends between the first part and the second part of the first photoelectric conversion region. The method of claim 9,
The first part and the second part of the first photoelectric conversion region are continuously connected under the plurality of first transfer gate electrodes. The method of claim 9,
one of the plurality of second transfer gate electrodes electrically connects a third portion of the second photoelectric conversion region and the floating diffusion region;
Another one of the plurality of second transfer gate electrodes electrically connects a fourth portion of the second photoelectric conversion region and the floating diffusion region;
The other one of the second extension parts extends between the third part and the fourth part of the second photoelectric conversion region. The method of claim 11,
The third part and the fourth part of the second photoelectric conversion region are continuously connected under the second transfer gate electrodes. The method of claim 8,
Each of the plurality of first transfer gate electrodes includes a lower part extending into the substrate toward the first photoelectric conversion region and an upper part protruding above the substrate;
Upper portions of neighboring first transfer gate electrodes among the plurality of first transfer gate electrodes are connected to each other. The method of claim 13,
Each of the plurality of second transfer gate electrodes includes a lower portion extending into the wave toward the second photoelectric conversion region and an upper portion protruding above the substrate;
Upper portions of neighboring second transfer gate electrodes among the plurality of second transfer gate electrodes are connected to each other. a substrate having first and second surfaces facing each other, the substrate including a pixel area;
A deep device isolation pattern penetrating the substrate along a direction perpendicular to the first surface, the deep device isolation pattern surrounding the pixel area along first and second directions that are parallel to the first surface and cross each other. that;
A first photoelectric conversion region and a second photoelectric conversion region disposed in the pixel region of the substrate and adjacent to each other in the first direction, and the deep device isolation pattern are interposed between the first photoelectric conversion region and the second photoelectric conversion region. including first extensions extending in the second direction, the first extensions being spaced apart from each other in the second direction;
a plurality of first transfer gate electrodes disposed on the pixel region of the substrate and on the first photoelectric conversion region; and
a plurality of second transfer gate electrodes disposed on the pixel region of the substrate and on the second photoelectric conversion region;
The first photoelectric conversion region extends from one side of one of the first extensions to one side of the other of the first extensions along the second direction;
The second photoelectric conversion region extends from the other side of the one of the first extension parts to the other side of the other one of the first extension parts along the second direction. The method of claim 15
A length of each of the first extension parts along the second direction is greater than a distance between the first extension parts along the second direction. The method of claim 15
The deep device isolation pattern further includes second extension portions extending into the pixel area along the first direction and spaced apart from each other in the first direction;
One of the second extension parts extends into the first photoelectric conversion area, and the other of the second extension parts extends into the second photoelectric conversion area. The method of claim 17
the substrate further comprises a floating diffusion region disposed between the first extensions and between the second extensions;
The plurality of first transfer gate electrodes and the plurality of second transfer gate electrodes are disposed adjacent to the floating diffusion region. The method of claim 18
one of the plurality of first transfer gate electrodes is disposed on a first portion of the first photoelectric conversion region;
Another one of the plurality of first transfer gate electrodes is disposed on a second portion of the first photoelectric conversion region;
the one of the second extension parts extends between the first part and the second part of the first photoelectric conversion region;
The first part and the second part of the first photoelectric conversion region are continuously connected under the first transfer gate electrodes. The method of claim 19
one of the plurality of second transfer gate electrodes is disposed on a third portion of the second photoelectric conversion region;
Another one of the plurality of second transfer gate electrodes is disposed on a fourth portion of the second photoelectric conversion region;
The other one of the second extension parts extends between the third part and the fourth part of the second photoelectric conversion region;
The third part and the fourth part of the second photoelectric conversion region are continuously connected under the second transfer gate electrodes.

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