KR20230125135A - Semiconductor device - Google Patents

Abstract

A semiconductor device capable of improving device performance and reliability is provided. A semiconductor device includes: an active region within a substrate, an element isolation film defining the active region within the substrate, an isolation impurity region including impurities of a first conductivity type within the substrate under the element isolation film, and extending in a first direction on the active region. a first gate electrode, a first source region disposed in the active region on one side of the first gate electrode, and a drain region disposed in the active region on the other side of the first gate electrode, wherein the device isolation layer surrounds the active region; 1 includes a peripheral portion and a first protrusion extending from the peripheral portion in a first direction and protruding toward the drain region, wherein the separation impurity region includes a second peripheral portion overlapping the first peripheral portion and a first protruding portion overlapping the first protruding portion. and the second protrusion, and in the first direction, the length of the drain region is smaller than the length of the first source region.

Description

Semiconductor device

The present invention relates to semiconductor devices. More specifically, the present invention relates to semiconductor devices including high voltage transistors.

A semiconductor device may include transistors of various sizes driven at various voltages. Among various transistors, a high voltage transistor driven at a high voltage may require a thick gate dielectric layer. In addition, the source/drain of the high voltage transistor has a lightly doped drain (LDD) structure or DDD ( Double Doped Drain) structure.

An object to be solved by the present invention is to provide a semiconductor device with improved performance and reliability.

The technical problems of the present invention are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description.

One aspect of the semiconductor device of the present invention for solving the above problems is an active region in a substrate, an element isolation film defining the active region in the substrate, and a first conductivity type impurity in the substrate under the element isolation film. On the separation impurity region, a first gate electrode extending in a first direction on the active region, a first source region disposed in the active region on one side of the first gate electrode, and a drain disposed in the active region on the other side of the first gate electrode A region, wherein the device isolation layer includes a first circumferential portion surrounding the active region and a first protrusion extending in a first direction from the circumferential portion and protruding toward the drain region, and the isolation impurity region comprises the first circumferential portion and and an overlapping second peripheral portion and a second protrusion overlapping the first protrusion, wherein in a first direction, a length of the drain region is less than a length of the first source region.

Another aspect of the semiconductor device of the present invention for solving the above problems is a substrate, first to third active regions arranged along a first direction within the substrate, and a second active region in a second direction crossing the first direction. first to third active regions having a length smaller than the lengths of the first and third active regions, a first gate electrode extending in a second direction on the first active region, and a first conductivity type in the second active region A drain region including impurities of a second gate electrode extending in a second direction on the third active region, and a first source region including impurities of a first conductivity type in the first active region. A first source region in which a first gate electrode is disposed between the first source region and the drain region, and a second source region including impurities of the first conductivity type in the second active region, the second gate electrode between the second source region and the drain region. Between the second source region and the first gate electrode and the second gate electrode, a separated impurity region is disposed along the drain region and the first direction and includes impurities of a second conductivity type different from the first conductivity type. include

Details of other embodiments of the invention are included in the detailed description and drawings.

1 is a layout diagram of a semiconductor memory device according to some embodiments.
FIG. 2 is a cross-sectional view taken along line C1 - C1 of FIG. 1 .
FIG. 3 is a cross-sectional view taken along line C2 - C2 of FIG. 1 .
4 is a layout diagram of a semiconductor memory device according to some embodiments.
5 is a layout diagram of a semiconductor memory device according to some embodiments.
6 is a layout diagram of a semiconductor memory device according to some embodiments.
7 to 17 are diagrams for explaining a method of manufacturing a semiconductor memory device according to some embodiments.

In this specification, although first, second, etc. are used to describe various elements or components, these elements or components are not limited by these terms, of course. These terms are only used to distinguish one element or component from another. Accordingly, it goes without saying that the first element or component mentioned below may also be the second element or component within the technical spirit of the present invention.

In the drawing of the semiconductor device according to some embodiments, a planar transistor is illustrated as an example, but is not limited thereto. A semiconductor device according to some embodiments includes a fin-type transistor (FinFET) including a channel region having a fin-type pattern shape, a transistor including nanowires or nanosheets, a multi-bridge channel field effect transistor (MBCFET ^TM ), or a vertical transistor (Vertical Transistor). FET), a tunneling transistor (tunneling FET), or a three-dimensional (3D) transistor. In addition, the technical concept of the present invention can be applied to transistors based on 2D materials (2D material based FETs) and heterostructures thereof. Also, a semiconductor device according to some embodiments may include a bipolar junction transistor, a lateral double diffusion transistor (LDMOS), or the like.

1 is a layout diagram of a semiconductor memory device according to some embodiments. FIG. 2 is a cross-sectional view taken along line C1 - C1 of FIG. 1 . FIG. 3 is a cross-sectional view taken along line C2 - C2 of FIG. 1 .

1 to 3 , a semiconductor device according to some embodiments includes a substrate 100, an isolation layer 701, an active region 501, an isolation impurity region 601, a first gate electrode 401, The second gate electrode 402, the gate dielectric layer 410, the gate spacer 420, the first source region 221, the second source region 222, the drain region 321, the interlayer insulating layer 111, and the source contact 210 and a drain contact 310 .

The substrate 100 may include a base substrate and an epitaxial layer grown on the base substrate, but is not limited thereto. For example, the substrate 100 may include only a base substrate without an epitaxial layer. The substrate 100 may be a silicon substrate, a gallium arsenide substrate, a silicon germanium substrate, a ceramic substrate, a quartz substrate, a glass substrate for a display, or a semiconductor on insulator (SOI) substrate. Hereinafter, the substrate 100 will be described as being a silicon substrate by way of example.

In some embodiments, the substrate 100 may be doped with a first conductivity type. For example, the first conductivity type may be a p-type. For example, the substrate 100 may include p-type impurities.

In some embodiments, the substrate 100 may include a first impurity region 801 and a second impurity region 802 . A first impurity region 801 and a second impurity region 802 may be sequentially formed below the separated impurity region 601 . For example, the first impurity region 801 may be interposed between the separated impurity region 601 and the second impurity region 802 .

The first impurity region 801 may be doped with impurities of the first conductivity type, and the second impurity region 802 may be doped with a second conductivity type different from the first conductivity type. For example, the first impurity region 801 may be a p-well containing p-type impurities, and the second impurity region 802 may be an n-well containing n-type impurities. can

The device isolation layer 701 may define an active region 501 in the substrate 100 . For example, the device isolation layer 701 may surround the active region 501 in a plan view. The device isolation layer 701 may be formed by filling an insulating material in a shallow trench formed in the substrate 100 . The device isolation layer 701 may include at least one of an insulating material, for example, silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof, but is not limited thereto.

Although the device isolation layer 701 is illustrated as being formed of a single layer, this is only exemplary. For example, it goes without saying that the device isolation layer 701 may be formed of a multi-layer.

The isolation impurity region 601 may be formed in the substrate 100 . In addition, the isolation impurity region 601 may overlap the device isolation layer 701 in a direction crossing the top surface of the substrate 100 (hereinafter, a vertical direction). That is, the isolation impurity region 601 may be formed in the substrate 100 disposed under the device isolation layer 701 (ie, disposed on a lower surface of the device isolation layer 701 ). In some embodiments, an upper surface of the isolation impurity region 601 may contact a lower surface of the isolation layer 701 .

The separation impurity region 601 may be doped with the first conductivity type. For example, the isolation impurity region 601 may include p-type impurities. Forming the isolation impurity region 601 may include, for example, an ion implantation process, but is not limited thereto. The p-type impurity may include, for example, boron (B) or aluminum (Al), but is not limited thereto. In some embodiments, the isolation impurity region 601 may include boron (B).

The first gate electrode 401 and the second gate electrode 402 may be disposed on the active region 501 . The first gate electrode 401 and the second gate electrode 402 may each extend in a first direction D1 parallel to the top surface of the substrate 100 . The first gate electrode 401 and the second gate electrode 402 may be spaced apart from each other and arranged along a second direction D2 crossing the first direction D1.

The first gate electrode 401 and the second gate electrode 402 may be formed of, for example, polycrystalline silicon (poly Si), amorphous silicon (a-Si), titanium (Ti), titanium nitride (TiN), or tungsten nitride ( WN), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), titanium carbide (TiC), tantalum carbide (TaC), tantalum carbonitride (TaCN), tantalum silicon nitride (TaSiN), tantalum ( Ta), cobalt (Co), lutedium (Ru), aluminum (Al), tungsten (W), and at least one of combinations thereof, but is not limited thereto.

In some embodiments, the length G1 of the first gate electrode 401 and the second gate electrode 402 in the first direction D1 may be about 3 μm or more and about 50 μm or less. In some embodiments, a length G2 of the first gate electrode 401 and the second gate electrode 402 in the second direction D2 may be greater than or equal to about 0.5 μm and less than or equal to about 1.5 μm.

The first gate electrode 401 and the second gate electrode 402 may be disposed on the gate dielectric layer 410 .

The gate dielectric layer 410 may include, for example, silicon oxide, silicon oxynitride, silicon nitride, and a high-k material having a higher dielectric constant than silicon oxide. The high dielectric constant material is, for example, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon Zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, It may include at least one of yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, and combinations thereof, but is limited thereto It is not.

In some embodiments, gate spacers 420 may be formed on the substrate 100 . The gate spacer 420 may extend along side surfaces of the first gate electrode 401 and the second gate electrode 402 . The gate spacer 420 may include an insulating material such as, for example, at least one of silicon oxynitride (SiON), silicon carbonitride (SiCN), and silicon oxycarbonitride (SiOCN), but is not limited thereto.

Also, although not shown, a gate capping pattern may be further formed on upper surfaces of the first gate electrode 401 and the second gate electrode 402 . Also, although not shown, an etch stop layer may be further formed on the gate spacer 420 and the gate capping pattern.

The first source region 221 may be disposed in the active region 501 on one side of the first gate electrode 401 . The second source region 222 may be disposed in the active region 501 on one side of the second gate electrode 402 . The drain region 321 may be disposed in the active region 501 on the other side of the first gate electrode 401 and the active region 501 on the other side of the second gate electrode 402 . In other words, the drain region 321 may be disposed between the first gate electrode 401 and the second gate electrode 402 . The first source region 221 , the second source region 222 , and the drain region 321 may each extend in the first direction D1 .

The first source region 221, the second source region 222, and the drain region 321 may include impurities of the second conductivity type. For example, when the transistor formed on the substrate 100 is an NFET, each of the first source region 221 , the second source region 222 , and the drain region 321 may include an n-type impurity. The n-type impurity may include, for example, phosphorus (P) or arsenic (As), but is not limited thereto.

In some embodiments, the first source region 221 may include a first high-concentration source region 211 and a first low-concentration source region 201 . The first low-concentration source region 201 may surround the first high-concentration source region 211 . The first low-concentration source region 201 may be closer to the first gate electrode 401 than the first highly-concentrated source region 211 . The doping concentration of the first high-concentration source region 211 may be higher than that of the first low-concentration source region 201 .

In some embodiments, the second source region 222 may include a second high-concentration source region 212 and a second low-concentration source region 202 . The second low-concentration source region 202 may surround the second high-concentration source region 212 . The second low-concentration source region 202 may be closer to the second gate electrode 402 than the second high-concentration source region 212 . The doping concentration of the second high-concentration source region 212 may be higher than that of the second low-concentration source region 202 .

The drain region 321 may be disposed between the first gate electrode 401 and the second gate electrode 402 . In some embodiments, the drain region 321 may include a heavily doped drain region 311 and a lightly doped drain region 301 . The low-concentration drain region 301 may surround the heavily-concentrated drain region 311 . The lightly doped drain region 301 may be closer to the first gate electrode 401 and the second gate electrode 402 than the heavily doped drain region 311 . The doping concentration of the heavily doped drain region 311 may be higher than that of the lightly doped drain region 301 .

The interlayer insulating film 111 may be disposed on the substrate 100 . The interlayer insulating layer 111 may cover the substrate 100 , the isolation impurity region 601 , the source contact 210 , the first gate electrode 401 , the second gate electrode 402 , and the device isolation layer 701 .

The interlayer insulating layer 111 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low-k material having a lower dielectric constant than silicon oxide. The low dielectric constant material is, for example, FOX (Flowable Oxide), TOSZ (Torene SilaZene), USG (Undoped Silica Glass), BSG (Borosilica Glass), PSG (PhosphoSilica Glass), BPSG (BoroPhosphoSilica Glass), PETEOS (Plasma Enhanced Tetra Ethyl Ortho Silicate), FSG(Fluoride Silicate Glass), CDO(Carbon Doped Silicon Oxide), Xerogel, Airgel, Amorphous Fluorinated Carbon, OSG(Organo Silicate Glass), Parylene, BCB(bis-benzocyclobutenes), SiLK, polyimide, porous It may include at least one of a polymeric material and a combination thereof, but is not limited thereto.

The source contact 210 may be disposed on each of the first source region 221 and the second source region 222 . The source contact 210 may pass through the interlayer insulating layer 111 and be connected to each of the first source region 221 and the second source region 222 . For example, the source contact 210 may extend in a vertical direction and pass through the interlayer insulating layer 111 . The source contact 210 is electrically connected to each of the first source region 221 and the second source region 222 to apply a voltage to each of the first source region 221 and the second source region 222. can

The source contact 210 may include a conductive material such as, for example, aluminum (Al), copper (Cu), or tungsten (W), but is not limited thereto.

The drain contact 310 may be disposed on the drain region 321 . The drain contact 310 may be connected to the drain region 321 . For example, the drain contact 310 may extend in a vertical direction and pass through the interlayer insulating layer 111 . The drain contact 310 may be electrically connected to the drain region 321 to apply a voltage to the drain region 321 .

The drain contact 310 may include a conductive material such as aluminum (Al), copper (Cu), or tungsten (W), but is not limited thereto.

The device isolation layer 701 may include a first peripheral portion B1 and a first protrusion E1. The first peripheral portion B1 may surround the active region 501 . The first protrusion E1 may protrude toward the drain region 321 from the first circumferential portion B1 . For example, the first protrusion E1 may protrude from a portion of the first circumferential portion E1 extending in the second direction D2 toward the drain region 321 in the first direction D1 . The drain region 321 and the first protrusion E1 may be arranged in a line along the first direction D1.

The separation impurity region 601 may include a second peripheral portion B2 and a second protrusion E2. The second peripheral portion B2 may surround the device isolation layer 701 . The second protrusion E2 may protrude toward the drain region 321 from the second circumferential portion B2 . For example, the second protrusion E2 may protrude from a portion of the second peripheral portion E2 extending in the second direction D2 toward the drain region 321 in the first direction D1 . The drain region 321 and the second protrusion E2 may be arranged in a line along the first direction D1.

The first circumferential portion B1 of the device isolation layer 701 and the second circumferential portion B2 of the separation impurity region 601 may overlap. In addition, the first protrusion E1 of the isolation layer 701 and the second protrusion E2 of the isolation impurity region 601 may overlap. Here, overlapping means overlapping in a direction (vertical direction) crossing the upper surface of the substrate 100 .

As the device isolation layer 701 includes the first protrusion E1, the extension length of the drain region 321 may be smaller than the extension lengths of the first source region 221 and the second source region 222. . For example, as shown in FIG. 1 , the length L2 of the drain region 321 extending in the first direction D1 is the first source region 221 and the second source region 221 in the first direction D1. (222) may be smaller than the length (L1) extending.

In some embodiments, the distance K1 of the first source region 221 and the second source region 222 from the separation impurity region 601 is the distance K1 of the drain region 321 from the separation impurity region 601 ( K2) may be the same. However, the technical idea of the present invention is not limited thereto, and the separation distance K1 of the first source region 221 and the second source region 222 from the impurity region 601 is the separation of the drain region 321. It goes without saying that it may be larger or smaller than the distance K2 from the impurity region 601 .

In some embodiments, the width W1 of the second protrusion E2 may be greater than or equal to about 0.1 μm and less than or equal to 1 μm. Here, the width W1 of the second protrusion E2 may mean the maximum width of the second protrusion E2 in the second direction D2. For example, the width W1 of the second protrusion E2 may be measured on the same plane as the upper surface of the substrate 100 .

The high voltage transistor is a transistor having relatively high breakdown voltages and may be driven at a high voltage of, for example, about 5 V to about 100 V. In such a high voltage transistor, leakage current and/or device breakdown due to a punch-through phenomenon may be a problem. In order to prevent this, a high-concentration impurity region (hereinafter referred to as a separation impurity region) may be formed on the lower surface of the device isolation layer to control the expansion of the depletion region of the source/drain. However, in a high voltage transistor having a relatively large channel width for a high driving current, control using the isolation impurity region may not be easy. For example, in a multi-finger transistor, since the central portion of the source/drain disposed inside the active region is disposed far from the separation impurity region, expansion of the depletion region may not be easily controlled.

In contrast, in a semiconductor device according to some embodiments, the depletion region is effectively depleted even for a source/drain (eg, drain region 321) disposed inside the active region 501 by using the above-described isolation impurity region 601. You can control the expansion. Specifically, as described above, the isolation impurity region 601 protrudes from the second peripheral portion B2 surrounding the periphery of the active region 501 toward the drain region 321 disposed inside the active region 501. Since the second protrusion E2 is provided, the distance between the center of the drain region 321 and the separation impurity region 601 can be reduced. Also, since the second protruding portion E2 of the separation impurity region 601 may protrude toward the drain region 321 between the gate electrodes, a relatively large channel width of the active region 501 may be maintained. Through this, a semiconductor device with improved performance and reliability may be provided.

4 is a layout diagram of a semiconductor memory device according to some embodiments. For convenience of explanation, parts overlapping with those described above with reference to FIG. 1 are briefly described or omitted.

Referring to FIG. 4 , a semiconductor device according to some embodiments includes a third source region 223 . A fourth source region 224 , a second drain region 322 , a third gate electrode 403 , a fourth gate electrode 404 , and a fifth gate electrode 405 may be further included.

The active region 501 of the substrate 100 may include a first active region A1 , a second active region A2 , and a third active region A3 .

The first active region A1 may include a first source region 221 and a first gate electrode 401 .

The second active region A2 may include the first drain region 321 .

The third active region A3 may include a second source region 222 and a second gate electrode 402 .

The first active region A1 , the second active region A2 , and the third active region A3 may be sequentially disposed in the first direction D1 . In other words, the second active region A2 may be disposed between the first active region A1 and the third active region A3.

The device isolation layer 701 may protrude toward the first drain region 321 in the second direction D2 . Accordingly, the length S2 of the second active region A2 in the second direction D2 is the length S1 of the first active region A1 and the third active region A3 in the second direction D2. , S3).

5 is a layout diagram of a semiconductor memory device according to some embodiments.

For convenience of explanation, parts overlapping with those described above with reference to FIG. 1 are briefly described or omitted.

Referring to FIG. 5 , the separation impurity region 601 may protrude toward the first source region 221 and the second source region 222 in the first direction D1 .

The length L2 of the drain region 321 in the first direction D1 may be smaller than the lengths L1 of the first source region 221 and the second source region 222 in the first direction D1. there is.

The device isolation layer 701 includes a first peripheral portion B1, a first protrusion E1 protruding from the first peripheral portion B1 toward the drain region 321 in a first direction D1, and a first source region ( 221) may include a third protrusion E3 protruding in the first direction D1.

The separation impurity region 601 includes a second peripheral portion B2, a second protrusion E2 protruding from the second peripheral portion B2 toward the drain region 321 in the first direction D1, and a first source region. A fourth protrusion E4 protruding in the first direction D1 toward 221 may be included.

In addition, the third protrusion E3 of the isolation layer 701 and the fourth protrusion E4 of the isolation impurity region 601 may overlap each other.

A length L4 in the first direction of the first protruding portion E1 protruding toward the drain region 321 in the first direction D1 protrudes toward the first source region 221 in the first direction D1. may be greater than the length L3 of the third protrusion E3 in the first direction.

Accordingly, the length L2 of the drain region 321 in the first direction D1 is greater than the lengths L1 of the first source region 221 and the second source region 222 in the first direction D1. can be small

In some embodiments, distances of the first source region 221 and the second source region 222 from the active region 501 may be the same as the distance of the drain region 321 from the active region 501 .

6 is a layout diagram of a semiconductor memory device according to some embodiments.

For convenience of description, the overlapping parts with those described above with reference to FIG. 4 are briefly described or omitted.

Referring to FIG. 6 , the device isolation layer 701 may protrude toward the first drain region 321 in the second direction D2 . In addition, the device isolation layer 701 may protrude in the second direction D2 toward the first source region 221 and the second source region 222 .

The length S2 of the second active region A2 in the second direction D2 is the length S1 of the first active region A1 including the first source region 221 in the second direction D2. ) and the length S3 of the third active region A3 including the second source region 222 in the second direction D2.

7 to 17 are diagrams for explaining a method of manufacturing a semiconductor memory device according to some embodiments. For convenience of description, portions overlapping with those described above with reference to FIGS. 1 to 6 are briefly described or omitted.

Referring to FIGS. 7 and 8 , a first conductivity type impurity region 801 and a second conductivity type impurity region 802 are formed in the substrate 100 . For reference, FIG. 8 is a cross-sectional view taken along line C1 - C1 of FIG. 7 .

For example, the n-type second impurity region 802 may be formed in the p-type substrate by using an ion implantation process. Subsequently, a p-type first impurity region 801 may be formed on the second impurity region 802 by using an ion implantation process.

Referring to FIGS. 9 and 10 , a device isolation trench 900 may be formed in the substrate 100 . For reference, FIG. 10 is a cross-sectional view taken along line C1 - C1 of FIG. 9 .

For example, a device isolation trench 900 may be formed by etching a portion of the substrate 100 . The device isolation trench 900 may include a fifth peripheral portion B5 and a fifth protrusion E5. The circumference part B5 may surround the circumference of the substrate 100 . The fifth protrusion E5 may protrude from the fifth circumferential portion B5 in the first direction D1.

Referring to FIGS. 11 and 12 , an isolation impurity region 601 may be formed on the substrate 100 within the device isolation trench 900 . For reference, FIG. 12 is a cross-sectional view taken along line C1 - C1 of FIG. 11 .

Referring to FIGS. 13 and 14 , a device isolation layer 701 may be formed on the substrate 100 . Although not shown, a planarization process may then be performed. The planarization process may include, for example, a chemical mechanical polishing (CMP) process, but is not limited thereto. For reference, FIG. 14 is a cross-sectional view taken along line C1 - C1 of FIG. 13. Referring to FIG. 16, a first low-concentration source region 201 and a second low-concentration source region 202 are formed on a substrate 100. can form After forming the first low-concentration source region 201 and the second low-concentration source region 202 , a gate dielectric layer 410 may be formed on the substrate 100 .

Subsequently, a first gate electrode 401 and a second gate electrode 402 may be formed on the gate dielectric layer 410 . A gate spacer 420 may be formed surrounding sidewalls of each of the first gate electrode 401 and the second gate electrode 402 .

Subsequently, a first highly-concentrated source region 211 and a second highly-concentrated source region 212 may be formed. The first high-concentration source region 211 and the second high-concentration source region 212 may be formed in the first low-concentration source region 201 and the second low-concentration source region 202 , respectively.

Subsequently, an interlayer insulating film 111 may be formed on the substrate 100 . The interlayer insulating layer 111 may cover the first gate electrode 401 and the second gate electrode 402 . For reference, FIG. 16 is a cross-sectional view taken along line C1 - C1 of FIG. 15 .

Referring to FIG. 17 , a source contact hole 210h may be formed in the interlayer insulating layer 111 . The source contact hole 210h may penetrate the interlayer insulating layer 111 to expose the first source region 221 and the second source region 222 .

Subsequently, referring to FIG. 2 , the source contact 210 may fill the source contact hole 210h. In other words, the source contact 210 may pass through the interlayer insulating layer 111 and be connected to each of the first source region 221 and the second source region 222 .

Although the embodiments of the present invention have been described with reference to the accompanying drawings, the present invention is not limited to the above embodiments and can be manufactured in a variety of different forms, and those skilled in the art in the art to which the present invention belongs A person will understand that the present invention may be embodied in other specific forms without changing the technical spirit or essential features. Therefore, the embodiments described above should be understood as illustrative in all respects and not limiting.

100: substrate 107: interlayer insulating film
111: second insulating film 221: first source region
222: second source region 210: source contact
321: first drain region 322: second drain region
401: first gate electrode 402: second gate electrode
410: gate dielectric layer 420: gate spacer
501 active region 601 separation impurity region
701: element isolation film 801: first impurity region
802 second impurity region 900 device isolation trench

Claims (10)

active regions within the substrate;
In the substrate, a device isolation layer defining the active region;
an isolation impurity region including impurities of a first conductivity type in the substrate under the device isolation layer;
a first gate electrode extending in a first direction on the active region;
a first source region disposed in the active region at one side of the first gate electrode; and
A drain region disposed in the active region on the other side of the first gate electrode,
The device isolation layer includes a first circumferential portion surrounding the active region and a first protrusion extending from the circumferential portion in the first direction and protruding toward the drain region;
the separated impurity region includes a second circumferential portion overlapping the first circumferential portion and a second protruding portion overlapping the first protruding portion;
In the first direction, a length of the drain region is smaller than a length of the first source region. The method of claim 1 , wherein the active region includes a first side surface extending in the first direction and a second side surface extending in a second direction crossing the first direction,
The second side surface includes a trench leading toward the drain region,
The semiconductor device of claim 1 , wherein the first protrusion and the second protrusion are disposed within the trench. The semiconductor device of claim 1 , further comprising first and second gate electrodes having a width of the first gate electrode in the first direction ranging from 3 μm to 50 μm. The semiconductor device of claim 1 , further comprising first and second gate electrodes, wherein a width of the first gate electrode in a second direction crossing the first direction is between 0.5 μm and 1.5 μm. The method of claim 1 , further comprising: a second gate electrode extending in the first direction on the active region;
a second source region disposed in the active region at one side of the second gate electrode; Including more,
The second gate electrode is disposed between the drain region and the second source region;
In the first direction, a length of the drain region is smaller than a length of the second source region. The semiconductor device according to claim 1 , wherein the first source region and the drain region include impurities of a second conductivity type different from the first conductivity type. 7. The semiconductor device according to claim 6, wherein the first conductivity type is p-type and the second conductivity type is n-type. The semiconductor device of claim 1 , wherein a width of the device isolation layer of the first protrusion is 0.1 μm or more and 1 μm or less. Board;
In the substrate, first to third active regions are arranged along a first direction, wherein a length of the second active region in a second direction crossing the first direction is greater than the lengths of the first and third active regions. small first to third active regions;
a first gate electrode extending in the second direction on the first active region;
a drain region including impurities of a first conductivity type in the second active region;
a second gate electrode extending in the second direction on the third active region;
a first source region including impurities of the first conductivity type in the first active region, wherein the first gate electrode is disposed between the first source region and the drain region;
a second source region including impurities of the first conductivity type in the second active region, wherein the second gate electrode is disposed between the second source region and the drain region; and
a separation impurity region disposed between the first gate electrode and the second gate electrode along the drain region and the first direction and including impurities of a second conductivity type different from the first conductivity type; semiconductor device. The semiconductor device according to claim 9 , wherein a width of each of the first and second gate electrodes in the second direction is 3 μm or more and 50 μm or less.

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