KR20230113229A - Semiconductor devices and methods of manufacturing the same - Google Patents

Abstract

Provided is a semiconductor device comprising: a substrate; bit lines located on the substrate, spaced apart from each other in a first direction, and extending in a second direction different from the first direction; first and second semiconductor patterns located on the bit line, spaced apart in the first direction and the second direction, and extending in a third direction different from the first and second directions; a back gate electrode located between the first and second semiconductor patterns and extending in the first direction; a first word line located in correspondence with the back gate electrode with the first semiconductor pattern in between and extending in the first direction and a second word line located in correspondence with the back gate electrode with the second semiconductor pattern in between and extending in the first direction; and an interlayer insulation pattern located between the substrate and the bit line. Accordingly, bit line resistance can be improved compared to a vertical channel transistor (VCT) using a silicon bit line.

Description

Semiconductor device and its manufacturing method {SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME}

The present disclosure relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a memory device including a vertical channel and a manufacturing method thereof.

It is required to increase the degree of integration of semiconductor memory devices in order to meet the excellent performance and low price demanded by consumers. In the case of a semiconductor memory device, since the degree of integration is an important factor in determining the price of a product, an increased degree of integration is particularly required.

In the case of a two-dimensional or planar semiconductor memory device, since the degree of integration is mainly determined by the area occupied by a unit memory cell, it is greatly affected by the level of fine pattern formation technology. However, since ultra-expensive equipment is required for miniaturization of the pattern, although the degree of integration of the 2D semiconductor memory device is increasing, it is still limited. Accordingly, semiconductor memory devices including a vertical channel transistor having a channel extending in a vertical direction have been proposed.

In one aspect of the present disclosure, since a metal bit line can be formed, a bit line resistance can be improved compared to a vertical channel transistor (VCT) using a silicon bit line, and a bit line shield can be formed, such that a bit line It is possible to control the coupling between them, it is possible to reduce the wafer cost by not using a Silicon On Insulator (SOI) substrate, and it is possible to reduce stress and torsion by not needing wafer bonding. Provided is a semiconductor device and a method of manufacturing the same, which can be freed from a photo overlay condition on the rear surface of a wafer associated with distortion.

A semiconductor device according to one aspect includes a substrate; bit lines located on the substrate, spaced apart from each other in a first direction, and extending in a second direction different from the first direction; first and second semiconductor patterns positioned on the bit line, spaced apart from each other in the first and second directions, and extending in a third direction different from the first and second directions; a back gate electrode positioned between the first and second semiconductor patterns and extending in a first direction; and a first word line positioned corresponding to the back gate electrode with the first semiconductor pattern interposed therebetween and extending in a first direction, and positioned corresponding to the back gate electrode and extending in the first direction with the second semiconductor pattern interposed therebetween. and an interlayer insulating pattern positioned between the substrate and the bit line.

A method of manufacturing a semiconductor device according to another aspect includes preparing a substrate structure including a substrate, a first sacrificial layer, a second sacrificial layer, and a semiconductor layer; patterning the first sacrificial layer, the second sacrificial layer, and the semiconductor layer in the second direction, removing the first sacrificial layer, and forming an interlayer insulating pattern in the first sacrificial layer removed region; removing the second sacrificial layer and forming a bit line in a region from which the second sacrificial layer was removed; patterning the semiconductor layer in a first direction different from the second direction, and then forming a back gate electrode; After patterning the semiconductor layer positioned between the back gate electrodes in a first direction, a first semiconductor pattern is formed on one side of the back gate electrode and a second semiconductor pattern is formed on the other side; A first word line extending in the first direction is formed on one side of the first semiconductor pattern, and a second word line extending in the first direction is formed on the other side of the second semiconductor pattern.

According to embodiments, a semiconductor device and a method of manufacturing the same can form a metal bit line, improve bit line resistance compared to a vertical channel transistor (VCT) using a silicon bit line, and form a bit line shield. , Coupling between bit lines can be controlled, wafer cost can be reduced by not using an SOI substrate, and wafer bonding is not required, which frees the wafer from photo overlay conditions associated with stress and twist. It provides a semiconductor device and a method of manufacturing the same, which can be.

1 is a perspective view of a semiconductor device according to one aspect;
FIG. 2 is a plan view of the semiconductor device of FIG. 1 .
FIG. 3 is a cross-sectional view taken along line II′ of FIG. 1 .
FIG. 4 is a perspective view of a semiconductor device according to another aspect, corresponding to FIG. 1 .
5 to 17 and FIGS. 19 to 22 are cross-sectional views illustrating intermediate stages of a method of manufacturing a semiconductor device according to an exemplary embodiment.
18 is a cross-sectional view showing an intermediate step of a method of manufacturing a semiconductor device according to another aspect, and is a cross-sectional view corresponding to FIG. 17 .

Hereinafter, with reference to the accompanying drawings, various embodiments of the present disclosure will be described in detail so that those skilled in the art can easily implement them. This disclosure may be embodied in many different forms and is not limited to the embodiments set forth herein.

In order to clearly describe the present disclosure, parts irrelevant to the description have been omitted, and the same reference numerals are assigned to the same or similar components throughout the specification.

In addition, since the size and thickness of each component shown in the drawings are arbitrarily indicated for convenience of description, the present disclosure is not necessarily limited to the illustrated bar. In the drawings, the thickness is shown enlarged to clearly express the various layers and regions. And in the drawings, for convenience of description, the thicknesses of some layers and regions are exaggerated.

In addition, when a part such as a layer, film, region, plate, etc. is said to be "on" or "on" another part, this includes not only the case of being "directly on" the other part, but also the case where another part is in the middle. . Conversely, when a part is said to be "directly on" another part, it means that there is no other part in between. In addition, being "above" or "on" a reference part means being located above or below the reference part, and does not necessarily mean being located "above" or "on" in the opposite direction of gravity. .

In addition, throughout the specification, when a certain component is said to "include", it means that it may further include other components without excluding other components unless otherwise stated.

In addition, throughout the specification, when it is referred to as "planar image", it means when the target part is viewed from above, and when it is referred to as "cross-sectional image", it means when a cross section of the target part cut vertically is viewed from the side.

In addition, throughout the specification, two directions that are parallel to the top surface of the substrate and cross each other are defined as a first direction D1 and a second direction D2, respectively, and a direction perpendicular to the top surface of the substrate is defined as a third direction D3. Defined by In example embodiments, the first direction D1 and the second direction D2 may be orthogonal to each other.

A semiconductor device according to an aspect will be described with reference to FIGS. 1 to 3 .

FIG. 1 is a perspective view of a semiconductor device according to one side, FIG. 2 is a plan view of the semiconductor device of FIG. 1 , and FIG. 3 is a cross-sectional view taken along line II′ of FIG. 1 .

However, in order to avoid complexity of drawings in FIGS. 1 to 3 , some components included in the semiconductor device are not shown, but are not limited thereto.

1 to 3 , a semiconductor device according to an aspect includes a substrate 100, a bit line 360, first and second semiconductor patterns 137_1 and 137_2, a back gate electrode 215, first and second semiconductor patterns 137_1 and 137_2, Second word lines 305_1 and 305_2 and an interlayer insulating pattern 187 are included.

Optionally, the semiconductor device may further include first and second insulating patterns 185 and 186, first and second gate insulating layers 207 and 297, a direct contact 340, and a buried contact 605. there is.

The substrate 100 may include a semiconductor material, an insulating material, or a conductive material.

For example, the substrate 100 may be a bulk silicon substrate, and may not be a Silicon On Insulator (SOI) substrate or a Germanium On Insulator (GOI) substrate. That is, as will be described with reference to FIGS. 5 to 22 described later, a method of manufacturing a semiconductor device according to one aspect uses a bulk silicon wafer, without wafer bonding, and uses a vertical channel transistor (VCT). Provides a method for manufacturing. Accordingly, it is possible to reduce wafer cost, and since wafer bonding is not required, photo overlay conditions on the rear side of the wafer associated with stress and twist can be relieved.

The bit line 360 may be positioned on the substrate 100 and may extend in the second direction D2 .

The bit lines 360 may be spaced apart from each other in the first direction D1 and disposed in plurality. For example, the first and second bit lines 360_1 alternately disposed while being spaced apart from each other in the first direction D1. 360_2). The first and second bit lines 360_1 and 360_2 may be positioned between a first insulating pattern 185 to be described later, and a second bit line to be described later may be positioned between the first bit line 360_1 and the second bit line 360_2. An insulating pattern 186 may be located.

For example, the bit line 360 may include a metal such as tungsten, titanium, or tantalum. Alternatively, the bit line 360 may include a second conductive pattern, a barrier pattern, and a first conductive pattern sequentially stacked on the substrate 100 along the third direction D3 . The first conductive pattern may include, for example, polysilicon doped with n-type or p-type impurities, and the barrier pattern may include, for example, a metal nitride such as titanium nitride, tantalum nitride, or tungsten nitride, The second conductive pattern may include, for example, a metal such as tungsten, titanium, or tantalum.

The first insulating pattern 185 may be positioned on the substrate 100 and may extend in the third direction D3. A plurality of first insulating patterns 185 may be disposed apart from each other in the first and second directions D1 and D2 .

The first and second bit lines 360_1 and 360_2 may be positioned between the first insulating patterns 185 spaced apart in the first direction D1 .

Between the first insulating patterns 185 spaced apart in the second direction D2 , first and second word lines 305_1 and 305_2 and back gate electrodes 215 may be alternately positioned.

The first insulating pattern 185 may have a protrusion 185_M extending in the third direction D3 toward the substrate 100 . The first insulating pattern 185 may extend from the inside of the substrate 100, that is, from the protruding portion 185_M to upper portions of the first and second semiconductor patterns 137_1 and 137_2 in the third direction D3.

As will be described with reference to FIGS. 5 to 22 described below, in a method of manufacturing a semiconductor device according to an aspect, a vertical channel transistor is manufactured using a bulk silicon wafer without wafer bonding, and the first insulating pattern No junction exists between the substrate 185 and the substrate 100, the first insulating pattern 185 has a protrusion 185_M extending toward the substrate 100 in the third direction D3, and An area 185 may extend from the inside of the substrate 100 to upper portions of the first and second semiconductor patterns 137_1 and 137_2 in the third direction D3.

For example, the first insulating pattern 185 may include an oxide such as silicon oxide.

The second insulating pattern 186 may be positioned on an interlayer insulating layer 187 to be described later and may extend in a third direction D3.

A plurality of second insulating patterns 186 may be disposed spaced apart from each other in the first and second directions D1 and D2 .

The first bit line 360_1 may be positioned on one side of the second insulating pattern 186 spaced apart in the first direction D1 , and the second bit line 360_2 may be positioned on the other side. That is, the first and second bit lines 360_1 and 360_2 may be disposed with the second insulating pattern 186 interposed therebetween.

For example, the first insulating pattern 185, the first bit line 360_1, the second insulating pattern 186, and the second bit line 360_2 may be sequentially positioned along the first direction D1. , and this pattern may be repeated along the first direction D1.

Between the second insulating patterns 186 spaced apart in the second direction D2 , first and second word lines 305_1 and 305_2 described later and a back gate electrode 215 may be alternately positioned.

In the third direction D3 , the second insulating pattern 186 may extend from above the interlayer insulating layer 187 to upper portions of the first and second semiconductor patterns 137_1 and 137_2 in the third direction D3 .

For example, the second insulating pattern 186 may include an oxide such as silicon oxide.

The interlayer insulating pattern 187 is positioned between the substrate 100 and the bit line 360 .

A plurality of interlayer insulating patterns 187 may be disposed extending in the second direction D2 and spaced apart from each other in the first direction D1.

A first insulating pattern 185 may be positioned between the interlayer insulating patterns 187 spaced apart in the first direction D1 .

A first bit line 360_1, a second insulating pattern 186, and a second bit line 360_2 are sequentially positioned on the interlayer insulating pattern 187 in the third direction D3 along the first direction D1. can do.

In addition, the interlayer insulating pattern 187 may have a protrusion 187_M extending in the third direction D3 toward the substrate 100 . A part of the interlayer insulating pattern 187 , that is, the protrusion 187_M of the interlayer insulating pattern 187 may be located inside the substrate 100 .

As will be described with reference to FIGS. 5 to 22 described later, in the method of manufacturing a semiconductor device according to one aspect, as a vertical channel transistor is manufactured using a bulk silicon wafer without wafer bonding, the substrate 100 An interlayer insulating pattern 187 is formed between the and bit lines 360, no junction exists between the interlayer insulating pattern 187 and the substrate 100, and the interlayer insulating pattern 187 faces the substrate 100. It may have a protrusion 187_M extending in the third direction D3.

For example, the interlayer insulating pattern 187 may include an oxide such as silicon oxide.

The first and second semiconductor patterns 137_1 and 137_2 are positioned on each of the bit lines 360 and may extend in the third direction D3.

Along the first direction D1 , the first semiconductor pattern 137_1 may be positioned on the first and second bit lines 360_1 and 360_2 , and the first and second bit lines 360_1 and 360_2 alternately As the plurality of first semiconductor patterns 137_1 are spaced apart from each other, the plurality of first semiconductor patterns 137_1 may be spaced apart along the first direction D1. Also, along the first direction D1 , the second semiconductor pattern 137_2 may be positioned on the first and second bit lines 360_1 and 360_2 , and the first and second bit lines 360_1 and 360_2 may be As the plurality of second semiconductor patterns 137_2 are alternately spaced apart, the plurality of second semiconductor patterns 137_2 may be spaced apart along the first direction D1 and arranged in plurality.

The pair of first semiconductor patterns 137_1 may be positioned between the first insulating patterns 185 in the first direction D1, and the second insulating patterns 186 may be between the pair of first semiconductor patterns 137_1. ) can be located. In addition, the pair of second semiconductor patterns 137_2 may be positioned between the first insulating patterns 185 in the first direction D1, and the second insulating patterns 137_2 may be positioned between the pair of second semiconductor patterns 137_2. (186) may be located.

Along the second direction D2 , the first semiconductor pattern 137_1 may be spaced apart from the first bit line 360_1 or the second bit line 360_2 , and the second semiconductor pattern 137_2 may be the first bit line 360_1 or the second bit line 360_2 . Alternatively, they may be spaced apart from each other on the second bit line 360_2. For example, the first semiconductor pattern 137_1 and the second semiconductor pattern 137_2 may be alternately spaced apart from each other along the second direction D2 .

Between the first and second semiconductor patterns 137_1 and 137_2 spaced apart in the second direction D2, first and second word lines 305_1 and 305_2 described later and a back gate electrode 215 may be alternately positioned. can For example, the first word line 305_1, the first semiconductor pattern 137_1, the back gate electrode 215, the second semiconductor pattern 137_2, and the second word line 305_2 along the second direction D2. ) may be sequentially arranged, and such a pattern may be repeated along the second direction D2.

For example, the first and second semiconductor patterns 137_1 and 137_2 may include a single crystal semiconductor material such as single crystal silicon or single crystal germanium, or may include a polycrystalline semiconductor material such as polysilicon or polygermanium, and may include a channel of a semiconductor device. role can be fulfilled.

Optionally, a buried contact 605 may be positioned on each of the first and second semiconductor patterns 137_1 and 137_2 .

Accordingly, the buried contacts 605 may be spaced apart from each other in the first direction D1 and the second direction D2, and the first insulating material is interposed between the buried contacts 605 in the first direction D1. The pattern 185 and the second insulating pattern 186 may be alternately disposed, and the sixth insulating layer 540 and the second and seventh insulating layers ( 310 and 545) may be alternately arranged.

Upper and lower surfaces of the buried contact 605 and the second, sixth, and seventh insulating layers 310, 540, and 545 may have substantially the same height, and the lower surface of the buried contact 605 may have a first and upper portions of the second semiconductor patterns 137_1 and 137_2 .

For example, the buried contact 605 includes a conductive material, for example, doped polysilicon, conductive metal nitride, conductive metal silicon nitride, metal carbonitride, conductive metal silicide, conductive metal oxide, two-dimensional material, and It may contain at least one of metals.

Optionally, a direct contact 340 may be positioned below each of the first and second semiconductor patterns 137_1 and 137_2 .

Accordingly, the direct contacts 340 may be spaced apart from each other in the first and second directions D1 and D2, and between the direct contacts 340 in the first direction D1, the first insulating pattern ( 185) and the second insulating pattern 186 may be alternately disposed, and the third insulating layer 270 and the fourth insulating layer 330 may be alternately disposed between the direct contact 340 in the second direction D2. can

Upper and lower surfaces of the direct contact 340 and the third and fourth insulating layers 270 and 330 may have substantially the same height, and the upper surfaces of the direct contact 340 may have first and second semiconductor patterns 137_1, 137_2) may be connected to the lower part.

As an example, the direct contact 340 includes a conductive material, for example, doped polysilicon, conductive metal nitride, conductive metal silicon nitride, metal carbonitride, conductive metal silicide, conductive metal oxide, two-dimensional material, and metal. may include at least one of them.

The back gate electrode 215 is positioned between the first and second semiconductor patterns 137_1 and 137_2 and extends in the first direction D1.

In addition, the first word line 305_1 is positioned to correspond to the back gate electrode 215 with the first semiconductor pattern 137_1 interposed therebetween and extends in the first direction D1, and the second word line 305_2 is It is positioned to correspond to the back gate electrode 215 with the second semiconductor pattern 137_2 interposed therebetween and extends in the first direction D1. That is, the first semiconductor pattern 137_1 is positioned between the first word line 305_1 and the back gate electrode 215, and the second semiconductor pattern 137_2 is positioned between the second word line 305_2 and the back gate electrode 215. ) is located. For example, the first word line 305_1, the first semiconductor pattern 137_1, the back gate electrode 215, the second semiconductor pattern 137_2, and the second word line 305_2 along the second direction D2. These may be sequentially arranged, and such a pattern may be repeated along the second direction D2.

That is, each of the first and second semiconductor patterns 137_1 and 137_2 includes a first sidewall positioned on one side and a second sidewall positioned on the other side in the second direction D2, and the first semiconductor pattern 137_1 The first word line 305_1 may be disposed adjacent to the first sidewall of the first semiconductor pattern 137_1 , and the back gate electrode 215 may be disposed adjacent to the second sidewall of the first semiconductor pattern 137_1 . In addition, the back gate electrode 215 may be disposed adjacent to the first sidewall of the second semiconductor pattern 137_2, and the second word line 305_2 may be adjacent to the second sidewall of the second semiconductor pattern 137_2. can be placed.

For example, the back gate electrode 215 may include a metal such as molybdenum, ruthenium, or tungsten, a metal nitride such as titanium nitride, tantalum nitride, or tungsten nitride, or a conductive material such as metal silicide. can

For example, the first and second word lines 305_1 and 305_2 may be made of, for example, a metal such as molybdenum, ruthenium, or tungsten, a metal nitride such as titanium nitride, tantalum nitride, or tungsten nitride, or a metal silicide. may contain the same conductive material.

As described above, the semiconductor device according to one aspect may include a vertical channel transistor (VCT) structure, and the vertical channel transistor may include first and second semiconductor patterns 137_1 and 137_2 serving as channels, a front First and second word lines 305_1 and 305_2 serving as gate electrodes, and a back gate electrode 215 may be included. As the back gate electrode 215 of the vertical channel transistor increases the threshold voltage, even if the vertical channel transistor has a small size, the threshold voltage decreases and leakage current characteristics are prevented from deteriorating.

In addition, one back gate electrode 215 is formed between the first and second word lines 305_1 and 305_2, and the first and second semiconductor patterns 137_1 and 137_2 disposed on both sides of the back gate electrode 215 ), it is possible to increase the degree of integration of the semiconductor device compared to a so-called double gate structure in which gate electrodes are formed on both sides of one channel, respectively.

For example, the first and second word lines 305_1 and 305_2 positioned on both sides of the back gate electrode 215 in the second direction D2 may form one word line pair, and one word line pair. may be disposed in plurality so as to be spaced apart from each other along the second direction D2. In this case, a second insulating layer 310 including an oxide such as silicon oxide may be formed between pairs of word lines adjacent to each other in the second direction D2 .

For example, the heights of the upper and lower surfaces of the back gate electrode 215 in the third direction D3 may be substantially the same as those of the first and second word lines 305_1 and 305_2 , respectively. It is not limited thereto, and the heights of the upper and lower surfaces of the back gate electrode 215 in the third direction D3 may be greater or smaller than the heights of the upper and lower surfaces of the first and second word lines 305_1 and 305_2, respectively. can

Optionally, the lower surface of the back gate electrode 215 may be covered by the third insulating layer 270 and the upper surface of the back gate electrode 215 may be covered by the sixth insulating layer 540 . In addition, lower surfaces of the first and second word lines 305_1 and 305_2 may be covered by a fourth insulating film 330 , and upper surfaces of the first and second word lines 305_1 and 305_2 may be covered by a seventh insulating film 545 . ) can be covered by

Optionally, lower surfaces of the third insulating layer 270 and the fourth insulating layer 330 may have substantially the same height and may contact the upper surface of the upper surface of the bit line 360 . In addition, upper surfaces of the sixth insulating layer 540 and the seventh insulating layer 545 may have substantially the same height.

For example, the second, third, fourth, sixth, and seventh insulating layers 310 , 270 , 330 , 540 , and 545 may include an oxide such as silicon oxide.

For example, a first gate insulating layer 207 may be positioned between the first and second semiconductor patterns 137_1 and 137_2 and the back gate electrode 215 .

The first gate insulating layer 207 may cover not only sidewalls of the back gate electrode 215 but also sidewalls of the sixth insulating layer 540 and the third insulating layer 270 positioned above and below the back gate electrode 215 , respectively. ) and the third insulating layer 270 may also be covered.

In addition, a second gate insulating layer 297 may be positioned between the first and second semiconductor patterns 137_1 and 137_2 and the first and second word lines 305_1 and 305_2 .

The second gate insulating film 297 may cover not only the sidewalls of the first and second word lines 305_1 and 305_2 but also the sidewalls of the seventh insulating film 545 and the fourth insulating film 330 respectively formed above and below the first and second word lines 305_1 and 305_2. It may also cover between the first and second word lines 305_1 and 305_2 and the fourth insulating layer 330 .

The first and second gate insulating layers 207 and 297 may include, for example, oxide such as silicon oxide. In contrast, the first and second gate insulating films 207 and 297 include silicon oxide and contact the first and second semiconductor patterns 137_1 and 137_2, and, for example, hafnium oxide and zirconium oxide. It may also have a composite film structure including a metal oxide having a high permittivity, such as a second film in contact with the sidewall of the first film.

Although not shown in FIGS. 1 to 3 , the first etch stop layer, the interlayer insulating layer, and the capping layer may selectively form the first and second semiconductor patterns 137_1 and 137_2 , the first insulating pattern 185 , and the second insulating pattern ( 186), the first and second gate insulating layers 207 and 297, and the second, sixth, and seventh insulating layers 310, 540, and 545 may be sequentially stacked, and the contact plug structure penetrates them to form the first insulating layer. It may be connected to top surfaces of the first and second semiconductor patterns 137_1 and 137_2 or to the buried contact 605 .

The first etch stop layer and the capping layer may include, for example, an insulating nitride such as silicon nitride, and the interlayer insulating layer may include, for example, an oxide such as silicon oxide.

As the plurality of first and second semiconductor patterns 137_1 and 137_2 are disposed to be spaced apart from each other in the first and second directions D1 and D2, the contact plug structure also corresponds to this in the first and second directions D1. , D2) may be arranged in plurality so as to be spaced apart from each other.

The contact plug structure includes not only upper surfaces of the first and second semiconductor patterns 137_1 and 137_2 , but also first and second gate insulating layers 207 and 297 adjacent to the first and second semiconductor patterns 137_1 and 137_2 . It may partially contact the top surface of the second, sixth, and seventh insulating films 310, 540, and 545.

The contact plug structure may include a lower contact plug, an ohmic contact pattern, and an upper contact plug sequentially stacked in the third direction D3.

The lower contact plug may include, for example, polysilicon doped with n-type impurities or p-type impurities, and the ohmic contact pattern may include, for example, a metal silicide such as cobalt silicide, nickel silicide, or titanium silicide. The upper contact plug may include a conductive material such as metal, metal nitride, or metal silicide.

Optionally, a second etch stop layer may be positioned on the interlayer insulating layer and the contact plug structure, and a first capacitor electrode extending in the third direction D3 through the second etch stop layer may be positioned.

As the plurality of contact plug structures are disposed to be spaced apart from each other in the first and second directions D1 and D2, the first capacitor electrodes are also spaced apart from each other in the first and second directions D1 and D2 correspondingly. It may be formed in plurality.

First and second support films contacting sidewalls are formed at the center and upper portion of the first capacitor electrode in the third direction D3 to prevent the first capacitor electrode from falling over.

A dielectric layer may be formed on surfaces of the first capacitor electrodes, the first and second support layers, and a top surface of the second etch stop layer, and a second capacitor electrode may be formed on the dielectric layer. The first and second capacitor electrodes and the dielectric layer may together constitute a capacitor.

The second etch stop layer may include an insulating nitride such as silicon boron nitride or silicon carbonitride, and the first and second support layers may include an insulating nitride such as silicon nitride. The first capacitor electrode may include, for example, a metal nitride such as titanium nitride or tantalum nitride, or a metal such as titanium, tantalum, or tungsten, and the dielectric layer may have a high permittivity such as hafnium oxide or zirconium oxide. The second capacitor electrode may include, for example, silicon-germanium doped with impurities.

Meanwhile, other data storage structures may be formed on each of the contact plug structures instead of capacitors, and the data storage structures include, for example, a phase change material, a transition metal oxide, a magnetic material, and the like, and a variable resistance pattern in which resistance is varied. can include

Hereinafter, a semiconductor device according to another aspect will be described with reference to FIG. 4 .

FIG. 4 is a perspective view of a semiconductor device according to another aspect, corresponding to FIG. 1 .

Since the embodiment shown in FIG. 4 has substantially the same parts as the embodiment shown in FIG. 1, a description thereof will be omitted and differences will be mainly described.

In FIG. 1, the second insulating pattern 186 is positioned between the first and second bit lines 360_1 and 360_2, whereas in FIG. 4, the shield pattern 400 is between the first and second bit lines 360_1 and 360_2. ) is shown as being located.

The shield pattern 400 may extend in the second direction D2 along the first and second bit lines 360_1 and 360_2 and may be disposed in plurality to be spaced apart from each other in the first direction D1.

The shield pattern 400 may be positioned between the first and second bit lines 360_1 and 360_2 in the first direction D1. For example, the first insulating pattern 185, the first bit line 360_1, the shield pattern 400, and the second bit line 360_2 may be sequentially positioned along the first direction D1, This pattern may be repeated along the first direction D1.

Optionally, a spacer may be positioned between the shield pattern 400 and the first and second bit lines 360_1 and 360_2. The spacer may include, for example, an oxide such as silicon oxide.

Also, the height of the top surface of the shield pattern 400 may be higher than the height of the top surface of the bit line 360 and may extend to the height of the top surface of the direct contact 340 .

For example, the shield pattern 400 may include a metal nitride such as titanium nitride or tantalum nitride.

The shield pattern 400 can reduce disturbance and parasitic capacitance between the bit lines 360, thereby reducing RC-delay and improving operating speed.

Meanwhile, although only the cell region of the semiconductor device is illustrated in FIGS. 1 to 4 , some components shown in FIGS. 1 to 4 may be formed in the peripheral circuit region of the semiconductor device.

For example, in the case of the first and second word lines 305_1 and 305_2, FIG. 1 shows that they extend in the first direction D1, but each of the first and second words constituting one word line pair The lines 305_1 and 305_2 may include portions extending in the second direction D2 in the peripheral circuit area, and when viewed from the top, the first and second word lines 305_1 and 305_2 together have a ring shape as a whole. can However, a separator separating the first and second word lines 305_1 and 305_2 from each other may be formed in the peripheral circuit area or in the cell area in some cases. Accordingly, the first and second word lines 305_1 and 305_2 They may be electrically insulated from each other.

In addition, in the case of the shield pattern 400 disposed between the first and second bit lines 360_1 and 360_2 and extending in the second direction D2, a portion extending in the first direction D1 in the peripheral circuit area Accordingly, a plurality of shield patterns 400 spaced apart from each other in the first direction D1 in the cell area may be connected to each other in the peripheral circuit area. Meanwhile, contact plugs and wires electrically connected to the first and second bit lines 360_1 and 360_2 and the shield pattern 400 may be additionally formed in the peripheral circuit area.

Hereinafter, a method of manufacturing a semiconductor device according to an aspect will be described with reference to FIGS. 5 to 22 .

5 to 17 and 19 to 22 are cross-sectional views illustrating an intermediate step of a method of manufacturing a semiconductor device according to one aspect, and FIG. 18 is a cross-sectional view showing an intermediate step of a method of manufacturing a semiconductor device according to another aspect. It is a cross section corresponding to 17.

Referring to FIG. 5 , a substrate structure 101 including a substrate 100 , a first sacrificial layer 105 , a second sacrificial layer 115 , and a semiconductor layer 130 is prepared.

For example, the substrate 100, the first sacrificial layer 105, the second sacrificial layer 115, and the semiconductor layer 130 may be sequentially stacked along the third direction D3.

The substrate 100 may include a semiconductor material, an insulating material, or a conductive material.

For example, the substrate 100 may be a bulk silicon substrate, and may not be a Silicon On Insulator (SOI) substrate or a Germanium On Insulator (GOI) substrate.

For example, the first sacrificial layer 105 , the second sacrificial layer 115 , and the semiconductor layer 130 may be formed on the substrate 100 using an epitaxial growth method.

The first sacrificial layer 105 , the second sacrificial layer 115 , and the semiconductor layer 130 may include different materials. For example, the first and second sacrificial layers 105 and 115 may include SiGe, and the semiconductor layer 130 may include Si. For example, the first and second sacrificial layers 105 and 115 may include low concentration, medium concentration, or high concentration of Ge. In the case of low concentration, the Ge content is greater than 0 at% to 15 at% or less, in the case of medium concentration, the Ge content may be 15 at% to 35 at%, and in the case of high concentration, the Ge content may be defined as greater than 35 at% .

However, the etch rate of the first sacrificial layer 105 may be greater than that of the second sacrificial layer 115 . For example, the difference in etching rate between the first sacrificial layer 105 and the second sacrificial layer 115 may use the difference in concentration of Ge included in the first sacrificial layer 105 and the second sacrificial layer 115. . As described in FIGS. 11 to 14 described later, the first sacrificial layer 105 among the first sacrificial layer 105 and the second sacrificial layer 115 is removed first, and then the first sacrificial layer 105 is removed. This is to remove the second sacrificial layer 115 after forming the interlayer insulating pattern 187 in the region 105_T1.

Referring to FIG. 6 , the semiconductor layer 130, the second sacrificial layer 115, and the first sacrificial layer 105 are selectively patterned to a partial depth of the substrate 100 in the second direction D2. 1 A preliminary semiconductor pattern 135_P1 may be formed.

For example, the patterning of the semiconductor layer 130, the second sacrificial layer 115, and the first sacrificial layer 105 forms a mask structure (not shown) on the semiconductor layer 130 and uses it as an etching mask. can be done using

For example, the mask structure may extend in the second direction D2 and may be formed in plurality so as to be spaced apart from each other along the first direction D1. The mask structure may include, for example, an oxide such as silicon oxide and may include an insulating nitride such as silicon nitride.

Accordingly, the first preliminary semiconductor patterns 135_P1 formed through the etching process may extend in the second direction D2 and may be formed in plurality to be spaced apart from each other along the first direction D1.

At this time, in the first preliminary semiconductor pattern 135_P1 formed on the substrate 100, the patterned first sacrificial layer 105, the second sacrificial layer 115, and the semiconductor layer 130 are stacked and formed in the second direction D2. can be extended to

A first trench 135_T1 exposing the substrate 100 and extending in the second direction D2 may be formed between first preliminary semiconductor patterns 135_P1 adjacent to each other in the first direction D1 .

Referring to FIG. 7 , a first preliminary insulating pattern 185_P filling the first trench 135_T1 may be formed between the first preliminary semiconductor patterns 135_P1.

For example, the first preliminary insulating pattern 185_P may be formed through a deposition process such as a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process.

Optionally, when the first trench 135_T1 is formed to a partial depth of the substrate 100, the first preliminary insulating pattern 185_P is formed to a partial depth of the substrate 100, and then the first insulating pattern 185 It may have a protrusion 185_M extending in the third direction D3 toward the substrate 100 .

Referring to FIG. 8 , the semiconductor layer 130 may be patterned to form first and second preliminary semiconductor structures 137_P1 and 137_P2 , and an upper surface of the second sacrificial layer 115 may be exposed.

For example, patterning of the semiconductor layer 130 may be performed by forming a mask structure (not shown) on the semiconductor layer 130 and using it as an etching mask.

For example, the mask structure may extend in the second direction D2 and may be formed in plurality so as to be spaced apart from each other along the first direction D1. The mask structure may include, for example, an oxide such as silicon oxide and may include an insulating nitride such as silicon nitride.

The first and second preliminary semiconductor structures 137_P1 and 137_P2 may extend in the second direction D2 and may be formed in plurality to be spaced apart from each other along the first direction D1. In this case, the first preliminary semiconductor structure 137_P1 may be positioned on one side of the first preliminary insulating pattern 185_P, and the second preliminary semiconductor structure 137_P2 may be positioned on the other side of the first preliminary insulating pattern 185_P. A second trench 135_T2 exposing a top surface of the second sacrificial layer 115 and extending in the second direction D2 may be formed between the first and second preliminary semiconductor structures 137_P1 and 137_P2 .

Referring to FIG. 9 , a first spacer 137_S1 may be selectively formed on sidewalls of the first and second preliminary semiconductor structures 137_P1 and 137_P2 . The first spacer 137_S1 serves to protect the first and second preliminary semiconductor structures 137_P1 and 137_P2 in a direct contact 340 and bit line 360 formation process, which will be described later. However, the first spacer 137_S1 may not be formed on the upper surface of the second sacrificial layer 115 .

10, the second sacrificial layer 115 and the first sacrificial layer 105 through the second trench 135_T2 between the first and second preliminary semiconductor structures 137_P1 and 137_P2, and optionally the substrate ( The second preliminary semiconductor pattern 135_P2 may be formed by patterning to a partial depth of 100).

The second preliminary semiconductor pattern 135_P2 may extend in the second direction D2 and may be formed in plurality to be spaced apart from each other along the first direction D1. In this case, the first preliminary insulating pattern 185_P may be positioned between the second preliminary semiconductor patterns 135_P2, and the second preliminary semiconductor pattern 135_P2 positioned on one side of the first preliminary insulating pattern 185_P may be positioned on the third preliminary insulating pattern 135_P2. It may include the first sacrificial layer 105, the second sacrificial layer 115, and the first preliminary semiconductor structure 137_P1 sequentially stacked in the direction D3, and other parts of the first preliminary insulating pattern 185_P may be included. The second preliminary semiconductor pattern 135_P2 located on the side includes the first sacrificial layer 105, the second sacrificial layer 115, and the second preliminary semiconductor structure 137_P1 sequentially stacked in the third direction D3. can do.

A third trench 135_T3 exposing the substrate 100 and extending in the second direction D2 may be formed between second preliminary semiconductor patterns 135_P2 adjacent to each other in the first direction D1 . That is, the second preliminary semiconductor pattern 135_P2, the first preliminary insulating pattern 185_P, the second preliminary semiconductor pattern 135_P2, and the third trench 135_T3 may be sequentially positioned in the first direction D1. , this pattern may be repeated along the first direction D1.

Referring to FIG. 11 , the first sacrificial layer 105 exposed through the third trench 135_T3 is removed.

For example, a wet etching process may be used to remove the first sacrificial layer 105 .

The first sacrificial layer 105 removal region 105_T1 is formed in the region where the first sacrificial layer 105 is located, and the sidewall of the first preliminary insulating pattern 185_P that is in contact with the first sacrificial layer 105 and the substrate The upper surface of the 100 and the lower surface of the second sacrificial layer 115 may be exposed to the outside. At this time, the exposed parts may remain without being affected by the etching solution. For example, since the etching rate of the second sacrificial layer 115 is slower than that of the first sacrificial layer 105 due to the difference in Ge concentration, the second sacrificial layer 115 is removed when the first sacrificial layer 105 is removed. It may not be.

Referring to FIG. 12 , a preliminary interlayer insulating pattern 187_P filling the first sacrificial layer 105 removed region 105_T1 and the third trench 135_T3 may be formed.

For example, the preliminary interlayer insulating pattern 187_P may be formed through a deposition process such as a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process.

Optionally, when the third trench 135_T3 is formed to a partial depth of the substrate 100, a preliminary interlayer insulating pattern 187_P is formed to a partial depth of the substrate 100, and then the interlayer insulating pattern 187 is formed to a partial depth of the substrate 100 ( 100) may have a protrusion 187_M extending in the third direction D3.

Referring to FIG. 13 , the interlayer insulating pattern 187 may be formed by etching the preliminary interlayer insulating pattern 187_P until the second sacrificial layer 115 is exposed.

Accordingly, the interlayer insulating pattern 187 may be formed in a lower region between the first sacrificial layer 105 removed region 105_T1 and the first and second preliminary semiconductor structures 137_P1 and 137_P2. The height of the upper surface of the interlayer insulating pattern 187 may be the same as the height of the lower surface of the second sacrificial layer 115 or slightly lower than the height of the lower surface of the second sacrificial layer 115 .

Optionally, when the third trench 135_T3 is formed to a partial depth of the substrate 100, the interlayer insulating pattern 187 may have a protrusion 187_M extending toward the substrate 100 in the third direction D3. there is.

In addition, the upper surface of the interlayer insulating pattern 187 is exposed between the first and second preliminary semiconductor structures 137_P1 and 137_P2 and the second sacrificial layer 115 adjacent to each other in the first direction D1, and the second direction ( A fourth trench 135_T4 extending to D2) may be formed.

Referring to FIG. 14 , the second sacrificial layer 115 exposed through the fourth trench 135_T4 is removed.

For example, a wet etching process may be used to remove the second sacrificial layer 115 .

The second sacrificial layer 115 removal region 115_T1 is formed in the region where the second sacrificial layer 115 is located, and sidewalls and interlayer insulation of the first preliminary insulating pattern 185_P in contact with the second sacrificial layer 115 are formed. Upper surfaces of the pattern 187 and lower surfaces of the first and second preliminary semiconductor structures 137_P1 and 137_P2 may be exposed to the outside. At this time, the exposed parts may remain without being affected by the etching solution.

Referring to FIG. 15 , a direct contact 340 may be selectively formed under the first and second preliminary semiconductor structures 137_P1 and 137_P2 exposed through the removal region 115_T1 of the second sacrificial layer 115 .

For example, the direct contact 340 may be formed by doping n-type or p-type impurities by performing a doping process such as a GPD process or a PLAD process on the lower portions of the first and second preliminary semiconductor structures 137_P1 and 137_P2. .

Referring to FIG. 16 , a bit line 360 is formed in the removed region 115_T1 of the second sacrificial layer 115 .

For example, the bit line 360 may include a metal such as tungsten, titanium, or tantalum, and in this case, the bit line 360 may be formed in an embossed manner. That is, after forming a metal pattern on the upper surface of the second sacrificial layer 115 removed region 115_T1 and the interlayer insulating pattern 187, the metal pattern is patterned to form a metal pattern on the second sacrificial layer 115 removed region 115_T1. The bit line 360 may be formed in the removed region 115_T1 of the second sacrificial layer 115 by removing the metal pattern formed on the upper surface of the interlayer insulating pattern 187 while leaving the pattern.

Through this, the first bit line 360_1 is formed in the region 115_T1 of the second sacrificial layer 115 removed below the first preliminary semiconductor structure 137_P1, and the lower portion of the second preliminary semiconductor structure 137_P1 is formed. A second bit line 360_2 may be formed in the removed region 115_T1 of the second sacrificial layer 115 positioned at .

Referring to FIG. 17 , the first spacer 137_S1 positioned on the sidewall of the first and second preliminary semiconductor structures 137_P1 and 137_P2 is removed, and the first and second bit lines 360_1 and 360_2 and the first And a second preliminary insulating pattern 186_P filling the fourth trench 135_T4 may be formed between the second preliminary semiconductor structures 137_P1 and 137_P2. However, the removal of the first spacer 137_S1 is optional, and the second preliminary insulating pattern 186_P may be formed without removing the first spacer 137_S1.

For example, the second preliminary insulating pattern 186_P may be formed through a deposition process such as a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process.

Referring to FIG. 18 , optionally, after forming the shield pattern 400 before forming the second preliminary insulating pattern 186_P, the second preliminary insulating pattern 186_P may be formed on the shield pattern 400 . there is.

For example, after forming a spacer covering the sidewall of the bit line 360 exposed through the fourth trench 135_T4 and forming a shield layer filling the fourth trench 135_T4 between the spacers, The shield pattern 400 may be formed below the fourth trench 135_T4 by removing an upper portion of the shield layer through, for example, an etch-back process. In this case, the shield layer may be etched back so that its top height is substantially the same as that of the direct contact 340 .

Referring to FIG. 19 , the first and second preliminary semiconductor structures 137_P1 and 137_P2 are patterned in a first direction D1. In this case, the first and second preliminary insulating patterns 185_P and 186_P may also be patterned together.

For example, a dry etching process may be used to pattern the first and second preliminary semiconductor structures 137_P1 and 137_P2 and the first and second preliminary insulating patterns 185_P and 186_P.

Accordingly, a fifth trench 137_T1 extending in the first direction D1 may be formed.

Referring to FIG. 20 , after the third insulating film 270 is selectively formed under the fifth trench 137_T1, the example is formed on sidewalls and lower surfaces of the fifth trench 137_T1 or on the upper surface of the third insulating film 270. For example, the first gate insulating film 207 is formed by performing a deposition process such as a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process.

Thereafter, a back gate electrode 215 filling the fifth trench 137_T1 is formed on the first gate insulating layer 207 .

Optionally, after the upper portion of the back gate electrode 215 is removed by, for example, an etch-back process, the sixth insulating layer 540 may be formed on the upper portion of the back gate electrode 215 .

Referring to FIG. 21 , the first and second preliminary semiconductor structures 137_P1 and 137_P2 between the back gate electrode 215 are patterned in the first direction D1 to form a first semiconductor pattern on one side of the back gate electrode 215. (137_1) is formed, and a second semiconductor pattern (137_2) is formed on the other side. At this time, the first and second preliminary insulating patterns 185_P and 186_P are also patterned together to form the first and second insulating patterns 185 and 186 .

Accordingly, a sixth trench 137_T2 extending in the first direction D1 may be formed between the neighboring first and second semiconductor patterns 137_1 and 137_2 .

Referring to FIG. 22 , after the fourth insulating film 330 is selectively formed under the sixth trench 137_T2 , an example is formed on sidewalls and lower surfaces of the sixth trench 137_T2 or on the upper surface of the fourth insulating film 330 . For example, the second gate insulating layer 297 is formed by performing a deposition process such as a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process.

Thereafter, a first word line 305_1 extending in the first direction D1 is formed on one side of the first semiconductor pattern 137_1 on the second gate insulating layer 297, and the other side of the second semiconductor pattern 137_2 is formed. A second word line 305_2 extending in the first direction D1 is formed on the side.

For example, after forming a metal pattern on the sidewall and lower surface of the sixth trench 137_T2 or the upper surface of the fourth insulating film 330, the metal pattern is patterned to form a first word line on one side of the first semiconductor pattern 137_1. 305_1 may be formed, and a second word line 305_2 may be formed on the other side of the second semiconductor pattern 137_2.

Thereafter, a second insulating film 310 may be formed between the first and second word lines 305_1 and 305_2, and a seventh insulating film 545 may be formed on the first and second word lines 305_1 and 305_2. .

Optionally, a buried contact 605 may be formed on the first and second semiconductor patterns 137_1 and 137_2 .

For example, the buried contact 605 is formed by doping the first and second semiconductor patterns 137_1 and 137_2 with n-type or p-type impurities by performing a doping process such as a GPD process or a PLAD process, for example. can be formed

Next, the first and second semiconductor patterns 137_1 and 137_2, the first insulating pattern 185, the second insulating pattern 186, the first and second gate insulating films 207 and 297, and the second and second insulating patterns 185 A first etch stop layer, an interlayer insulating layer, and a capping layer are sequentially formed on the sixth and seventh insulating layers 310, 540, and 545, and partially etched to form upper surfaces of the first and second semiconductor patterns 137_1 and 137_2. can be exposed.

Thereafter, a lower contact plug layer is formed on the first and second semiconductor patterns 137_1 and 137_2 and the capping layer, and the lower contact plug layer is planarized until the upper surface of the capping layer is exposed. , and may be removed through an etch-back process to form a lower contact plug.

Thereafter, an ohmic contact pattern and an upper contact plug sequentially stacked on top of the lower contact plug may be formed.

In the ohmic contact pattern, a metal film is formed on the lower contact plug and the capping film, a heat treatment process is performed on the metal film, and a metal silicide film is formed by reacting the metal film formed on the lower contact plug with the lower contact plug. can be formed by removing

An upper contact plug may be formed by forming an upper contact plug film over the ohmic contact pattern and the capping film, and planarizing the upper contact plug film until a top surface of the capping film is exposed.

Thereafter, a second etch stop layer, a first mold layer, a first support layer, a second mold layer, and a second support layer are sequentially stacked on the capping layer and the upper contact plug, and partially etched to form the upper surface of the upper contact plug. After exposure, a first capacitor electrode may be formed on the upper contact plug.

The first and second mold layers may include, for example, oxide such as silicon oxide.

After exposing the surface of the first capacitor electrode and the surfaces of the first and second support films by removing the first and second mold films, the exposed surfaces of the first capacitor electrode and the first and second support films and the second A dielectric layer may be formed on an upper surface of the etch stop layer.

After that, a second capacitor electrode may be formed on the dielectric layer.

The first and second capacitor electrodes and the dielectric film formed therebetween may together form a capacitor.

As described above, in the method of manufacturing a semiconductor device according to one aspect, a vertical channel transistor (VCT) may be manufactured using a bulk silicon wafer without wafer bonding. Accordingly, it is possible to reduce wafer cost, and since wafer bonding is not required, photo overlay conditions on the rear side of the wafer associated with stress and twist can be relieved.

Although the embodiments of the present disclosure have been described in detail above, the scope of the present disclosure is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present disclosure defined in the following claims are also disclosed. falls within the scope of the rights of

100: substrate
101: substrate structure
105: first sacrificial layer 105_T1: first sacrificial layer removal region
115: second sacrificial layer 115_T1: second sacrificial layer removal region
130: semiconductor layer 135_P1: first preliminary semiconductor pattern
135_T1: first trench 135_T2: second trench
135_T3: third trench 135_T4: fourth trench
135_P2: second preliminary semiconductor pattern
137_1, 137_2: first and second semiconductor patterns
137_P1: first preliminary semiconductor structure 137_P2: second preliminary semiconductor structure
137_S1: first spacer
137_T1: fifth trench 137_T2: sixth trench
185: first insulating pattern
185_M: protruding portion of the first insulating pattern 185_P: first preliminary insulating pattern
186: second insulating pattern 186_P: second preliminary insulating pattern
187 Interlayer insulation pattern
187_M: projection of interlayer insulation pattern 187_P: preliminary interlayer insulation pattern
215: back gate electrode
207, 297: first and second gate insulating films
270: third insulating film
305_1, 305_2: first and second word lines
310: second insulating film 330: fourth insulating film
340: direct contact
360: bit line 360_1, 360_2: first and second bit lines
400: shield pattern
540: 6th insulating film 545: 7th insulating film
605: buried contact

Claims (10)

Board;
bit lines positioned on the substrate, spaced apart from each other in a first direction, and extending in a second direction different from the first direction;
first and second semiconductor patterns positioned on the bit line, spaced apart from each other in the first and second directions, and extending in a third direction different from the first and second directions;
a back gate electrode positioned between the first and second semiconductor patterns and extending in the first direction; and
A first word line positioned to correspond to the back gate electrode with the first semiconductor pattern interposed therebetween and extending in the first direction, and positioned to correspond to the back gate electrode with the second semiconductor pattern interposed therebetween; A second word line extending in the first direction; includes,
Including an interlayer insulating pattern positioned between the substrate and the bit line,
semiconductor device. In paragraph 1,
The interlayer insulating pattern has a protrusion extending toward the substrate,
The semiconductor device of claim 1 , wherein the protruding portion of the interlayer insulating pattern is located inside the substrate. In paragraph 1,
The semiconductor device,
a first insulating pattern positioned on the substrate and extending in the third direction; and
A second insulating pattern positioned between the first insulating patterns and extending in the third direction;
The bit line includes first and second bit lines disposed between the first insulating pattern and disposed with the second insulating pattern interposed therebetween;
The interlayer insulating pattern is positioned between the first insulating pattern and positioned under the second insulating pattern and the first and second bit lines,
semiconductor device. In paragraph 3,
The first insulating pattern has a protrusion extending toward the substrate,
The first insulating pattern extends from the inside of the substrate to upper portions of the first and second semiconductor patterns in the third direction.
semiconductor device. In paragraph 3,
The semiconductor device,
Spaced apart from each other in the first direction and extending in the second direction,
located between the first and second bit lines in the first direction;
Further comprising a shield pattern positioned between the interlayer insulating pattern and the second insulating pattern in the third direction,
semiconductor device. In paragraph 1,
The semiconductor device,
Further comprising a direct contact between the bit line and the first and second semiconductor patterns,
Further comprising buried contacts on the first and second semiconductor patterns,
semiconductor device. preparing a substrate structure including a substrate, a first sacrificial layer, a second sacrificial layer, and a semiconductor layer;
patterning the first sacrificial layer, the second sacrificial layer, and the semiconductor layer in a second direction, removing the first sacrificial layer, and forming an interlayer insulating pattern in a region from which the first sacrificial layer is removed;
removing the second sacrificial layer and forming a bit line in a region from which the second sacrificial layer was removed;
patterning the semiconductor layer in a first direction different from the second direction, and then forming a back gate electrode;
After patterning the semiconductor layer positioned between the back gate electrodes in the first direction, forming a first semiconductor pattern on one side of the back gate electrode and a second semiconductor pattern on the other side of the back gate electrode;
forming a first word line extending in the first direction on one side of the first semiconductor pattern and forming a second word line extending in the first direction on the other side of the second semiconductor pattern;
A method of manufacturing a semiconductor device. In paragraph 7,
After patterning the first sacrificial layer, the second sacrificial layer, and the semiconductor layer in a second direction,
forming first preliminary semiconductor patterns spaced apart from each other in the first direction and extending in the second direction different from the first direction;
Forming a first preliminary insulating pattern between the first preliminary semiconductor patterns;
Patterning the first preliminary semiconductor pattern to include first and second preliminary semiconductor structures spaced apart from each other in the first direction, extending in the second direction, and disposed with the first preliminary insulating pattern interposed therebetween, Forming a second preliminary semiconductor pattern;
After forming the bit line, forming a second preliminary insulating pattern between the second preliminary semiconductor patterns,
A method of manufacturing a semiconductor device. In paragraph 7,
After removing the second sacrificial layer and forming direct contacts at lower ends of the first and second preliminary semiconductor structures exposed through the region from which the second sacrificial layer was removed, the region from which the second sacrificial layer was removed forming the bit line;
Forming a buried contact on the first and second semiconductor patterns,
A method of manufacturing a semiconductor device. In paragraph 7,
After forming the bit line, a shield pattern is formed on the interlayer insulating pattern.