KR20230109528A - Nonvolatile memory device and storage device including nonvolatile memory device - Google Patents

Abstract

A nonvolatile memory device according to an embodiment of the present invention includes a memory cell array including a plurality of memory cells, a plurality of bit lines and word lines connected to the plurality of memory cells, and a common source connected to the plurality of memory cells. A control logic circuit including a line, a common source line noise control logic circuit, generating a plurality of voltages including first and second voltages, receiving the plurality of voltages, and selecting at least one of the plurality of voltages. and a common source line driver configured to control a voltage of a common source line by receiving the selected at least one voltage, wherein the common source line noise control logic circuit controls the plurality of voltages based on program information. The voltage selector may be controlled to select at least one of

Description

A non-volatile memory device and a storage device including a non-volatile memory device

The present invention relates to a semiconductor memory, and more particularly, to a nonvolatile memory device and a storage device including the nonvolatile memory device.

Non-volatile memory includes Read Only Memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable and Programmable ROM (Electrically Erasable and Programmable ROM). Programmable ROM (EEPROM), flash memory, phase-change random access memory (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), ferroelectric RAM (Ferroelectric RAM, FRAM) ), etc.

As semiconductor manufacturing technology develops, attempts to implement a nonvolatile memory in a three-dimensional structure continue. A 3D structure can provide a larger number of memory cells while using the same chip area as compared to a 2D structure. However, the 3D structure of the nonvolatile memory has a problem in that the process difficulty is higher than that of the 2D structure and unintended noise is generated.

An object of the present invention is to provide a nonvolatile memory device capable of equalizing noise of a common source line and a storage device including the nonvolatile memory device.

A nonvolatile memory device according to an embodiment of the present invention includes a memory cell array including a plurality of memory cells, a plurality of bit lines and word lines connected to the plurality of memory cells, and a common source connected to the plurality of memory cells. A control logic circuit including a line, a common source line noise control logic circuit, generating a plurality of voltages including first and second voltages, receiving the plurality of voltages, and selecting at least one of the plurality of voltages. and a common source line driver configured to control a voltage of a common source line by receiving the selected at least one voltage, wherein the common source line noise control logic circuit controls the plurality of voltages based on program information. The voltage selector may be controlled to select at least one of

A method of operating a nonvolatile memory device according to an embodiment of the present invention includes generating a plurality of voltages including first and second voltages by a control logic circuit, and performing a voltage selector to generate the plurality of voltages based on program information. The method may include selecting at least one of the voltages, and controlling a voltage of the common source line by a common source line driver by receiving the selected voltage.

A storage device according to an embodiment of the present invention includes a nonvolatile memory device and a memory controller for controlling the nonvolatile memory device, wherein the nonvolatile memory device includes a memory cell array including a plurality of cells, the A plurality of voltages including a plurality of bit lines and word lines connected to a plurality of memory cells, a common source line connected to the plurality of memory cells, a common source line noise control logic circuit, and including first and second voltages. A control logic circuit for generating a voltage, a voltage selector for receiving the plurality of voltages and selecting at least one of the plurality of voltages, and a common source line driver for receiving the selected at least one voltage and controlling a common source line voltage. The common source line noise control logic circuit may control the voltage selector to select at least one of the plurality of voltages based on program information.

According to the present invention, noise of the common source line can be made uniform by controlling the voltage of the common source line. Accordingly, a nonvolatile memory device having improved performance and reliability and a storage device including the nonvolatile memory device are provided.

1 is a block diagram showing a nonvolatile memory device according to an exemplary embodiment of the present invention.
FIG. 2 is a circuit diagram showing an example of one memory block among the memory blocks of FIG. 1 .
3 shows an example in which a nonvolatile memory device performs a program operation in response to a program command.
4 shows an example in which a nonvolatile memory device performs program loops of a program operation in response to a program command.
5A to 5C illustrate an operation of the nonvolatile memory device of FIG. 1 .
6 shows an example of a common source line driver according to an embodiment of the present invention.
7 shows an example of a common source line driver according to an embodiment of the present invention.
8 is a flowchart illustrating an operation of a nonvolatile memory device according to an exemplary embodiment of the present invention.
9 illustrates a storage device including a nonvolatile memory device according to an embodiment of the present invention.

In the following, embodiments of the present invention will be described clearly and in detail to the extent that a person skilled in the art can easily practice the present invention.

1 is a block diagram showing a nonvolatile memory device according to an exemplary embodiment of the present invention. Referring to FIG. 1 , a nonvolatile memory device 100 includes a memory cell array 110, a row decoder circuit 120, a page buffer circuit 130, a data input and output circuit 140, a buffer circuit 150, It includes a control logic and voltage generation circuit (160, hereinafter referred to as a control logic circuit), a voltage selector 170, a common source line driver 180, and a temperature sensing circuit 190.

The memory cell array 110 includes a plurality of memory blocks BLK1 to BLKz (z is a positive integer). Each memory block includes a plurality of memory cells. Each memory block may be connected to the row decoder circuit 120 through at least one ground select line GSL, word lines WL, and at least one string select line SSL. Some of the word lines WL may be used as dummy word lines. Each memory block may be connected to the page buffer circuit 130 through a plurality of bit lines BL. The plurality of memory blocks BLK1 to BLKz may be commonly connected to a plurality of bit lines BL.

For example, each of the plurality of memory blocks BLK1 to BLKz may be a unit of an erase operation. Memory cells belonging to each memory block may be simultaneously erased. As another example, each memory block may be divided into a plurality of sub-blocks. Each of the plurality of sub blocks may be a unit of an erase operation.

The row decoder circuit 120 is connected to the memory cell array 110 through ground select lines GSL, word lines WL, and string select lines SSL. The row decoder circuit 120 operates under the control of the control logic circuit 160 .

The row decoder circuit 120 decodes the row address RA received from the buffer circuit 160, and generates string select lines SSL, word lines WL, and ground select lines according to the decoded row address. The voltages applied to (GSL) can be controlled.

The page buffer circuit 130 is connected to the memory cell array 110 through a plurality of bit lines BL. The page buffer circuit 130 is connected to the data input and output circuit 140 through a plurality of data lines DL. The page buffer circuit 130 operates under the control of the control logic circuit 160 .

During a program operation, the page buffer circuit 130 may store data to be written in memory cells. Based on the stored data, the page buffer circuit 130 may apply voltages to the plurality of bit lines BL. During a read operation or during a verify read operation of a program operation or an erase operation, the page buffer circuit 130 may sense voltages of the bit lines BL and store the detection result.

The data input and output circuit 140 is connected to the page buffer circuit 130 through a plurality of data lines DL. The data input and output circuit 140 may receive the column address CA from the buffer circuit 150 . The data input/output circuit 140 may output the data read by the page buffer circuit 130 to the buffer circuit 150 according to the column address CA. The data input/output circuit 140 may transfer data received from the buffer circuit 150 to the page buffer circuit 130 depending on the column address CA.

The buffer circuit 150 may receive the command CMD and the address ADDR from an external device through the first signal lines SIGL1 and exchange data DATA with the external device. The buffer circuit 150 may operate under the control of the control logic circuit 160 . The buffer circuit 150 may transfer the command CMD to the control logic circuit 160 . The buffer circuit 150 may transfer the row address RA of the address ADDR to the row decoder circuit 120 and transfer the column address CA to the data input/output circuit 140 . The buffer circuit 150 may exchange data DATA with the data input and output circuit 140 .

The control logic circuit 160 supplies various voltages necessary for the nonvolatile memory device 100 to operate, for example, a plurality of program voltages, a plurality of program verify voltages, a plurality of pass voltages, and a plurality of read voltages. , a plurality of erase voltages, and the like.

The control logic circuit 160 may exchange the control signal CTRL with an external device through the second signal lines SIGL2. The control logic circuit 160 may control the buffer circuit 150 to route the command CMD, address ADDR, and data DATA. The control logic circuit 160 may decode the command CMD received from the buffer circuit 150 and control the nonvolatile memory device 100 according to the decoded command.

The control logic circuit 160 may include a common source line noise control logic circuit 165 . Common source line noise control logic circuit 165 may control voltage selector 170 . For example, the common source line noise control logic circuit 165 may control the voltage selector 170 to select at least one of a plurality of voltages received from the control logic circuit 160 based on program information. Common source line noise control logic circuit 165 may control voltage selector 170 to provide a selected voltage to common source line driver 180 .

As another example, the common source line noise control logic circuit 165 can control the voltage selector 170 to vary the selected voltage to another voltage. In this case, the other voltage may be at least one other voltage among the plurality of voltages received by the voltage selector 170 .

The common source line noise control logic circuit 165 may control the common source line driver 180 . For example, common source line noise control logic circuit 165 can control the transistors of common source line driver 180 . The common source line noise control logic circuit 165 may control the transistor of the common source line driver 180 to turn on or off in response to the received voltage.

As another example, when the common source line driver 180 includes two or more transistors, the common source line noise control logic circuit 165 may separate and control each transistor.

As another example, the common source line noise control logic circuit 165 may control the common source line driver 180 to control the voltage of the common source line CSL.

The voltage selector 170 may be connected to the control logic circuit 160 and the common source line driver 180 . The voltage selector 170 may receive a plurality of voltages from the control logic circuit 160 .

Voltage selector 170 may operate under the control of common source line noise control logic circuit 165 . For example, the voltage selector 170 selects at least one of the received voltages based on program information under the control of the common source line noise control logic circuit 165, and uses the selected voltage as the common source line driver 180 ) can be provided. In this case, the voltage selector 170 may select as many voltages as the number of transistors of the common source line driver 180 .

As another example, the voltage selector 170 may vary the selected voltage into another voltage under the control of the common source line noise control logic circuit 165 . In this case, the other voltage may be at least one other voltage among the plurality of voltages received by the voltage selector 170 .

The common source line driver 180 may be connected to the voltage selector 170 and the common source line CSL. The common source line driver 180 may be configured to control the voltage of the common source line CSL or provide a bias according to the control of the control logic circuit 160 . Alternatively, the common source line driver 180 may ground the common source line CSL.

Common source line driver 180 may receive at least one voltage from voltage selector 170 . The voltage received by the common source line driver 180 may be a gate voltage of a transistor of the common source line driver 180 .

The common source line driver 180 may include at least one transistor. A transistor of the common source line driver 180 may be turned on or off by receiving a voltage from the voltage selector 170 under the control of the common source line noise control logic circuit 165 . When the common source line driver 180 includes two or more transistors, the common source line driver 180 may separate and control each of the transistors according to the control of the common source line noise control logic circuit 165 .

The temperature sensing circuit 190 may be connected to the control logic circuit 160 . The temperature sensing circuit 190 may sense the temperature of the surrounding area and provide a sensing result signal to the common source line noise control logic circuit 165 . In this case, the common source line noise control logic circuit 165 may control the voltage selector 170 to select at least one of the received voltages based on a detection result.

In the above-described embodiment, under the control of the common source line noise control logic circuit 165, the voltage selector 170 may select at least one of a plurality of received voltages based on program information. The common source line driver 180 may receive at least one voltage selected from the voltage selector 170 . In response to the received voltage, at least one transistor of the common source line driver 180 may be turned on or off under the control of the common source line noise control logic circuit 165 .

In the above-described embodiment, since the channel resistance of the transistor of the common source line driver 180 changes as the voltage selector 170 and the common source line driver 180 are controlled by the common source noise control logic circuit 165, Noise of the common source line CSL can be equally adjusted.

For example, the nonvolatile memory device 100 may be manufactured using a bonding method. The memory cell array 110 is fabricated on a first wafer and includes a row decoder circuit 120, a page buffer circuit 130, a data input and output circuit 140, a buffer circuit 150, and a control logic circuit 160. can be fabricated on the second wafer. The nonvolatile memory device 100 may be implemented by facing the upper surface of the first wafer and the upper surface of the second wafer and combining them.

As another example, the nonvolatile memory device 100 may be manufactured in a cell over periphery (COP) method. A row decoder circuit 120, a page buffer circuit 130, a data input and output circuit 140, a buffer circuit 150, a control logic circuit 160, a voltage generator 170, a common source line driver ( 180), and a peripheral circuit including a temperature sensing circuit 190 may be implemented. A memory cell array 110 may be implemented on top of the peripheral circuit. A peripheral circuit and the memory cell array 110 may be connected through through vias.

FIG. 2 is a circuit diagram showing an example of one memory block BLKa among the memory blocks BLK1 to BLKz of FIG. 1 of FIG. 1 . Referring to FIG. 2 , a plurality of cell strings CS11 , CS12 , CS21 , and CS22 may be arranged in rows and columns on the substrate SUB. Each row may extend along the first direction. Each row may extend along the second direction. The plurality of cell strings CS11 , CS12 , CS21 , and CS22 may be commonly connected to a common source line CSL formed on (or in) the substrate SUB. In FIG. 2 , in order to help understand the structure of the memory block BLKa, the position of the substrate SUB is exemplarily indicated. The substrate SUB may include a semiconductor material having a P conductivity type. However, the scope of the present invention is not limited thereto.

The cell strings of each row are commonly connected to the ground selection line GSL, and to corresponding string selection lines among the first string selection lines SSL1a and SSL1b and the second string selection lines SSL2a and SSL2b can be connected Cell strings of each column may be connected to corresponding bit lines among the first and second bit lines BL1 and BL2 . For example, the first and second bit lines BL1 and BL2 may be the bit lines of the first bit line group BG1, the bit lines of the second bit line group BG2, or the third bit line group. It may be included in the bit lines of (BG3).

Each cell string may include at least one ground select transistor GST connected to the ground select line GSL and a plurality of memory cells MC1 to MC8 respectively connected to a plurality of word lines WL1 to WL8. there is. The cell strings of the first row may further include string select transistors SSTa and SSTb respectively connected to the first string select lines SSL1a and SSL1b. The cell strings of the second row may further include string select transistors SSTa and SSTb respectively connected to the second string select lines SSL2a and SSL2b.

In each cell string, the ground selection transistor GST, the memory cells MC1 to MC8, and the string selection transistors SSTa and SSTb are serially connected in a direction perpendicular to the substrate SUB, for example, along a third direction. and may be sequentially stacked along a direction perpendicular to the substrate SUB. In each of the cell strings CS11 , CS12 , CS21 , and CS22 , at least one of the memory cells MC1 to MC8 may be used as a dummy memory cell. The dummy memory cell may be unprogrammed (eg, program prohibited) or programmed differently from the memory cells MC1 to MC8.

For example, memory cells positioned at the same height and associated with one string select line SSL1a, SSL1b, SSL2a, or SSL2b may form one physical page. Memory cells of one physical page may be connected to one sub word line. Sub word lines of physical pages positioned at the same height may be commonly connected to one word line. Hereinafter, the term 'word line' may refer to a word line or a sub-word line, and will be interpreted according to context.

Due to the resistance component present in the common source line CSL, when a current flows through the common source line CSL, a change in the common source line voltage VCSL occurs. Here, the common source line voltage (VCSL) is proportional to the cell current due to on-cell. For example, when the amount of current flowing through the common source line CSL increases as the number of on-cell memory cells connected to the selected word line increases, the common source line voltage VCSL may increase. Such a change in the common source line voltage VCSL becomes a noise voltage (hereinafter referred to as noise) existing in the common source line CSL.

3 shows an example in which a nonvolatile memory device performs a program operation in response to a program command. In FIG. 3 , a horizontal axis may indicate threshold voltages (VTH) of memory cells, and a vertical axis may indicate the number of memory cells.

Referring to FIGS. 1 to 3 , the nonvolatile memory device 100 may program memory cells in an erase state (E) into first to seventh program states P1 to P7 . The nonvolatile memory device 100 may program memory cells into first to seventh program states P1 to P7 using the first to seventh verification voltages VFY1 to VFY7 .

During the program operation, the threshold voltage of each of the memory cells may maintain an erase state (E) or may be programmed into one of the first to seventh program states P1 to P7. The program state may indicate a range of threshold voltages of memory cells. For example, memory cells programmed to the first program state P1 may be programmed to have a threshold voltage within a threshold voltage range indicated by the first program state P1. Similarly, memory cells programmed in the second to seventh program states P2 to P7 may be programmed to have threshold voltages included in threshold voltage ranges indicated by the second to seventh program states P2 to P7. there is.

4 shows an example in which a nonvolatile memory device performs program loops of program operations in response to a program command. In FIG. 4 , the horizontal axis indicates time (T), and the vertical axis indicates voltage (V) applied to the selected word line.

Referring to FIGS. 1 , 3 and 4 , during a program operation, the nonvolatile memory device 100 may perform first to m th program loops LP1 to LPm (where m is a positive integer). . Each of the first to m th program loops LP1 to LPm may include a program for applying the program voltage VPGM and verification for applying the first to seventh verification voltages VFY1 to VFY7 . Threshold voltages of memory cells of a selected word line (eg, a selected sub word line) may rise by applying the program voltage VPGM. Verification read may be performed by applying the first to seventh verification voltages VFY1 to VFY7 . For example, when the threshold voltage of a memory cell programmed to the first program state P1 is lower than the first verification voltage VFY1 , the corresponding memory cell may be determined to be a program fail. When the threshold voltage of a memory cell programmed to the first program state P1 is higher than the first verification voltage VFY1 , the corresponding memory cell may be program inhibited. Similarly, the nonvolatile memory device 100 may program the memory cells into the second to seventh program states P2 to P7 using the second to seventh verification voltages VFY2 to VFY7 .

As the program loop progresses (or is repeated), the level of the program voltage VPGM may increase. In initial program loops such as the first program loop LP1, some of the first to seventh verification voltages VFY1 to VFY7, such as the seventh verification voltage VFY7, higher than other verification voltages are not applied. may not be As the program loop progresses (or repeats), program states having a lower threshold voltage range than other program states, such as the first program state P1, may be programmed and passed before other program states. Among the first to seventh verification voltages VFY1 to VFY7 , a verification voltage (eg, the first verification voltage VFY1 ) corresponding to a programmed program state passed first may not be applied any longer.

5A to 5C illustrate operations of the nonvolatile memory device 100 of FIG. 1 . In FIG. 5A , the horizontal axis indicates the temperature Temp., and the vertical axis indicates the voltage VSEL selected from the voltage selector 170 . 5B, the horizontal axis indicates the distance between the common source line driver 180 and the cell string indicated by the address ADDR received from the external device, and the vertical axis indicates the voltage VSEL selected from the voltage selector 170. points to In FIG. 5C , a horizontal axis indicates a programmed state of memory cells, and a vertical axis indicates a voltage VSEL selected from the voltage selector 170 .

Referring to FIGS. 1 and 5A , the temperature detection circuit 190 may sense the temperature of the surrounding area and provide a signal resulting from the detection to the common source line control logic circuit 165 . The common source line noise control logic circuit 165 may control the voltage selector 170 to select at least one of the received voltages based on a detection result.

As a result of the detection, since the resistance of the common source line CSL is lower when the temperature of the peripheral area is low (Cold Temp.) than when the temperature of the peripheral area is high (Hot Temp.), the voltage (VSEL) selected from the voltage selector 170 ) can descend.

As a result of the detection, since the resistance of the common source line CSL is higher when the temperature of the peripheral area is high (Hot Temp.) than when the temperature of the peripheral area is low (Cold Temp.), the voltage (VSEL) selected from the voltage selector 170 ) can rise.

Referring to FIGS. 1 and 5B , when the address ADDR received from the external device points to a cell string close to the common source line driver, the common source line CSL is more Since the resistance is low, the voltage VSEL selected from the voltage selector 170 may fall.

Since the resistance of the common source line CSL is higher when the address ADDR received from the external device points to a cell string farther from the common source line driver than when it points to a cell string close to the common source line driver, the voltage selector 170 ), the voltage VSEL selected from may rise.

Referring to FIGS. 1, 3, and 5C, when the memory cells are programmed in the first program state P1, the distribution of threshold voltages VTH of the memory cells is greater than when the memory cells are programmed in the seventh program state P7. Since it is low, the voltage VSEL selected from the voltage selector 170 may fall.

When the memory cells are programmed in the seventh program state P7, the distribution of threshold voltages VTH of the memory cells is higher than that when the memory cells are programmed in the first program state P1, so the voltage selected by the voltage selector 170 (VSEL) may rise.

6 shows an example of a common source line driver 280 according to an embodiment of the present invention. Referring to FIGS. 1 and 6 , the voltage selector 170 may receive a plurality of voltages V1 to Vk (k is a positive integer), and the common source line driver 180 may include a transistor.

The voltage selector 170 may select one of the received voltages V1 to Vk based on program information under the control of the common source line noise control logic circuit 165 . In this case, the program information may include a temperature, an address (ADDR) received from an external device, and a program state. The voltage selector 170 may provide the selected voltage as the gate voltage VG of the transistor of the common source line driver 280 .

A transistor of the common source line driver 280 may receive a voltage selected by the voltage selector 170 . In response to the received voltage, the common source line driver 280 may control the voltage of the common source line CSL according to the control of the common source line noise control logic circuit 165 . As the common source line CSL is controlled by the common source line driver 280, noise of the common source line CSL can be equally adjusted.

7 shows an example of a common source line driver 380 according to an embodiment of the present invention. 1 and 7 , the voltage selector 170 receives a plurality of voltages V1 to Vk (k is a positive integer), and the common source line driver 380 includes transistors TR1 to TRm (m is a positive integer smaller than k). In this case, the common source line driver 380 may separate and control each of the transistors TR1 to TRm according to the control of the common source line noise control logic circuit 165 .

The voltage selector 170 may select m voltages V1 to Vk from among the received voltages V1 to Vk based on the program information under the control of the common source line noise control logic circuit 165 . Each of the selected m voltages may have the same value or different values. In this case, the program information may include a temperature, an address (ADDR) received from an external device, and a program state. The voltage selector 170 may provide each of the m selected voltages as gate voltages VG1 to VGm of the transistor of the common source line driver 380 .

Transistors TR1 to TRm of the common source line driver 380 may receive m voltages selected by the voltage selector 170 . In response to the received voltages, each of the transistors TR1 to TRm of the common source line driver 380 may be turned on or off according to the control of the common source line noise control logic circuit 165. .

The common source line driver 380 may control the voltage of the common source line CSL according to the control of the common source line noise control logic circuit 165 . As the common source line CSL is controlled by the common source line driver 380, noise of the common source line CSL can be equally adjusted.

8 is a flowchart illustrating an operation of the nonvolatile memory device 100 according to an exemplary embodiment of the present invention.

Referring to FIGS. 5, 6, and 8 , in step S110, the control logic circuit 160 may generate a plurality of voltages. The control logic circuit 160 may provide the generated voltages to the voltage selector 170 .

In step S120, the voltage selector 170 may select at least one of a plurality of received voltages based on program information. Voltage selector 170 may provide the selected voltage to the common source line driver.

For example, the voltage selector 170 may select one of the received voltages V1 to Vk based on program information under the control of the common source line noise control logic circuit 165 . The voltage selector 170 may provide the selected voltage as the gate voltage VG of the transistor of the common source line driver 280 .

As another example, the voltage selector 170 may select m voltages V1 to Vk from among the received voltages V1 to Vk based on program information under the control of the common source line noise control logic circuit 165 . The voltage selector 170 may provide each of the m selected voltages as gate voltages VG1 to VGm of the transistor of the common source line driver 380 .

In step S130, the common source line driver may control the voltage of the common source line by receiving the selected voltage. For example, a transistor of the common source line driver 280 may receive a voltage selected by the voltage selector 170 . In response to the received voltage, the common source line driver 280 may control the voltage of the common source line CSL according to the control of the common source line noise control logic circuit 165 .

As another example, the transistors TR1 to TRm of the common source line driver 380 may receive m voltages selected by the voltage selector 170 . In response to the received voltages, the common source line driver 380 may control the voltage of the common source line CSL according to the control of the common source line noise control logic circuit 165 .

In the above-described embodiment, as the common source line CSL is controlled by the common source line driver, noise of the common source line CSL can be uniformly adjusted.

9 illustratively shows a storage device 400 including a nonvolatile memory device according to an embodiment of the present invention. Referring to FIG. 9 , the storage device 400 may include a nonvolatile memory device 410 , a memory controller 420 , and an external buffer 430 . The nonvolatile memory device 410 may include a plurality of memory cells. Each of the plurality of memory cells may store two or more bits.

For example, the nonvolatile memory device 410 may include at least one of various nonvolatile memory devices such as a flash memory device, a phase change memory device, a ferroelectric memory device, a magnetic memory device, and a resistive memory device. The nonvolatile memory device 410 may be the nonvolatile memory device 100 described with reference to FIGS. 1 to 8 .

The memory controller 420 may receive various requests for writing data into the nonvolatile memory device 410 or reading data from the nonvolatile memory device 410 from an external host device. The memory controller 420 may store (or buffer) user data communicated with an external host device in the external buffer 430 and store meta data for managing the storage device 400 in the external buffer 430 . there is.

The memory controller 420 may access the nonvolatile memory device 410 through the first signal lines SIGL1 and the second signal lines SIGL2 . For example, the memory controller 420 may transmit commands and addresses to the nonvolatile memory device 410 through the first signal lines SIGL1. The memory controller 420 may exchange data with the nonvolatile memory device 410 through the first signal lines SIGL1.

The memory controller 420 may transmit a first control signal to the nonvolatile memory device 410 through the second signal lines SIGL2 . The memory controller 420 may receive a second control signal from the nonvolatile memory device 410 through the second signal lines SIGL2 .

For example, the memory controller 420 may be configured to control two or more nonvolatile memory devices. The memory controller 420 may include different first signal lines and different second signal lines for each of the two or more nonvolatile memory devices.

As another example, the memory controller 420 may share one first signal line for two or more nonvolatile memory devices. The memory controller 420 may share some of the second signal lines for two or more nonvolatile memory devices, and may separately provide the remaining part.

External buffer 430 may include random access memory. For example, the external buffer 430 may include at least one of a dynamic random access memory, a phase change random access memory, a ferroelectric random access memory, a magnetic random access memory, and a resistive random access memory.

The memory controller 420 includes a bus 421, a host interface 422, an internal buffer 423, a processor 424, a buffer controller 425, a memory manager 426, and an error correction code block 427 (ECC). block) (Error Correction Code block).

The bus 421 may provide communication channels between components within the memory controller 420 . The host interface 422 may receive various requests from an external host device and interpret the received requests. Host interface 422 may store interpreted requests in internal buffer 423 .

The host interface 422 may transmit various responses to an external host device. The host interface 422 may exchange signals with an external host device based on a predetermined communication protocol. Internal buffer 423 may include random access memory. For example, internal buffer 423 may include static random access memory or dynamic random access memory.

The processor 424 may drive an operating system or firmware for driving the memory controller 420 . The processor 424 may read the interpreted requests stored in the internal buffer 423 and generate commands and addresses for controlling the nonvolatile memory device 410 . Processor 424 may pass the generated instructions and addresses to memory manager 426 .

The processor 424 may store various meta data for managing the storage device 400 in the internal buffer 423 . Processor 424 can access external buffer 430 through buffer controller 425 . The processor 424 may control the buffer controller 425 and the memory manager 426 to transmit user data stored in the external buffer 430 to the nonvolatile memory device 410 .

The processor 424 may control the host interface 422 and the buffer controller 425 to transmit data stored in the external buffer 430 to an external host device. The processor 624 may control the buffer controller 425 and the memory manager 426 to store data received from the nonvolatile memory device 410 in the external buffer 430 . The processor 424 may control the host interface 422 and the buffer controller 425 to store data received from an external host device in the external buffer 430 .

The buffer controller 425 may write data to the external buffer 430 or read data from the external buffer 430 under the control of the processor 424 . The memory manager 426 may communicate with the nonvolatile memory device 410 through the first signal lines SIGL1 and the second signal lines SIGL2 under the control of the processor 424 .

The memory manager 426 may access the nonvolatile memory device 410 under the control of the processor 424 . For example, the memory manager 426 may access the nonvolatile memory device 410 through the first signal lines SIGL1 and the second signal lines SIGL2 . The memory manager 426 may communicate with the nonvolatile memory device 410 based on a standard-based protocol or a protocol determined by a manufacturer.

The error correction code block 427 may perform error correction encoding on data transmitted to the nonvolatile memory device 410 using an error correction code (ECC). The error correction code block 427 may perform error correction decoding on data received from the nonvolatile memory device 410 using an error correction code (ECC).

For example, in the storage device 400 , the external buffer 430 and the buffer controller 425 may be omitted. When external buffer 430 and buffer controller 425 are omitted, functions described as performed by external buffer 430 and buffer controller 425 may be performed by internal buffer 423 .

In the above-described embodiments, components according to the technical idea of the present invention have been described using terms such as first, second, and third. However, terms such as first, second, and third are used to distinguish components from each other and do not limit the present invention. For example, terms such as first, second, third, etc. do not imply order or numerical meaning in any form.

What has been described above are specific examples for carrying out the present invention. The present invention will include not only the above-described embodiments, but also embodiments that can be simply or easily changed in design. In addition, the present invention will also include techniques that can be easily modified and practiced in the future using the above-described embodiments.

100: non-volatile memory device
400: storage device

Claims (10)

a memory cell array including a plurality of memory cells;
a plurality of bit lines and word lines coupled to the plurality of memory cells;
a common source line connected to the plurality of memory cells;
a control logic circuit including a common source line noise control logic circuit and generating a plurality of voltages including first and second voltages;
a voltage selector receiving the plurality of voltages and selecting at least one of the plurality of voltages; and
A common source line driver controlling a voltage of a common source line by receiving the selected at least one voltage;
wherein the common source line noise control logic circuit controls the voltage selector to select at least one of the plurality of voltages based on program information. According to claim 1,
Further comprising a temperature sensing circuit for sensing the temperature of the surrounding area and transmitting the sensing result to the control logic circuit,
The nonvolatile memory device of claim 1 , wherein the program information is a temperature of the peripheral area. According to claim 1,
The nonvolatile memory device according to claim 1 , wherein the program information is an address received from an external device. According to claim 1,
The nonvolatile memory device according to claim 1 , wherein the program information is a program state. According to claim 1,
The common source line driver includes a first transistor;
The voltage selector selects the first voltage as a gate voltage of the transistor. According to claim 1,
The common source line driver includes first and second transistors;
wherein the voltage selector selects each of the first and second voltages as gate voltages of the first and second transistors. According to claim 6,
Each of the first and second voltages turns on or turns off the first and second transistors. In the operating method of a nonvolatile memory device,
generating, by a control logic circuit, a plurality of voltages including first and second voltages;
selecting at least one of the plurality of voltages by a voltage selector based on program information; and
and receiving the selected voltage so that the common source line driver controls the voltage of the common source line. According to claim 8,
The program information is a temperature, an address received from an external device, or a program status. non-volatile memory devices; and
A memory controller for controlling the nonvolatile memory device,
The non-volatile memory device:
a memory cell array including a plurality of cells;
a plurality of bit lines and word lines coupled to the plurality of memory cells;
a common source line connected to the plurality of memory cells;
a control logic circuit including a common source line noise control logic circuit and generating a plurality of voltages including first and second voltages;
a voltage selector receiving the plurality of voltages and selecting at least one of the plurality of voltages; and
A common source line driver controlling a common source line voltage by receiving the selected at least one voltage;
wherein the common source line noise control logic circuit controls the voltage selector to select at least one of the plurality of voltages based on program information.

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