KR20230108206A - Computational SSDs accelerating deep learning service on large-scale graphs - Google Patents

Abstract

As a preferred embodiment of the present invention, computational storage supporting acceleration of graph machine learning includes an SSD for storing a graph data set; and an FPGA for downloading a graph machine learning model programmed by a host in the form of a data flow graph to memory. ; Including, the hardware logic fabricated in the FPGA is characterized in that it performs access to the SSD through a PCIe switch.

Description

Computational storage that supports graph machine learning acceleration {Computational SSDs accelerating deep learning service on large-scale graphs}

The present invention relates to a computational storage that supports accelerated graph machine learning.

Unlike existing neural network-based machine learning techniques, graph-based neural network learning models (GNN) can express associations between data, making them suitable for large-scale social network services (SNS) such as Facebook, Google, LinkedIn, and Uber. It is used in a wide range of fields and applications such as navigation, new drug development, etc. When analyzing a user network stored in a graph structure, it is possible to recommend realistic products and items that were not possible with existing neural network-based machine learning, and recommend friends that seem to be inferred by humans.

In the past, in order to perform such GNN machine learning, efforts have been made to accelerate the GNN inference process by using systems used for neural network machine learning, such as DPU (Data Processing Unit) or GPU (Graphics Processing Unit). However, in the GNN pre-processing process, such as loading graph data from storage to memory and sampling, serious bottlenecks and memory shortages have shown limitations in actual system application.

US 11232156 B1

A preferred embodiment of the present invention proposes a computational storage CSSD (Computational SSD) capable of accelerating the entire GNN process by accelerating not only the GNN inference process but also the GNN pre-processing process.

Another preferred embodiment of the present invention proposes a computational storage CSSD capable of programming a graph machine learning model capable of supporting various hardware structures and software required for GNN preprocessing and GNN inference.

As a preferred embodiment of the present invention, the computational storage supporting acceleration of graph machine learning includes an operation unit (FPGA) disposed near a storage (SSD); a graph storage unit that provides an interface for storing or accessing graph data sets in the storage, and outputs the graph data sets and metadata managing them; A graph that converts the graph machine learning model programmed in the form of a data flow graph by the host into a data flow graph in a preset format, downloads it to the memory of the operation unit, and executes it to perform graph machine learning preprocessing and graph machine learning inference. and an accelerator generation unit that downloads the bit file of the host, sets a setting memory value based on the bit file, designs the hardware logic of the calculation unit, and creates the graph machine learning inference accelerator. characterized by

As a preferred embodiment of the present invention, the operation unit is divided into a first area and a second area, and the first area and the second area have coprocessor ports and system bus lanes disposed thereon so that the second area can be programmed. characterized by being able to

As a preferred embodiment of the present invention, the first area is a fixed area and includes hardware logic used when executing the graph storage unit, the graph execution unit, and the accelerator generation unit, and the second area is dynamically As a programmable area, it is characterized in that a user can define an operation executable in hardware through the graph execution unit.

As a preferred embodiment of the present invention, when the graph storage unit stores the graph included in the graph data set, it simultaneously converts the graph into a graph structure that is easy to search for neighbors, so that the graph execution unit stores the graph in the storage. It is characterized in that node sampling or embedding sampling is performed immediately when accessing the stored graph.

As a preferred embodiment of the present invention, when the graph storage unit stores the graph structure included in the graph data set, if the number is greater than or equal to a predetermined number based on the number of node neighbors for each index of each node, type H is used, and if the number is less than or equal to a predetermined number, L type is used. It is characterized by generating a graph bitmap classified by type and stored as metadata, and also generating a mapping table to which a logical page number is assigned to each index of each node.

As a preferred embodiment of the present invention, the graph execution unit directly accesses the graph data set stored in the storage through an interface provided by the graph storage unit when executing the data flow graph in the preset format.

As another preferred embodiment of the present invention, the computational storage supporting graph machine learning acceleration is an SSD for storing a graph data set; and a graph machine learning model programmed by a host in the form of a data flow graph in memory. A download FPGA; hardware logic fabricated in the FPGA performs access to the SSD through a PCIe switch, the FPGA is divided into a first area and a second area, and the first area is fixed to the hardware logic The second area is a dynamically programmable area, and a coprocessor port and a system bus lane are disposed in the first area and the second area, so that a bit file defined by a user in the second area can be programmed. characterized by

As another preferred embodiment of the present invention, a method for supporting acceleration of graph machine learning in computational storage includes the steps of storing a graph data set in a storage (SSD); and a data flow by a host in an operation unit (FPGA). and downloading a graph machine learning model programmed in a graph form to a memory, wherein the hardware logic fabricated in the FPGA accesses the SSD through a PCIe switch, and the FPGA has a first area and a second area The first area is a fixed hardware logic, the second area is a dynamically programmable area, and the first area and the second area are arranged with coprocessor ports and system bus lanes, so that the second area It is characterized in that a user-defined bit file can be programmed in the area.

As a preferred embodiment of the present invention, computational storage supporting acceleration accelerates not only the GNN inference process but also the GNN preprocessing process when performing GNN machine learning by removing the process of moving large-scale graph data by arranging an FPGA near an SSD. It works.

As a preferred embodiment of the present invention, the computational storage that supports acceleration provides a software framework that can easily program various graph machine learning models and neural network acceleration hardware logic that can be freely changed by users, enabling fast GNN inference. It works.

1 shows an example of a computational storage structure supporting accelerated graph machine learning as a preferred embodiment of the present invention.
2 is a diagram showing the internal configuration of a computational storage that supports accelerating graph machine learning as a preferred embodiment of the present invention.
3 to 6 show diagrams for explaining the operation of a graph storage unit as a preferred embodiment of the present invention.
7 shows an example of a graph machine learning model programmed in the form of a dataflow graph as a preferred embodiment of the present invention.
8 to 9 show an example for explaining the operation of a graph execution unit as a preferred embodiment of the present invention.
10 is a diagram for explaining the operation of an accelerator generating unit as a preferred embodiment of the present invention.

Hereinafter, an embodiment will be described in detail with reference to the accompanying drawings.

As a preferred embodiment of the present invention, it relates to a computational storage that supports accelerated graph machine learning.

1 shows an example of a computational storage structure supporting accelerated graph machine learning as a preferred embodiment of the present invention.

As a preferred embodiment of the present invention, the computational storage (Computational SSD, hereinafter CSSD 100) includes an SSD 110 and an FPGA 120. The FPGA 120 is disposed near the SSD 110, and hardware logic fabricated in the FPGA 120 accesses the SSD 110 through the switch 130. One example of switch 130 is a PCIe switch.

As a preferred embodiment of the present invention, the CSSD (100) arranges the FPGA (120) near the SSD (110) to remove the process of moving large-scale graph data, thereby performing the GNN inference process as well as the GNN pre-processing process when performing GNN machine learning. can even be accelerated.

An example of an interface between the host CPU 140 and the CSSD 100 is PCIe. The host CPU may access the NVMe SSD 150 or the FPGA I/O 160 using PCIe base address registers (PCIe BARs) of the CSSD mapped to the system memory map. In this case, since the internal hardware of the CSSD 100, the SSD 110 and the FPGA 120 are separated, the input and output of the NVMe SSD 150 is requested through the PCIe BAR of the SSD 110,

For the input/output request, the FPGA input/output 160 is requested through the PCIe BAR of the FPGA 120. SSD 110 and FPGA 120 are placed in the same PCIe card.

2 is a diagram showing the internal configuration of a computational storage that supports accelerating graph machine learning as a preferred embodiment of the present invention.

As a preferred embodiment of the present invention, the CSSD (200) places a programmable calculation unit near the storage. An example of storage is an SSD, and an example of a programmable computing unit is an FPGA. The CSSD 200 receives a graph data set and a GNN model and outputs a GNN inference result.

To this end, the CSSD 200 includes a graph storage unit 220, a graph execution unit 240, and an accelerator generation unit 260. The CSSD 200 communicates with the host 210 using a remote procedure call (RPC) function. The host 210 may refer to and update a graph data set, execute a graph machine learning operation, create a custom accelerator, and register a custom operation through a remote procedure call. In this case, the graph storage unit 220 of the CSSD 200 references and updates graph data sets, the graph execution unit 240 executes graph machine learning calculations and registers custom calculations, and the accelerator generation unit 260 Handles the creation of custom accelerators.

The functions of remote procedure call (RPC) used in CSSD 200 are shown in Table 1.

Service Type RPC function Service Type RPC function Graph storage unit (220)
(Bulk) UpdateGraph
(EdgeArray, Embeddings) Graph storage unit (220)
(Unit, Get) GetEmbed(VID) GetNeighbors(VID) Graph storage unit (220)
(Unit, Update) Addvertex (VID, Embed) Graph execution unit 240 Run(DFG, batch) DeleteVertex(VID) Plugins (shared_lib) AddEgdt(dstVIC, srcVIC) Accelerator generator (260) Program (bitfile) DeleteEdge(dstVIC, srcVIC) UpdateEmbed(VIC, Embed)

The detailed operation of each remote procedure call is as follows.

· UpdateGraph(EdgeArray, Embeddings): Save multiple edges (EdgeArray) and multiple feature vectors (Embeddings) to the graph storage at once.

· AddVertex(VID, Embed): Stores a new node whose feature vector is Embed and whose node index value is VID.

· DeleteVertex(VID): Deletes the feature vector and neighbor list of the node whose node index value is VID.

· AddEdge(dstVID,srcVID), DeleteEdge(dstVID,srcVID): Add/delete edge with srcVID as the index of the source node and dstVID as the index of the destination node.

· UpdateEmbed(VID,Embed): Updates the feature vector of the node whose node index value is VID to Embed.

· GetEmbed(VID), GetNeighbors(VID): Refers to the feature vector/neighbor list of the node whose node index value is VID.

· Run(DFG,batch): Runs the DFG model for the node index list (batch) that is the target of the graph machine learning operation.

· Plugin (shared_lib): Registers user-customized operations in the form of a shared library.

· Program (bitfile): Program the bitfile in the user area of the FPGA.

The graph storage unit 220 provides an interface for storing or accessing graph data sets in storage. A graph data set includes a graph structure and node embeddings. The graph storage unit 220 may store the graph data set in storage by distinguishing areas into a graph structure, an embedding table, and metadata. The embedding table stores feature vectors of each node. While feature vectors are stored in a contiguous space in the order of node index, adjacency lists are stored in the two methods described below in consideration of graph search and update efficiency.

When storing the graph structure included in the graph data set, the graph storage unit 220 simultaneously converts the graph into an adjacency list, which is a graph structure that is easy to search for neighbors. Node sampling or embedding sampling can be performed immediately when the graph execution unit 240 accesses the graph stored in the storage through this processing process.

3 to 6, when the graph storage unit 220 stores the graph structure included in the graph data set, if the number is greater than or equal to a preset number based on the number of node neighbors for each index of each node, the graph storage unit 220 is an H type if it is less than or equal to the preset number. It is divided into L type and stored in the graph bitmap 310 in the form of metadata.

The graph bitmap 310 is stored in NAND in the CSSD 200 in the form of metadata, but is cached and used in DRAM during calculation processing. In the graph bitmap 310, V0, V1, ..., V7 represent the index of each node. And '1' represents the L type, and '0' represents the H type.

The graph storage unit 220 creates mapping tables 320a and 320b to which logical page numbers are allocated for each node index constituting the graph bitmap 310. In the case of L-type nodes having fewer than a predetermined number of neighbors, a neighbor list of multiple nodes may be stored in a single page. Therefore, the index of the node where the L-type metadata is stored creates a mapping table 320a in a range-based format that stores a neighbor list of multiple nodes in a single page. H-type nodes with many neighbors are stored across multiple pages because they have more neighbors than a single page can store. Accordingly, the index of the node where the H-type metadata is stored generates a mapping table 320b in the form of a linked list.

The graph storage unit 220 performs a binary search on the mapping table 320a when searching for a neighbor list of an L-type node, maps a page in which a neighbor list of a node having a specific arrival node index is stored, and uses the metadata of the page to obtain the desired node. Determines the location where the neighbor list of is stored and reads the neighbor list. The metadata of the corresponding page includes the number of neighbor lists stored in the page and offset information within the page. Offset information within a page is used to manage the start address of each neighbor list when a plurality of neighbor lists are stored in a single page.

When searching for the neighbor list of an H-type node, the graph storage unit 220 can read the neighbor list by accessing the found logical page address while sequentially searching the mapping table in the form of a linked list. This is because the H-type neighbor list uses a single page, unlike the L-type, in which the neighbor lists of several nodes are stored together in a single page.

4 shows a neighbor list reference operation among remote calling procedure APIs provided by the graph storage unit 220 as a preferred embodiment of the present invention. Both the H type and the L type can refer to mapping information of a target node index through binary search. However, unlike the H type that allocates the entire page to a single node, the L type requires a range search because a single page is shared by multiple nodes. Since the mapping table stores the index of the largest node included in the pointed page, it can be seen that the neighbor list of V5 is stored like that of V6 in the embodiment of FIG. 4 . Through the metadata of the logical page 7, it can be seen that the neighbor list of two nodes is stored in the corresponding page, and the two stored nodes are V5 and V6. By referring to the offset where the neighbor list of V5 is stored, the neighbor list of V5 can finally be read.

5 shows an operation of adding a node among remote calling procedure APIs provided by the graph storage unit 220 as a preferred embodiment of the present invention. In the case of a newly added node, since the number of neighboring nodes is one, it is classified as an L type. The graph storage unit 220 checks the metadata of the page indicated by the last entry of the L-type mapping table to determine whether there is free space, and if it is determined that there is no free space, a new page is allocated and the L-type mapping table is extended. do. Specifically, since logical page #8 has no free space, the neighbor list of the newly added V21 node is stored in logical page #9. Subsequently, when a new neighbor (V1) is added to node V21, V1 is added to the V21 neighbor list stored in logical page 9, and metadata of the corresponding page is updated.

6, as a preferred embodiment of the present invention, shows in detail a node deletion operation among the remote call procedure APIs provided by the graph storage unit 220.

The graph storage unit 220 performs a node deletion operation by deleting the neighbor list of the target node and then deleting all edges connected to the target node. The embodiment of FIG. 6 illustrates a process of deleting an L-type V5 node. The graph storage unit 220 reads the neighbor list of V5 stored in logical page number 7. Then, all edges to which V5 is connected are deleted. At this time, the process of searching for V5 in the neighbor list of all neighboring nodes of V5 and deleting is repeated. After deleting all edges associated with V5, delete V5's neighbor list from logical page 7 and update the associated metadata. Metadata is updated in the form of (the number of neighbor lists stored in a page, offset information within a page). The process of deleting the H-type node is similar to this, but the process of deleting the neighbor list of the target node disconnects the linked list and updates the mapping information, unlike the L-type node.

The graph execution unit 240 receives a GNN program from the host and outputs a GNN inference result. Further explanation will be made with reference to FIGS. 7 to 9 . An example of the GNN program is a graph machine learning model programmed by the host 210 in the form of a dataflow graph (hereinafter referred to as DFG). 7 shows an example of DFG type programming.

The graph execution unit 240 converts the DFG 810 defined by the user into a DFG 820 in a preset format. For example, the graph execution unit 240 converts the DFG 810 defined by the user into a DFG 820 in a predefined format with operation types, input values, and output values of each DFG node. Then, the DFG converted into a preset format is downloaded to the memory of the FPGA and executed to perform GNN pre-processing and GNN inference.

In a preferred embodiment of the present invention, by programming a graph machine learning model in the form of a DFG, the user can download and execute the DFG as CSSD without cross-compilation and modification of the storage stack.

Referring to FIG. 8, the graph execution unit 240 includes "BatchPre" (811), "SpMMMean" (812), "GEMM" (813), and "ReLU" (814) of the DFG (FIG. 8, 810) defined by the user. ) into a DFG in a preset format and then executed. "BatchPre" (811) is an operation required for GNN pre-processing, and "SpMMMean" (812), "GEMM" (813) and "ReLU" (814) are operations required for GNN inference. In this process, the graph execution unit 240 directly accesses the storage in the CSSD 200 through the graph storage unit 220 to read the graph and the embedding.

As a preferred embodiment of the present invention, the graph execution unit 240 internally stores a mapping table 830 for mapping operation types and hardware codes in a memory such as DRAM, so that DFG programming is possible even if the user does not know the inside of the hardware. support to do Also, when a single operation can be performed by multiple hardware, the hardware to execute the operation is determined based on priority.

Referring to FIG. 9, when a single operation called "GEMM" can be performed by the CPU 910, the vector processor 920, and the systolic array 930, the operation is performed based on a priority set for each device. The hardware to run on is determined. In the memory, “GEMM”<SA> (Systolic array) (930), “GEMM”<VP> (Vector Processor) (920), and “GEMM” CPU> (910) is stored, and among them, the code of the hardware selected based on the priority is executed. At this time, the graph execution unit 240 changes the program counter to the hardware code memory address stored in the mapping table, so that the corresponding device can perform acceleration. Finally, the graph execution unit 240 performs acceleration by jumping the program counter to the hardware code memory address stored in the mapping table.

The accelerator generator 260 downloads the bit file 1012 from the host to the DRAM 1130, sets the value of the setting memory 1120 based on the bit file 1012, and generates a graph machine learning inference accelerator in the FPGA. do. The configuration memory 1120 refers to FPGA memory. A bit file means a hardware program file defined by a user.

In FIG. 10 , FPGAs 1200 and 1300 may be divided into a shell area 1200 and a user area 1300 . In this case, DFX (Dynamic Function eXchange) technology can be used. DFX (Dynamic Function eXchange) technology supports partition boundary storage method and dynamic programming method.

The partition boundary (bondary) storage method defines the boundary (partition pin) of a fixed area and a dynamically programmable area in the form of a design checkpoint file. Users can design hardware that uses the boundaries of the design checkpoint file as input pins or output picks.

In the dynamic programming method, a bit file defined by a user is programmed into an FPGA in a dynamically programmable area through an Internal Configuration Access Port (ICAP).

As a preferred embodiment of the present invention, the shell area 1200 is a fixed area and includes hardware logic used when the graph storage unit, graph execution unit, and accelerator generation unit 1270 are executed. Examples of hardware logic include DRAM controller 1210, DMA engine 1220, PCIe termination 1230, PCIe switch 1240, O3 core 1250, bus 1260, and the like. In the user area 1300, a user can freely arrange a neural network accelerator for graph machine learning. In the shell area 1200 and the user area 1300, a coprocessor port and a system bus lane are arranged so that a bit file defined by a user in the user area 1300 can be programmed. For example, the user area 1300 may be programmed with a bit file in the form of a vector processor 262 and a systolic array 264, as in the embodiment of FIG. 2 .

A user may define an operation executable in hardware in the user area 1300 through an API provided by the graph execution unit 240 .

The devices described above may be implemented as hardware components, software components, and/or a combination of hardware components and software components. For example, devices and components described in the embodiments may include, for example, a processor, a controller, an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA) , a programmable logic unit (PLU), microprocessor, or any other device capable of executing and responding to instructions. A processing device may run an operating system (OS) and one or more software applications running on the operating system. A processing device may also access, store, manipulate, process, and generate data in response to execution of software. For convenience of understanding, there are cases in which one processing device is used, but those skilled in the art will understand that the processing device includes a plurality of processing elements and/or a plurality of types of processing elements. It can be seen that it can include. For example, a processing device may include a plurality of processors or a processor and a controller. Other processing configurations are also possible, such as parallel processors.

Software may include a computer program, code, instructions, or a combination of one or more of the foregoing, which configures a processing device to operate as desired or processes independently or collectively. You can command the device. Software and/or data may be any tangible machine, component, physical device, virtual equipment, computer storage medium or device, intended to be interpreted by or provide instructions or data to a processing device. can be embodied in Software may be distributed on networked computer systems and stored or executed in a distributed manner. Software and data may be stored on one or more computer readable media.

The method according to the embodiment may be implemented in the form of program instructions that can be executed through various computer means and recorded on a computer readable medium. The computer readable medium may include program instructions, data files, data structures, etc. alone or in combination. Program commands recorded on the medium may be specially designed and configured for the embodiment or may be known and usable to those skilled in computer software. Examples of computer-readable recording media include magnetic media such as hard disks, floppy disks and magnetic tapes, optical media such as CD-ROMs and DVDs, and magnetic media such as floptical disks. - includes hardware devices specially configured to store and execute program instructions, such as magneto-optical media, and ROM, RAM, flash memory, and the like. Examples of program instructions include high-level language codes that can be executed by a computer using an interpreter, as well as machine language codes such as those produced by a compiler.

As described above, although the embodiments have been described with limited examples and drawings, those skilled in the art can make various modifications and variations from the above description. For example, the described techniques may be performed in an order different from the method described, and/or components of the described system, structure, device, circuit, etc. may be combined or combined in a different form than the method described, or other components may be used. Or even if it is replaced or substituted by equivalents, appropriate results can be achieved. Therefore, other implementations, other embodiments, and equivalents of the claims are within the scope of the following claims.

Claims (15)

a calculation unit (FPGA) disposed near the storage (SSD);
a graph storage unit that provides an interface for storing or accessing graph data sets in the storage, and outputs the graph data sets and metadata managing them;
A graph that converts the graph machine learning model programmed in the form of a data flow graph by the host into a data flow graph in a preset format, downloads it to the memory of the operation unit, and executes it to perform graph machine learning preprocessing and graph machine learning inference. executive unit; and
After downloading the bit file of the host, setting a setting memory value based on the bit file, designing the hardware logic of the calculation unit, and generating the graph machine learning inference accelerator. Computational storage that supports accelerated graph machine learning. The method of claim 1, wherein the calculation unit
It is divided into a first area and a second area, and the first area and the second area are arranged with coprocessor ports and system bus lanes to support graph machine learning acceleration, characterized in that the second area can be programmed. computed storage. According to claim 2,
The first area is a fixed area and includes hardware logic used when executing the graph storage unit, the graph execution unit, and the accelerator generation unit. According to claim 2,
The second area is a dynamically programmable area, and a computational storage supporting acceleration of graph machine learning, characterized in that a user can define an operation executable in hardware through the graph execution unit. According to claim 1,
The hardware logic fabricated in the calculation unit is computational storage that supports graph machine learning acceleration, characterized in that for accessing the storage through a PCIe switch. The method of claim 1, wherein the graph storage unit
When the graph included in the graph data set is stored, a process of converting the graph into a graph structure that is easy to search for neighbors is simultaneously performed, and when the graph execution unit accesses the graph stored in the storage, node sampling or embedding sampling is immediately performed. Computational storage that supports acceleration of graph machine learning, characterized in that it is performed. The method of claim 1, wherein the graph storage unit
When storing the graph structure included in the graph data set, based on the number of node neighbors for each index of each node, the graph bitmap stored as metadata is divided into an H type if the number is greater than or equal to a preset number and an L type if the number is less than the preset number. Computational storage that supports acceleration of graph machine learning, characterized in that it generates a mapping table to which a logical page number is allocated for each index of each node. According to claim 7,
The H-type is a case where the number of neighbors of a node is greater than the number of neighbors that can be stored in a single page, and the index of the node where the H-type metadata is stored generates a mapping table in the form of a linked list. Supported computed storage. According to claim 7,
The L-type is a case where the number of neighbors of a node is smaller than the number of neighbors that can be stored in a single page, and the index of the node where the L-type metadata is stored is a mapping table in a range-based format storing a list of neighbors of multiple nodes in a single page. Computational storage that supports accelerating graph machine learning, characterized in that it generates. The method of claim 1, wherein the graph execution unit
Computational storage that supports accelerated graph machine learning, characterized in that when the data flow graph in the preset format is executed, the graph data set stored in the storage is directly accessed through an interface provided by the graph storage unit. According to claim 1,
Computational storage supporting graph machine learning acceleration, characterized in that the storage and the calculation unit are disposed in the same PCIe card. SSD for storing the graph data set; and
An FPGA that downloads a graph machine learning model programmed by a host in the form of a data flow graph into memory;
Hardware logic fabricated in the FPGA accesses the SSD through a PCIe switch, the FPGA is divided into a first area and a second area,
The first area has fixed hardware logic, and the second area is a dynamically programmable area, and coprocessor ports and system bus lanes are disposed in the first area and the second area. Computational storage that supports acceleration of graph machine learning, characterized in that the bit file defined by can be programmed. Storing a graph data set in a storage (SSD); And
Including; downloading a graph machine learning model programmed by a host in the form of a data flow graph in a memory in an operation unit (FPGA);
Hardware logic fabricated in the FPGA accesses the SSD through a PCIe switch, the FPGA is divided into a first area and a second area,
The first area has fixed hardware logic, and the second area is a dynamically programmable area, and coprocessor ports and system bus lanes are disposed in the first area and the second area. A method for supporting graph machine learning acceleration in computational storage, characterized in that the bit file defined by can be programmed. 14. The method of claim 13, wherein the FPGA is disposed near the storage (SSD). According to claim 1,
The first area is a fixed area and includes hardware logic used when executing a graph storage unit, a graph execution unit, and an accelerator generation unit.

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