KR20230105288A - Voltage generator and semiconductor device including the same - Google Patents

Abstract

A voltage generator according to an embodiment of the present invention includes a first charge pump having a plurality of first pumping capacitors, and a plurality of second pumping capacitors having a capacitance different from that of each of the plurality of first pumping capacitors. A charge pump circuit that includes a second charge pump and supplies a power supply voltage to a power mesh, a controller that outputs a control signal based on a target level of the power supply voltage, and outputs a clock signal to the charge pump circuit. and an oscillator that outputs the clock signal to one of the first charge pump and the second charge pump based on the control signal.

Description

Voltage generator and semiconductor device including the same

The present invention relates to a voltage generator and a semiconductor device including the same.

The semiconductor device includes a voltage generator that generates a power supply voltage required for operation using an external power supply voltage provided by an external host. For example, the voltage generator may output a power voltage higher than the external power voltage. The voltage generator may include a charge pump to generate a power supply voltage higher than the external power supply voltage. The operation of the charge pump may be controlled according to the target level of the power supply voltage. If the target level is high, consumption of the target circuit receiving the power voltage may increase instead of improving the ripple characteristic of the power supply voltage. On the other hand, when the target level decreases, the ripple characteristic of the power supply voltage may deteriorate. Therefore, it is necessary for the voltage generator to operate adaptively according to the variation of the target level.

One of the problems to be achieved by the technical idea of the present invention includes a plurality of charge pumps having different pumping capacitors, and actually among the plurality of charge pumps with reference to a target level of a power supply voltage and PVT information of a semiconductor device. A voltage generator capable of minimizing deterioration of ripple characteristics according to a target level and stably maintaining a charge supply amount of a charge pump by adaptively selecting a select charge pump that outputs a power supply voltage, and a semiconductor device including the same is in

A voltage generator according to an embodiment of the present invention includes a first charge pump having a plurality of first pumping capacitors, and a plurality of second pumping capacitors having a capacitance different from that of each of the plurality of first pumping capacitors. A charge pump circuit that includes a second charge pump and supplies a power supply voltage to a power mesh, a controller that outputs a control signal based on a target level of the power supply voltage, and outputs a clock signal to the charge pump circuit. and an oscillator that outputs the clock signal to one of the first charge pump and the second charge pump based on the control signal.

A voltage generator according to an embodiment of the present invention determines a target level of a power supply voltage supplied to a plurality of charge pumps including pumping capacitors of different capacities and a predetermined circuit area through a power mesh, and the target level Based on a comparison result of a controller outputting a control signal for determining one selected charge pump from among the plurality of charge pumps based on a reference voltage determined according to the control signal and a voltage detected by the power mesh, and an oscillator determining whether to output a clock signal input to the selected charge pump.

A semiconductor device according to an embodiment of the present invention includes a plurality of unit memory areas each including a power mesh supplying a power voltage, and a logic circuit controlling the plurality of unit memory areas, the logic circuit comprising: and a voltage generator configured to set the power voltage included in each of the plurality of unit memory areas to a predetermined target level, wherein the voltage generator increases and maintains the level of the power mesh at the target level. and a controller selecting one of the plurality of charge pumps as a selection charge pump based on the target level.

According to an embodiment of the present invention, one of a plurality of charge pumps included in the voltage generator is adaptively selected according to the target level of the power supply voltage to be supplied to the power mesh, the PVT information of the semiconductor device, and the like to set the power voltage. can be printed out. A charge pump including pumping capacitors of different capacities may be selected from among a plurality of charge pumps according to the target level, PVT information, etc., thereby minimizing deterioration of the ripple characteristic of the power supply voltage according to the power voltage and PVT information, It is possible to stably maintain the charge supply of the charge pump.

Various advantageous advantages and effects of the present invention are not limited to the above description, and will be more easily understood in the process of describing specific embodiments of the present invention.

1 is a schematic diagram of a semiconductor device according to an exemplary embodiment of the present invention.
2 is a schematic block diagram of a voltage generator according to an embodiment of the present invention.
3A and 3B are circuit diagrams schematically illustrating charge pumps included in a voltage generator according to an embodiment of the present invention.
4 is a circuit diagram simply illustrating a comparison circuit included in a voltage generator according to an embodiment of the present invention.
5 is a diagram simply showing a voltage generator according to an embodiment of the present invention.
6 and 7 are diagrams provided to explain the operation of the voltage generator according to an embodiment of the present invention.
8A and 8B are diagrams provided to explain the operation of a voltage generator according to an embodiment of the present invention.
9 is a diagram provided to explain the operation of a voltage generator according to an embodiment of the present invention.
10 to 12 are diagrams provided to explain the operation of the voltage generator according to an embodiment of the present invention.
13 to 16 are diagrams provided to explain the operation of the voltage generator according to an embodiment of the present invention.
17 is a schematic diagram of a semiconductor device according to an exemplary embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

1 is a schematic diagram of a semiconductor device according to an exemplary embodiment of the present invention.

Referring to FIG. 1 , a semiconductor device 10 according to an exemplary embodiment may include a voltage generator 20 and a power mesh 30 . The power mesh 30 may include metal wires disposed on a circuit block that performs a predetermined function in the semiconductor device 10 and may have a predetermined capacity. The capacitance of the power mesh 30 may be expressed as a power capacitor CPWR as shown in FIG. 1 .

The voltage generator 20 may supply the power mesh 30 with a power voltage required for operation of circuit blocks included in the semiconductor device by using the external power voltage VEXT. For example, the voltage of the power mesh 30 may be increased to a target level by the output current IOUT output by the voltage generator 20 . In one embodiment, charge may be supplied to the power mesh 30 by the output current IOUT, and when the voltage of the power mesh 30 increases to a target level by the supplied charge, the voltage generator 20 The output of the output current (IOUT) can be stopped.

The voltage generator 20 may include a charge pump that provides an output current IOUT so that a power voltage having a higher level than the external power voltage VEXT may be applied to the power mesh 30 . For example, the charge pump includes switches that are turned on/off by a predetermined clock signal and at least one pumping capacitor, and a charge supply amount of the charge pump may vary according to a frequency of the clock signal.

In order for the circuit blocks included in the semiconductor device to stably operate, the power mesh 30 must be able to stably maintain the power supply voltage at a target level, and in particular, a ripple component included in the power supply voltage may need to be minimized. . The magnitude of the ripple component included in the power supply voltage may vary depending on the capacity of the pumping capacitor included in the charge pump and the target level of the power supply voltage to be supplied to the power mesh 30 . For example, as the target level decreases, the ripple component may increase. When the target level increases, the ripple component decreases, but instead, the charge supply amount of the charge pump may decrease.

A charge supply amount of the charge pump may be affected by a capacitance of a pumping capacitor included in the charge pump. For example, if the capacitance of the pumping capacitor is large, the charge supply amount of the charge pump may increase, and if the capacitance of the pumping capacitor is small, the charge supply amount of the charge pump may decrease.

In one embodiment of the present invention, in order to use the above characteristics, the voltage generator 20 may include two or more charge pumps including pumping capacitors of different capacities. For example, the voltage generator 20 may operate one selected charge pump among two or more charge pumps according to a target level of the power supply voltage, and control the remaining charge pumps not to operate.

For example, when the target level is relatively low, a charge pump including a small capacitance pumping capacitor may be activated, and when the target level is relatively high, a charge pump including a large capacitance pumping capacitor may be activated. Therefore, under the condition of outputting a large target level with little influence of the ripple component, a supply voltage of the target level can be stably provided to the power mesh 30 by sufficiently securing the charge supply amount of the charge pump. In addition, in a condition in which a small target level having a relatively large influence of the ripple component must be output, the ripple component can be minimized by generating a power supply voltage with a charge pump having a small capacitance pumping capacitor.

2 is a schematic block diagram of a voltage generator according to an embodiment of the present invention.

Referring to FIG. 2 , a voltage generator 100 according to an embodiment of the present invention includes a charge pump circuit 110 including a plurality of charge pumps 111 to 113, a controller 120, and an oscillator 130. and a comparator circuit 140 and the like. The output current IOUT output by the charge pump circuit 110 in the voltage generator 100 is supplied to the power mesh 200 and may be used as a voltage necessary for the operation of a circuit block connected to the power mesh 200.

Each of the plurality of charge pumps 111 to 113 included in the charge pump circuit 110 may include at least one switch element and at least one pumping capacitor. In one embodiment of the present invention, capacities of pumping capacitors included in each of the plurality of charge pumps 111 to 113 may be different from each other. For example, the capacitance of the first pumping capacitor included in the first charge pump 111 may be different from the capacitance of the second pumping capacitor included in the second charge pump 112 .

In the embodiment shown in FIG. 2 , the charge pump circuit 110 is illustrated as including N charge pumps 111 to 113 (N is a natural number greater than or equal to 3), but the charge pumps 111 to 113 The number of may be variously modified according to embodiments. However, in the voltage generator 100 according to an embodiment of the present invention, the charge pump circuit 110 may include at least two or more charge pumps.

The controller 120 may control the operation of the oscillator 130 and the comparison circuit 140 . For example, the controller 120 may determine a plurality of values based on at least one of process, voltage, temperature (PVTI) information (PVTI) of the semiconductor device and a target level (TG) of a power supply voltage to be supplied to the power mesh 200. One selected charge pump may be determined among the charge pumps 111 to 113 . The controller 120 may deactivate charge pumps other than the selected charge pump.

The oscillator 130 may output a clock signal CLK. The oscillator 130 may operate in response to control from the controller 120 . In one embodiment, the oscillator 130 outputs the clock signal CLK to only a selected charge pump among the plurality of charge pumps 111 to 113 in response to the control signal CTR transmitted by the controller 120, The clock signal CLK may not be output to the remaining charge pumps. Therefore, the selected charge pump determined by the controller 120 operates to supply the output current IOUT to the power mesh 200, and the power supply voltage of the power mesh 200 is set to the target due to the charge supplied by the output current IOUT. level (TG).

Alternatively, the oscillator 130 outputs the clock signal CLK to the plurality of charge pumps 111 to 113, and the controller 120 clocks only one selected charge pump among the plurality of charge pumps 111 to 113. It may be controlled so that the signal CLK is input. In this case, a selection circuit may be additionally connected between the output terminal of the oscillator 130 and the input terminal of the charge pump circuit 110, and for example, the selection circuit may be implemented with a plurality of switch elements or a demultiplexer.

The controller 120 may also provide the control signal CTR to the comparison circuit 140 . For example, the comparison circuit 140 includes a comparator that compares a reference voltage with a feedback voltage, and an output of the comparator may be input to the oscillator 130 as an enable signal EN. For example, whether the oscillator 130 operates may be determined according to the enable signal EN. When the oscillator 130 is activated and operated by the enable signal EN, the charge pump circuit 110 outputs an output current IOUT, and conversely, the oscillator 130 is operated by the enable signal EN. If stopped, the charge pump circuit 110 may also stop outputting the output current IOUT.

Among the voltages input to the comparator in the comparison circuit 140, the level of the feedback voltage may be determined by the sensing voltage VDET detected by the power mesh 200. Meanwhile, the level of the reference voltage may be determined according to the control signal CTR output from the controller 120 to the comparison circuit 140 . Accordingly, the controller 120 may determine whether the charge pump circuit 110 continuously supplies the output current IOUT or stops supplying the output current IOUT using the control signal CTR.

For example, when it is determined that the level of the feedback voltage is sufficient, that is, when it is determined that the power supply voltage of the power mesh 200 has a sufficient level compared to the target level (TG), the controller 120 sets the feedback voltage as the reference voltage. A control signal CTR adjusted to be smaller than the voltage may be output. In this case, the oscillator 130 is inactivated by the enable signal EN output from the comparator, so that the output of the clock signal CLK is stopped, and the output of the output current IOUT is also stopped.

On the other hand, if it is determined that the power supply voltage of the power mesh 200 is smaller than the target level (TG), the controller 120 may output a control signal (CTR) for adjusting the reference voltage to be greater than the feedback voltage. Therefore, the oscillator 130 is activated by the enable signal EN, and the clock signal CLK is input to the charge pump selected by the control signal CTR to generate an output current IOUT in the power mesh 200. can be supplied. The power supply voltage of the power mesh 200 may increase to the target level TG by the charge provided by the output current IOUT.

3A and 3B are circuit diagrams schematically illustrating charge pumps included in a voltage generator according to an embodiment of the present invention.

Referring to FIG. 3A , the charge pump 210 included in the voltage generator according to an embodiment of the present invention includes a plurality of diodes DI, a plurality of pumping capacitors CP, and an output capacitor COUT. can include A plurality of diodes DI are connected in series, and a plurality of pumping capacitors CP may be connected to a node between the plurality of diodes DI. The first diode receives a power supply voltage VCC having a predetermined level, and the last diode can output an output current IOUT to an output node.

Each of the plurality of pumping capacitors CP may be charged or discharged by the clock signal CLK or the complementary clock signal CLKB which is phase-converted to have the opposite phase to the clock signal CLK by the inverter INV. For example, in the embodiment shown in FIG. 3A , odd-numbered pumping capacitors CP are charged or discharged by the clock signal CLK, and even-numbered pumping capacitors CP are charged by the complementary clock signal CLKB. can be charged or discharged by

As described above, the voltage generator may include a plurality of charge pumps. In one embodiment of the present invention, the pumping capacitors CP included in the plurality of charge pumps may have different capacitances.

Next, referring to FIG. 3B , the charge pump 220 included in the voltage generator according to an embodiment of the present invention includes a plurality of switch elements SW1 to SW4, at least one pumping capacitor CP, and an output capacitor. (COUT), etc. Among the plurality of switch elements (SW1-SW4), the first switch element (SW1) receives the power supply voltage (VCC), and the second switch element (SW2) and the third switch element (SW3) are supplied with a ground voltage or the like. nodes can be connected. The fourth switch element SW4 may be connected between the output node and the pumping capacitor CP.

The first switch element SW1 and the third switch element SW3 are turned on/off by the clock signal CLK, and the second switch element SW2 and the fourth switch element SW4 generate the complementary clock signal CLKB. It can be turned on/off by When the second switch element SW2 and the fourth switch element SW4 are turned on, charges may be charged in the pumping capacitor CP by the power supply voltage VCC. When the first switch element SW1 and the third switch element SW3 are turned on, the charge charged in the pumping capacitor CP is shared with the output capacitor COUT, and the output current IOUT is output through the output node. It can be.

4 is a circuit diagram simply illustrating a comparison circuit included in a voltage generator according to an embodiment of the present invention.

Referring to FIG. 4 , a comparator circuit 230 according to an embodiment of the present invention may include a first voltage divider circuit 231, a second voltage divider circuit 232, and a comparator 232. . The first voltage divider circuit 231 includes a plurality of unit resistors 231R connected between a first power node supplying the first power voltage VDD and a second power node supplying the second power voltage VSS. ) and at least one resistance switch RSW1 and RSW2. The second voltage divider circuit 232 may include a plurality of unit resistors 232R connected between a node supplying the sensing voltage VDET and the second power node. The sensing voltage VDET may be a voltage detected by a power mesh connected to an output terminal of the voltage generator.

In the embodiment shown in FIG. 4 , the first voltage divider circuit 231 may include a first resistance switch RSW1 and a second resistance switch RSW2. The first resistance switch RSW1 is connected in parallel with the first unit resistance RU1 of the plurality of unit resistors 231R, and the second resistance switch RSW2 is the second unit of the plurality of unit resistors 231R. It may be connected in parallel with the resistor RU2.

Referring to FIG. 4 , the non-inverting input terminal of the comparator 233 is connected to the first intermediate node MN1 of the first voltage divider circuit 231, and the inverting input terminal is connected to the second intermediate node of the second voltage divider circuit 232. It can be connected to node MN2. The comparator 233 may compare the voltage of the first intermediate node MN1 and the voltage of the second intermediate node MN2 to determine the level of the enable signal EN. For example, the voltage of the first intermediate node MN1 may be defined as a reference voltage, and the voltage of the second intermediate node MN2 may be defined as a feedback voltage.

The enable signal EN may be a signal for determining whether an oscillator included in the voltage generator, together with the comparison circuit 230, operates. In one embodiment, the oscillator is activated and operates when the enable signal EN is at a first level, and the oscillator is deactivated and stops operating when the enable signal EN is at a second level different from the first level.

In an embodiment, when one of the first resistance switch RSW1 and the second resistance switch RSW2 is turned on, the other one may be turned off. For example, when the first resistance switch RSW1 is turned on, the voltage of the first intermediate node MN1 increases, and conversely, when the second resistance switch RSW2 is turned on, the voltage of the first intermediate node MN1 increases. may decrease. Turning on/off of the first resistance switch RSW1 and the second resistance switch RSW2 may be determined by a control signal output from a controller included in the voltage generator together with the comparison circuit 230 .

For example, when the power supply voltage of the power mesh is lower than the target level, the controller may increase the voltage of the first intermediate node MN1 by turning on the first resistance switch RSW1. Accordingly, the enable signal EN may increase to a high level, and the oscillator may be activated to output a clock signal to the charge pump, so that the charge pump may supply charge to the power mesh. On the other hand, when the power supply voltage of the power mesh is greater than the target level, the controller may turn on the second resistance switch RSW2 to reduce the voltage of the first intermediate node MN1. In this case, the enable signal EN decreases to a low level, and the oscillator is deactivated, so that the operation of the charge pump may be stopped.

5 is a diagram simply showing a voltage generator according to an embodiment of the present invention.

Referring to FIG. 5 , a voltage generator 300 according to an embodiment of the present invention may include a charge pump circuit 310, a controller 320, an oscillator 330, a comparator circuit 340, and the like. . The charge pump circuit 310 includes a plurality of charge pumps 311-313, and at least one of the plurality of charge pumps 311-313 is activated as a selected charge pump to supply a power supply voltage to the power mesh 400. can supply

The controller 320 outputs a control signal CTR, and operations of the oscillator 330 and the comparison circuit 340 may be controlled by the control signal CTR. For example, the oscillator 330 outputs a clock signal CLK to a charge pump selected from among the plurality of charge pumps 311 to 313, and the charge supply amount of the selected charge pump may be determined according to the frequency of the clock signal CLK. there is. For example, when the frequency of the clock signal CLK increases, the charge supply amount of the selective charge pump may increase.

The comparison circuit 340 may include a first voltage divider circuit 341 , a second voltage divider circuit 342 , and a comparator 343 . The comparator 343 includes a first input terminal and a second input terminal, the first input terminal may be connected to the first voltage divider circuit 341, and the second input terminal may be connected to the second voltage divider circuit 342. The first voltage divider circuit 341 includes a plurality of unit resistors 341R and resistor switches RSW1 and RSW2, and the second voltage divider circuit 342 includes a plurality of unit resistors (without a separate resistor switch). 342R).

The comparator 343 converts the reference voltage, which is the voltage of the first intermediate node MN1 of the first voltage divider circuit 341, and the feedback voltage, which is the voltage of the second intermediate node MN2 of the second voltage divider circuit 342. By comparing each other, an enable signal EN may be output. In the embodiment shown in FIG. 5, when the voltage of the first intermediate node MN1 is greater than the voltage of the second intermediate node MN2, the enable signal EN is set to the first level, and the first intermediate node ( When the voltage of MN1 is lower than the voltage of the second intermediate node MN2, the enable signal EN may be set to a second level lower than the first level.

The enable signal EN may determine whether the oscillator 330 operates. For example, when the enable signal EN is at the first level, the oscillator 330 outputs the clock signal CLK to the selected charge pump, and when the enable signal EN is at the second level, the oscillator 330 outputs the clock signal to the selected charge pump. The output of (CLK) can be stopped.

The voltage of the first intermediate node MN1 may be determined by the control signal CTR output from the controller 320 . For example, the first resistance switch RSW1 is turned on/off by the complementary signal of the control signal CTR output from the inverter INV, and the second resistance switch RSW2 is turned on/off by the control signal CTR. can be turned off As described above with reference to FIG. 4 , when the first resistance switch RSW1 is turned on, the voltage of the first intermediate node MN1 increases, and when the second resistance switch RSW2 is turned on, the first intermediate node MN1 increases. The voltage of node MN1 may decrease. Meanwhile, the voltage of the second intermediate node MN2 is not affected by the control signal CTR and may be determined by the detected voltage VDET detected from the power mesh 400 .

The controller 320 may determine on/off of each of the first resistance switch RSW1 and the second resistance switch RSW2 in consideration of the target level of the power supply voltage to be set in the power mesh 400 . If the power supply voltage of the power mesh 400 is unintentionally decreased, the voltage of the second intermediate node MN2 may become smaller than the voltage of the first intermediate node MN1. In this case, the enable signal EN is set to the first level, the oscillator 330 outputs the clock signal CLK, and the selected charge pump outputs the output current IOUT to the power mesh 400, thereby generating power. Electric charge may be supplied to the mesh 400 .

Meanwhile, when the power supply voltage of the power mesh 400 is maintained at a target level or higher, the voltage of the second intermediate node MN2 may be higher than or equal to the voltage of the first intermediate node MN1. In this case, when the enable signal EN is set to the second level and the oscillator 330 stops outputting the clock signal CLK, the operation of the selected charge pump can be stopped.

Meanwhile, the plurality of charge pumps 311 to 313 included in the charge pump circuit 310 may include pumping capacitors having different capacities. For example, the first pumping capacitor included in the first charge pump 311, the second pumping capacitor included in the second charge pump 312, and the Nth pumping capacitor included in the Nth charge pump 313 are each other. may have different capacities.

The size of a ripple component included in the power supply voltage supplied to the power mesh 400 may vary according to the capacity of the pumping capacitor. For example, as the capacitance of the pumping capacitor decreases, the size of a ripple component included in the power supply voltage may also decrease. However, when a charge pump having a small capacitance pumping capacitor supplies the output current IOUT to the power mesh 400, the charge supply amount determined by the output current IOUT may decrease.

In one embodiment of the present invention, reference is made to the target level (TG) of the power supply voltage to be supplied to the power mesh 400 and the PVT information (PI, VI, TI) of the semiconductor device including the voltage generator 300. Thus, the controller 320 can select an optimal charge pump that can reduce the ripple component of the power supply voltage and stably secure the charge supply amount. Thus, the power supply voltage of the power mesh 400 can be stably maintained.

For example, the size of the ripple component included in the power supply voltage decreases as the target level of the power supply voltage increases, and may decrease as the capacitance of a pumping capacitor included in the charge pump supplying the output current IOUT decreases. In one embodiment of the present invention, the controller 320 may select a charge pump including a large capacity pumping capacitor from the charge pump circuit 310 when the target level of the power supply voltage to be set in the power mesh 400 is high. there is. In addition, when the target level of the power supply voltage to be set in the power mesh 400 is low, the controller 320 may select a charge pump including a small capacitance pumping capacitor from the charge pump circuit 310 . Accordingly, an increase in the ripple component due to the target level of the power supply voltage may be minimized, and the power supply voltage of the power mesh 400 may be stably maintained at the target level.

The PVT information (PI, VI, TI) includes process information (PI) indicating process deviation, voltage information (VI) corresponding to the level of an external power supply voltage supplied from an external host to the semiconductor device including the voltage generator 300, and the like; and temperature information TI indicating a temperature detected by a temperature sensor included in the semiconductor device along with the voltage generator 300 . The controller 320 actually outputs current ( IOUT) can be determined by the optional charge pump supplying it.

Also, the controller 320 may control the operation of the selected charge pump by referring to at least one of process information PI, voltage information VI, temperature information TI, and target level TG. For example, when the level of the external power supply voltage included in the voltage information VI and/or the target level TG increases, the controller 320 controls the oscillator 330 to increase the frequency of the clock signal CLK. It is possible to output a control signal (CTR) to Also, when the temperature included in the temperature information TI increases, the controller 320 may output a control signal CTR that controls the oscillator 330 to decrease the frequency of the clock signal CLK. However, these are only examples, and a method for the controller 320 to control the oscillator 330 may be variously modified according to process information PI, voltage information VI, temperature information TI, and the like.

6 and 7 are diagrams provided to explain the operation of the voltage generator according to an embodiment of the present invention.

In one embodiment of the present invention described with reference to FIGS. 6 and 7 , the voltage generator 300 may have a structure as previously described with reference to FIG. 5 . 6 and 7 , the voltage generator 300 includes a charge pump circuit 310 including a plurality of charge pumps 311 to 313, a controller 320, an oscillator 330, and a comparison circuit 340. ) and the like.

The oscillator 330 may determine a selected charge pump that actually operates among the plurality of charge pumps 311 to 313 by referring to the control signal CTR output from the controller 320 . For example, the oscillator 330 may output the clock signal CLK only to the selected charge pump with reference to the control signal CTR, and may not output the clock signal CLK to the other charge pumps other than the selected charge pump. there is.

Alternatively, the controller 320 may directly select the selected charge pump. In this case, the control signal CTR may be input to the charge pump circuit 310 . For example, the charge pump circuit 310 is a switch circuit that transfers the clock signal CLK output from the oscillator 330 to a charge pump selected from among the plurality of charge pumps 311 to 313 according to the control signal CTR. can include For example, the switch circuit may include a demultiplexer.

For example, the capacitance of each of the plurality of first pumping capacitors included in the first charge pump 311 may be smaller than the capacitance of each of the plurality of second pumping capacitors included in the second charge pump 312 . For example, the capacitance of each of the second pumping capacitors may be twice or more than the capacitance of each of the first pumping capacitors.

The controller 320 determines the first charge pump as the selected charge pump when the target level of the power supply voltage to be supplied to the power mesh 400 is relatively low, and determines the second charge pump when the target level of the power supply voltage is relatively high. can be determined as an optional charge pump. For example, the controller 320 compares the target level of the power supply voltage with a predetermined reference level, selects a first charge pump when the target level is less than the reference level, and selects a second charge pump when the target level is greater than the reference level. You can choose.

As described above, as the target level increases, the ripple component included in the power supply voltage decreases, and as the target level decreases, the ripple component included in the power supply voltage increases. In addition, as the capacitance of the pumping capacitor included in the selected charge pump increases, the ripple component included in the power supply voltage increases, and as the capacitance of the pumping capacitor decreases, the ripple component included in the power supply voltage decreases.

In one embodiment of the present invention, the controller 320 may select a first charge pump including pumping capacitors of small capacitance when the target level is low. Accordingly, an increase in the ripple component due to the small target level may be offset by the first charge pump including pumping capacitors having small capacitance. On the other hand, if the target level is high, the controller 320 may select the second charge pump including pumping capacitors with large capacities. Accordingly, the power supply voltage at a high target level may be effectively maintained by the second charge pump including large-capacitance pumping capacitors.

8A and 8B are diagrams provided to explain the operation of a voltage generator according to an embodiment of the present invention.

In an embodiment of the present invention described with reference to FIGS. 8A and 8B , the voltage generator 300 may have a structure as previously described with reference to FIG. 5 . 8A and 8B , the voltage generator 300 includes a charge pump circuit 310 including a plurality of charge pumps 311 to 313, a controller 320, an oscillator 330, and a comparison circuit 340. ) and the like.

In an embodiment described with reference to FIGS. 8A and 8B , the selected charge pump may be the first charge pump 311 . However, in the exemplary embodiment illustrated in FIGS. 8A and 8B , whether or not the oscillator 330 outputs the clock signal CLK to the first charge pump 311 may be changed by the comparison circuit 340 .

First, referring to FIG. 8A , the first resistance switch RSW1 included in the first resistance divider circuit 341 is turned off by the control signal CTR output from the controller 320, and the second resistance switch (RSW2) can be turned on. Accordingly, the reference voltage that is the voltage of the first intermediate node MN1 may be set relatively high.

Next, referring to FIG. 8B , the first resistance switch RSW1 included in the first resistance divider circuit 341 is turned on by the control signal CTR output from the controller 320, and the second resistance Switch RSW2 may be turned off. Accordingly, the reference voltage that is the voltage of the first intermediate node MN1 may be set relatively low.

The oscillator 330 may be activated or deactivated by the enable signal EN. For example, when the enable signal EN is at the first level, the oscillator 330 outputs the clock signal CLK to the first charge pump 311 that is the selected charge pump, and the enable signal EN is at the first level. If the second level is smaller than the second level, the oscillator 330 may not output the clock signal CLK to the first charge pump 311 . In an embodiment described with reference to FIGS. 8A and 8B , the oscillator 330 determines that the feedback voltage of the second intermediate node MN2 determined by the detected voltage VDET detected from the power mesh 400 is the reference voltage. The clock signal CLK may be output to the first charge pump 311 until .

Therefore, the time at which the oscillator 330 outputs the clock signal CLK in the embodiment shown in FIG. 8A is the time at which the oscillator 330 outputs the clock signal CLK in the embodiment shown in FIG. 8B. can be longer When the controller 320 needs to increase the charge supply amount of the voltage generator 300, for example, the target level (TG) of the power supply voltage to be set in the power mesh 400 is high, or the power mesh 400 ), a control signal (CTR) for turning off the first resistance switch RSW1 and turning on the second resistance switch RSW2 as shown in FIG. can output On the other hand, when the power supply voltage of the power mesh 400 is stably maintained at the target level, the controller 320 turns on the first resistance switch RSW1 and turns on the second resistance switch RSW2, as shown in FIG. 8B. Power consumption of the voltage generator 300 may be reduced by outputting the control signal CTR for turning off.

9 is a diagram provided to explain the operation of a voltage generator according to an embodiment of the present invention.

Referring to FIG. 9 , the voltage generator according to an embodiment of the present invention may select one of a plurality of charge pumps according to a target level of a power supply voltage to be supplied to the power mesh. 9 , the voltage generator includes a first charge pump and a second charge pump, and the capacitance of the pumping capacitor included in the first charge pump is the capacitance of the pumping capacitor included in the second charge pump. may be smaller than

9 may be a graph showing the size of the ripple component and the charge supply amount of the voltage generator according to the target level of the power supply voltage. Referring to FIG. 9 , a comparative example and an embodiment for the size of the ripple component together with the charge supply amount are shown in graph form. The target level may be selected in the range between the minimum target level (TGmin) and the maximum target level (TGmax).

For example, when the target level is less than the first target level TG1, the voltage generator may control the first charge pump to supply electric charges to the power mesh. When the target level is small, the magnitude of the ripple component may increase in the power supply voltage. Therefore, the increase in the magnitude of the ripple component may be minimized by selecting the first charge pump including the pumping capacitor having a relatively small capacitance.

Meanwhile, when the target level is equal to or higher than the first target level TG1, the voltage generator may control the second charge pump to supply electric charges to the power mesh. When the target level is high, the size of a ripple component in the power supply voltage may be relatively small. Accordingly, when the target level is high, the second charge pump having a large ripple component during operation can be selected, and a sufficient charge supply amount can be secured.

In the embodiment shown in FIG. 9 , a comparative example of the size of the ripple component may correspond to a case where the second charge pump supplies charges to the power mesh regardless of the target level. Accordingly, at a target level lower than the first target level TG1, a ripple component greater than the first ripple voltage VRP1 may appear in the power supply voltage.

On the other hand, in one embodiment of the present invention, by selecting the first charge pump at a target level smaller than the first target level TG1, as shown in FIG. It can be limited to less than the voltage (VRP1). In this way, by limiting the size of the ripple component included in the power supply voltage, a circuit operating by receiving the supply voltage from the power mesh can operate stably.

Referring to FIG. 9 , in a section where the target level is greater than the first target level TG1 and less than the second target level TG2, the magnitude of the ripple component may increase as the target level increases. However, in a section where the target level is greater than the second target level TG2, the size of the ripple component decreases as the target level increases again, and as a result, the size of the ripple component may be limited to less than the first ripple voltage VRP1. there is.

10 to 12 are diagrams provided to explain the operation of the voltage generator according to an embodiment of the present invention.

10 to 12 are diagrams illustrating output changes of the voltage generator according to various information input to the controller of the voltage generator, for example, a target level of a power supply voltage and/or PVT information. As an example, FIG. 10 may be a diagram showing the output of a voltage generator when process information is a first process value among PVT information, and FIG. 11 may be a diagram showing an output of a voltage generator when process information is a second process value. 12 may be a diagram illustrating an output of a voltage generator when process information is a third process value.

For example, the first process value may correspond to a case where a process change in a manufacturing process for manufacturing a semiconductor device including a voltage generator is a typical-typical corner of a nominal case. The second process value may correspond to the slow corner where the process variation exhibits a smaller-than-nominal active drive current and smaller leakage current, and the third process value may correspond to the fast corner where the process variation exhibits a larger-than-nominal active drive current and a large leakage current. can respond

Referring first to FIG. 10 , when the process information is the first process value, the basic output current OUTD output by the voltage generator may have a first basic period TD1. The basic output current OUTD may have the same period as a clock signal initially set as a basic basis by an oscillator included in the voltage generator.

As described above, the oscillator may change the frequency of the clock signal in response to a control signal received from the controller. As shown in FIG. 10 , the oscillator may output a low output current OUTL by lowering the frequency of the clock signal or output a high output current OUTH by increasing the frequency of the clock signal. The first low period TL1 of the low output current OUTL may be longer than the first basic period TD1, and the first high period TH1 of the high output current OUTH may be shorter than the first basic period TD1. there is.

Next, referring to FIG. 11 , when the process information is the second process value, the basic output current OUTD output by the voltage generator may have a second basic period TD2. Referring to FIGS. 10 and 11 together, the second basic period TD2 may be longer than the first basic period TD1. This may be because the effective driving current and leakage current of the transistor included in the semiconductor device decrease when the process information representing the process change of the semiconductor device is the second process value. As a result, as the current characteristics of the transistor deteriorate and the response speed also decreases, as shown in FIG. 11 , the frequency of the initially output basic output current OUTD may decrease.

Therefore, in the embodiment shown in FIG. 11, when the selective charge pump supplies charges to the power mesh with the basic output current OUTD, the power supply voltage of the power mesh does not increase to the target level or the power supply voltage increases. It can be slow. Accordingly, when the process information is the second process value, the controller may output a control signal for controlling the oscillator to output a clock signal having a higher frequency than the default clock signal.

The oscillator may output the clock signal by lowering the frequency of the clock signal or by increasing the frequency of the clock signal in response to the control signal received from the controller. However, in the embodiment shown in FIG. 11 , the second low period TL2 of the low output current OUTL output by the select charge pump in response to the clock signal having a lowered frequency is longer than the second basic period TD2. may not support On the other hand, the second high period TH2 of the high output current OUTH may be shorter than the second basic period TD2, so the controller may increase the frequency of the clock signal to increase the amount of charge delivered to the power mesh. there is.

Referring to FIG. 12 , when the process information is the third process value, the basic output current OUTD output from the voltage generator may have a third basic period TD3. Referring to FIGS. 10 and 12 together, the third basic period TD3 may be shorter than the first basic period TD1. This may be because the effective driving current and leakage current of transistors included in the semiconductor device increase when the process information representing the process change of the semiconductor device is the third process value. Accordingly, the frequency of the basic output current OUTD output by the select charge pump in response to the initially set clock signal may increase, and the charge supply amount may also increase.

Contrary to the embodiment shown in FIG. 11 , in the embodiment shown in FIG. 12 , when the oscillator drives the selective charge pump with a clock signal initially set, excessive charges may be supplied to the power mesh. Accordingly, when the process information is the third process value, the controller may output a control signal that controls the oscillator to lower and output the frequency of the initially set clock signal. In this case, the optional charge pump can output a low output current (OUTL).

13 to 16 are diagrams provided to explain the operation of the voltage generator according to an embodiment of the present invention.

13 may be a graph showing a charge supply amount of a voltage generator according to voltage information received by a controller of the voltage generator. Referring to FIG. 13 , the voltage information includes the level of the external power supply voltage VEXT, which is generated by an external host or an external power supply device and provided to the semiconductor device including the voltage generator. can be voltage.

Referring to FIG. 13 , the charge supply amount of the voltage generator may increase as the level of the external power voltage VEXT increases. However, even under the condition that the external power supply voltage VEXT of the same level is applied, the charge supply amount output from the voltage generator may appear different from each other according to process information, temperature information, and the like. For example, the first graph 501 corresponds to a case where the process information has a first process value as described above with reference to FIG. 10, and the second graph 502 corresponds to a second graph 502 as described with reference to FIG. 12. It may correspond to the case of having a process value. Therefore, under the condition that the external power supply voltage VEXT of the same level is input, the charge supply amount of the voltage generator corresponding to the second graph 502 may be greater than the charge supply amount of the voltage generator corresponding to the first graph 501. there is.

Meanwhile, the controller of the voltage generator may control the oscillator so that the frequency of the clock signal input to the selected charge pump increases as the level of the external power supply voltage VEXT received as voltage information increases. Hereinafter, it will be described in more detail with reference to FIGS. 14 and 15 together.

14 and 15 may be diagrams for explaining the operation of the voltage generator according to the level of the external power supply voltage VEXT. Referring to FIG. 14 , when the oscillator outputs the first clock signal CLK1 having the first cycle TP1 , the selected charge pump selected by the controller can output the first output current OUT1 . The power supply voltage of the power mesh connected to the voltage generator may be charged to a target level by the first output current OUT1.

When the external power supply voltage VEXT input to the semiconductor device including the voltage generator increases, the controller may change the control signal so that the oscillator provides a clock signal with a higher frequency to the selected charge pump. Referring to FIG. 15 , in response to the control of the controller, the oscillator may provide a second clock signal CLK2 having a second period TP2 shorter than the first period TP1 to the selected charge pump.

The selective charge pump may output the second output current OUT2 to the power mesh in response to the second clock signal CLK2. Compared to FIG. 14 , since the second output current OUT2 having a faster frequency is supplied to the power mesh, the power supply voltage of the power mesh can be charged to the target level more quickly.

Referring to the embodiment described above with reference to FIGS. 8A and 8B , the voltage generator includes a comparison circuit, and the comparison circuit compares the feedback voltage corresponding to the power supply voltage of the power mesh with the reference voltage corresponding to the target level. You can control whether the oscillator is operating or not. For example, as shown in FIG. 15, when the selected charge pump increases the amount of charge supplied to the power mesh in response to an increase in the external power supply voltage VEXT and the power supply voltage of the power mesh quickly reaches the target level, the comparison circuit The operation of the oscillator may be stopped by

16 may be a graph showing a charge supply amount of a voltage generator according to a target level of a power supply voltage. Referring to FIG. 16 , as the target level increases, the charge supply amount of the selected charge pump may decrease. However, similar to that described with reference to FIG. 13, even under the condition that the power supply voltage of the power mesh should be increased to the same target level, the charge supply amount output by the voltage generator may be different depending on process information, temperature information, and the like. For example, as the process information has different process values, the charge supply amount according to the target level in each of the semiconductor devices may appear as a first graph 503 and a second graph 504 .

17 is a schematic diagram of a semiconductor device according to an exemplary embodiment of the present invention.

Referring to FIG. 17 , the semiconductor device 600 may be a memory device and may include a plurality of unit memory areas 610 . For example, when the semiconductor device 600 is a dynamic random access memory (DRAM), the unit memory area 610 may be defined as a memory bank. Each of the plurality of unit memory areas 610 may include a memory cell array 611 , a row decoder 612 , a sense amplifier circuit 613 , a column decoder 614 , and the like.

An operation of the semiconductor device 600 may be controlled by the logic circuit 605 . The logic circuit 605 stores data received from the outside in at least one of the plurality of unit memory areas 610, or stores data received from the outside in at least one of the plurality of unit memory areas 610 based on address information received from the outside. Data can be read and output to the outside.

In each of the plurality of unit memory areas 610, the row decoder 612 is connected to the memory cell array 611 through a plurality of word lines, and the sense amplifier circuit 613 is connected to the memory cell array through a plurality of bit lines. (611) can be connected. At least one of a plurality of word lines and at least one of a plurality of bit lines are selected according to address information transmitted by the logic circuit 605, and data is stored in the memory cell array 611 by the sense amplifier circuit 613. or data recorded in the memory cell array 611 can be read.

Also, the logic circuit 605 may include an input/output circuit for exchanging signals with an external device. Referring to FIG. 17 , a plurality of unit memory areas 610 may be disposed on both sides of the logic circuit 605 , and the logic circuit 605 may be disposed in a center region of the semiconductor device 600 . Accordingly, by forming the semiconductor device 600 with a center pad structure in which pads are disposed in the center, wiring patterns connecting the input/output circuits of the logic circuit 605 and the pads can be efficiently designed.

Logic circuit 605 may include voltage generator 606 . The voltage generator 606 controls the operation of each of the unit memory areas 610 and/or the logic circuit 605 using an external power supply voltage provided by an external power supply device such as a Power Management Integrated Circuit (PMIC) or an external host. It can generate the required supply voltage. For example, a power supply voltage required for operation of each of the unit memory areas 610 may be supplied from the voltage generator 606 . Each of the unit memory areas 610 includes a power mesh formed in a mesh shape, and the voltage generator 606 supplies charge to the power mesh until the voltage level of the power mesh increases to a target level. A power supply voltage may be supplied to each of the regions 610 .

The power supply voltage set to the power mesh by the charge supplied by the voltage generator 606 has a predetermined ripple component, and as described above, the magnitude of the ripple component increases as the target level of the power supply voltage decreases, and the charge is applied to the power mesh. It may increase as the capacitance of the pumping capacitor of the charge pump supplied decreases. The voltage generator 606 according to an embodiment of the present invention includes a plurality of charge pumps implemented with pumping capacitors of different capacities, and has small capacitance pumping capacitors when the target level of the power supply voltage is low. , and if the target level of the power supply voltage is high, a charge pump having large capacitance pumping capacitors can be selected.

Accordingly, it is possible to effectively limit the ripple component so that the magnitude of the ripple component appearing in the power supply voltage of the power mesh does not exceed a predetermined level. In addition, while effectively limiting the size of the ripple component, the charge supply amount delivered by the charge pump to the power mesh is maintained so as not to fall below the charge consumption required by the power mesh, so that the semiconductor device 600 can operate stably. there is.

The present invention is not limited by the above-described embodiments and accompanying drawings, but is intended to be limited by the appended claims. Therefore, various forms of substitution, modification, and change will be possible by those skilled in the art within the scope of the technical spirit of the present invention described in the claims, which also falls within the scope of the present invention. something to do.

10, 600: semiconductor device
20, 100, 300, 606: voltage generator
30, 200, 400: power mesh
110, 310: charge pump circuit
120, 320: controller
130, 330: oscillator
140, 340: comparison circuit
CTR: control signal
EN: enable signal

Claims (10)

A first charge pump having a plurality of first pumping capacitors, and a second charge pump having a plurality of second pumping capacitors having a capacitance different from that of each of the plurality of first pumping capacitors, a charge pump circuit that supplies power voltage to the mesh);
a controller outputting a control signal based on the target level of the power supply voltage; and
an oscillator outputting a clock signal to the charge pump circuit; Including,
wherein the oscillator outputs the clock signal to one of the first charge pump and the second charge pump based on the control signal.
According to claim 1,
A first voltage divider circuit providing a reference voltage determined based on the control signal, a second voltage divider circuit providing a feedback voltage determined based on the voltage detected by the power mesh, and the reference voltage and the feedback voltage a comparison circuit including a comparator for comparing Including more,
The enable signal output from the comparator is input to the oscillator.
According to claim 2,
wherein the oscillator outputs the clock signal in response to the enable signal or stops output of the clock signal.
According to claim 1,
Wherein the oscillator adjusts the frequency of the clock signal based on the control signal, the voltage generator.
According to claim 4,
Wherein the controller determines the control signal based on at least one of the target level and PVT (Process, Voltage, Temperature) information.
According to claim 1,
The capacitance of each of the plurality of first pumping capacitors is smaller than the capacitance of each of the plurality of second pumping capacitors;
When the target level is equal to or less than a predetermined reference level, the controller generates the control signal so that the oscillator outputs the clock signal to the first charge pump;
and if the target level is greater than the reference level, the controller generates the control signal to cause the oscillator to output the clock signal to the second charge pump.
According to claim 1,
wherein the oscillator blocks the clock signal output to the other one of the first charge pump and the second charge pump based on the control signal.
a plurality of charge pumps including pumping capacitors of different capacities;
a controller that determines a target level of a power supply voltage supplied to a predetermined circuit area through a power mesh and outputs a control signal that determines a selected charge pump from among the plurality of charge pumps based on the target level; and
an oscillator that determines a frequency of a clock signal input to the selected charge pump based on a comparison result between a reference voltage determined according to the control signal and a voltage detected by the power mesh; A voltage generator comprising a.
a plurality of unit memory areas each including a power mesh supplying a power supply voltage; and
a logic circuit controlling the plurality of unit memory areas; Including,
The logic circuit includes a voltage generator configured to set the power supply voltage included in each of the plurality of unit memory areas to a predetermined target level;
The voltage generator selects one of a plurality of charge pumps for supplying charge to the power mesh so that the level of the power supply voltage is increased and maintained at the target level, and one of the plurality of charge pumps based on the target level. A semiconductor device including a controller that selects with a charge pump.
According to claim 9,
The plurality of charge pumps include a first charge pump including first pumping capacitors and a second charge pump including second pumping capacitors having a higher capacitance than the first pumping capacitors,
wherein the controller selects the first charge pump when the target level is less than a predetermined reference level, and selects the second charge pump when the target level is greater than or equal to the reference level.

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