KR20230090210A - System on chip, security system, and method for performing authentication - Google Patents

Abstract

A system-on-chip, a security system, and a method for performing authentication are disclosed. The system-on-chip according to the technical idea of the present disclosure includes: a non-volatile memory configured to include a key storage area and a key indicator area; and an authenticator configured to confirm the storage location using key indicator data in response to an authentication request received from an external device, obtain key data stored in the storage location from the non-volatile memory, and obtain an asymmetric key of the input key and key data received from the external device as input to perform an encryption algorithm.

Description

SYSTEM ON CHIP, SECURITY SYSTEM, AND METHOD FOR PERFORMING AUTHENTICATION}

The technical idea of the present disclosure relates to an electronic device, and more particularly, to a system on a chip, a security system, and a method for performing authentication.

A debugging device is provided to debug the system on chip. The system-on-chip blocks access of unauthorized debugging devices from the outside. Such a debugging device can perform system-on-chip debugging only when it passes an authentication process using a cryptographic algorithm or the like performed in the system-on-chip. At this time, some information referred to in the authentication process is stored inside the system-on-chip during the manufacturing process of the system-on-chip, and the stored information does not change after the system-on-chip is shipped.

However, there is a problem in that the security function for the system-on-chip is disabled when information once stored is leaked. Therefore, even after the system-on-chip is shipped, information related to the security function needs to be changed as needed.

The technical idea of the present disclosure provides a system-on-chip for changing a key for authentication even after the system-on-chip is shipped, a security system, and a method for performing authentication.

A system-on-a-chip that authenticates a debugging device performing a debugging operation according to the technical idea of the present disclosure includes a debug port configured to receive an authentication request and input key data from the debugging device, a slot in which the key data is stored, and an empty slot. A non-volatile memory configured to include a key storage area including a key storage area, and a key indicator area in which key indicator data indicating a slot in the key storage area is stored, and the slot where the key data is stored is identified using the key indicator data in response to an authentication request. and an authenticator configured to obtain key data from a non-volatile memory and perform an encryption algorithm with an input key of the input key data and an asymmetric key of the key data as inputs.

In addition, a security system according to the technical idea of the present disclosure includes an external device that transmits an input key, and a system-on-chip that performs authentication of the external device based on the input key, and the system-on-chip includes at least one A non-volatile memory configured to include a key storage area in which key data is stored, and a key indicator area in which key indicator data indicating a storage location of data in the key storage area is stored, and the storage location is identified using the key indicator data, and an authenticator configured to obtain key data stored in a storage location from a memory and perform an encryption algorithm using an input key and an asymmetric key of the key data as input.

In addition, a method for authenticating an external device according to the technical idea of the present disclosure includes obtaining key indicator data from a one time programmable (OTP) memory, and using the key indicator data to perform authentication on a plurality of slots included in the OTP memory. Among them, checking the slot where the key data is stored, reading the key data from the OTP memory to obtain an asymmetric key, and using the input key received from the external device and the asymmetric key of the key data as input to perform the encryption algorithm. It includes steps to perform.

According to the technical concept of the present disclosure, by changing a key for authentication even after the system-on-chip is shipped, there is an effect of further strengthening the security of the system-on-chip.

1 is a diagram for explaining a security system according to an embodiment of the present disclosure.
2 is a diagram for explaining a method of operating a security system according to an embodiment of the present disclosure.
3 is a flowchart for explaining an authentication method according to an embodiment of the present disclosure.
4 is a diagram for explaining a method of changing an asymmetric key according to an embodiment of the present disclosure.
5 is a diagram for explaining a non-volatile memory according to an embodiment of the present disclosure.
6A and 6B are diagrams for explaining an embodiment of storing valid key data.
7A, 7B and 7C are diagrams for explaining an embodiment of storing invalid key data.
8 is a block diagram illustrating a security system according to another embodiment of the present disclosure.
9 is a block diagram illustrating a security system according to another embodiment of the present disclosure.

Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

1 is a diagram for explaining a security system according to an embodiment of the present disclosure.

Referring to FIG. 1 , a security system 1 may include an external device 10 and a system on chip 100 .

The external device 10 may communicate with the system on chip 100 through a communication interface. The external device 10 may access the system-on-chip 100 and change or correct parameters built into the system-on-chip 100 and internal information of the system-on-chip 100 . Such an external device 10 may be implemented as, for example, a host or a debugging device.

In order for the external device 10 to change internal information of the system on chip 100, the external device 10 must be authenticated by the system on chip 100. In one embodiment, the external device 10 may transmit an authentication request to the system on chip 100 . Also, the external device 10 may transmit an input key required for an authentication operation.

In one embodiment, when the external device 10 is implemented as a debugging device, the external device 10 may be a Joint Test Action Group (JTAG). JTAG refers to a method of transmitting output data or receiving input data in a serial communication method for digital input/output of a specific node in a digital circuit. JTAG may be a debugging device used for developing an embedded system.

The system on chip 100 may include a debug port 110 , an authenticator 120 , a security processor 130 , and a non-volatile memory 140 .

The debug port 110 may receive or transmit a signal related to an authentication operation and/or a debugging operation from the external device 10 . For example, authentication requests and input keys may be provided to system on chip 100 through debug port 110 .

The authenticator 120 may perform authentication on the external device 10 . For example, the authenticator 120 may perform an authentication operation using an input key received from the external device 10 and a previously stored asymmetric key. Specifically, for example, the authenticator 120 may perform an encryption algorithm using an input key and an asymmetric key. If the input key and the asymmetric key match each other by an encryption algorithm, it may be determined that authentication of the external device 10 is successful.

In one embodiment, the authenticator 120 may control the non-volatile memory 140 to obtain data stored in the non-volatile memory 140 . Specifically, for example, the authenticator 120 provides a read command and address to the non-volatile memory 140, the non-volatile memory 140 reads data and provides the read data to the authenticator 120. can Specifically, for another example, when the system on chip 100 is booted (or powered on), data stored in the non-volatile memory 140 is provided to the authenticator 120, and the authenticator 120 can be temporarily stored in

An "authenticator" of the present disclosure may be referred to as an "authentication protocol module".

The security processor 130 may control the non-volatile memory 140 . Specifically, for example, the secure processor 130 may provide data, a write command, and an address to the non-volatile memory 140 . Accordingly, data may be stored in the non-volatile memory 140 .

The nonvolatile memory 140 may perform an operation indicated by a command on a memory cell selected by an address among memory cells. Here, the command may be, for example, a write command (or program command), a read command, or an erase command, and an operation indicated by the command may be, for example, a write operation (or program operation), a read operation, or an erase operation. can

The nonvolatile memory 140 may be, for example, a flash memory. Flash memory includes, for example, NAND flash memory, vertical NAND, NOR flash memory, resistive random access memory, and phase-change memory. Change Memory), Magnetoresistive Random Access Memory, and the like may be included. In one embodiment, the non-volatile memory 140 may be one time programmable (OTP) memory.

In one embodiment, the non-volatile memory 140 may include a key storage area 141 and a key indicator area 142 . The key storage area 141 may be an area in which at least one key data is stored. The key indicator area 142 may be an area where key indicator data is stored. The key indicator data may be data indicating a storage location of data in the key storage area 141 . A “storage location” of the present disclosure may be a storage unit of key data. A "storage location" in this disclosure may be referred to as a "slot". That is, the non-volatile memory 140 may include a plurality of slots for storing key data. The "key indicator data" of this disclosure may be referred to as "revocation information".

In one embodiment, when the non-volatile memory 140 includes the key storage area 141 and the key indicator area 142, the authenticator 120 may check the storage location using the key indicator data. Also, the authenticator 120 may obtain key data stored in a storage location from the non-volatile memory 140 . Then, the authenticator 120 may perform an encryption algorithm by inputting an input key and an asymmetric key of key data.

2 is a diagram for explaining a method of operating a security system according to an embodiment of the present disclosure.

Referring to FIG. 2 , the external device 210 and the system on chip 220 may respectively correspond to the external device 10 and the system on chip 100 shown in FIG. 1 .

In step S100, the external device 210 transmits an authentication request to the system on chip 220.

In step S110, the system on chip 220 performs an authentication operation in response to the authentication request.

In step S120, the system on chip 220 determines whether authentication is successful.

If authentication fails (S120, No), in step S130, the system on chip 220 transmits a signal indicating inaccessibility to the external device 210.

If the authentication succeeds (S120, Yes), in step S140, the system on chip 220 transmits a signal indicating permission of access to the external device 210.

In step S150, the external device 210 transmits an access request to the system on chip 220 to obtain internal information.

In step S160 , the system on chip 220 transmits internal information to the external device 210 .

In step S170, the external device 210 performs a debugging operation based on internal information.

In step S180 , the external device 210 transmits debugging information to the system on chip 220 .

Hereinafter, a method of performing the authentication operation of the system on chip 220 shown in step S110 will be described in detail.

3 is a flowchart for explaining an authentication method according to an embodiment of the present disclosure.

Referring to FIGS. 1 and 3 , in step S111, the authenticator 120 obtains key indicator data from the non-volatile memory 140. Specifically, for example, the authenticator 120 transmits a read command and an address to the non-volatile memory 140, and the non-volatile memory 140 provides key indicator data to the authenticator 120. In one embodiment, when non-volatile memory 140 is implemented as an OTP memory, authenticator 120 obtains key indicator data from the OTP memory.

In step S112, the authenticator 120 checks the storage location where the key data to be used in the authentication operation is stored, based on the key indicator data. In one embodiment, when the non-volatile memory 140 is implemented as an OTP memory, the authenticator 120 identifies a slot in which key data is stored among a plurality of slots included in the OTP memory using key indicator data. .

In step S113, the authenticator 120 obtains key data from the non-volatile memory. In one embodiment, when the non-volatile memory 140 is implemented as an OTP memory, the authenticator 120 reads key data from the OTP memory to obtain an asymmetric key. Here, the asymmetric key may be a value of a key to be used for an authentication operation.

In step S114, the authenticator 120 performs an encryption algorithm by inputting an input key and an asymmetric key of key data. Here, the input key may be a key received from the external device 10 .

4 is a diagram for explaining a method of changing an asymmetric key according to an embodiment of the present disclosure.

Referring to FIGS. 1 and 4 , the external device 410 and the system on chip 420 may respectively correspond to the external device 10 and the system on chip 100 shown in FIG. 1 . Alternatively, the external device 410 and the system on chip 420 may respectively correspond to the external device 210 and the system on chip 220 shown in FIG. 2 . It is assumed that the external device 410 shown in FIG. 4 is authenticated with respect to the system on chip 420 .

In step S200, the external device 410 transmits a key change command and new key data. Referring to FIG. 1 , for example, the authenticator 120 receives a key change command and new key data through the debug port 110 in response to the external device 10 being authenticated. In one embodiment, the new key data may be valid data. In another embodiment, the new key data may be invalid data.

In step S210, the system on a chip 420 checks an empty slot based on the key indicator data. Referring to FIG. 1 , for example, the authenticator 120 identifies an empty slot among a plurality of slots included in a non-volatile memory (eg, OPT memory) using key indicator data.

In step S220, the system on chip 420 stores new key data in an empty slot.

In step S230, the system on chip 420 updates the key indicator data to point to the slot where the new key data is stored.

In step S240, the system on chip 420 transmits a change completion response.

In one embodiment, when the key indicator data is updated, authenticator 120 may obtain new key data in response to a new authentication request from an unauthenticated device. Here, the unauthenticated device may be a device different from the authenticated external device 410 .

5 is a diagram for explaining a non-volatile memory according to an embodiment of the present disclosure.

Referring to FIG. 5 , the nonvolatile memory 500 may correspond to the nonvolatile memory 140 shown in FIG. 1 .

The nonvolatile memory 500 may include a key storage area 510 and a key indicator area 520 .

In one embodiment, the key storage area 510 may include first through Nth slots. N may be an integer greater than or equal to 2. Referring to FIG. 5 , for example, the key storage area 510 may include first to third slots (Slot#1, Slot#2, and Slot#3). However, it is not limited thereto. Hereinafter, it is assumed that the number of slots is three. The key storage area 510 may store at least one key data. Referring to FIG. 5 , for example, the first key data (Key_1) may be stored in the first slot (Slot#1), and the second and third slots (Slot#2 and Slot#3) may be empty. . However, it is not limited thereto.

The key indicator region 520 may include first through Nth bit cells. The first to Nth bit cells may respectively correspond to the first to Nth bit positions. For example, the kth bit cell may correspond to the kth bit position. Here, k may be a natural number less than or equal to N. Referring to FIG. 5 , for example, the key indicator area 520 may include first to third bit cells Bit#1, Bit#2, and Bit#3. However, it is not limited thereto. Hereinafter, it is assumed that the number of bit cells is three. At this time, the key indicator data being stored in the key indicator area 520 may correspond to the fact that the first to third bit cells Bit#1, Bit#2, and Bit#3 are programmed or free. there is. Among the first to third bit cells Bit#1, Bit#2, and Bit#3, the first bit cell Bit#1 may be a most significant bit (MSB), and the third bit cell Bit#3 may correspond to a least significant bit (LSB), but is not limited thereto.

The third bit cell (Bit#3), the second bit cell (Bit#2), and the first bit cell (Bit#1) may be sequentially programmed.

In one embodiment, when the first to kth bit cells of the first to Nth bit cells are programmed, the storage location where the key data is stored, specifically, the storage location where the key to be used for the authentication operation is stored is in the first to Nth slots. Of these, it may be the k-th slot. The first to k th bit cells may correspond to the first to k th bit positions (k is a natural number less than or equal to N). Referring to FIG. 5 , for example, when only the third bit cell (Bit#3) among the first to third bit cells (Bit#1, Bit#2, and Bit#3) is programmed, a key to be used for authentication operation is stored. The storage location may be the first slot (Slot#1) among the first to third slots (Slot#1, Slot#2, and Slot#3). For another example, the second bit cell (Bit#2 ) and the third bit cell (Bit#3) are programmed, the storage location in which the key to be used for the authentication operation is stored is the second slot (of the first to third slots (Slot#1, Slot#2, Slot#3) (Slot # 2) For another example, if the first to third bit cells (Bit # 1, Bit # 2, and Bit # 3) are programmed, the storage location where the key to be used for the authentication operation is stored is It may be the third slot ((Slot#3) among the first to third slots (Slot#1, Slot#2, and Slot#3).

6A and 6B are diagrams for explaining an embodiment of storing valid key data.

Referring to FIG. 6A , it is assumed that the first key data Key_1 is stored in the non-volatile memory 640 during the manufacturing process of the system on chip 600 . The first key data Key_1 may be stored, for example, in the first slot Slot#1 of the key storage area 641 . When the system on chip 600 is shipped, it is assumed that the second and third slots Slot#2 and Slot#3 of the key storage area 641 are empty. Key indicator data stored in the key indicator area 642 may indicate the first slot (Slot#1). Specifically, only the third bit cell (Bit#3) among the first to third bit cells (Bit#1, Bit#2, and Bit#3) included in the key indicator area 642 is programmed, and the first and first Bit cells Bit#1 and Bit#1 may be free.

An authenticated external device (eg, the external device 10 shown in FIG. 1 ) may provide the second key data Ket_2 and the key change command CCMD to the system on chip 600 . In this case, the second key data Ket_2 and the key change command CCMD may be transferred to the authenticator 620 through the debug port 610 . In one embodiment, the second key data (Ket_2) may be valid data.

The authenticator 620 may receive a key change command (CCMD) and second key data (Ket_2). Also, the authenticator 620 may check an empty storage location in the key storage area 641 using the key indicator data. For example, since the third bit cell (Bit#3) is programmed in the key indicator area 642 and the first and second bit cells (Bit#1, Bit#2) are free, the current key indicator data is It may point to the slot (Slot#1). The authenticator 620 may confirm that at least the second slot (Slot#2) is empty. Accordingly, the second slot (Slot#2) may be an empty storage location. The authenticator 620 may provide slot data Slot_INFO and second key data Ket_2 to the security processor 630 . The slot data (Slot_INFO) may be data indicating an empty storage location, that is, an empty slot. Referring to FIG. 6A , slot data (Slot_INFO) may indicate a second slot (Slot#2).

The security processor 630 includes an address (ADD) corresponding to an empty storage location (eg, the second slot (Slot # 2)), valid key data (eg, second key data (Ket_2)), And the write command WCMD may be provided to the non-volatile memory 640 . The non-volatile memory 640 stores valid key data (eg, second key data (Ket_2)) in an empty storage location (eg, second slot (Slot#2)) in response to the write command (WCMD). can be saved.

Meanwhile, the current key indicator data points to the first slot (Slot#1), and since the key data to be used for the authentication operation is the second key data (Ket_2), it is necessary to update the key indicator data.

Referring to FIG. 6B , the security processor 630 may control the non-volatile memory 640 to update key indicator data. Specifically, for example, the security processor 630 includes data DATA, an address ADD corresponding to a bit cell in a free state (eg, the second bit cell Bit#2), and a write command WCMD. ) can be provided to the non-volatile memory 640. Here, the data DATA may be for programming a bit cell in a free state. The nonvolatile memory 640 may program a bit cell (eg, the second bit cell Bit#2) in a free state. Among the first to third bit cells Bit#1, Bit#2, and Bit#3, the second and third bit cells Bit#2 and Bit#3 are programmed, and the first bit cell Bit#1 Since it is free, the key indicator data may indicate the second slot (Slot#2).

The authenticator 620 may transmit a response (RPN) to the key change command (CCMD) to an authenticated external device (eg, the external device 10 shown in FIG. 1) through the debug port 610. .

When the key indicator data is updated, the authenticator 620 may obtain second key data Ket_2 from the non-volatile memory 640 in response to the new authentication request.

As described above, there is an effect of further strengthening the security of the system on chip 600 by changing a key for authentication after the system on chip 600 is shipped.

7A, 7B, and 7C are diagrams for explaining an embodiment of storing invalid key data.

Referring to FIG. 7A , it is assumed that the first key data (Key_1) is stored in the first slot (Slot#1) of the key storage area 641 during the manufacturing process of the system on chip 600. Also, it is assumed that the second and third slots Slot#2 and Slot#3 of the key storage area 641 are empty when the system on chip 600 is shipped.

Referring to FIG. 7B , an authenticated external device (eg, the external device 10 shown in FIG. 1 ) provides invalid key data (IVD_KEY) and a key change command (CCMD) to the system-on-chip 600. can do. In one embodiment, the invalid key data (IVD_KEY) may be data having an arbitrary value, for example. Alternatively, in one embodiment, the invalid key data (IVD_KEY) may be dummy data.

The authenticator 620 may receive a key change command (CCMD) and invalid key data (IVD_KEY) through the debug port 610 . Also, the authenticator 620 may check an empty storage location (eg, the second slot (Slot #2)) in the key storage area 641 using the key indicator data. The authenticator 620 may provide slot data (Slot_INFO) and invalid key data (IVD_KEY) to the security processor 630. Referring to FIG. 7A, the slot data (Slot_INFO) is the second slot (Slot#2). can represent

The security processor 630 includes an address (ADD) corresponding to an empty storage location (eg, the second slot (Slot # 2) shown in FIG. 7A), invalid key data (IVD_KEY), and a write command ( WCMD) to the non-volatile memory 640.

Referring to FIG. 7C , the security processor 630 may control the non-volatile memory 640 to update key indicator data. Specifically, for example, the security processor 630 includes data DATA, an address ADD corresponding to a bit cell in a free state (eg, the second bit cell Bit#2), and a write command WCMD. ) can be provided to the non-volatile memory 640. Among the first to third bit cells Bit#1, Bit#2, and Bit#3, the second and third bit cells Bit#2 and Bit#3 are programmed, and the first bit cell Bit#1 Since it is free, the key indicator data may indicate the second slot (Slot#2).

The authenticator 620 may transmit a response (RPN) to the key change command (CCMD) to an authenticated external device (eg, the external device 10 shown in FIG. 1) through the debug port 610. .

Since the system on chip 600 performs an authentication operation using invalid key data (IVD_KEY), authentication of an unauthorized external device can be prevented.

As described above, after the system on chip 600 is shipped, the key for authentication is changed to invalid data, thereby preventing hacking.

8 is a block diagram illustrating a security system according to another embodiment of the present disclosure.

Referring to FIG. 8 , the security system 3 includes a system on chip 1000, an external debugger 1051, a display device 1550, an external memory 1850, and a power management integrated circuit (PMIC). (1950).

The external debugger 1051 may correspond to the external device 10 shown in FIG. 1 . The external debugger 1051 may transmit an authentication request and input key data to the system on chip 1000 . If the external debugger 1051 is authenticated, the external debugger 1051 may obtain internal information of the system on chip 1000 and perform a debugging operation based on the internal information.

The system on chip 1000, the display device 1550, the external memory 1850, and the PMIC 1950 may be implemented as a handheld device. Portable devices include a mobile phone, a smart phone, a tablet personal computer (PDA), a personal digital assistant (PDA), an enterprise digital assistant (EDA), a digital still camera, and a digital video camera. , a portable multimedia player (PMP), a personal navigation device or portable navigation device (PND), a handheld game console, or an e-book.

The system-on-chip 1000 includes an authentication protocol module 1001, a central processing unit (CPU) 1100, a security controller 1101, a neural processing unit (NPU) 1200, graphics A graphics processing unit (GPU) 1300, a timer 1400, a display controller 1500, a random access memory (RAM) 1600, a read only memory (ROM) 1700, a memory controller 1800, A clock management unit (CMU) 1900 and a bus 1050 may be included. The system on chip 1000 may further include other components in addition to the illustrated components.

The authentication protocol module 1001 may correspond to the authenticator 120 shown in FIG. 1 .

The CPU 1100 may also be called a processor and may process or execute programs and/or data stored in the external memory 1850 . For example, the CPU 1100 may process or execute programs and/or data in response to an operation clock signal output from the CMU 1900 .

The CPU 1100 may be implemented as a multi-core processor. A multi-core processor is a computing component having two or more independent substantive processors (called 'cores'), each of which executes program instructions. can read and execute. Programs and/or data stored in the ROM 1700, the RAM 1600, and/or the external memory 1850 may be loaded into a memory (not shown) of the CPU 1100 as needed.

The security controller 1101 may read programs and/or data stored in the ROM 1700 , the RAM 1600 , and/or the external memory 1850 under the control of the CPU 1100 . Alternatively, the security controller 1101 may store programs and/or data stored in the ROM 1700 , the RAM 1600 , and/or the external memory 1850 under the control of the CPU 1100 . The CPU 1100 and the security controller 1101 may be included in the security processor 130 shown in FIG. 1 .

The NPU 1200 can efficiently process large-scale calculations using an artificial neural network. The NPU 1200 may perform deep learning by supporting simultaneous matrix operations.

The GPU 1300 may convert read data read from the external memory 1850 by the memory controller 1800 into a signal suitable for the display device 1550 .

The timer 1400 may output a count value representing time based on an operation clock signal output from the CMU 1900 .

The display device 1550 may display image signals output from the display controller 1500 . For example, the display device 1550 may be implemented as a liquid crystal display (LCD), a light emitting diode (LED) display, an organic LED (OLED) display, an active-matrix OLED (AMOLED) display, or a flexible display. . The display controller 1500 may control the operation of the display device 1550.

RAM 1600 may temporarily store programs, data, or instructions. For example, programs and/or data stored in the memory may be temporarily stored in the RAM 1600 under the control of the CPU 1100 or according to booting codes stored in the ROM 1700 . The RAM 1600 may be implemented as dynamic RAM (DRAM) or static RAM (SRAM).

ROM 1700 may store permanent programs and/or data. The ROM 1700 may be implemented as an erasable programmable read-only memory (EPROM) or electrically erasable programmable read-only memory (EEPROM).

In one embodiment, ROM 1700 may be implemented as an OTP memory. The ROM 1700 may correspond to the nonvolatile memory 140 shown in FIG. 1 .

The memory controller 1800 may communicate with the external memory 1850 through an interface. The memory controller 1800 controls overall operations of the external memory 1850 and controls data exchange between the host and the external memory 1850 . For example, the memory controller 1800 may write data to or read data from the external memory 1850 according to a request of a host. Here, the host may be a master device such as the CPU 1100 , the GPU 1300 , or the display controller 1500 .

The external memory 1850 is a storage medium for storing data, and may store an Operating System (OS), various programs, and/or various data. The external memory 1850 may be, for example, DRAM, but is not limited thereto. For example, the external memory 1850 may be a nonvolatile memory device (eg, a flash memory, phase change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), or FeRAM device). In another embodiment of the present invention, the external memory 1850 may be a built-in memory provided inside the system on chip 1000. Also, the external memory 1850 may be a flash memory, an embedded multimedia card (eMMC), or universal flash storage (UFS).

The CMU 1900 generates an operating clock signal. The CMU 1900 may include a clock signal generator such as a phase locked loop (PLL), a delayed locked loop (DLL), or a crystal oscillator.

An operating clock signal may be supplied to the GPU 1300 . Of course, the operation clock signal may be supplied to other components (eg, the CPU 1100 or the memory controller 1800). The CMU 1900 may change the frequency of the operating clock signal.

Each of the CPU 1100, NPU 1200, GPU 1300, timer 1400, display controller 1500, RAM 1600, ROM 1700, memory controller 1800, and CMU 1900 is a bus ( 1050) to communicate with each other.

The PMIC 1950 may be implemented outside the system on a chip 1000 . However, it is not limited thereto, and a power management unit (PMU) capable of performing the function of the PMIC 1950 may be included in the system-on-chip 1000 .

9 is a block diagram illustrating a security system according to another embodiment of the present disclosure.

Referring to FIG. 9 , the security system 4 may be implemented as a personal computer (PC), a data server, or a portable electronic device.

The security system 4 includes a system on chip 2000, a camera module 2100, a display 2200, a power source 2300, an input/output port 2400, a memory 2500, a storage 2600, and an external memory 2700. ), and a network device 2800.

The camera module 2100 refers to a module capable of converting an optical image into an electrical image. Accordingly, the electrical image output from the camera module may be stored in the storage 2600 , the memory 2500 , or the external memory 2700 . Also, an electrical image output from the camera module may be displayed through the display 2200 .

The display 2200 may display 2200 data output from the storage 2600 , the memory 2500 , the input/output port 2400 , the external memory 2700 , or the network device 2800 . The display 2200 may be the display device 1550 shown in FIG. 8 .

The power source 2300 may supply an operating voltage to at least one of the components. Power source 2300 may be controlled by PMIC 1950 shown in FIG. 8 .

The input/output port 2400 refers to ports capable of transmitting data to the security system 4 or data output from the security system 4 to an external device. For example, the input/output port 2400 may be a port for connecting a pointing device such as a computer mouse, a port for connecting a printer, or a port for connecting a USB drive.

The memory 2500 may be implemented as volatile memory or non-volatile memory. According to an embodiment, a memory controller capable of controlling a data access operation for the memory 2500, eg, a read operation, a write operation (or program operation), or an erase operation, is integrated or embedded in the system-on-chip 2000. It can be. According to another embodiment, the memory controller may be implemented between the system on chip 2000 and the memory 2500 .

The storage 2600 may be implemented as a hard disk drive or a solid state drive (SSD).

The external memory 2700 may be implemented as a secure digital (SD) card or a multimedia card (MMC). According to embodiments, the external memory 2700 may be a subscriber identification module (SIM) card or a universal subscriber identity module (USIM) card.

The network device 2800 refers to a device capable of connecting the security system 4 to a wired network or a wireless network.

As described above, there is an effect of further strengthening the security of the system on chip by changing a key for authentication even after the system on chip is shipped.

As above, exemplary embodiments have been disclosed in the drawings and specifications. Although the embodiments have been described using specific terms in this specification, they are only used for the purpose of explaining the technical idea of the present disclosure, and are not used to limit the scope of the present disclosure described in the claims. . Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical scope of protection of the present disclosure should be determined by the technical spirit of the appended claims.

Claims (10)

In a system-on-chip that authenticates a debugging device performing a debugging operation,
a debug port configured to receive an authentication request and input key data from the debugging device;
a nonvolatile memory configured to include a key storage area including a slot in which key data is stored and an empty slot, and a key indicator area in which key indicator data indicating a slot in the key storage area is stored; and
In response to the authentication request, a slot in which the key data is stored is identified using the key indicator data, the key data is obtained from the non-volatile memory, and an input key of the input key data and an asymmetric key of the key data are obtained. A system on a chip comprising an authenticator configured to perform a cryptographic algorithm on input. According to claim 1,
The key storage area,
It includes first to Nth slots (N is an integer greater than or equal to 2),
The key indicator area,
A system on a chip comprising first to Nth bit cells corresponding to first to Nth bit positions, respectively. According to claim 2,
The slot where the key data is stored,
When the first to kth bit cells corresponding to the first to kth bit positions (k is a natural number less than or equal to N) among the first to Nth bit cells are programmed, the kth slot among the first to Nth slots is programmed. Characterized in that, a system on a chip. According to claim 1,
and a secure processor configured to control the non-volatile memory. According to claim 4,
The authenticator,
When the debugging device is authenticated, receiving a key change command and valid key data from the debugging device;
Checking the empty slot in the key storage area using the key indicator data;
providing the slot data indicating the empty slot and the valid key data to the secure processor;
The security processor,
providing an address corresponding to the empty slot, the valid key data, and a write command to the non-volatile memory;
and controlling the non-volatile memory to update the key indicator data. According to claim 5,
The authenticator,
and obtaining the valid key data in response to a new authentication request received through the debug port when the key indicator data is updated. According to claim 4,
The authenticator,
When the debugging device is authenticated, receiving a key change command and invalid key data from the debugging device;
Checking an empty slot in the key storage area using the key indicator data;
providing slot data indicating the empty slot and invalid key data to the secure processor;
The security processor,
providing an address corresponding to the empty slot, the invalid key data, and a write command to the non-volatile memory;
and controlling the non-volatile memory to update the key indicator data. According to claim 1,
The non-volatile memory,
A system on a chip, characterized in that it is a one time programmable (OTP) memory. an external device that transmits an input key; and
A system-on-chip performing authentication of the external device based on the input key;
The system on a chip,
a nonvolatile memory configured to include a key storage area in which at least one key data is stored, and a key indicator area in which key indicator data indicating a storage location of data in the key storage area is stored; and
Authentication configured to identify the storage location using the key indicator data, obtain key data stored in the storage location from the non-volatile memory, and perform an encryption algorithm using the input key and an asymmetric key of the key data as inputs. A security system that includes a ki. A method for authenticating an external device,
obtaining key indicator data from a one time programmable (OTP) memory;
checking a slot in which key data is stored among a plurality of slots included in the OTP memory using the key indicator data;
obtaining an asymmetric key by reading the key data from the OTP memory; and
And performing an encryption algorithm with an input key received from the external device and an asymmetric key of the key data as an input.

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