KR20230087700A - Scan Driver and Display apparatus comprising thereof - Google Patents

Abstract

Each of the plurality of stages of the scan driver according to an embodiment of the present invention controls voltage levels of the first control node and the second control node by a first start signal and a second start signal, and generates a first carry signal. a first control unit that outputs; a second control unit controlling voltage levels of a third control node and a fourth control node according to the first start signal and the second start signal and outputting a second carry signal; and a pull-up transistor having a gate connected to the first control node and a pull-down transistor having a first gate connected to the third control node, wherein an on-voltage output through the pull-up transistor and an off-voltage output through the pull-down transistor An output unit for outputting a scan signal based on; includes.

Description

Scan driver and display device including the same

The present invention relates to a scan driver and a display device including the same.

The display device includes a pixel unit including a plurality of pixels, a scan driver unit, a data driver unit, and a control unit. The scan driver includes stages connected to the scan lines, and the stages supply scan signals to the scan lines connected to them in response to signals from the controller.

An object of the present invention is to provide a scan driver capable of stably outputting a scan signal and a display device including the same. The technical problems to be achieved by the present invention are not limited to the above-mentioned technical problems, and other technical problems not mentioned will be clearly understood by those skilled in the art from the description of the present invention. .

The scan driver according to an embodiment of the present invention includes a plurality of stages, and each of the plurality of stages is configured to control voltage levels of the first control node and the second control node by a first start signal and a second start signal. a first control unit that controls and outputs a first carry signal; a second control unit controlling voltage levels of a third control node and a fourth control node according to the first start signal and the second start signal and outputting a second carry signal; and a pull-up transistor having a gate connected to the first control node and a pull-down transistor having a first gate connected to the third control node, wherein an on-voltage output through the pull-up transistor and an off-voltage output through the pull-down transistor An output unit for outputting a scan signal based on; includes.

Transistors constituting each of the plurality of stages may be N-channel oxide thin film transistors.

A circuit of the first control unit and a circuit of the second control unit may be symmetrical based on a node to which a terminal for applying an off voltage to the first control unit and the second control unit is connected.

The pull-up transistor is connected between a first voltage input terminal to which a first voltage of an on voltage is applied and a first output node to which a first output terminal for outputting the scan signal is connected, and the pull-down transistor has a third voltage of an off voltage It may be connected between an applied third voltage input terminal and the first output node.

The first start signal applied to the first stage is a first scan start signal, the second start signal is an inverted signal of the first start signal, and the first stage is applied to each of the stages subsequent to the first stage. The start signal and the second start signal may be the first carry signal and the second carry signal output from a previous stage.

The first controller may include a first transistor connected between a first voltage input terminal to which a first voltage of an on voltage is applied and the first control node, and a gate connected to a first input terminal to which the first start signal is applied. ; a second transistor connected between the first voltage input terminal and the second control node, and having a gate connected to a second input terminal to which the second start signal is applied; a third transistor connected between the first control node and a node to which a second voltage input terminal receiving a second voltage of an off voltage is connected, and having a gate connected to the second control node; a fourth transistor connected between the second control node and the node, and having a gate connected to the first control node; a fifth transistor connected between a clock terminal to which a clock signal is applied and a second output node to which a second output terminal outputting the first carry signal is connected, and having a gate connected to the first control node; a sixth transistor connected between the second voltage input terminal and the second output node, and having a gate connected to the second control node; a first capacitor connected between the first control node and the second output node; and a second capacitor connected between the second control node and the second voltage input terminal.

In a first period of a frame, the second start signal is applied with an on-voltage during at least part of the first period so that the second control node is set to an on-voltage of the first voltage through the second transistor; The first control node is set to an off voltage of the second voltage through a third transistor, and in a second period subsequent to the first period, the first start signal is turned on at least part of the second period. is applied, the first control node may be set to an on-voltage of the first voltage through the first transistor, and the second control node may be set to an off-voltage of the second voltage through the fourth transistor. .

The first controller outputs the first carry signal based on the second voltage output through the sixth transistor during the first period and the clock signal output through the fifth transistor during the second period. can do.

The clock signal output in the second period may include a plurality of pulses.

The third transistor includes a pair of sub-transistors connected in series between the first control node and the node, and the first control unit is configured between the first voltage input terminal and an intermediate node of the pair of sub-transistors. A connected seventh transistor may be further included.

The second controller may include an eighth transistor connected between a first voltage input terminal to which a first voltage of an on voltage is applied and the third control node, and a gate connected to a second input terminal to which the second start signal is applied. ; a ninth transistor connected between the first voltage input terminal and the fourth control node, and having a gate connected to a first input terminal to which the first start signal is applied; a tenth transistor connected between the third control node and a node to which a second voltage input terminal receiving a second off voltage is applied, and having a gate connected to the fourth control node; an eleventh transistor connected between the fourth control node and the node, and having a gate connected to the third control node; a twelfth transistor connected between a clock terminal to which a clock signal is applied and a third output node to which a third output terminal outputting the second carry signal is connected, and having a gate connected to the third control node; a thirteenth transistor connected between the second voltage input terminal and the third output node, and having a gate connected to the fourth control node; a third capacitor coupled between the third control node and the third output node; and a fourth capacitor connected between the fourth control node and the second voltage input terminal.

In a first period of a frame, the second start signal is applied with an on-voltage during at least part of the first period, and the third control node is set to an on-voltage of the first voltage through the eighth transistor. The fourth control node is set to an off voltage of the second voltage through an eleventh transistor, and in a second period subsequent to the first period, the first start signal is turned on at least part of the second period. is applied, the fourth control node may be set to an on-voltage of the first voltage through the ninth transistor, and the third control node may be set to an off-voltage of the second voltage through the tenth transistor. .

The second controller outputs the second carry signal based on the clock signal output through the twelfth transistor in the first period and the second voltage output through the thirteenth transistor in the second period. can do.

The clock signal output during the first period may include a plurality of pulses.

The tenth transistor includes a pair of sub-transistors connected in series between the third control node and the node, and the second control unit is connected between the first voltage input terminal and an intermediate node of the pair of sub-transistors. A connected 14th transistor may be further included.

A display device according to an exemplary embodiment of the present invention includes a pixel unit including a plurality of pixels, each of the plurality of pixels connected to a scan line and a data line; and a scan driver configured to output a scan signal to the scan line of each of the plurality of pixels, wherein the scan driver includes a plurality of stages, each of the plurality of stages comprising a first start signal and a second a first control unit controlling voltage levels of the first control node and the second control node according to a start signal and outputting a first carry signal; a second control unit controlling voltage levels of a third control node and a fourth control node according to the first start signal and the second start signal and outputting a second carry signal; and a pull-up transistor having a gate connected to the first control node and a pull-down transistor having a first gate connected to the third control node, wherein an on-voltage output through the pull-up transistor and an off-voltage output through the pull-down transistor An output unit for outputting a scan signal based on; includes.

The transistors constituting the pixel circuit of each of the pixels and the transistors constituting each of the stages may be N-channel oxide thin film transistors.

A circuit of the first control unit and a circuit of the second control unit may be symmetrical based on a node to which a terminal for applying an off voltage to the first control unit and the second control unit is connected.

The pull-up transistor is connected between a first voltage input terminal to which a first voltage of an on voltage is applied and a first output node to which a first output terminal for outputting the scan signal is connected, and the pull-down transistor has a third voltage of an off voltage It may be connected between an applied third voltage input terminal and the first output node.

The first start signal applied to the first stage is a first scan start signal, the second start signal is an inverted signal of the first start signal, and each of the stages subsequent to the first stage The first start signal and the second start signal applied to may be the first carry signal and the second carry signal output from a previous stage.

According to an embodiment of the present invention, it is possible to provide a scan driver capable of stably outputting a scan signal and a display device including the same. The effects of the present invention are not limited to the above-mentioned effects, and may be variously extended without departing from the spirit of the present invention.

1 is a diagram schematically illustrating a display device according to an exemplary embodiment.
2 is a diagram schematically illustrating a scan driver according to an exemplary embodiment.
FIG. 3 is a diagram showing waveforms of some input/output signals applied to the scan driver of FIG. 2 .
4 is a circuit diagram illustrating a stage included in the scan driver of FIG. 2 according to an exemplary embodiment.
FIG. 5 is a waveform diagram illustrating an example of an operation of the stage of FIG. 4 .
6A and 6B are equivalent circuit diagrams illustrating pixels according to an exemplary embodiment.

Since the present invention can apply various transformations and have various embodiments, specific embodiments will be illustrated in the drawings and described in detail in the detailed description. Effects and features of the present invention, and methods for achieving them will become clear with reference to the embodiments described later in detail together with the drawings. However, the present invention is not limited to the embodiments disclosed below and may be implemented in various forms.

In the following embodiments, terms such as first and second are used for the purpose of distinguishing one component from another component without limiting meaning.

In the following examples, expressions in the singular number include plural expressions unless the context clearly dictates otherwise.

In the following embodiments, terms such as include or have mean that features or components described in the specification exist, and do not preclude the possibility that one or more other features or components may be added.

In the following embodiments, when a part such as a film, region, component, etc. is said to be on or on another part, not only when it is directly above the other part, but also when another film, region, component, etc. is interposed therebetween. Including if there is

In the drawings, the size of components may be exaggerated or reduced for convenience of explanation. For example, since the size and thickness of each component shown in the drawings are arbitrarily shown for convenience of description, the present invention is not necessarily limited to those shown.

In this specification, "A and/or B" represents the case of A, B, or A and B. In addition, in the present specification, "at least one of A and B" represents the case of A, B, or A and B.

In the following embodiments, when X and Y are connected, when X and Y are electrically connected, when X and Y are functionally connected, and when X and Y are directly connected. can Here, X and Y may be objects (eg, devices, elements, circuits, wires, electrodes, terminals, conductive films, layers, etc.). Therefore, it is not limited to a predetermined connection relationship, for example, a connection relationship shown in the drawings or detailed description, and may include connections other than those shown in the drawings or detailed description.

When X and Y are electrically connected, for example, an element (eg, a switch, a transistor, a capacitive element, an inductor, a resistance element, a diode, etc.) that enables the electrical connection of X and Y, A case in which one or more is connected between X and Y may be included.

In the following embodiments, “on” used in connection with a device state may refer to an activated state of the device, and “off” may refer to a deactivated state of the device. “On” when used in connection with a signal received by a device may refer to a signal that activates the device, and “off” may refer to a signal that deactivates the device. The device may be activated by a high-level voltage or a low-level voltage. For example, a P-type transistor is activated (turned on) by a low-level voltage, and an N-type transistor is activated (turned on) by a high-level voltage. Accordingly, it should be understood that the "on" voltages for the P-type and N-type transistors are opposite (low vs. high) voltage levels. Hereinafter, a voltage for turning on a transistor is referred to as an on voltage, and a voltage for turning off a transistor is referred to as an off voltage.

1 is a diagram schematically illustrating a display device according to an exemplary embodiment.

The display device 10 according to an exemplary embodiment of the present invention is an organic light emitting display device, an inorganic light emitting display device (inorganic light emitting display or inorganic EL display device), and a quantum dot light emitting display device such as It may be a display device.

Referring to FIG. 1 , a display device 10 according to an exemplary embodiment may include a pixel unit 110 , a scan driver 130 , a data driver 150 , and a control unit 170 .

A plurality of pixels PXs and signal lines capable of applying electrical signals to the plurality of pixels PXs may be disposed in the pixel unit 110 . The pixel unit 110 may be a display area for displaying an image.

The plurality of pixels PX may be repeatedly arranged in a first direction (x direction, row direction) and a second direction (y direction, column direction). The plurality of pixels PX may be arranged in various forms such as a stripe arrangement, a pentile arrangement, and a mosaic arrangement to implement an image. Each of the plurality of pixels PX includes an organic light emitting diode as a display element, and the organic light emitting diode may be connected to the pixel circuit. The pixel circuit may include a plurality of transistors and at least one capacitor. In one embodiment, the plurality of transistors included in the pixel circuit may be N-type thin film transistors. The N-type thin film transistor may be an oxide thin film transistor in which an active pattern (semiconductor layer) includes an amorphous or crystalline oxide. Oxide thin film transistors have excellent off current characteristics.

Signal lines capable of applying electrical signals to the plurality of pixels PX may include a plurality of scan lines SL extending in a first direction and a plurality of data lines DL extending in a second direction. can The plurality of scan lines SL may be spaced apart from each other along the second direction and transfer scan signals to the pixels PX. The plurality of data lines DL are spaced apart from each other along the first direction and may transmit data signals to the pixels PX. Each of the plurality of pixels PX may be connected to at least one corresponding scan line among the plurality of scan lines SL and a corresponding data line among the plurality of data lines DL. In FIG. 1 , for convenience of illustration, it is shown that one scan line is connected to the pixel PX, but each pixel PX may be connected to a plurality of scan lines according to the number of transistors constituting the pixel circuit.

The scan driver 130 may be connected to a plurality of scan lines SL, generate a scan signal in response to a control signal SCS from the controller 170, and sequentially supply the scan signal to the scan lines SL. there is. The scan line SL is connected to the gate of a transistor included in the pixel circuit, and the scan signal may transfer the scan signal to the gate of the transistor. The scan signal may be a square wave signal in which an on-voltage for turning on the transistor and an off-voltage for turning off the transistor are repeated. In one embodiment, the on voltage may be a high level voltage (hereinafter referred to as 'high voltage').

The data driver 150 may be connected to a plurality of data lines DL and supply data signals to the data lines DL in response to the control signal DCS from the control unit 170 . The data signal supplied to the data lines DL may be supplied to the pixels PX to which the scan signal is supplied. To this end, the data driver 150 may supply data signals to the data lines DL in synchronization with the scan signal.

The control unit 170 may generate a scan control signal (SCS) and a data control signal (DCS) based on signals input from the outside. The controller 170 may supply the scan control signal SCS to the scan driver 130 and the data control signal DCS to the data driver 150 .

2 is a diagram schematically illustrating a scan driver according to an exemplary embodiment. FIG. 3 is a diagram showing waveforms of some input/output signals applied to the scan driver of FIG. 2 .

Referring to FIG. 2 , the scan driver 130 may include a plurality of first to nth stages ST1 to STn. Each of the first to nth stages ST1 to STn may correspond to a pixel row (pixel line) provided in the pixel unit 110 . The number of stages of the scan driver 130 may be variously modified according to the number of pixel rows.

Each of the plurality of first to nth stages ST1 to STn includes a first input terminal IN1, a second input terminal IN2, a clock terminal CK, a first voltage input terminal V1, and a second voltage. It may include an input terminal V2, a third voltage input terminal V3, a first output terminal OUT1, a second output terminal OUT2, and a third output terminal OUT3.

The first input terminal IN1 may receive the first scan start signal STV1 or the previous first carry signal as a first start signal. In one embodiment, the first scan start signal STV1 is applied to the first input terminal IN1 of the first stage ST1, and the second to nth stages ST2 to ST2 to STn) A first carry signal output from a previous stage may be applied to each first input terminal IN1. The second input terminal IN2 may receive the second scan start signal STV2 or the previous second carry signal as a second start signal. In an embodiment, the second scan start signal STV2 is applied to the second input terminal IN2 of the first stage ST1, and the second to nth stages ST2 to ST2 to STn) A second carry signal output from a previous stage may be applied to each second input terminal IN2. For example, the first stage ST1 may start driving by the first scan start signal STV1 and the second scan start signal STV2 and generate and output the first output signal Out[1]. there is. The first carry signal CRA[n-1] output from the n−1 th stage and the second carry signal CRB output from the n−1 th stage are connected to the first input terminal IN1 and the second input terminal IN2 of the n th stage STn. [n-1]) is input, and the nth stage STn can generate and output the nth output signal Out[n].

As shown in FIG. 3 , the first scan start signal STV1 and the second scan start signal STV2 may be signals in which a low level voltage (hereinafter referred to as 'low voltage') and a high voltage alternate. The first scan start signal STV1 and the second scan start signal STV2 may have one low voltage period and one high voltage period during one frame. The second scan start signal STV2 may be an inverted signal of the first scan start signal STV1. Here, a frame (frame period) may be a period for displaying one frame image.

The clock terminal CK may receive the first clock signal CLK1 or the second clock signal CLK2. The first clock signal CLK1 and the second clock signal CLK2 may be alternately applied to the first to nth stages ST1 to STn. For example, the first clock signal CLK1 may be applied to the clock terminal CK of odd-numbered stages, and the second clock signal CLK2 may be applied to the clock terminals CK of even-numbered stages. As shown in FIG. 3 , the first clock signal CLK1 and the second clock signal CLK2 may be square wave signals repeating a high voltage and a low voltage. The first clock signal CLK1 and the second clock signal CLK2 may have the same waveform and have phase shifted signals. For example, the second clock signal CLK2 may be an inverted signal having the same waveform as the first clock signal CLK1 and a 180 degree phase difference (half cycle phase difference). That is, pulses (high voltage periods) of the first clock signal CLK1 and the second clock signal CLK2 may not overlap.

The first voltage input terminal (V1) receives the first voltage (VGH) as a high voltage, the second voltage input terminal (V2) receives the second voltage (VGL1) as a low voltage, and the third voltage input terminal ( V3) may receive the third voltage VGL2, which is a low voltage. The third voltage VGL2 may be a lower voltage than the second voltage VGL1. The first voltage VGH, the second voltage VGL1, and the third voltage VGL2 may be supplied as global signals from the control unit 170 shown in FIG. 1 and/or a power supply unit not shown.

The first output terminal OUT1 may output an output signal. An output signal may be supplied to a pixel through a corresponding scan line. The second output terminal OUT2 may output the first carry signal. The third output terminal OUT3 may output the second carry signal.

The plurality of first to nth stages ST1 to STn generate first to nth output signals (Out[1], Out[2], Out[3] in response to the first start signal and the second start signal. , Out[4], ..., Out[n]). Here, an output signal output from each of the first to nth stages ST1 to STn may be a scan signal. The first to nth output signals Out[1], Out[2], Out[3], Out[4], ..., Out[n] are the first clock signal CLK1 and the second clock signal. It can be shifted by the phase difference of the signal CLK2 and outputted sequentially.

The first carry signals CRA[1], CRA[2], CRA[3], CRA[4] output from the second output terminals OUT2 of the first to nth stages ST1 to STn; ...) can be applied to the first input terminal IN1 of the next stage. The second carry signals CRB[1], CRB[2], CRB[3], CRB[4] output from the third output terminals OUT3 of the first to nth stages ST1 to STn; ...) can be applied to the second input terminal IN2 of the next stage. In one embodiment, the first carry signal and the second carry signal output from the second output terminal OUT2 and the third output terminal OUT3 of the last n-th stage STn are applied to a dummy stage at a later stage (not shown). It can be.

4 is a circuit diagram illustrating a stage included in the scan driver of FIG. 2 according to an exemplary embodiment. FIG. 5 is a waveform diagram illustrating an example of an operation of the stage of FIG. 4 .

Each of the first to nth stages ST1 to STn has a plurality of nodes, and hereinafter, some nodes among the plurality of nodes are used to control the first to third output nodes N1 to N3 and the first to fourth nodes. It is referred to as nodes A, B, C, and D.

Hereinafter, the kth stage STk outputting the kth output signal Out[k] to the kth row of the pixel unit 110 will be described as an example. In one embodiment, the plurality of transistors included in each circuit of the first to nth stages ST1 to STn may be N-type thin film transistors. The N-type thin film transistor may be an oxide thin film transistor.

The kth stage (STk, where k is a natural number) shown in FIG. 4 may include a first control unit 210 , a second control unit 230 and an output unit 250 .

The first control unit 210 and the second control unit 230 may be vertically symmetrical circuits based on the node E. The input signals of the first control unit 210 and the second control unit 230 include a first start signal, a second start signal, a clock signal CLK, a first voltage VGH, a second voltage VGL1, and a third voltage VGL1. It may include voltage VGL2. In the case of the first stage ST1, the first start signal and the second start signal may be the first scan start signal STV1 and the second scan start signal STV2. In the case of the 2nd to nth stages ST2 to STn, the first start signal and the second start signal are the first carry signal CRA[i] output from the previous stage and the second carry signal CRB[i]. ) can be.

The first controller 210 may control the voltages of the first control node A and the second control node B based on the input signals. The first control unit 210 outputs the first carry signal CRA[k] based on the clock signal CLK or the second voltage VGL1 according to the voltages of the first control node A and the second control node B. ) can be generated and output to the second output terminal OUT2 connected to the second output node N2.

The first controller 210 includes a first transistor TR1 , a second transistor TR2 , a third transistor TR3 , a fourth transistor TR4 , a fifth transistor TR5 , a sixth transistor TR6 , and a third transistor TR3 . It may include a first capacitor (C1) and a second capacitor (C2). The first controller 210 may further include a seventh transistor TR7.

The first transistor TR1 may be connected between the first voltage input terminal V1 and the first control node A. A gate of the first transistor TR1 may be connected to the first input terminal IN1.

The second transistor TR2 may be connected between the first voltage input terminal V1 and the second control node B. A gate of the second transistor TR2 may be connected to the second input terminal IN2.

The third transistor TR3 may be connected between the first control node A and the node E. The third transistor TR3 may include a pair of sub-transistors connected in series between the first control node A and the node E. In one embodiment, the third transistor TR3 may include the 3-1st transistor TR3-1 and the 3-2nd transistor TR3-2. Gates of the 3-1st transistor TR3-1 and the 3-2nd transistor TR3-2 may be connected to the second control node B.

The fourth transistor TR4 may be connected between the second control node B and the node E. can be connected A gate of the fourth transistor TR4 may be connected to the first control node A.

The fifth transistor TR5 may be connected between the clock terminal CK and the second output node N2. A gate of the fifth transistor TR5 may be connected to the first control node A. The fifth transistor TR5 may be turned on or off according to the voltage of the first control node A. When the first control node A is set to a high voltage, the fifth transistor TR5 is turned on, and the clock signal CLK is converted to the second carry signal CRA[k] through the fifth transistor TR5. It can be output through the output terminal (OUT2).

The sixth transistor TR6 may be connected between the node E and the second output node N2. A gate of the sixth transistor TR6 may be connected to the second control node B. The sixth transistor TR6 may be turned on or off according to the voltage of the second control node B. When the second control node B is set to a high voltage, the sixth transistor TR6 is turned on and the second voltage VGL1 is transmitted as the first carry signal CRA[k] through the sixth transistor TR6. It can be output through the 2nd output terminal (OUT2).

The seventh transistor TR7 may be connected between the intermediate node (common electrode) of the 3-1 and 3-2 transistors TR3-1 and TR3-2 and the first voltage input terminal V1. A gate of the seventh transistor TR7 may be connected to the first control node A. When the seventh transistor TR7 is turned on, the first voltage VGH is applied to the intermediate node of the 3-1 and 3-2 transistors TR3-1 and TR3-2, thereby forming the third transistor TR3. It is possible to minimize the current leakage of the first control node (A) through.

The first capacitor C1 may be connected between the first control node A and the second output node N2. When the fifth transistor TR5 is turned on, the voltage of the first control node A may be bootstrapped by the first capacitor C1. The second capacitor C2 may be connected between the second control node B and the node E.

The second controller 230 may control the voltages of the third control node C and the fourth control node D based on the input signals. The second control unit 230 outputs the second carry signal CRB[k] based on the clock signal CLK or the second voltage VGL1 according to the voltages of the third control node C and the fourth control node D. ) can be generated and output to the third output terminal OUT3 connected to the third output node N3.

The second control unit 230 includes the eighth transistor TR8, the ninth transistor TR9, the tenth transistor TR10, the eleventh transistor TR11, the twelfth transistor TR12, the thirteenth transistor TR13, and the second control unit 230. It may include a third capacitor (C3) and a fourth capacitor (C4). The second controller 230 may further include a 14th transistor TR14.

The eighth transistor TR8 may be connected between the first voltage input terminal V1 and the third control node C. A gate of the eighth transistor TR8 may be connected to the second input terminal IN2.

The ninth transistor TR9 may be connected between the first voltage input terminal V1 and the fourth control node D. A gate of the ninth transistor TR9 may be connected to the first input terminal IN1.

The tenth transistor TR10 may be connected between the third control node C and the node E. The tenth transistor TR10 may include a pair of sub-transistors connected in series between the third control node C and the node E. In one embodiment, the tenth transistor TR10 may include a 10-1 th transistor TR10-1 and a 10-2 th transistor TR10-2. Gates of the 10-1 transistor TR10-1 and the 10-2 transistor TR10-2 may be connected to the fourth control node D.

An eleventh transistor TR11 may be connected between the fourth control node D and the node E. can be connected A gate of the eleventh transistor TR11 may be connected to the third control node C.

The twelfth transistor TR12 may be connected between the clock terminal CK and the third output node N3. A gate of the twelfth transistor TR12 may be connected to the third control node C. The twelfth transistor TR12 may be turned on or off according to the voltage of the third control node C. When the third control node C is set to a high voltage, the twelfth transistor TR12 is turned on, and the clock signal CLK is converted into the second carry signal CRB[k] through the twelfth transistor TR12. It can be output through the output terminal (OUT3).

The thirteenth transistor TR13 may be connected between the node E and the third output node N3. A gate of the thirteenth transistor TR13 may be connected to the fourth control node D. The thirteenth transistor TR13 may be turned on or off according to the voltage of the fourth control node D. When the fourth control node D is set to a high voltage, the thirteenth transistor TR13 is turned on and the second voltage VGL1 is transmitted as the second carry signal CRB[k] through the thirteenth transistor TR13. It can be output through 3 output terminals (OUT3).

The fourteenth transistor TR14 may be connected between the intermediate node (common electrode) of the 10-1 th transistor TR10-1 and the 10-2 th transistor TR10-2 and the first voltage input terminal V1. A gate of the fourteenth transistor TR14 may be connected to the third control node C. When the 14th transistor TR14 is turned on, the first voltage VGH is applied to the intermediate node of the 10th-1st transistor TR10-1 and the 10-2nd transistor TR10-2, thereby forming the 10th transistor TR10. It is possible to minimize the current leakage of the third control node (C) through.

The third capacitor C3 may be connected between the third control node C and the third output node N3. When the twelfth transistor TR12 is turned on, the voltage of the third control node C may be bootstrapped by the third capacitor C3. The fourth capacitor C4 may be connected between the fourth control node D and the node E.

The output unit 250 supplies the first voltage VGH or the third voltage VGL2 according to the voltages of the first control node A and the third control node C to the first output node N1. It can be output through the output terminal (OUT1). The first control node (A) and the third control node (C) may be alternately set to the on voltage on a frame basis.

The output unit 250 may include a fifteenth transistor TR15 as a pull-up transistor for outputting a high voltage and a sixteenth transistor TR16 as a pull-down transistor for outputting a low voltage. The fifteenth transistor TR15 may be turned on or off by the first controller 210 . The sixteenth transistor TR16 may be turned on or off by the second controller 230 . The fifteenth transistor TR15 and the sixteenth transistor TR16 may be alternately turned on in frame units.

The fifteenth transistor TR15 may be connected between the first voltage input terminal V1 and the first output node N1. A gate of the fifteenth transistor TR15 may be connected to the first control node A. The fifteenth transistor TR15 may be turned on or off according to the voltage of the first control node A. When the first control node A is set to a high voltage, the 15th transistor TR15 is turned on and the first voltage VGH of the high voltage is output as the kth output signal Out[k] through the 15th transistor TR15. ) can be output to the first output terminal OUT1.

The sixteenth transistor TR16 may be connected between the third voltage input terminal V3 and the first output node N1. A gate of the sixteenth transistor TR16 may be connected to the third control node C. The sixteenth transistor TR16 may be turned on or off according to the voltage of the third control node C. When the third control node C is set to a high voltage, the sixteenth transistor TR16 is turned on, and the third voltage VGL2 of the low voltage is output through the sixteenth transistor TR16 to the kth output signal Out[k]. ) can be output to the first output terminal OUT1.

5, the previous first carry signal CRA[i] and the previous second carry signal CRB[i] as start signals, the clock signal CLK, and the first to fourth control nodes A, B, Node voltages of C and D), the first carry signal CRA[k], the second carry signal CRB[k], and the output signal Out[k] are shown.

The previous first carry signal CRA[i] and the previous second carry signal CRB[i] are the first carry signal and the second carry signal output from the previous stage, and the previous stage may be at least one previous stage. there is. For example, as shown in FIGS. 4 and 5 , the previous first carry signal CRA[i] and the previous second carry signal CRB[i] may be signals output from the preceding stage. .

The clock signal CLK may be the first clock signal CLK1 or the second clock signal CLK2.

The high voltage may be an on voltage, and the low voltage may be an off voltage. Hereinafter, the operation of the stage in one frame will be described with reference to FIG. 5 . One frame may include a first period P1 in which an off voltage scan signal is output and a second period P2 in which an on voltage scan signal is output.

In the first period (P1), the first control node (A) and the fourth control node (D) are set to the off voltage, and the second control node (B) and the third control node (C) are set to the on voltage It can be.

During the first period P1, the low voltage first carry signal CRA[i] is applied to the first input terminal IN1, and the second carry signal CRB[i] having a waveform of the clock signal CLK ) may be applied to the second input terminal IN2. The second carry signal CRB[i] applied as a waveform of the clock signal CLK during the first period P1 includes a plurality of pulses and is applied as a high voltage during at least part of the first period P1. can

The second transistor TR2 of the first control unit 210 and the eighth transistor TR8 of the second control unit 230 turn on and Turn-off can be repeated. When the second transistor TR2 and the eighth transistor TR8 are turned on by the high voltage of the second carry signal CRB[i], the first voltage VGH is applied to the second control node B and the third control node. The second control node (B) and the third control node (C) may be set to a high voltage. When the second transistor TR2 and the eighth transistor TR8 are turned off by the low voltage of the second carry signal CRB[i], the second control node B and the third control node C are high voltage can be maintained.

The fourteenth transistor TR14, the gate of which is connected to the third control node C, is turned on so that a high voltage can be transferred to the intermediate node of the tenth transistor TR10.

The first transistor TR1 of the first control unit 210 and the ninth transistor TR9 of the second control unit 230 are turned off by the low voltage first carry signal CRA[i], and The third transistor TR3 and the eleventh transistor TR11, the gates of which are connected to the second control node B and the third control node C, may be turned on. Accordingly, the second voltage VGL1 is transferred to the first control node A through the third transistor TR3, and the second voltage VGL1 is transferred to the fourth anode D through the eleventh transistor TR11. , the first control node (A) and the fourth control node (D) may be set to a low voltage. The fourth transistor TR4 and the tenth transistor T10, the gates of which are connected to the first control node A and the fourth control node D, may be turned off.

The 16th transistor TR16 of the output unit 250, the 6th transistor TR6 of the first control unit 210, the gates of which are connected to the high voltage second control node B and the third control node C, Each of the twelfth transistors TR12 of the second controller 230 may be turned on. The third voltage VGL2 is transferred to the first output node N1 through the sixteenth transistor TR16, and the second voltage VGL1 is transferred to the second output node N2 through the sixth transistor TR6. and the clock signal CLK can be transferred to the third output node N3 through the twelfth transistor TR12. Accordingly, the output unit 250 outputs the kth output signal Out[k] of the low voltage through the first output terminal OUT1, and the first control unit 210 outputs the low voltage through the second output terminal OUT2. The low voltage first carry signal CRA[k] is output, and the second controller 230 outputs the second carry signal CRB[k] following the waveform of the clock signal CLK through the third output terminal OUT3. ]) can be output.

During the first period P1 , the transistor of the pixel circuit to which the k th output signal Out[k] of the low voltage is applied as a gate may be turned off.

In the second period (P2), the first control node (A) and the fourth control node (D) are set to the on voltage, and the second control node (B) and the third control node (C) are set to the off voltage It can be.

In the second period P2, the first carry signal CRA[i] having the waveform of the clock signal CLK is applied to the first input terminal IN1, and the low voltage second carry signal CRB[i] ) may be applied to the second input terminal IN2. The first carry signal CRA[i] applied as a waveform of the clock signal CLK in the second period P2 includes a plurality of pulses and is applied as a high voltage in at least part of the second period P2. can

The first transistor TR1 of the first control unit 210 and the ninth transistor TR9 of the second control unit 230 are turned on by the first carry signal CRA[i] in which the high voltage and the low voltage are repeated. Turn off can be repeated. When the first transistor TR1 and the ninth transistor TR9 are turned on by the high voltage of the first carry signal CRA[i], the first voltage VGH is applied to the first control node A and the fourth control node. It is transferred to the node D, and the first control node A and the fourth control node D may be set to a high voltage. When the first transistor TR1 and the ninth transistor TR9 are turned off by the low voltage of the first carry signal CRA[i], the first control node A and the fourth control node D are high. voltage can be maintained. The seventh transistor TR7, the gate of which is connected to the first control node A, is turned on so that a high voltage can be transmitted to the middle node of the third transistor TR3.

The second transistor TR2 of the first control unit 210 and the eighth transistor TR8 of the second control unit 230 are turned off by the low voltage second carry signal CRB[i], and The fourth transistor TR4 and the tenth transistor TR10, the gates of which are connected to the first control node A and the fourth control node D, may be turned on. Accordingly, the second voltage VGL1 is transferred to the second control node B through the fourth transistor TR4, and the second voltage VGL1 is transferred to the third control node C through the tenth transistor TR10. , the second control node (B) and the third control node (C) may be set to a low voltage. The third transistor TR3 and the eleventh transistor T11, the gates of which are connected to the second control node B and the third control node C, may be turned off.

The 15th transistor TR15 of the output unit 250, the gate of which is connected to the first control node A having a high voltage, the fifth transistor TR5 of the first control unit 210, and the fourth control node D having a high voltage The thirteenth transistor TR13 of the second control unit 230 having a gate connected to ) may be turned on. The first voltage VGH is transferred to the first output node N1 through the fifteenth transistor TR15, and the clock signal CLK is transferred to the second output node N2 through the fifth transistor TR5. , the second voltage VGL1 may be transferred to the third output node N3 through the thirteenth transistor TR13. Accordingly, the output unit 250 outputs the kth output signal Out[k] of the high voltage through the first output terminal OUT1, and the first control unit 210 outputs the high voltage through the second output terminal OUT2. The first carry signal CRA[k] following the waveform of the clock signal CLK is output, and the second controller 230 outputs the low voltage second carry signal CRB[k] through the third output terminal OUT3. ]) can be output.

When the first control node (A) and the third control node (C) are in high voltage, the voltage level is boosted by the first capacitor (C1) and the third capacitor (C3), respectively, and the second control node (B) and the second control node (C) respectively. 4 When the control node (D) is a high voltage, it may be higher than the voltage level.

During the second period P2 , the transistor of the pixel circuit to which the k th output signal Out[k] of the high voltage is applied as a gate may be turned on.

5, the length of the second period P2 is longer than that of the first period P1, but this is exemplary, and the first period depends on the function performed by the transistor of the pixel circuit to which the output signal is applied. The lengths of (P1) and the second period (P2) may be adjusted.

6A and 6B are equivalent circuit diagrams illustrating pixels according to an exemplary embodiment.

Referring to FIG. 6A , the pixel PX may include a pixel circuit PC and an organic light emitting diode OLED as a display element connected to the pixel circuit PC. The pixel circuit PC includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, and a capacitor Cst. The first transistor T1 is a driving transistor whose source-drain current is determined according to the gate-source voltage, and the second to fourth transistors T2 to T4 are switching transistors turned on/off according to the gate voltage. can be

The first transistor T1 includes a gate connected to the first node Na, a first terminal connected to the second node Nb, and a second terminal connected to the third node Nc. A first terminal of the first transistor T1 is connected to a driving voltage line supplying the first power voltage ELVDD via a fourth transistor T4, and a second terminal is connected to a first electrode of the organic light emitting diode OLED. (pixel electrode, anode). The first transistor T1 serves as a driving transistor, receives the data signal DATA according to the switching operation of the second transistor T2, and controls the amount of driving current flowing to the organic light emitting diode OLED. .

The second transistor T2 (data write transistor) includes a gate connected to the first scan line SL1, a first terminal connected to the data line DL, and a first node Na (or the gate of the first transistor T1). ) and a second terminal connected to The second transistor T2 is turned on according to the scan signal SC input through the first scan line SL1 to electrically connect the data line DL and the first node Na, and The data signal DATA input through may be transmitted to the first node Na.

The third transistor T3 (initialization transistor) includes a gate connected to the second scan line SL2, a first terminal connected to the third node Nc (or the second terminal of the first transistor T1), and an initialization voltage ( INT) and a second terminal connected to the initialization voltage line. The third transistor T3 may be turned on by the scan signal SS supplied to the second scan line SL2 and transfer the initialization voltage INT transferred to the initialization voltage line to the third node Nc.

The fourth transistor T4 (emission control transistor) has a gate connected to the third scan line SL3, a first terminal connected to the driving voltage line, and a second node Nb (or the first terminal of the first transistor T1). It includes a second terminal connected to. The fourth transistor T4 is turned on according to the scan signal EM transmitted through the third scan line SL3 so that current flows through the organic light emitting diode OLED.

The capacitor Cst may be connected between the first node Na and the second terminal of the first transistor T1. The capacitor Cst may store a voltage corresponding to a difference between the voltage received from the second transistor T2 and the potential of the second terminal of the first transistor T1.

The organic light emitting diode (OLED) includes a first electrode (pixel electrode, anode) connected to the second terminal of the first transistor T1, and a second electrode (counter electrode) to which the second power source voltage ELVSS, which is a common voltage, is applied. , cathode). The organic light emitting diode (OLED) can emit light having a predetermined luminance by driving current supplied from the first transistor (T1).

In another embodiment, the fourth transistor T4 may be connected between the first transistor T1 and the organic light emitting diode OLED. For example, like the pixel circuit PC shown in FIG. 6B, the fourth transistor T4 includes a gate connected to the third scan line SL3, a first terminal connected to the third node Nc, and an organic light emitting diode. (OLED) may include a second terminal connected to the first electrode.

6A and 6B, the first to fourth transistors T1 to T4 of the pixel circuit PC may be N-type transistors. For example, the first to fourth transistors T1 to T4 may be oxide thin film transistors.

In one embodiment, each stage of the scan driver 130 shown in FIG. 2 is connected to gates of the second to fourth transistors T2 to T4 of the pixel circuit PC shown in FIGS. 6A and 6B. It may be connected to one of the first to third scan lines SL1 to SL3. The output signal output from the first output terminal OUT1 of each stage of the scan driver 130 shown in FIG. 2 is the scan signals SC, SS, and SL1 applied to the first to third scan lines SL1 to SL3. EM) may be one of them. For example, each stage of the scan driver 130 shown in FIG. 2 is connected to the third scan line SL3 of the pixel circuit PC shown in FIGS. 6A and 6B provided in a corresponding row, and the third scan An output signal can be output as the scan signal EM through the line SL3. Accordingly, the scan signal EM may be supplied to the gate of the fourth transistor T4 of the pixel circuit PC.

When the high voltage scan signal EM is supplied, that is, when the stage outputs the high voltage output signal, the fourth transistor T4 is turned on so that the organic light emitting diode OLED can emit light. That is, the second period P2 of FIG. 5 may be a light emission period. When the low voltage scan signal EM is supplied, that is, when the stage outputs the low voltage output signal, the fourth transistor T4 is turned off so that the organic light emitting diode OLED may not emit light. That is, the first period P1 of FIG. 5 may be a non-emitting period. In this case, the second period P2 may be longer than the first period P1.

The pixel circuit PC shown in FIGS. 6A and 6B is exemplary, and various pixel circuits PC including at least one transistor to which at least one scan signal is applied may be applied to an embodiment of the present invention. For example, the pixel circuit PC of the pixel PX includes a first transistor T1 serving as a driving transistor, a second transistor T2 transmitting data signals, and a fourth transistor controlling light emission of the organic light emitting diode OLED. The transistor T4 may be included, and the third transistor T3 may be omitted or at least one transistor for another function may be further included.

As such, the present invention has been described with reference to one embodiment shown in the drawings, but this is merely exemplary, and those skilled in the art will understand that various modifications and variations of the embodiment are possible therefrom. Therefore, the true technical scope of protection of the present invention should be determined by the technical spirit of the appended claims.

10: display device
110: pixel unit
130: injection drive unit
150: data driving unit
170: control unit
ST: stage

Claims (20)

In the scan driving unit including a plurality of stages,
Each of the plurality of stages,
a first control unit controlling voltage levels of the first control node and the second control node according to the first start signal and the second start signal and outputting a first carry signal;
a second control unit controlling voltage levels of a third control node and a fourth control node according to the first start signal and the second start signal and outputting a second carry signal; and
A pull-up transistor having a gate connected to the first control node and a pull-down transistor having a first gate connected to the third control node, wherein an on-voltage output through the pull-up transistor and an off-voltage output through the pull-down transistor are A scan driver including an output unit for outputting a scan signal on the basis of. According to claim 1,
The scan driver, wherein the transistors constituting each of the plurality of stages are N-channel oxide thin film transistors. According to claim 1,
A circuit of the first control unit and a circuit of the second control unit are symmetrical with respect to a node to which a terminal for applying an off voltage to the first control unit and the second control unit is connected. According to claim 1,
The pull-up transistor is connected between a first voltage input terminal to which a first voltage of an on voltage is applied and a first output node to which a first output terminal for outputting the scan signal is connected,
The pull-down transistor is connected between a third voltage input terminal to which a third voltage of an off voltage is applied and the first output node. According to claim 1,
The first start signal applied to the first stage is a first scan start signal, the second start signal is an inverted signal of the first start signal,
wherein the first start signal and the second start signal applied to each of the stages subsequent to the first stage are the first carry signal and the second carry signal output from a previous stage. The method of claim 5, wherein the first control unit,
a first transistor connected between a first voltage input terminal to which a first voltage of the turn-on voltage is applied and the first control node, and a gate connected to a first input terminal to which the first start signal is applied;
a second transistor connected between the first voltage input terminal and the second control node, and having a gate connected to a second input terminal to which the second start signal is applied;
a third transistor connected between the first control node and a node to which a second voltage input terminal receiving a second voltage of an off voltage is connected, and having a gate connected to the second control node;
a fourth transistor connected between the second control node and the node, and having a gate connected to the first control node;
a fifth transistor connected between a clock terminal to which a clock signal is applied and a second output node to which a second output terminal outputting the first carry signal is connected, and having a gate connected to the first control node;
a sixth transistor connected between the second voltage input terminal and the second output node, and having a gate connected to the second control node;
a first capacitor coupled between the first control node and the second output node; and
and a second capacitor connected between the second control node and the second voltage input terminal. According to claim 6,
In the first period of the frame,
The second start signal is applied with an on-voltage during at least part of the first period, the second control node is set to the on-voltage of the first voltage through the second transistor, and the third transistor through the third transistor. 1 control node is set to the off voltage of the second voltage,
In the second period following the first period,
The first start signal is applied with an on-voltage during at least part of the second period, the first control node is set to the on-voltage of the first voltage through the first transistor, and the first control node is set to the on-voltage of the first voltage through the fourth transistor. The scan driver, wherein the second control node is set to an off voltage of the second voltage. According to claim 7,
The first controller outputs the first carry signal based on the second voltage output through the sixth transistor during the first period and the clock signal output through the fifth transistor during the second period. , the scan driving unit. According to claim 8,
wherein the clock signal output in the second period includes a plurality of pulses. According to claim 6,
The third transistor includes a pair of sub-transistors connected in series between the first control node and the node;
The first control unit,
The scan driver further comprising a seventh transistor connected between the first voltage input terminal and an intermediate node of the pair of subtransistors. The method of claim 5, wherein the second control unit,
an eighth transistor connected between a first voltage input terminal to which a first voltage of an on voltage is applied and the third control node, and a gate connected to a second input terminal to which the second start signal is applied;
a ninth transistor connected between the first voltage input terminal and the fourth control node, and having a gate connected to a first input terminal to which the first start signal is applied;
a tenth transistor connected between the third control node and a node to which a second voltage input terminal receiving a second off voltage is applied, and having a gate connected to the fourth control node;
an eleventh transistor connected between the fourth control node and the node, and having a gate connected to the third control node;
a twelfth transistor connected between a clock terminal to which a clock signal is applied and a third output node to which a third output terminal outputting the second carry signal is connected, and having a gate connected to the third control node;
a thirteenth transistor connected between the second voltage input terminal and the third output node, and having a gate connected to the fourth control node;
a third capacitor connected between the third control node and the third output node; and
and a fourth capacitor connected between the fourth control node and the second voltage input terminal. According to claim 11,
In the first period of the frame,
The second start signal is applied with an on-voltage during at least part of the first period, the third control node is set to the on-voltage of the first voltage through the eighth transistor, and the third control node is set to the on-voltage of the first voltage through the eleventh transistor. 4 control node is set to the off voltage of the second voltage,
In the second period following the first period,
During at least part of the second period, the first start signal is applied with an on-voltage, the fourth control node is set to the on-voltage of the first voltage through the ninth transistor, and the first start signal is set to the on-voltage of the first voltage through the tenth transistor. 3, the scan driver, the control node is set to the off voltage of the second voltage. According to claim 12,
The second controller outputs the second carry signal based on the clock signal output through the twelfth transistor in the first period and the second voltage output through the thirteenth transistor in the second period. , the scan driving unit. According to claim 13,
The scan driver, wherein the clock signal output in the first period includes a plurality of pulses. According to claim 11,
The tenth transistor includes a pair of sub-transistors connected in series between the third control node and the node;
The second control unit,
The scan driver further comprising a 14th transistor connected between the first voltage input terminal and an intermediate node of the pair of sub-transistors. a pixel unit including a plurality of pixels, each of the plurality of pixels connected to a scan line and a data line; and
A scan driver outputting a scan signal to the scan line of each of the plurality of pixels;
The scan driver includes a plurality of stages,
Each of the plurality of stages,
a first control unit controlling voltage levels of the first control node and the second control node according to the first start signal and the second start signal and outputting a first carry signal;
a second control unit controlling voltage levels of a third control node and a fourth control node according to the first start signal and the second start signal and outputting a second carry signal; and
A pull-up transistor having a gate connected to the first control node and a pull-down transistor having a first gate connected to the third control node, wherein an on-voltage output through the pull-up transistor and an off-voltage output through the pull-down transistor are A display device comprising: an output unit for outputting a scan signal based on According to claim 16,
The display device, wherein the transistors constituting the pixel circuit of each of the pixels and the transistors constituting each of the stages are N-channel oxide thin film transistors. According to claim 16,
A circuit of the first control unit and a circuit of the second control unit are symmetrical with respect to a node to which a terminal for applying an off voltage to the first control unit and the second control unit is connected. According to claim 16,
The pull-up transistor is connected between a first voltage input terminal to which a first voltage of an on voltage is applied and a first output node to which a first output terminal for outputting the scan signal is connected,
The pull-down transistor is connected between a third voltage input terminal to which a third voltage of an off voltage is applied and the first output node. According to claim 16,
The first start signal applied to the first stage is a first scan start signal, the second start signal is an inverted signal of the first start signal,
The first start signal and the second start signal applied to each of the stages subsequent to the first stage are the first carry signal and the second carry signal output from a previous stage.

Images