KR20230083974A - Storage device - Google Patents

Abstract

The storage device includes a plurality of non-volatile memories including an internal temperature sensor; a memory controller communicating with the plurality of nonvolatile memories through a first interface and having a plurality of operation commands defined for each temperature range of the nonvolatile memories; and one or more external temperature sensors communicating with the memory controller through a second interface, wherein the memory controller obtains a temperature value from the one or more external temperature sensors in a first cycle, and transmits a temperature value of the internal temperature sensor to the external temperature sensor. The temperature range of the non-volatile memory is obtained at a second cycle different from the first cycle, and the difference between the temperature value of the at least one external temperature sensor and the temperature value of the internal temperature sensor is equal to or less than a first threshold value, the temperature value of the external temperature sensor Determines a temperature range of the non-volatile memory in which the difference between the temperature values exceeds the first threshold value based on the temperature value of the internal temperature sensor, and determines a target non-volatile memory among the plurality of non-volatile memories. An operation command corresponding to a temperature range of the target nonvolatile memory is provided to the memory from among the plurality of operation commands.

Description

Storage device {STORAGE DEVICE}

The present invention relates to a storage device including a non-volatile memory.

Semiconductor memories are classified into volatile memory devices and non-volatile memory devices. A volatile memory device loses stored data when power is cut off, but a non-volatile memory device can preserve stored data even when power is cut off. Non-volatile memory includes read only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable and programmable ROM (EEPROM), flash memory, phase-change RAM (PRAM), magnetic RAM (MRAM), Resistive RAM (RRAM), Ferroelectric RAM (FRAM), and the like.

Operating characteristics of the non-volatile memory may vary depending on the temperature of the non-volatile memory. Errors may frequently occur in the non-volatile memory when the ideal temperature of the non-volatile memory is different from the temperature in the mounting environment or when the temperature at the time of programming data and the temperature at the time of reading the data are different.

An object of the present invention is to provide a storage device capable of compensating for operating characteristics that vary depending on the temperature of a non-volatile memory.

An object of the present invention is to provide a storage device capable of determining a temperature value of a non-volatile memory while minimizing performance degradation of the storage device.

A storage device according to an embodiment of the present invention includes a plurality of non-volatile memories including an internal temperature sensor; a memory controller communicating with the plurality of nonvolatile memories through a first interface and having a plurality of operation commands defined for each temperature range of the nonvolatile memories; and one or more external temperature sensors communicating with the memory controller through a second interface, wherein the memory controller obtains a temperature value from the one or more external temperature sensors in a first cycle, and transmits a temperature value of the internal temperature sensor to the external temperature sensor. The temperature range of the non-volatile memory is obtained at a second cycle different from the first cycle, and the difference between the temperature value of the at least one external temperature sensor and the temperature value of the internal temperature sensor is equal to or less than a first threshold value, the temperature value of the external temperature sensor Determines a temperature range of the non-volatile memory in which the difference between the temperature values exceeds the first threshold value based on the temperature value of the internal temperature sensor, and determines a target non-volatile memory among the plurality of non-volatile memories. An operation command corresponding to a temperature range of the target nonvolatile memory is provided to the memory from among the plurality of operation commands.

A storage device according to an embodiment of the present invention includes a plurality of non-volatile memories including an internal temperature sensor; and a memory controller that controls the plurality of nonvolatile memories and has a plurality of operation commands defined for each temperature section of the nonvolatile memories, wherein the memory controller refers to the temperature value of the internal temperature sensor to determine the temperature of the nonvolatile memories. determine the temperature range of each of the non-volatile memories, periodically monitor the input/output workload of each of the non-volatile memories, and the internal temperature sensor of the first non-volatile memory when the amount of the input/output workload exceeds the predetermined range in a predetermined time period The temperature range of the first nonvolatile memory is updated with reference to, and an operation command corresponding to the temperature range of the target nonvolatile memory among the plurality of operation commands is sent to a target nonvolatile memory among the plurality of nonvolatile memories. to provide.

A storage device according to an embodiment of the present invention includes a plurality of non-volatile memories; a memory controller that controls the plurality of nonvolatile memories and has a plurality of operation commands defined for each temperature range of the nonvolatile memories; and providing a Command Latch Enable (CLE) signal and an Address Latch Enable (ALE) signal output from the memory controller to one of the plurality of non-volatile memories, and a data signal between the memory controller and the plurality of non-volatile memories. and a channel through which the CLE signal is enabled, wherein the memory controller controls a temperature range in which a temperature value of a target nonvolatile memory among the plurality of nonvolatile memories among the plurality of operation commands belongs in a first time period during which the CLE signal is enabled. A data signal including a corresponding operation command is provided to the target nonvolatile memory, a data signal including a real address is provided to the target nonvolatile memory during a second time period during which the ALE signal is enabled, and the CLE signal A data signal including a confirm command is provided to the target nonvolatile memory during a third time period in which is enabled.

The storage device according to an embodiment of the present invention may compensate for operating characteristics that vary depending on the temperature of the nonvolatile memory by defining an operation command for each temperature range of the nonvolatile memory.

In a storage device according to an embodiment of the present invention, a time for transmitting a separate operating parameter is reduced by allowing a memory controller to provide an operation command determined according to an operation period to which a temperature value of the non-volatile memory belongs to the non-volatile memory. savings can be made

In the storage device according to an embodiment of the present invention, an input/output burden for a memory controller to refer to a temperature sensor inside a non-volatile memory to determine a temperature value of the non-volatile memory can be reduced, thereby minimizing performance degradation of the storage device. can

The problems to be solved by the present invention are not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the description below.

1 is a block diagram illustrating a storage device according to an exemplary embodiment of the present invention.
2 to 4 are diagrams for explaining a non-volatile memory in more detail.
5 is a diagram for explaining a read voltage compensated according to a current temperature of a nonvolatile memory.
6 is a diagram for explaining in detail a channel connecting a memory controller and a nonvolatile memory.
7A and 7B are timing diagrams illustrating a command transmission method according to a comparative example and an embodiment of the present invention.
8A and 8B are diagrams illustrating operation commands according to an embodiment of the present invention.
9 is a diagram illustrating a temperature range for each nonvolatile memory according to an embodiment of the present invention.
10 to 12 are flowcharts illustrating operations of a storage device according to example embodiments.
13 and 14 are diagrams illustrating the structure of a storage device according to an embodiment of the present invention.
15 are diagrams illustrating a system to which a storage device according to an embodiment of the present invention is applied.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

1 is a block diagram illustrating a storage device according to an exemplary embodiment of the present invention.

Referring to FIG. 1 , a storage device 100 may include a memory controller 110 , a memory device 120 , an external temperature sensor 130 , a first interface 101 and a second interface 102 . The memory controller 110 and the memory device 120 may be connected through the first interface 101 . Also, the memory controller 110 and the external temperature sensor 130 may be connected through the second interface 102 .

The memory device 120 may include a plurality of non-volatile memories NVM11 to NVM24. Each of the nonvolatile memories NVM11 to NVM24 may be connected to one of the plurality of channels CH1 and CH2 through a corresponding way. For example, the non-volatile memories NVM11-NVM14 are connected to the first channel CH1 through ways W11-W14, and the non-volatile memories NVM21-NVM24 are connected to ways W21-W24. It can be connected to the second channel (CH2) through. In an exemplary embodiment, each of the nonvolatile memories NVM11 to NVM24 may be implemented as an arbitrary memory unit capable of operating according to individual commands from the memory controller 110 . For example, each of the nonvolatile memories NVM11 to NVM24 may be implemented as a chip or die, but the present invention is not limited thereto. Also, the number of channels included in the storage device 100 and the number of non-volatile memories connected to each channel are not limited.

The memory controller 110 may transmit and receive signals to and from the memory device 120 through a plurality of channels CH1 and CH2. For example, the memory controller 110 may transmit commands, addresses, and data to the memory device 120 or receive data from the memory device 120 through channels CH1 and CH2 .

The memory controller 110 may select one of the nonvolatile memories (NVM11 to NVM24) connected to the corresponding channel through each channel and transmit/receive signals with the selected nonvolatile memory. For example, the memory controller 110 may select the nonvolatile memory NVM11 among the nonvolatile memories NVM11 to NVM24 connected to the first channel CH1 . The memory controller 110 may transmit commands, addresses, and data to the selected non-volatile memory NVM11 or receive data from the selected non-volatile memory NVM11 through the first channel CH1.

The memory controller 110 may transmit and receive signals to and from the memory device 120 in parallel through different channels. For example, while transmitting a command to the memory device 120 through a first channel CH1 , the memory controller 110 may transmit another command to the memory device 120 through a second channel CH2 . For example, while receiving data from the memory device 120 through a first channel CH1, the memory controller 110 may receive other data from the memory device 120 through a second channel CH2. there is.

Each of the non-volatile memories connected to the memory controller 110 through the same channel may perform internal operations in parallel. For example, the memory controller 110 may sequentially transmit commands and addresses to the nonvolatile memories NVM11 to NVM14 through the first channel CH1. When a command and an address are transmitted to the nonvolatile memories NVM11 to NVM14, each of the nonvolatile memories NVM11 to NVM14 may perform an operation according to the command in parallel.

The memory controller 110 may control overall operations of the memory device 120 . The memory controller 110 may control each of the nonvolatile memories NVM11 to NVM24 connected to the channels CH1 and CH2 by transmitting signals to the channels CH1 and CH2. For example, the memory controller 110 may control a selected one of the nonvolatile memories NVM11 to NVM14 by transmitting a command and an address through the first channel CH1.

Each of the nonvolatile memories NVM11 to NVM24 may operate in response to control of the memory controller 110 . For example, the nonvolatile memory NVM11 may program data according to a command and an address provided through the first channel CH1. For example, the nonvolatile memory NVM21 may read data according to a command and an address provided through the second channel CH2 and transmit the read data to the memory controller 110 .

The nonvolatile memories NVM11 to NVM24 may have different operating characteristics according to temperature values of the nonvolatile memories NVM11 to NVM24. For example, even if a program operation is performed on memory cells using the same operating parameters for the nonvolatile memories (NVM11 to NVM24), the threshold voltage distributions of the memory cells are different from those of the nonvolatile memories (NVM11 to NVM24) during the program operation. may vary depending on the temperature value of In addition, even if a read operation is performed on memory cells having the same threshold voltage using the same operating parameter for the nonvolatile memories (NVM11 to NVM24), the temperature value at the time of the program operation of the nonvolatile memories (NVM11 to NVM24) A read operation result may vary according to a difference in temperature value during the read operation.

If the operating characteristics of the nonvolatile memories (NVM11 to NVM24) can be compensated according to the temperature values of the nonvolatile memories (NVM11 to NVM24) measured by the temperature sensor when a program operation or a read operation is performed on the nonvolatile memories (NVM11 to NVM24), the nonvolatile memory Error occurrence of NVM11-NVM24 may be reduced. Each of the non-volatile memories NVM11-NVM24 may include an internal temperature sensor NTS, and the temperature measured by the internal temperature sensor NTS is used to determine the temperature value of the non-volatile memories NVM11-NVM24. can be used

Meanwhile, if a large amount of communication is induced between the memory controller 110 and the memory device 120 to compensate for the operating characteristics of the non-volatile memories NVM11 to NVM24 according to temperature values, the performance of the storage device 100 may deteriorate. can For example, the memory controller 110 uses the channels CH1 and CH2 to acquire the temperature values of the nonvolatile memories NVM11 to NVM24 measured by the internal temperature sensor NTS. (NVM11-NVM24). Also, when the memory controller 110 transmits commands and addresses to the nonvolatile memories NVM11-NVM24 through the channels CH1 and CH2, an operation determined according to the temperature values of the nonvolatile memories NVM11-NVM24. Parameters may need to be sent together. The processing time for the command may be delayed by the time required to transmit the temperature value and the operating parameters through the channels CH1 and CH2. That is, the processing time for the command requested by the memory controller 110 may be delayed by the time during which the channels CH1 and CH2 are occupied for transmitting the temperature value and operating parameters.

Accordingly, the storage device 100 is required to be able to compensate operating characteristics according to temperature values of the nonvolatile memories NVM11 to NVM24 while minimizing performance degradation.

According to an embodiment of the present invention, different operation commands may be defined for each temperature range. Among the operation commands, the memory controller 110 may provide an operation command determined according to a temperature range to which a temperature value of the target non-volatile memory to which a command operation is to be instructed belongs to the target non-volatile memory. The target nonvolatile memory may perform a command operation using different operating parameters according to the operation command. According to an embodiment of the present invention, when the memory controller 110 transmits an operating command, separate operating parameters may not be transmitted according to the current temperature, and thus the command processing time may be reduced.

According to an embodiment of the present invention, the storage device 100 may include an external temperature sensor 130 located outside the nonvolatile memories NVM11 to NVM24. In order for the memory controller 110 to obtain a temperature value from the internal temperature sensor NTS, it may need to communicate with the non-volatile memory through a channel. While the memory controller 110 acquires a temperature value from the nonvolatile memory through a channel, performance of the storage device 100 may be degraded because signals cannot be transmitted and received to and from the nonvolatile memory.

On the other hand, the memory controller 110 may obtain a temperature value from the external temperature sensor 130 through the second interface 102 separate from the channel. For example, the second interface 102 may transmit and receive signals between the memory controller 110 and the external temperature sensor 130 through inter-integrated circuit (I2C) communication. Since the memory controller 110 can transmit/receive signals to and from the non-volatile memory even while acquiring the temperature value from the external temperature sensor 130, acquiring the temperature value from the external temperature sensor 130 is may have little effect on performance.

According to an embodiment of the present invention, the memory controller 110 estimates the temperature values of the non-volatile memories NVM11 to NVM24 based on the temperature values of the external temperature sensor 130 or the memory controller 110 and the non-volatile memories. Temperature values of the non-volatile memories NVM11 to NVM24 may be estimated based on an input/output workload between the memories NVM11 to NVM24. The performance of the storage device 100 is improved because the time required to acquire the temperature values of the nonvolatile memories NVM11 to NVM24 from the internal temperature sensor NTS through the channels CH1 to CH2 can be reduced. It can be.

2 to 4 are diagrams for explaining a non-volatile memory in more detail.

2 is an exemplary block diagram illustrating a non-volatile memory. Referring to FIG. 2 , the nonvolatile memory 300 may include a control logic circuit 320, a memory cell array 330, a page buffer 340, a voltage generator 350, and a row decoder 360. . Although not shown in FIG. 2 , the nonvolatile memory 300 may further include a memory interface circuit for receiving a command CMD and an address ADDR from the outside and exchanging data DATA with the outside. Column logic, a pre-decoder, a temperature sensor, a command decoder, an address decoder, and the like may be further included.

The control logic circuit 320 may generally control various operations within the nonvolatile memory 300 . The control logic circuit 320 may output various control signals in response to the command CMD and/or the address ADDR from the memory interface circuit 310 . For example, the control logic circuit 320 may output a voltage control signal CTRL_vol, a row address X-ADDR, and a column address Y-ADDR.

The memory cell array 330 may include a plurality of memory blocks BLK1 to BLKz (where z is a positive integer), and each of the plurality of memory blocks BLK1 to BLKz may include a plurality of memory cells. there is. The memory cell array 330 may be connected to the page buffer unit 340 through bit lines BL, and may include word lines WL, string select lines SSL, and ground select lines GSL. It can be connected to the row decoder 360 through

In an exemplary embodiment, the memory cell array 330 may include a 3D memory cell array, and the 3D memory cell array may include a plurality of NAND strings. Each NAND string may include memory cells respectively connected to word lines vertically stacked on a substrate. U.S. Patent Publication No. 7,679,133, U.S. Patent Publication No. 8,553,466, U.S. Patent Publication No. 8,654,587, U.S. Patent Publication No. 8,559,235, and U.S. Patent Application Publication No. 2011/0233648 are incorporated herein by reference. are combined In an exemplary embodiment, the memory cell array 330 may include a 2D memory cell array, and the 2D memory cell array may include a plurality of NAND strings disposed along row and column directions.

The page buffer 340 may include a plurality of page buffers PB1 to PBn (n is an integer greater than or equal to 3), and the plurality of page buffers PB1 to PBn may include a plurality of bit lines BL. Each of the memory cells may be connected. The page buffer 340 may select at least one bit line from among the bit lines BL in response to the column address Y-ADDR. The page buffer 340 may operate as a write driver or a sense amplifier according to an operation mode. For example, during a program operation, the page buffer 340 may apply a bit line voltage corresponding to data to be programmed to a selected bit line. During a read operation, the page buffer 340 may detect data stored in a memory cell by sensing a current or voltage of a selected bit line.

The voltage generator 350 may generate various types of voltages for performing program, read, and erase operations based on the voltage control signal CTRL_vol. For example, the voltage generator 350 may generate a program voltage, a read voltage, a program verify voltage, an erase voltage, and the like as the word line voltage VWL.

The row decoder 360 may select one of the plurality of word lines WL and select one of the plurality of string select lines SSL in response to the row address X-ADDR. For example, during a program operation, the row decoder 360 may apply a program voltage and a program verify voltage to the selected word line, and during a read operation, may apply a read voltage to the selected word line.

3 is a diagram for explaining a 3D V-NAND structure applicable to a storage device according to an embodiment of the present invention. When the non-volatile memory of the storage device is implemented as a 3D V-NAND type flash memory, each of a plurality of memory blocks constituting the non-volatile memory may be expressed as an equivalent circuit as shown in FIG. 3 .

The memory block BLKi shown in FIG. 3 represents a three-dimensional memory block formed in a three-dimensional structure on a substrate. For example, a plurality of memory NAND strings included in the memory block BLKi may be formed in a direction perpendicular to the substrate.

Referring to FIG. 3 , the memory block BLKi may include a plurality of memory NAND strings NS11 to NS33 connected between the bit lines BL1 , BL2 , and BL3 and the common source line CSL. Each of the plurality of memory NAND strings NS11 to NS33 may include a string select transistor SST, a plurality of memory cells MC1, MC2, ..., MC8, and a ground select transistor GST. 3 illustrates that each of the plurality of memory NAND strings NS11 to NS33 includes eight memory cells MC1, MC2, ..., MC8, but is not necessarily limited thereto.

The string select transistor SST may be connected to corresponding string select lines SSL1 , SSL2 , and SSL3 . The plurality of memory cells MC1 , MC2 , ..., MC8 may be connected to corresponding gate lines GTL1 , GTL2 , ... , and GTL8 , respectively. The gate lines GTL1 , GTL2 , ..., GTL8 may correspond to word lines, and some of the gate lines GTL1 , GTL2 , ... , GTL8 may correspond to dummy word lines. The ground select transistor GST may be connected to corresponding ground select lines GSL1 , GSL2 , and GSL3 . The string select transistor SST may be connected to corresponding bit lines BL1 , BL2 , and BL3 , and the ground select transistor GST may be connected to the common source line CSL.

Word lines (eg, WL1) having the same height may be commonly connected, and ground select lines GSL1, GSL2, and GSL3 and string select lines SSL1, SSL2, and SSL3 may be separated from each other. 3 shows that the memory block BLKi is connected to eight gate lines GTL1, GTL2, ..., GTL8 and three bit lines BL1, BL2, BL3, but is not necessarily limited thereto. no.

The memory block BLKi may have different bit densities according to the number of bits stored in the memory cells included in the memory block BLKi.

4 is a graph for explaining threshold voltage distributions of a memory cell.

Due to minute differences in electrical characteristics between a plurality of memory cells, the threshold voltage of each memory cell programmed with the same data forms a threshold voltage distribution within a certain range. 4 illustrates a threshold voltage distribution that memory cells may have when the memory cells are triple level cells (TLCs) that store 3-bit data. Referring to FIG. 4 , the horizontal axis of the graph represents the magnitude of the threshold voltage, and the vertical axis represents the number of memory cells.

The memory cell may have a threshold voltage corresponding to one of the erase state E and the first to seventh program states P1 to P7. The first to seventh read voltages Vc1 to Vc7 may be read voltages for distinguishing respective states. For example, when a first read voltage Vc1 is applied to a word line to which memory cells are connected, a current having a lower threshold voltage than the first read voltage Vc1 may flow smoothly to a bit line to which the first memory cells are connected. there is. That is, the first memory cells may be read on-cell. On the other hand, current may not flow in the bit line to which the second memory cells having a threshold voltage higher than the first read voltage Vc1 are connected. That is, the second memory cells may be read as off cells.

When the first read voltage Vc1 is applied to the memory cells, the erase state E and other states can be distinguished. Similarly, when the second to seventh read voltages Vc2 to Vc7 are further applied, both the erase state E and the program states P1 to P7 can be distinguished.

Meanwhile, operating characteristics of memory cells may vary depending on the temperature of the nonvolatile memory. For example, when a read voltage having the same level is applied to a word line in order to read memory cells having the same threshold voltage, a higher amount of current may flow through the bit line as the temperature of the nonvolatile memory increases. . Such a change in operating characteristics may affect a read operation result of the non-volatile memory, and may also affect a program operation result accompanying a verify operation performed in a similar manner to the read operation.

5 is a diagram for explaining a read voltage compensated according to a current temperature of a nonvolatile memory.

Referring to FIG. 5 , the horizontal axis of the graph represents the magnitude of the threshold voltage, and the vertical axis represents the number of memory cells. 5 illustrates a default level of a read voltage Vc for distinguishing two arbitrary threshold voltage states PA and PB adjacent to each other and threshold voltage states PA and PB.

If the temperature of the nonvolatile memory is higher than the default temperature, a larger amount of current may flow through the bit line, and memory cells having a threshold voltage higher than the default level of the read voltage Vc may be incorrectly read as on-cell. Accordingly, when the temperature of the nonvolatile memory is higher than the default temperature, operating characteristics that vary depending on the temperature of the nonvolatile memory may be compensated for by applying the read voltage Vc to which the first offset O1 is reflected at the default level. On the other hand, if the temperature of the non-volatile memory is lower than the default temperature, a smaller amount of current may flow through the bit line, and memory cells having a threshold voltage lower than the default level of the read voltage Vc may be incorrectly read as off cells. . Accordingly, when the temperature of the non-volatile memory is lower than the default temperature, operating characteristics may be compensated by applying the read voltage Vc to which the second offset O2 is reflected at the default level.

According to an embodiment of the present invention, operation commands that vary according to a temperature range may be defined. The memory controller may transmit an operation command corresponding to a temperature range to which a temperature value of the target nonvolatile memory belongs to the target nonvolatile memory. The target nonvolatile memory may perform an operation using different operating parameters according to temperature by interpreting the operating command. Accordingly, operating characteristics of the non-volatile memory that vary depending on temperature can be compensated for. For example, memory cells of a nonvolatile memory may have a uniform threshold voltage distribution regardless of a temperature at which memory cells are programmed. Also, when the memory controller instructs a read operation to the target nonvolatile memory, the temperature of the nonvolatile memory when the memory cells are read, instead of calculating the difference between the temperature when the memory cells are programmed and the temperature when the memory cells are read each time. Data can be read without error by transmitting the operation command determined based on the target non-volatile memory to the target non-volatile memory.

Hereinafter, a method of transmitting an operation command to a non-volatile memory by a memory controller according to an embodiment of the present invention will be described in detail with reference to FIGS. 6 to 8B.

6 is a diagram for explaining in detail a channel connecting a memory controller and a nonvolatile memory.

Referring to FIG. 6 , the storage device 100 may include a memory controller 110 , a target nonvolatile memory 121 and a channel CH. The memory controller 110 of FIG. 6 may correspond to the memory controller 110 described with reference to FIG. 1 . Also, the target nonvolatile memory 121 of FIG. 6 is a nonvolatile memory to which the memory controller 110 intends to instruct an operation, and may correspond to any one of the nonvolatile memories NVM11 to NVM24 of FIG. 1 . . Also, the channel CH of FIG. 6 may correspond to any one of the channels CH1 and CH2 of FIG. 1 .

The memory controller 110 may include eleventh to fourteenth pins P11 to P14. The target nonvolatile memory 121 may include twenty-first to twenty-fourth pins P21 to P24. The 11th to 14th pins P11 to P14 and the 21st to 24th pins P21 to P24 may correspond to each other. The memory controller 110 and the target nonvolatile memory 121 may transmit and receive signals through the 11th to 14th pins P11 to P14 and the 21st to 24th pins P21 to P24.

The memory controller 110 transmits a command latch enable (CLE) signal, an address latch enable (ALE) signal, and a write enable (nWE) signal to the target nonvolatile memory 121 through eleventh to thirteenth pins P11 to P13. can transmit The memory controller 110 transmits the data signal DQ[7:0] to the target nonvolatile memory 121 through the fourteenth pin P14 or transmits the data signal DQ from the target nonvolatile memory 121. [7:0]) can be received.

The target nonvolatile memory 121 may receive the CLE signal, the ALE signal, and the nWE signal from the memory controller 110 through the twenty-first to twenty-third pins P21 to P23. The target nonvolatile memory 121 receives the data signal DQ[7:0] from the memory controller 110 through the 24th pin P24 or the data signal DQ[7:0] to the memory controller 110. ]) can be transmitted. The command CMD, address ADDR, and data DATA may be transferred through the data signal DQ[7:0]. The data signal DQ[7:0] may be transmitted through a plurality of data signal lines. In this case, the twenty-fourth pin P24 may include a plurality of pins corresponding to a plurality of data signal lines.

The target nonvolatile memory 121 receives a command CMD from a data signal DQ[7:0] received in an enable period of the CLE signal (eg, a high level state) based on the toggle timings of the nWE signal. can be obtained. The target nonvolatile memory 121 receives the address ADDR from the data signal DQ[7:0] received during the enable period of the ALE signal (eg, high level state) based on the toggle timings of the nWE signal. can be obtained.

In an exemplary embodiment, the nWE signal can toggle between a high level and a low level while maintaining a fixed state (eg, high level or low level). For example, the nWE signal may toggle in a section in which a command CMD or an address ADDR is transmitted. Accordingly, the target nonvolatile memory 121 may obtain the command CMD or the address ADDR based on the toggle timings of the nWE signal.

The memory controller 110 may transmit the data signal DQ[7:0] including the command CMD or the address ADDR to the target nonvolatile memory 121 together with the nWE signal for toggling. As the CLE signal having an enable state is transmitted, the memory controller 110 transmits the data signal DQ[7:0] including the command CMD to the target nonvolatile memory 121, and transmits the enable signal to the target nonvolatile memory 121. As the ALE signal having is transmitted, the data signal DQ[7:0] including the address ADDR may be transmitted to the target nonvolatile memory 121 .

7A and 7B are timing diagrams illustrating a command transmission method according to a comparative example and an embodiment of the present invention.

7A shows a command transmission method according to a comparative example different from the embodiment of the present invention. According to the comparative example, the memory controller 110 may obtain a temperature value from the target nonvolatile memory 121 and then determine an operating parameter based on the temperature value. Also, the memory controller 110 may provide operation parameters together with commands and addresses to the target nonvolatile memory 121 . The timing diagram of FIG. 7A shows timing at which the memory controller 110 provides commands, addresses, and operation parameters to the target nonvolatile memory 121 .

Referring to FIG. 7A , the memory controller 110 sends a data signal (DQ[7:0) including an operation command OPCMD to the target nonvolatile memory 121 in a first time period PR1 in which the CLE signal is enabled. ]) can be transmitted. For example, the operation command OPCMD may be one of a program command, a read command, and an erase command.

The memory controller 110 may transmit the data signal DQ[7:0] including the real address to the target nonvolatile memory 121 in the second time period PR2 when the ALE signal is enabled. For example, the real address may be transmitted over 5 clock cycles and may include column addresses C1 and C2 and row addresses R1-R3.

The memory controller 110 transmits the data signal DQ[7:0] including the operation parameters Z1-Z10 to the target nonvolatile memory 121 in the third time period PR3 when the ALE signal is enabled. can When the operation command CMD is a read command, the operation parameters Z1 to Z10 may include offset levels of read voltages.

The memory controller 110 may transmit the data signal DQ[7:0] including the confirm command CFCMD to the target nonvolatile memory 121 during the fourth time period PR4 when the CLE signal is enabled. The confirm command CFCMD may be a command for notifying the target nonvolatile memory 121 that all real addresses and operation parameters related to the operation command OPCMD have been transmitted.

The target nonvolatile memory 121 samples the data signal DQ[7:0] at the rising edges of the nWE signal to generate an operation command OPCMD, real addresses C1, C2, R1-R3, and an operation parameter Z1. -Z10) and confirm command (CFCMD). The operation command OPCMD may include signal values of the data signal DQ[7:0] at the first time point t1. The real addresses C1, C2, and R1-R3 may include signal values of the data signal DQ[7:0] at the second to sixth points in time t2 to t6. The operating parameters Z1 to Z10 may include signal values of the data signal DQ[7:0] at the seventh to sixteenth time points t7 to t16. Also, the confirm command CFCMD may include signal values of the data signal DQ[7:0] at the seventeenth time point t17.

When the target nonvolatile memory 121 obtains the confirm command CFCMD, it sets the operation parameters of the operation command OPCMD based on the operation parameters Z1 to Z10 previously received, and the real addresses C1, C2, and R1. For -R3), the operation indicated by the operation command (OPCMD) can be performed.

According to the comparative example, the memory controller 110 may compensate for the temperature-dependent operating characteristics of the target non-volatile memory 121 by transmitting operating parameters Z1 to Z10 according to the temperature of the target non-volatile memory 121 . . When the memory controller 110 transmits the operating parameters Z1 to Z10 separately, it may take an additional time corresponding to 10 clock cycles to transmit a command to the target nonvolatile memory 121 . When the memory controller 110 sequentially transmits a plurality of commands to a plurality of nonvolatile memories connected to one channel, the command transmission time may be further delayed.

7B shows a command transmission method according to an embodiment of the present invention. According to an embodiment of the present invention, the memory controller 110 does not acquire a temperature value from the target nonvolatile memory 121 every time, and monitors the external temperature sensor 130 or the input/output workload of the target nonvolatile memory 121. A temperature value of the target non-volatile memory 121 may be determined by using. Also, the memory controller 110 may determine an operation command corresponding to a temperature range to which the temperature value of the target nonvolatile memory 121 belongs, and provide the operation command and address to the target nonvolatile memory 121 .

The timing diagram of FIG. 7B shows timing at which the memory controller 110 provides operation commands and addresses to the target nonvolatile memory 121 . A method of determining the temperature value of the target nonvolatile memory 121 by the memory controller 110 will be described in detail with reference to FIGS. 10 to 12 .

Referring to FIG. 7B , the memory controller 110 sends a data signal (DQ[7:0) including an operation command OPCMD to the target nonvolatile memory 121 in a first time period PR1 in which the CLE signal is enabled. ]) can be transmitted. The operation command OPCMD may indicate one of a program operation, a read operation, and an erase operation within a temperature range to which the temperature value of the target nonvolatile memory 121 belongs. Even commands for instructing the same type of operation may have different signal values according to temperature ranges.

The memory controller 110 may transmit the data signal DQ[7:0] including the real address to the target nonvolatile memory 121 in the second time period PR2 when the ALE signal is enabled. For example, the real address may be transmitted over 5 clock cycles and may include column addresses C1 and C2 and row addresses R1-R3.

The memory controller 110 may transmit the data signal DQ[7:0] including the confirm command CFCMD to the target nonvolatile memory 121 during the third time period PR3 when the CLE signal is enabled.

The target nonvolatile memory 121 samples the data signal DQ[7:0] at rising edges of the nWE signal to generate an operation command OPCMD, real addresses C1, C2, R1-R3, and a confirm command CFCMD. ) can be obtained. The operation command OPCMD may include signal values of the data signal DQ[7:0] at the first time point t1. The real addresses C1, C2, and R1-R3 may include signal values of the data signal DQ[7:0] at the second to sixth points in time t2 to t6. Also, the confirm command CFCMD may include signal values of the data signal DQ[7:0] at the seventh time point t7.

When the target nonvolatile memory 121 obtains the confirm command CFCMD, the type of operation defined by the operation command OPCMD is performed according to the operation parameter defined by the operation command OPCMD, and the real addresses C1 and C2 , R1-R3).

According to an embodiment of the present invention, the memory controller 110 may transmit an operating command for which operating characteristics according to temperature may be compensated for to the target nonvolatile memory 121 within one clock cycle. Comparing the comparative example with the embodiment of the present invention, time corresponding to 10 clock cycles can be saved to transmit one command. Accordingly, command processing time may be reduced, and performance of the storage device 100 may be improved.

8A and 8B are diagrams illustrating operation commands according to an embodiment of the present invention.

8A illustrates a first example of operation commands for each temperature range defined in each operation type. Referring to FIG. 8A , the operation type may include a program operation, a read operation, and an erase operation. And, the temperature range may include the first to fifth temperature ranges R1 to R5. For each of the program operation, read operation, and erase operation, operation commands corresponding to the first to fifth temperature ranges R1 to R5 may be defined.

Values such as '61h', '81h', and '01h' exemplified for each operation type and temperature range in FIG. Indicates a command to be transmitted to the volatile memory 121. For example, if the memory controller 110 instructs a read operation when the current temperature of the target nonvolatile memory 121 is '-5°C', the enable period of the CLE signal includes '-5°C'. A value of '81h' corresponding to one temperature range R1 may be transmitted to the target nonvolatile memory 121 as an operation command OPCMD.

When receiving a command from the memory controller 110, the target nonvolatile memory 121 may set an operating parameter corresponding to an operation command indicated by the command and perform an operation defined in the operation command. For example, the target nonvolatile memory 121 may perform a read operation by applying read voltages having different levels when receiving the command '81h' and when receiving the command '82h'.

Meanwhile, referring to FIG. 8A , a default command may be determined among operation commands defined for each operation type. The default command is a command that can be transmitted to the target nonvolatile memory 121 to indicate each type of operation when the memory controller 110 cannot or does not determine the temperature value of the target nonvolatile memory 121. can refer to Default commands may be defined in advance. 8A illustrates a case where '60h', '80h', and '00h', which are commands corresponding to the fourth temperature range R4, are set as default commands.

According to an embodiment of the present invention, a default command may be set according to a request of a host. For example, the host may provide the average external temperature value of the storage device 100 to the storage device 100 through an interface for communication with the storage device 100 . The storage device 100 may set commands in the temperature range including the average external temperature value as default commands. When the storage device 100 is mounted in a fixed location, such as a server, the temperature of the storage device 100 may be maintained within a certain range. When a default command is set based on an external temperature value, the memory controller 110 may compensate for operating characteristics of the nonvolatile memory according to temperature even when the temperature value of the target nonvolatile memory 121 cannot be determined. Accordingly, reliability of the storage device 100 may be improved.

8A illustrates a case in which the same number of operation commands are defined in advance for each operation type. However, the present invention is not limited thereto. 8B illustrates a second example of operation commands for each temperature range defined in each operation type.

Referring to FIG. 8B , a case in which different numbers of operation commands are defined for a program operation, a read operation, and an erase operation is exemplified. For example, a difference in operating characteristics of a nonvolatile memory according to temperature may have a greater effect on a read operation than a program operation. In the example of FIG. 8B , operation parameters for read operation are further refined by defining only two commands, '61h' and '60h', as operation commands for program operation and 5 commands as operation commands for read operation. can be adjusted accordingly.

Meanwhile, the nonvolatile memories (NVM11 to NVM24) included in the storage device 100 may have different temperatures. For example, a nonvolatile memory disposed outside the storage device 100 may have a relatively low temperature since heat may be rapidly discharged compared to a nonvolatile memory disposed inside the storage device 100 .

According to an embodiment of the present invention, the memory controller 110 can effectively compensate for operating characteristics of each non-volatile memory by determining a temperature value for each of the non-volatile memories (NVM11 to NVM24).

9 is a diagram illustrating a temperature range for each nonvolatile memory according to an embodiment of the present invention.

The memory controller 110 may store temperature information for each of the nonvolatile memories NVM11 to NVM24. 9 illustrates a case in which the memory controller 110 manages a temperature range to which temperature values of the nonvolatile memories NVM11 to NVM24 belong in a table format. The memory controller 110 obtains a temperature range of the target nonvolatile memory by referring to the table to provide an operation command to the target nonvolatile memory, and provides an operation command corresponding to the temperature range to the target nonvolatile memory. can do.

Meanwhile, temperatures of the non-volatile memories NVM11 to NVM24 may vary according to time. In order for the memory controller 110 to obtain a temperature value from the internal temperature sensor NTS of each of the nonvolatile memories NVM11 to NVM24, it must communicate with the nonvolatile memories NVM11 to NVM24 through channels CH1 and CH2. can do. Since the memory controller 110 cannot perform input/output of signals different from those of the non-volatile memories NVM11-NVM24 while acquiring the temperature value, the memory controller 110 acquiring the temperature value at too frequent cycles may cause the storage device ( 100) may cause performance degradation.

Hereinafter, various methods for the memory controller 110 to determine temperature values of the nonvolatile memories NVM11 to NVM24 according to example embodiments will be described with reference to FIGS. 10 to 12 .

10 to 12 are flowcharts illustrating operations of a storage device according to example embodiments.

10 illustrates an operation of a storage device according to a first embodiment of the present invention.

In step S11, the memory controller may determine a temperature range for each nonvolatile memory (NVM). For example, the memory controller may obtain a temperature value from an internal temperature sensor of the nonvolatile memories (NVM), and determine a temperature range to which the temperature value belongs as a temperature range for each nonvolatile memory (NVM).

In step S12, the memory controller may monitor the input/output workload for each non-volatile memory (NVM).

As a first example, the memory controller may monitor a degree of wearout of each non-volatile memory (NVM) in a predetermined time period. Here, the degree of wear may be at least one of a program/erase (P/E) cycle of memory blocks included in the non-volatile memory, an erase count of the memory blocks, and the number of pages programmed in the non-volatile memory. . The P/E cycle may refer to an average value of the number of times that memory blocks included in the non-volatile memory (NVM) are programmed and erased.

As a second example, the memory controller may monitor the amount of data read from each non-volatile memory (NVM) in a predetermined time period.

In step S13, the memory controller may detect the non-volatile memory (NVM) in which the amount of input/output workload exceeds a predetermined range. It can be predicted that a lot of heat will be generated in the non-volatile memory (NVM) where the amount of I/O workload is greater than the specified range, and the temperature of the non-volatile memory (NVM) where the amount of I/O workload is less than the specified range is expected to drop. can On the other hand, it can be predicted that the temperature of the non-volatile memory (NVM), where the amount of I/O workload falls within the specified range, will be maintained at a similar level to the previous one. Accordingly, the memory controller transmits/receives a signal for obtaining a temperature value from an internal temperature sensor of the non-volatile memory (NVM) by maintaining the current temperature range of the non-volatile memory (NVM) within a predetermined range of the amount of input/output workload without updating. can save time

In step S14, the memory controller may update the current temperature range of the detected non-volatile memory (NVM). For example, the memory controller may obtain a temperature value from an internal temperature sensor of the detected nonvolatile memory (NVM), and determine a temperature range to which the temperature value belongs as the detected temperature range of the nonvolatile memory (NVM). there is.

In step S15 , the memory controller may provide an operation command corresponding to a temperature range of the target nonvolatile memory (NVM) to the target nonvolatile memory (NVM).

According to the first embodiment of the present invention, the time required for the memory controller to acquire the temperature from the internal temperature sensor through the channel to update the temperature range can be reduced. Accordingly, the memory controller can compensate for the operating characteristics of the non-volatile memory (NVM) according to the temperature while minimizing the transmission/reception time required for the channel to determine the temperature range.

11 illustrates an operation of a storage device according to a second embodiment of the present invention.

In step S21, the memory controller may determine a temperature range for each nonvolatile memory (NVM). For example, the memory controller may determine a temperature range for each nonvolatile memory (NVM) based on a temperature value from an internal temperature sensor of the nonvolatile memory (NVM).

In step S22, the memory controller may acquire temperature values from the plurality of external temperature sensors EST. Depending on implementation, the memory controller may obtain temperature values from a plurality of external temperature sensors EST disposed at different locations in the storage device. Meanwhile, the memory controller may obtain temperature values from the external temperature sensors EST through an interface separate from channels connected to the nonvolatile memories NVM.

In step S23, the memory controller may determine whether a temperature difference between the external temperature sensors (ETS) exceeds a threshold value. When the difference between the temperature values of the external temperature sensors (ETS) disposed at different locations exceeds a critical value, it may be predicted that a sudden temperature change occurs in the storage device. On the other hand, when the difference between the temperature values does not exceed the threshold value, it may be predicted that the temperature of the storage device is maintained relatively constant.

When the temperature difference exceeds the threshold value (Yes in step S23), the memory controller may update the temperature range for each nonvolatile memory (NVM). For example, the memory controller may determine a temperature range for each nonvolatile memory (NVM) based on a temperature value from an internal temperature sensor of the nonvolatile memory (NVM).

On the other hand, if the difference between the temperature values does not exceed the threshold value (“No” in step S23), the memory controller may use the previously determined temperature range as it is without updating the temperature range for each non-volatile memory (NVM). there is.

In step S26 , the memory controller may provide an operation command corresponding to a temperature range of the target nonvolatile memory (NVM) to the target nonvolatile memory (NVM).

According to the second embodiment of the present invention, when it is predicted that there is no sudden change in the temperature of the storage device, the update of the temperature range of the non-volatile memory (NVM) may be omitted. Accordingly, the memory controller can compensate for the temperature-dependent operating characteristics of the non-volatile memory (NVM) while minimizing the transmission/reception time required for the channel to determine the temperature range of the non-volatile memory (NVM).

12 illustrates an operation of a storage device according to a third embodiment of the present invention.

In step S31 , the memory controller may obtain a temperature value of the external temperature sensor ETS in a first cycle.

In step S32 , the memory controller may obtain the temperature value of the internal temperature sensor (NTS) for each nonvolatile memory (NVM) in a second cycle.

A ratio of the first period and the second period may be dynamically determined. For example, in a command queue for queuing commands to be executed in the non-volatile memory (NVM), the memory controller increases the ratio of the second cycle to the first cycle as the number of queued commands decreases, thereby increasing the temperature of the internal temperature sensor NTS. Temperature values can often be acquired. The memory controller may obtain a temperature value from an internal temperature sensor (NTS) for each non-volatile memory (NVM) while minimizing an effect on command processing speed.

Depending on implementation, the second period may be less frequent than the first period. That is, the memory controller can check the internal temperature sensor (NTS) relatively occasionally and the external temperature sensor (ETS) relatively frequently. When the memory controller checks the external temperature sensor (ETS), it does not occupy the channels connecting the memory controller and non-volatile memory (NVM), so that the memory controller frequently checks the external temperature sensor (ETS) affects the command processing speed. may be almost out of reach.

In step S33 , the memory controller may determine whether a difference between the temperature value of the internal temperature sensor NTS and the temperature value of the external temperature sensor ETS exceeds a threshold value for each nonvolatile memory (NVM).

In step S34, the memory controller may determine the temperature value of the external temperature sensor ETS as the temperature value of the nonvolatile memory (NVM) for the nonvolatile memory (NVM) in which the temperature difference does not exceed the threshold value. If the temperature value of the external temperature sensor (ETS) is determined as the current temperature value of the non-volatile memory (NVM), the temperature value of the non-volatile memory (NVM) can be updated without accessing the internal temperature sensor (NVM) through a channel. can

On the other hand, in step S35, the memory controller may determine the temperature value of the non-volatile memory (NVM) using the temperature value of the internal temperature sensor (NTS) for the non-volatile memory (NVM) where the temperature difference exceeds the threshold value. there is.

As a first example, the memory controller may determine the temperature value of the internal temperature sensor (NTS) of the nonvolatile memory (NVM) as the temperature value of the nonvolatile memory (NVM). However, the present invention is not limited thereto. Since there is a case where the temperature difference between the internal temperature sensor (NTS) and the external temperature sensor (ETS) is out of the threshold value due to a measurement error of the internal temperature sensor (NTS), the memory controller is currently configured according to the second and third examples below. You can also determine the temperature value.

As a second example, the memory controller may determine a temperature value of the nonvolatile memory (NVM) in which a temperature difference exceeds a threshold value as an average temperature value of the plurality of nonvolatile memories (NVM).

As a third example, the memory controller re-acquires a temperature value of an internal temperature sensor (NTS) of a non-volatile memory (NVM) in which a temperature difference exceeds a threshold value, and based on the re-obtained temperature value, the non-volatile memory (NVM) NVM) can also determine the temperature value.

In step S36, the memory controller may determine a temperature range for each non-volatile memory (NVM) based on the temperature value for each non-volatile memory (NVM).

In step S37 , the memory controller may provide an operation command corresponding to a temperature range of the target nonvolatile memory (NVM) to the target nonvolatile memory (NVM).

According to the third embodiment of the present invention, when it is determined that the internal temperature value of the non-volatile memory (NVM) and the temperature value of the external temperature sensor (ETS) are similar, the temperature value of the external temperature sensor (ETS) is used to compare the The temperature range of the volatile memory (NVM) can be determined. Accordingly, the memory controller can compensate for operating characteristics of the non-volatile memory (NVM) depending on the temperature while minimizing the input/output time of the channel for determining the temperature range of the non-volatile memory (NVM).

13 and 14 are diagrams illustrating the structure of a storage device according to an embodiment of the present invention.

Referring to FIG. 13 , the storage device 400 may include a memory controller 410 , nonvolatile memories NVM11 to NVM42 , and channels CH1 to CH4 . The memory controller 410 and the nonvolatile memories NVM11 - NVM42 may be stacked on the board 401 to form one package.

In the example of FIG. 13 , the memory controller 410 transmits and receives signals to and from the nonvolatile memories NVM11 to NVM12 through a first channel CH1 and transmits and receives signals to and from the nonvolatile memories NVM21 to NVM21 through a second channel CH2. NVM22), transmits and receives signals with non-volatile memories (NVM31-NVM32) through the third channel (CH3), and transmits and receives signals with the non-volatile memories (NVM41-NVM42) through the fourth channel (CH4). can send and receive. In the example of FIG. 13 , the storage device 400 may include nonvolatile memories (NVM11 to NVM42) connected to four channels (CH1 to CH4), but the number of nonvolatile memories and the number of channels are not limited.

Each of the nonvolatile memories NVM11 to NVM42 may include an internal temperature sensor NTS. Also, the memory controller 410 may include an external temperature sensor (ETS). The memory controller 410 may have to use channels CH1 to CH4 to acquire temperature values from the internal temperature sensors NTS of the nonvolatile memories NVM11 to NVM42. On the other hand, the memory controller 410 may access the external temperature sensor ETS through an interface separate from the channels CH1 to CH4. Accordingly, when the memory controller 410 obtains a temperature value through the external temperature sensor ETS, data transmission performance of the memory controller 410 and the nonvolatile memories NVM11 to NVM42 may not be affected.

According to an embodiment of the present invention, the memory controller 410 controls the temperature of the non-volatile memories NVM11-NVM42 by providing an operation command corresponding to a temperature range to which the temperature values of the non-volatile memories NVM11-NVM42 belong. It is possible to compensate for operating characteristics that vary according to the

The memory controller 410 acquires the temperature value of the external temperature sensor ETS in a first cycle, and the temperature value of the internal temperature sensor NTS of the non-volatile memories NVM11-NVM42 through the channels CH1-CH4. may be obtained in a second period that is rarer than the first period.

The memory controller 410 converts the temperature value of the external temperature sensor (ETS) to the temperature value of the non-volatile memory for the non-volatile memory in which the temperature difference between the external temperature sensor (ETS) and the internal temperature sensor (NTS) is equal to or less than the first threshold value. can be determined by In the example of FIG. 13 , the nonvolatile memory NVM41 adjacent to the memory controller 410 may be greatly affected by the temperature change of the memory controller 410, and the temperature value of the internal temperature sensor NTS and the external temperature sensor ( ETS) may be less than or equal to the first threshold value. The memory controller 410 may determine the temperature value of the non-volatile memory NVM41 using the temperature value of the external temperature sensor ETS, which has little effect on data transmission performance even when frequently accessed.

On the other hand, the memory controller 410 may determine the temperature value of the internal temperature sensor NTS as the temperature value of the nonvolatile memory with respect to the nonvolatile memory in which the temperature difference exceeds the first threshold. For example, the non-volatile memory (NVM12) far from the memory controller 410 may be less affected by the temperature change of the memory controller 410, and the temperature value of the internal temperature sensor (NTS) and the external temperature sensor (ETS) ) may be greater than or equal to the first threshold value. The memory controller 410 may determine the temperature value of the nonvolatile memory NVM12 by using the temperature value of the internal temperature sensor NTS of the nonvolatile memory NVM12.

Referring to FIG. 14 , a storage device 500 may include a substrate 501 in which a controller area 502 and a nonvolatile memory area 503 are defined. A memory controller 510 may be disposed in the controller area 502 of the substrate 501 , and a plurality of nonvolatile memory packages NVMPKG may be disposed in the nonvolatile memory area 503 . The nonvolatile memory packages NVMPKG may include a plurality of stacked nonvolatile memories (not shown), and each of the nonvolatile memories may include an internal temperature sensor. The memory controller 510 and the non-volatile memories may transmit and receive signals through channels (not shown). The memory controller 510 may obtain temperature values of non-volatile memories from an internal temperature sensor through channels.

The storage device 500 may further include one or more external temperature sensors. For example, the first external temperature sensor 531 may be disposed outside the nonvolatile memory area 503 on the substrate 501, and the second external temperature sensor 532 may be disposed within the nonvolatile memory area 503. It can be. The memory controller 510 may obtain temperature values from the first and second external temperature sensors 531 and 532 through an interface separate from channels for transmitting and receiving signals to and from the nonvolatile memories.

According to an embodiment of the present invention, the memory controller 510 may obtain temperature values from internal temperature sensors of non-volatile memories and determine each of the obtained temperature values as the temperature values of the non-volatile memories. The memory controller 510 may provide an operation command determined based on a current temperature value of a target nonvolatile memory among nonvolatile memories to the target nonvolatile memory.

When the difference between the temperature value of the first external temperature sensor 531 and the temperature value of the second external temperature sensor 532 is greater than or equal to a threshold value, the memory controller 510 receives a temperature value from the internal temperature sensors of the plurality of non-volatile memories. may be obtained, and the current temperature value may be updated with the obtained temperature value. On the other hand, when the difference between the temperature values is smaller than the threshold value, the memory controller 510 may maintain the temperature values of the non-volatile memories without updating them.

When the internal temperature or the external temperature of the nonvolatile memory area 503 changes rapidly, a temperature difference equal to or greater than a threshold value between the first and second external temperature sensors 531 and 532 may be detected. The memory controller 510 determines that the internal temperatures of the non-volatile memories do not significantly change until a temperature difference equal to or greater than a threshold value is detected, and may provide an operation command to the non-volatile memories using the previously determined temperature values. there is. According to an embodiment of the present invention, the performance of the storage device 500 can be improved because the input/output workload of the channels required to determine the temperature values of the non-volatile memories can be reduced.

15 are diagrams illustrating a system to which a storage device according to an embodiment of the present invention is applied.

15 is a diagram illustrating a system 1000 to which a storage device according to an embodiment of the present invention is applied. The system 1000 of FIG. 15 is basically a mobile phone such as a mobile phone, a smart phone, a tablet personal computer (PC), a wearable device, a healthcare device, or an internet of things (IOT) device. (mobile) system. However, the system 1000 of FIG. 15 is not necessarily limited to a mobile system, and can be used for vehicles such as a personal computer, a laptop computer, a server, a media player, or a navigation system. It may be an automotive device or the like.

Referring to FIG. 15 , the system 1000 may include a main processor 1100, memories 1200a and 1200b, and storage devices 1300a and 1300b, and additionally includes an image capturing device. 1410, user input device 1420, sensor 1430, communication device 1440, display 1450, speaker 1460, power supplying device 1470 and connections It may include one or more of the connecting interfaces 1480 .

The main processor 1100 may control the overall operation of the system 1000, and more specifically, the operation of other components constituting the system 1000. The main processor 1100 may be implemented as a general-purpose processor, a dedicated processor, or an application processor.

The main processor 1100 may include one or more CPU cores 1110 and may further include a controller 1120 for controlling the memories 1200a and 1200b and/or the storage devices 1300a and 1300b. Depending on embodiments, the main processor 1100 may further include an accelerator 1130 that is a dedicated circuit for high-speed data operations such as artificial intelligence (AI) data operations. Such an accelerator 1130 may include a graphics processing unit (GPU), a neural processing unit (NPU), and/or a data processing unit (DPU), and may be physically independent from other components of the main processor 1100. It may be implemented as a separate chip.

The memories 1200a and 1200b may be used as main memory devices of the system 1000 and may include volatile memories such as SRAM and/or DRAM, but may include non-volatile memories such as flash memory, PRAM, and/or RRAM. may be The memories 1200a and 1200b may also be implemented in the same package as the main processor 1100 .

The storage devices 1300a and 1300b may function as non-volatile storage devices that store data regardless of whether or not power is supplied, and may have a relatively large storage capacity compared to the memories 1200a and 1200b. The storage devices 1300a and 1300b may include storage controllers 1310a and 1310b and non-volatile memories (NVMs) 1320a and 1320b that store data under the control of the storage controllers 1310a and 1310b. can Non-volatile memory (1320a, 1320b) may include a flash memory of a 2-dimensional (2D) structure or a 3-dimensional (3D) V-NAND (Vertical NAND) structure, but other types of PRAM and / or RRAM, etc. It may also include non-volatile memory.

The storage devices 1300a and 1300b may be included in the system 1000 while being physically separated from the main processor 1100 or may be implemented in the same package as the main processor 1100 . In addition, the storage devices 1300a and 1300b have a form such as a solid state device (SSD) or a memory card, so that other components of the system 1000 can be accessed through an interface such as a connection interface 1480 to be described later. It may also be coupled to be detachable with the . The storage devices 1300a and 1300b may be devices to which standard rules such as UFS (Universal Flash Storage), eMMC (embedded multi-media card), or NVMe (non-volatile memory express) are applied, but are not necessarily limited thereto. It's not.

The photographing device 1410 may capture a still image or a video, and may be a camera, a camcorder, and/or a webcam.

The user input device 1420 may receive various types of data input from a user of the system 1000, and may use a touch pad, a keypad, a keyboard, a mouse, and/or It may be a microphone or the like.

The sensor 1430 can detect various types of physical quantities that can be acquired from the outside of the system 1000 and convert the detected physical quantities into electrical signals. The sensor 1430 may be a temperature sensor, a pressure sensor, an illuminance sensor, a position sensor, an acceleration sensor, a biosensor, and/or a gyroscope sensor.

The communication device 1440 may transmit and receive signals with other devices outside the system 1000 according to various communication protocols. Such a communication device 1440 may be implemented by including an antenna, a transceiver, and/or a modem (MODEM).

The display 1450 and the speaker 1460 may function as output devices that output visual information and auditory information to the user of the system 1000, respectively.

The power supply device 1470 may appropriately convert power supplied from a battery (not shown) and/or an external power source built into the system 1000 and supply the power to each component of the system 1000 .

The connection interface 1480 may provide a connection between the system 1000 and an external device connected to the system 1000 and capable of exchanging data with the system 1000. The connection interface 1480 is an Advanced Technology (ATA) Attachment), Serial ATA (SATA), external SATA (e-SATA), Small Computer Small Interface (SCSI), Serial Attached SCSI (SAS), Peripheral Component Interconnection (PCI), PCI express (PCIe), NVMe, IEEE 1394, It can be implemented in various interface methods such as USB (universal serial bus), SD (secure digital) card, MMC (multi-media card), eMMC, UFS, eUFS (embedded universal flash storage), CF (compact flash) card interface, etc. there is.

According to an embodiment of the present invention, the storage controllers 1310a and 1310b transmit a data signal including an operation command corresponding to a temperature range to which the temperature value of the nonvolatile memory 1320a and 1320b belongs, and transmits a data signal at a time when the CLE signal is enabled. It can be provided as non-volatile memory (1320a, 1320b) between. The nonvolatile memories 1320a and 1320b may perform an operation of the type defined in the operation command using an operation parameter defined in the operation command. Since the storage controllers 1310a and 1310b may not transmit a separate operating parameter according to the temperature value, the operating characteristics of the nonvolatile memories 1320a and 1320b according to the temperature condition can be compensated without increasing the command transmission time. there is.

According to an embodiment of the present invention, the storage controllers 1310a and 1310b may determine the temperature values of the nonvolatile memories 1320a and 1320b through channels connected to the nonvolatile memories 1320a and 1320b. , a temperature value may be obtained from the internal temperature sensor of 1320b). The storage controllers 1310a and 1310b may omit updating the temperature values of the nonvolatile memories 1320a and 1320b according to the amount of I/O workload of the nonvolatile memories 1320a and 1320b. Also, the storage controllers 1310a and 1310b may update the temperature values of the nonvolatile memories 1320a and 1320b based on the temperature values from the external temperature sensor connected through an interface separate from the channels according to conditions. there is. The storage controllers 1310a and 1310b may reduce the amount of I/O workload of the channel by reducing the frequency of acquiring the temperature value from the internal temperature sensor to determine the current temperature value. Accordingly, performance degradation of the storage devices 1300a and 1300b due to the determination of the current temperature value may be minimized.

According to an embodiment of the present invention, the main processor 1100 may provide external temperature information of the storage devices 1300a and 1300b to the storage controllers 1310a and 1310b. For example, the external temperature information may include average temperature information of a server in which the storage devices 1300a and 1300b are mounted. The storage controllers 1310a and 1310b may use the external temperature information to determine a default command among operation commands for each temperature range provided for a plurality of operation types. Even if the storage controller 1310a or 1310b cannot determine the temperature value of the nonvolatile memory 1320a or 1320b using an internal temperature sensor or the like, the storage controller 1310a or 1310b uses the default command to determine the temperature of the nonvolatile memory 1320a or 1320b. According to the operating characteristics can be compensated.

The present invention is not limited by the above-described embodiments and accompanying drawings, but is intended to be limited by the appended claims. Therefore, various forms of substitution, modification, and change will be possible by those skilled in the art within the scope of the technical spirit of the present invention described in the claims, which also falls within the scope of the present invention. something to do.

100, 400, 500: storage device
110, 410, 510: memory controller
NVM: non-volatile memory
NTS: internal temperature sensor
ETS, 431, 432: External temperature sensor

Claims (20)

a plurality of non-volatile memories including an internal temperature sensor;
a memory controller communicating with the plurality of nonvolatile memories through a first interface and having a plurality of operation commands defined for each temperature range of the nonvolatile memories; and
one or more external temperature sensors communicating with the memory controller through a second interface;
The memory controller
obtaining a temperature value from the one or more external temperature sensors in a first cycle, obtaining a temperature value of the internal temperature sensor in a second cycle different from the first cycle, and obtaining a temperature value of the one or more external temperature sensors and the internal temperature sensor A temperature range of the nonvolatile memory in which the difference between the temperature values of is less than or equal to a first threshold is determined based on the temperature value of the external temperature sensor, and the temperature range of the nonvolatile memory in which the difference between the temperature values exceeds the first threshold is determined. Determines using the temperature value of the internal temperature sensor, and provides an operation command corresponding to the temperature range of the target non-volatile memory among the plurality of operation commands to a target non-volatile memory among the plurality of non-volatile memories.
storage device.
According to claim 1,
The memory controller
Selecting an operation command corresponding to a temperature range of the target nonvolatile memory and an operation type to be instructed among operation commands for each temperature range defined in each operation type including program operation, read operation, and erase operation
storage device.
According to claim 1,
The memory controller
Determining a temperature range of a nonvolatile memory in which a difference between a temperature value of the one or more external temperature sensors and a temperature value of the internal temperature sensor exceeds the first threshold value based on an average temperature value of the plurality of nonvolatile memories
storage device.
According to claim 1,
A temperature value of the non-volatile memory in which a difference between a temperature value of the at least one external temperature sensor and a temperature value of the internal temperature sensor exceeds the first threshold value is acquired again through the first interface, and the obtained temperature value is Based on determining the temperature range of the non-volatile memory
storage device.
According to claim 4,
The memory controller
Receiving a temperature value outside the storage device from a host, and determining a command corresponding to a temperature range to which the received temperature value belongs as a default command in each of the operation types.
storage device.
According to claim 1,
the storage device
a substrate providing a nonvolatile memory area in which the plurality of nonvolatile memories are disposed and a memory controller area in which the memory controller is disposed;
The one or more external temperature sensors
A first external temperature sensor disposed within the non-volatile memory area and a second external temperature sensor disposed outside the non-volatile memory area.
storage device.
According to claim 6,
The memory controller
When the difference between the temperature value of the first external temperature sensor and the temperature value of the second external temperature sensor is greater than or equal to a second threshold value, the temperature ranges of the plurality of nonvolatile memories are updated based on the temperature value of the internal temperature sensor. doing
storage device.
According to claim 1,
the storage device
Further comprising a substrate on which the memory controller and the plurality of non-volatile memories are stacked
storage device.
According to claim 1,
The memory controller
Further comprising a command queue for queuing operation commands to be provided to the plurality of non-volatile memories, wherein a ratio of the first cycle and the second cycle is determined according to the number of commands queued in the command queue
storage device.
According to claim 9,
The memory controller
increasing the ratio of the second cycle to the first cycle when the number of commands queued in the operation commands queued in the command queue is less than or equal to a threshold value;
storage device.
According to claim 1,
The second interface is
Inter-Integrated Circuit (I2C) interface
storage device.
a plurality of non-volatile memories including an internal temperature sensor; and
A memory controller controlling the plurality of non-volatile memories and having a plurality of operation commands defined for each temperature range of the non-volatile memories;
The memory controller
The temperature range of each of the non-volatile memories is determined by referring to the temperature value of the internal temperature sensor, the input/output workload of each of the non-volatile memories is periodically monitored, and the amount of the input/output workload in a predetermined time period is determined. A temperature range of the first non-volatile memory is updated with reference to the internal temperature sensor of the first non-volatile memory out of a predetermined range, and among the plurality of operation commands is applied to a target non-volatile memory among the plurality of non-volatile memories. Providing an operation command corresponding to the temperature range of the target non-volatile memory
storage device.
According to claim 12,
The memory controller
Maintaining a temperature range of a second non-volatile memory belonging to a range in which the amount of the input/output workload is determined
storage device.
According to claim 12,
The I/O workload of each of the non-volatile memories is
Determined based on the increase in the degree of wearout of the non-volatile memories in the predetermined time period
storage device.
According to claim 12,
The I/O workload of each of the non-volatile memories is
Determined based on the amount of data read from each of the non-volatile memories in the predetermined time period
storage device.
According to claim 12,
the storage device
a substrate providing a nonvolatile memory area on which the plurality of nonvolatile memories are disposed and a memory controller area on which the memory controller is disposed;
a first external temperature sensor disposed in the non-volatile memory area; and
A second external temperature sensor disposed outside the non-volatile memory area
A storage device further comprising a.
According to claim 16,
When the difference between the temperature value of the first external temperature sensor and the temperature value of the second external temperature sensor is greater than or equal to a threshold value, the memory controller refers to the temperature value of the internal temperature sensor to determine the temperature range of the plurality of nonvolatile memories. to update
storage device.
a plurality of non-volatile memories;
a memory controller that controls the plurality of nonvolatile memories and has a plurality of operation commands defined for each temperature range of the nonvolatile memories; and
Provides a CLE (Command Latch Enable) signal and ALE (Address Latch Enable) signal output from the memory controller to one of the plurality of non-volatile memories, and transmits a data signal between the memory controller and the plurality of non-volatile memories. Including transmission and reception channels,
The memory controller
During a first time period during which the CLE signal is enabled, a data signal including an operation command corresponding to a temperature range to which a temperature value of a target nonvolatile memory belongs among the plurality of nonvolatile memories among the plurality of operation commands is transmitted to the target A data signal including a real address is provided to the nonvolatile memory during a second time period when the ALE signal is enabled, and a confirm command is provided during a third time period when the CLE signal is enabled. To provide a data signal to the target non-volatile memory
storage device.
According to claim 18,
The second time period is a time period after the first time period,
The third time period is a time period after the second time period.
storage device.
According to claim 18,
The memory controller
Selecting the operation command from among a plurality of predefined operation commands based on the type of operation to be instructed to the target nonvolatile memory and the temperature range.
storage device.

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