KR20230080278A - Receiver - Google Patents

Abstract

The present invention provides a receiver capable of detecting an offset voltage of a differential signal without using a separate voltage source or a separate current source. The receiver comprises: a differential signal generator receiving a single-ended signal, and generating a differential signal based on the single-ended signal, a reference signal, and a pair of compensation signals; a positive charging circuit charging a first node to a power level in a logic high interval of a clock signal; a negative charging circuit charging a second node to a power level in the logic high interval of the clock signal; a positive discharging circuit discharging the first node in accordance with a signal level of a positive signal included in the differential signal in a logic low interval of the clock signal; a negative discharging circuit discharging the second node in accordance with a signal level of a negative signal which is a complementary signal of the positive signal in the logic low interval of the clock signal; a comparator comparing a signal level of the first node and a signal level of the second node to output an offset detection signal of the differential signal; and an offset compensator inputting a reference signal and a pair of compensation signals adjusted based on an offset detection signal obtained from the comparator into the differential signal generator.

Description

receiver {RECEIVER}

The present invention relates to a receiver that receives a single-ended signal and outputs a differential signal.

An electronic device includes various functional blocks or devices configured to provide various functions. Various functional blocks or devices may exchange data with each other through a receiver.

Some receivers can generate a differential signal based on a single-ended signal received over a transmission line. A receiver may include elements paired with each other to generate a differential signal. When a mismatch or asymmetric aging occurs between paired devices, an offset may occur in a differential signal generated by a receiver. When offset occurs, it can adversely affect the RLM (Ratio of Level Separation Mismatch) or margin in the eye diagram of the differential signal.

Accordingly, it is required that the receiver be able to detect the offset of the differential signal and compensate for the offset.

An object of the present invention is to provide a receiver capable of detecting an offset voltage of a differential signal generated by a differential signal generator and compensating for an offset of the differential signal generator.

An object of the present invention is to provide a receiver including an offset voltage detection circuit capable of detecting an offset voltage of a differential signal without using a separate voltage source or current source.

A receiver according to an embodiment of the present invention includes a differential signal generator configured to receive a single-ended signal and generate a differential signal based on the single-ended signal, a reference signal, and a pair of compensation signals; a positive charging circuit for charging the first node to a power level during a logic high period of the clock signal; a negative charging circuit for charging a second node to a power level during a logic high period of the clock signal; a positive discharge circuit for discharging the first node according to a signal level of a positive signal included in the differential signal in a logic low period of the clock signal; a negative discharge circuit for discharging the second node according to a signal level of a negative signal that is a complementary signal of the positive signal in a logic low period of the clock signal; a comparator outputting an offset detection signal of the differential signal by comparing the signal level of the first node and the signal level of the second node; and an offset compensator inputting a reference signal adjusted based on the offset detection signal obtained from the comparator and a pair of compensation signals to the differential signal generator.

A receiver according to an embodiment of the present invention includes a differential signal generator configured to receive a single-ended signal and generate a differential signal based on the single-ended signal, a reference signal, and a pair of compensation signals; First and second nodes are charged by receiving power supply voltage in a charging period, and in a discharging period after the charging period, the first node is discharged according to the level of a positive signal among the differential signals, and a negative signal among the differential signals is charged. a boundary detector that discharges the second node according to the level of , outputs the signal of the first node as a positive boundary signal, and outputs the signal of the second node as a negative boundary signal; a comparator generating a plurality of offset detection signals within the discharge interval by comparing the level of the positive boundary signal and the level of the negative boundary signal; a voting unit outputting an offset polarity signal representing the discharge period using a plurality of offset detection signals obtained from the comparator; an up-down counter that increments or decrements a count value based on the offset polarity signal; and one or more digital-analog converters (DACs) outputting the reference signal adjusted based on the count value and a pair of compensation signals.

A receiver according to an embodiment of the present invention includes a differential signal generator configured to receive a single-ended signal and generate a differential signal based on the single-ended signal, a reference signal, and a pair of compensation signals; a boundary detector that periodically charges first and second nodes and discharges the charged first and second nodes based on the differential signal to output boundary signals corresponding to a minimum level of the differential signal; a comparator generating an offset detection signal by comparing levels of the boundary signals; a voting unit determining an offset polarity of the differential signal using the offset detection signals acquired from the comparator and outputting an offset polarity signal; A first count value is determined by increasing or decreasing a count value according to offset polarity signals output in an untwisted state of the input and output terminals of the boundary detector, and the input and output terminals of the boundary detector are twisted. Determine the second count value by increasing or decreasing the count value according to the offset polarity signals output from the state, and based on the first count value and the second count value, the final count value in which the effect of the offset of the boundary detector is canceled an up-down counter that outputs and one or more digital-analog converters (DACs) outputting the reference signal and a pair of compensation signals adjusted based on the final count value.

A receiver according to an embodiment of the present invention detects an offset voltage of a differential signal by comparing boundary levels of the differential signal, and adjusts a reference signal for generating a differential signal based on the detected offset voltage to generate a differential signal generator. Offset can be compensated.

The receiver according to an embodiment of the present invention may improve the RLM and margin in the eye diagram of the differential signal by reducing the magnitude of the offset voltage of the differential signal.

An offset voltage detection circuit included in a receiver according to an embodiment of the present invention generates boundary signals of a differential signal based on a received differential signal and detects an offset voltage of the differential signal according to a comparison result of the boundary signals. Power consumption for voltage detection can be reduced.

The problems to be solved by the present invention are not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the description below.

1 is a diagram showing a receiver according to an embodiment of the present invention.
2A to 2D are diagrams schematically illustrating an offset compensation method of a differential signal generator according to an embodiment of the present invention.
3 is a flowchart illustrating a method of operating a receiver according to an embodiment of the present invention.
4 is a block diagram schematically illustrating the structure of a boundary detector according to an embodiment of the present invention.
5 is a circuit diagram showing in detail the structure of a boundary detector according to an embodiment of the present invention.
6A and 6B are diagrams for explaining signal levels of boundary signals according to differential signals.
7A to 8C are diagrams for explaining in detail an offset compensation method of a differential signal generator according to an embodiment of the present invention.
9 is a diagram illustrating a receiver according to an embodiment of the present invention.
10A to 10C are diagrams for explaining in detail an offset compensation method of a differential signal generator according to an embodiment of the present invention.
11A to 11C are diagrams for explaining an offset compensation method of a differential signal generator according to an embodiment of the present invention.
12 to 13 are diagrams for explaining an effect of offset compensation according to an embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

1 is a diagram showing a receiver according to an embodiment of the present invention.

Referring to FIG. 1 , a receiver 100 includes a differential signal generator 110, a boundary detector 120, a comparator 130, a voting unit 140, an up-down counter 150, and a plurality of digital-analog converters (DACs). s (160, 170) may be included.

The differential signal generator 110 receives a single-ended signal VRX from the outside of the receiver 100 and outputs differential signals VSP and VSN based on the received single-ended signal VRX. can

A single ended signal may include a real signal and a ground signal. The signal level of the single-ended signal may be determined as a value measured with respect to the ground signal. When noise occurs in the real signal in a single-ended signal, it is difficult to cancel the noise.

A differential signal may include two signals having the same amplitude and opposite phases. Hereinafter, the two signals included in the differential signals VSP and VSN may be referred to as a positive signal VSP or a negative signal VSN. The negative signal VSN may be a complementary signal of the positive signal VSP.

A signal level of the differential signal may be determined by a difference between the two signals. Meanwhile, when two signals are transmitted through adjacent signal lines, common mode noise may be included in the two signals. Even if common mode noise is included in the two signals, a difference between the two signals may be maintained. Since the signal level of the differential signal is determined by the difference between the two signals, common mode noise can be canceled out.

Meanwhile, when an offset voltage is generated in the differential signal due to the offset of the differential signal generator 110 itself, the offset voltage is difficult to be easily removed even by the difference between the two signals. For example, the differential signal generator 110 may include a plurality of elements, and some of the plurality of elements may be paired with each other. Mismatches may occur between paired devices due to minute differences in manufacturing processes, or different levels of aging may occur when the devices are used. An offset may occur in the differential signal generator 110 due to mismatch or aging of paired elements.

Referring to FIG. 1 , a differential signal generator 110 may include a single ended to differential (S2D) converter 111, a differential amplifier 112, a decision feedback equalizer (DFE) 113, and a differential compensator 114. .

The S2D converter 111 may output differential signals VDI and VDIB based on the single-ended signal VRX received from the outside. The S2D converter 111 may use the reference signal Vref to output differential signals VDI and VDIB. For example, the S2D converter 111 outputs the main signal VDI having the same phase as the single-ended signal VRX, and an inverted signal obtained by inverting the phase of the main signal VDI with respect to the reference signal Vref. (VDIB) can be output.

The differential amplifier 112 may amplify the differential signal. In addition, the DFE 113 may remove the effect of ISI expected from the value of previous data of the differential signal from the current data in order to reduce the effect of Inter-Symbol Interference (ISI) of the amplified differential signal. Here, ISI refers to a phenomenon in which previously transmitted data affects currently transmitted data due to limitations in the bandwidth of a data channel. The differential compensator 114 may change the signal levels of the differential signal by the signal levels of the compensation signals VCP and VCN. The differential signals VDI and VDIB may pass through the differential amplifier 112 , the DFE 113 , and the differential compensator 114 to be output as final differential signals VSP and VSN.

Referring to FIG. 1 , the differential signal generator 110 may include a plurality of transistors M1 to M12. Among the transistors, M1 and M2, M4 and M5, M7 and M8, and M10 and M11 can be paired with each other. An offset may occur in the differential signal generator 110 due to a mismatch or aging of paired transistors, and an offset voltage may occur between the differential signals VSP and VSN.

According to an embodiment of the present invention, the receiver 100 detects the minimum level of each of the positive signal VSP and the negative signal VSN included in the differential signals VSP and VSN, and compares the minimum levels to the differential signal (VSP, VSN). VSP, VSN) can determine whether it has a positive offset voltage or a negative offset voltage. The receiver 100 may compensate for offsets of the differential signals VSP and VSN by adjusting the levels of the reference voltage Vref or the compensation voltages VCN and VCP according to the determination.

Upon receiving the differential signals VSP and VSN, the boundary detector 120 may output boundary signals VBP and VBN representing minimum levels of the differential signals VSP and VSN. According to an embodiment of the present invention, the boundary detector 120 may output the boundary signals VBP and VBN while periodically repeating charging and discharging of the boundary signals VBP and VBN.

For example, the boundary detector 120 may receive a power signal and charge the boundary signals VBP and VBN to the power level during the charging period. Also, the boundary detector 120 discharges the charged positive boundary signal VBP according to the level of the positive signal VSP in the discharging period after the charging period, and converts the charged negative boundary signal VBN into the negative signal VSN. ) can be discharged according to the level of

The comparator 130 may compare the signal levels of the boundary signals VBP and VBN, and output an offset detection signal indicating whether the positive boundary signal VBP or the negative boundary signal VBN is greater. .

The voting unit 140, the up-down counter 150, and the plurality of DACs 160 and 170 are adjusted to compensate for the offset of the differential signal generator 110 based on the offset detection signal output from the comparator 130. An offset compensator outputting a reference signal Vref and a pair of compensation signals VCP and VCN may be configured.

The voting unit 140 receives the offset detection signals from the comparator 130 several times within a predetermined period, and the differential signals VSP and VSN generate positive offset voltages within the predetermined period based on the offset detection signals. A final offset signal indicating whether it has a negative offset voltage or a negative offset voltage may be output. For example, the case where the positive signal VSP has a higher DC level than the negative signal VSN is defined as the case where the positive offset voltage is present, and the positive signal VSP has a lower DC level than the negative signal VSN. A case having a level may be defined as a case having a negative offset voltage.

The up-down counter 150 may have count values for determining the reference signal Vref and the compensation signals VCP and VCN. The up-down counter 150 may adjust the signal levels of the reference signal Vref and the pair of compensation signals VCP and VCN by increasing or decreasing the count value based on the final offset signal value.

Depending on the implementation, the count value may have M (M is a natural number) bit value, and the upper K (K is a natural number) bit value of the M bit values is used to determine the signal level of the reference signal Vref, and the lower ( M-K) bit values may be used to determine signal levels of the compensation signals VCP and VCN. For example, K can be (M/2).

The plurality of DACs 160 and 170 may receive the count value corresponding to a digital signal and output a reference signal Vref and compensation signals VCP and VCN corresponding to an analog signal. Depending on the implementation, the upper bit DAC 160 may receive the upper K-bit value of the count value and output the reference signal Vref. And, the lower bit DAC 170 may receive the lower (M-K) bit value of the count value and output the compensation signals VCP and VCN.

The level of the reference signal Vref may increase by a first unit level whenever the K-bit value increases by '1'. Also, the level of the positive compensation signal VCP decreases by a second unit level whenever the (M-K) bit value increases by '1', and the level of the negative compensation signal VCN decreases when the (M-K) bit value Whenever '1' is increased, it may increase by the second unit level.

The reference signal Vref can greatly adjust the level of the differential signals VSP and VSN, and the compensation signals VCP and VCN can finely adjust the level of the differential signals VSP and VSN. For example, the first unit level may have a greater value than the second unit level. However, the first unit level may have a value smaller than 2 ^(MK) times the second unit level so that the levels of the differential signals VSP and VSN can be finely adjusted in all voltage ranges.

The reference signal Vref and the compensation signals VCP and VCN may be fed back to the differential signal generator 110, and the differential signal generator 110 outputs differential signals VSP and VSN having reduced offset voltages. can do. That is, the offset of the differential signal generator 110 can be compensated for.

Hereinafter, an offset compensation process of the differential signal generator according to an embodiment of the present invention will be described in detail with reference to FIGS. 2A to 8C.

2A to 2D are diagrams schematically illustrating an offset compensation method of a differential signal generator according to an embodiment of the present invention.

2A is a graph showing the signal level of the single-ended signal VRX over time. The single-ended signal VRX may be a signal having one of two signal levels in a signal period. Differential signals VSP and VSN may be generated based on the single-ended signal VRX and the reference signal Vref.

2B is a graph showing signal levels of ideal differential signals (VSP, VSN) over time. When there is no offset in the differential signal generator 110, both the direct current levels of the positive signal VSP and the negative signal VSN may be equal to the level of the reference signal Vref. That is, the differential signals VSP and VSN may not have offset voltages. When the differential signals VSP and VSN do not have offset voltages, the minimum levels of the positive and negative signals VSP_min and VSN_min may also be the same.

2C is a graph showing signal levels of differential signals VSP and VSN with offset voltages over time. When there is asymmetry in the differential signal generator 110, DC levels of the positive signal VSP and the negative signal VSN may be different. The offset voltage Voff may represent a difference between DC levels of the positive signal VSP and the negative signal VSN.

Meanwhile, in FIG. 2C , the DC level of the positive signal VSP may be lower than that of the negative signal VSN, and the differential signals VSP and VSN may have negative offset voltages. When the differential signals VSP and VSN have negative offset voltages, the minimum level VSP_min of the positive signal may have a smaller value than the minimum level VSN_min of the negative signal.

2D is a graph illustrating levels of a reference voltage (Vref) and compensation voltages (VCP, VCN) for compensating an offset of a differential signal generator. As described with reference to FIG. 2C , when the differential signals VSP and VSN have negative offset voltages, the magnitude of the offset voltage between the differential signals VSP and VSN can be reduced by lowering the level of the reference voltage Vref. Alternatively, the level of the offset voltage between the differential signals VSP and VSN may be reduced by increasing the level of the positive compensation signal VCP and decreasing the level of the negative compensation signal VCN.

3 is a flowchart illustrating a method of operating a receiver according to an embodiment of the present invention.

In step S11, the receiver may generate differential signals VSP and VSN based on the received single-ended signal VRX, the reference signal Vref, and the compensation signals VCP and VCN. A method for generating differential signals (VSP, VSN) by the receiver has been described with reference to FIG. 1 .

In step S12, the receiver may generate boundary signals VBP and VBN of the differential signals VSP and VSN. The boundary signals VBP and VBN may correspond to the minimum levels VSP_min and VSN_min of the differential signal described in FIGS. 2B and 2C. A detailed method of generating the boundary signals VBP and VBN by the receiver will be described later with reference to FIGS. 4 to 6B.

In step S13, the receiver may generate a final offset signal by comparing the magnitudes of the boundary signals VBP and VBN within the discharge period.

In step S14, the receiver may increase or decrease the count value according to the final offset signal.

In step S15, based on the increased or decreased counter value, the adjusted reference signal Vref and compensation signals VCP and VCN may be output. Based on the adjusted reference signal Vref and the compensation signals VCP and VCN, differential signals VSP and VSN having reduced offset voltages may be output.

Hereinafter, a specific method for generating the boundary signals VBP and VBN by the receiver will be described with reference to FIGS. 4 to 6B.

4 is a block diagram schematically illustrating the structure of a boundary detector according to an embodiment of the present invention. 5 is a circuit diagram showing in detail the structure of a boundary detector according to an embodiment of the present invention. 6A and 6B are diagrams for explaining signal levels of boundary signals VBP and VBN according to differential signals VSP and VSN.

Referring to FIG. 4 , the boundary detector 120 may include a positive charge circuit 121 , a positive discharge circuit 122 , a negative charge circuit 123 and a negative discharge circuit 124 . The positive charging circuit 121 and the negative charging circuit 123, and the positive discharging circuit 122 and the negative discharging circuit 124 may be paired with each other.

The boundary detector 120 may operate based on a signal that swings at two levels, such as the clock signal CK. The boundary detector 120 may charge the positive boundary node BPN and the negative boundary node BNN in the charging period defined by the clock signal CK, and may charge the positive boundary node BPN in the discharging period defined by the clock signal CK. A boundary node (BPN) and a negative boundary node (BNN) may be discharged.

During the charging period, the positive charging circuit 121 may receive the power signal VDD and charge the positive boundary node BPN to the power level. Similarly, the negative charging circuit 123 may receive the power signal VDD and charge the negative boundary node BNN to the power level. In the charging period, the positive discharge circuit 122 and the negative discharge circuit 124 may be disabled.

In the discharging period, the positive charging circuit 121 and the negative charging circuit 123 may be disabled. Also, the positive discharge circuit 122 may receive the positive signal VSP and discharge the positive boundary node BPN according to the current level of the positive signal VSP. Similarly, the negative discharge circuit 124 may receive the negative signal VSN and discharge the negative boundary node BNN according to the current level of the negative signal VSN.

6A shows the levels of the differential signals VSP and VSN over time, and FIG. 6B shows the levels of the boundary signals VBP and VBN over time. Referring to FIGS. 6A and 6B , the length of the discharge period may be longer than one cycle of the differential signals VSP and VSN. The length of the discharge interval may vary depending on the implementation, but may have, for example, a length of several tens of cycles or hundreds of cycles of the differential signals VSP and VSN. Within the discharge period, the differential signals (VSP, VSN) may reach the minimum level several times. In the discharge period, the positive boundary node BPN and the negative boundary node BNN are gradually discharged according to the levels of the differential signals VSP and VSN, and have signal levels corresponding to minimum levels of the differential signals VSP and VSN.

Referring to FIG. 5 , the positive charging circuit 121 may include a first transistor T1. The first transistor T1 may be a PMOS transistor, and has a gate connected to the clock signal CK, a source connected to the power signal VDD, and a drain connected to the positive boundary node BPN. can be connected to The first transistor T1 may be turned on when the clock signal CK is in a logic low state to charge the positive boundary node BPN to the power level.

The negative charging circuit 123 may include a fourth transistor T4. The fourth transistor T4 may be a PMOS transistor, and may have a gate connected to the clock signal CK, a source connected to the power signal VDD, and a drain connected to the negative boundary node BNN. Like the first transistor T1, the fourth transistor T4 is also turned on when the clock signal CK is in a logic low state, so that the negative boundary node BNN can be charged to the power level.

The positive discharge circuit 122 may include second and third transistors T2 and T3. The second transistor T2 may be an NMOS transistor, and may have a gate connected to the clock signal CK, a drain connected to the drain of the third transistor T3, and a source connected to ground. The third transistor T3 may be a PMOS transistor, and may have a gate connected to the positive signal VSP and a source connected to the positive boundary node BPN.

The second transistor T2 may be turned on when the clock signal CK is in a logic high state. Also, the third transistor T3 may be turned on when the level of the positive signal VSP is smaller than the difference between the level of the positive boundary signal VBP and the threshold level (Vthp: Vthp is a positive number) of the third transistor T3. there is.

Referring to FIG. 6B , when the second and third transistors T2 and T3 are turned on, the positive boundary node BPN charged at the power level VDD may be discharged. The positive boundary node BPN may be gradually discharged over a plurality of signal periods according to the level of the positive signal VSP. When the level of the positive boundary signal VBP reaches the sum of the minimum level VSP_min of the positive signal and the threshold level Vthp, the positive boundary node BPN may be discharged. When the level of the positive boundary signal VBP reaches the sum of the minimum level of the positive signal VSP_min and the threshold level Vthp, the level of the positive signal VSP becomes the difference between the positive boundary signal VBP level and the threshold level Vthp. This is because it cannot be smaller than the difference and the third transistor T3 cannot be turned on any more.

Referring back to FIG. 5 , the negative discharge circuit 124 may include fifth and sixth transistors T5 and T6. The fifth transistor T5 may be an NMOS transistor, and may have a gate connected to the clock signal CK, a drain connected to the drain of the sixth transistor T6, and a source connected to the ground. The sixth transistor T6 may be a PMOS transistor, and may have a gate connected to the negative signal VSN and a source connected to the negative boundary node BNN.

Like the second transistor T2, the fifth transistor T5 may be turned on when the clock signal CK is in a logic high state. Similar to the third transistor T3, the sixth transistor T6 is turned on when the level of the negative signal VSN is less than the sum of the level of the negative boundary signal VBN and the threshold level Vthp of the fifth transistor T5. It can be.

Referring to FIG. 6B , when the fifth and sixth transistors T5 and T6 are turned on, the negative boundary node BNN charged at the power level may be discharged. When the level of the negative boundary signal VBN reaches the sum of the minimum level VSP_min of the negative signal and the threshold level Vthp, the discharge of the negative boundary node BNN may be terminated.

As described with reference to FIG. 2C , the difference between the minimum levels VSP_min and VSN_min of the differential signal may correspond to the offset Voff. The boundary voltages VBP and VBN may further include a threshold level component Vthp in addition to the minimum levels VSP_min and VSN_min of the differential signal. However, if the third and sixth transistors T3 and T6 have the same threshold level Vthp, the threshold level component Vthp may be canceled in the difference between the boundary voltages VBP and VBN. Accordingly, it is possible to determine whether the differential signals VSP and VSN have a positive offset or a negative offset by comparing the boundary voltages VBP and VBN.

Referring to FIGS. 4 and 5 , the boundary detector 120 detects boundary nodes BPN and BNN using a power supply signal VDD and differential signals VSP and VSN without using a separate voltage source or current source. By charging and discharging, it is possible to generate boundary signals VBP and VBN corresponding to the minimum levels VSP_min and VSN_min of the differential signal. Accordingly, the boundary detector 120 may not consume fixed DC power to determine the offset voltage of the differential signals VSP and VSN. Accordingly, it is possible to improve the noise margin of the differential signals VSP and VSN while reducing power consumption of the receiver 100 .

Hereinafter, with reference to FIGS. 7A to 8C , a method of compensating for an offset of a differential signal based on boundary signals VBP and VBN will be described in detail.

7A is a graph showing the levels of the boundary signals VBP and VBN over time, and FIG. 7B is a graph showing the levels of the reference signal Vref and the compensation signals VCP and VCN over time.

As described with reference to FIGS. 4 to 6B , the boundary detector 120 may generate boundary signals VBP and VBN for offset compensation while repeating a charging section and a discharging section. Hereinafter, the sum of a set of charge period and discharge period may be referred to as a detection period.

The comparison operation of the boundary signals VBP and VBN may be performed several times in one detection period, and based on the comparison operation results, whether the differential signals VSP and VSN have a positive offset voltage or a negative offset voltage Voltage is determined, and count values for determining the levels of the reference signal Vref and the compensation signals VCP and VCN may be increased or decreased.

The levels of the reference signal Vref and the compensation signals VCP and VCN may converge to a constant value over several detection periods. 7A and 7B show the levels of the boundary signals VBP and VBN and the levels of the reference signal Vref and the compensation signals VCP and VCN in several detection periods.

Referring to FIG. 7A , the level of the positive boundary signal VBP may be greater than the level of the negative boundary signal VBN in the first detection period DP1 . Referring to FIG. 7B , in the second detection period DP2 , which is a detection period following the first detection period DP1 , the positive compensation signal VCP may decrease and the negative compensation signal VCN may increase. Meanwhile, the reference signal Vref may be maintained.

Referring to FIG. 7A , even in the second detection period DP2 , the level of the positive boundary signal VBP may still be greater than the level of the negative boundary signal VBN. Referring to FIG. 7B , in a detection period following the second detection period DP2 , the positive compensation signal VCP may decrease and the negative compensation signal VCN may increase.

As detection cycles are repeated several times, values of the compensation signals VCP and VCN are periodically changed, and offset voltages of the differential signals VSP and VSN may gradually decrease. Referring to FIG. 7A , it can be seen that the level difference between the boundary signals VBP and VBN in the third detection period DP3 is reduced compared to that in the first detection period PD1 .

8A to 8C are graphs showing levels of signals after offset compensation is completed. 8A is a graph showing the levels of the differential signals VSP and VSN over time, FIG. 8B is a graph showing the levels of the boundary signals VBP and VBN over time, and FIG. 8C is a graph showing the levels of the reference signals over time ( Vref) and the level of the compensation signals VCP and VCN.

Referring to FIG. 8A , after offset compensation is completed, the differential signals VSP and VSN may have the same DC level. The minimum levels of the differential signals VSP and VSN may also be the same.

Referring to FIG. 8B , after offset compensation is completed, the boundary signals VBP and VBN may have substantially the same level. Referring to FIG. 8C , after offset compensation is completed, the levels of the reference signal Vref and the compensation signals VCP and VCN may converge to levels similar to those in the third detection period DP3 of FIG. 7B .

According to an embodiment of the present invention, the receiver 100 calculates the offset voltage of the differential signals VSP and VSN in real time using the differential signals VSP and VSN generated based on the single-ended signal VRX received from the outside. , and the offset of the differential signal generator 110 can be dynamically compensated. The receiver 100 can effectively compensate for the offset even when the offset of the differential signal generator 110 fluctuates due to asymmetric aging of elements included in the differential signal generator 110 over time. Thus, the noise margin of the receiver 100 can be improved.

Meanwhile, referring to FIG. 5 again, the boundary detector 120 may also include paired elements. Paired elements of the boundary detector 120 may also have mismatches or the elements may age asymmetrically. That is, not only the differential signal generator 110 but also the boundary detector 120 may have an offset. The first offset of the differential signal generator 110 and the second offset of the boundary detector 120 may be reflected in the signal level difference between the boundary signals VBP and VBN.

Hereinafter, referring to FIGS. 9 to 10C , when the first offset of the differential signal generator 110 is compensated for using the boundary signals VBP and VBN, the effect of the second offset of the boundary detector 120 is described. A removable receiver is described.

9 is a diagram illustrating a receiver according to an embodiment of the present invention.

Referring to FIG. 9 , the receiver 200 includes a differential signal generator 210, a boundary detector 220, a comparator 230, a voting unit 240, an up-down counter 250, and a plurality of DACs 260 and 270. can include

The differential signal generator 210, the boundary detector 220, the comparator 230, the voting unit 240, and the plurality of DACs 260 and 270 are the differential signal generator 110 and the boundary detector described with reference to FIG. 120, the comparator 130, the voting unit 140, and the plurality of DACs 160 and 170 may operate in substantially the same manner.

The differential signal generator 210 and the boundary detector 220 may include paired elements. Asymmetry may occur in the differential signal generator 210 and the boundary detector 220 due to mismatch or asymmetric aging of paired devices. That is, a first offset may occur in the differential signal generator 210 and a second offset may occur in the boundary detector 220 . In FIG. 9 , an offset voltage that may be generated by a first offset is shown as a first offset voltage (Voff1), and an offset voltage that may be generated by a second offset is shown as a second offset voltage (Voff2).

According to an embodiment of the present invention, the receiver 200 twists the differential signals VSP and VSN at the input terminal 215 of the boundary detector 220 and twists the boundary signals VBP and VBN at the output terminal 225. can do. The receiver 200 performs first offset compensation in an untwisted state of the input terminal 215 and the output terminal 225, and performs secondary offset compensation in a twisted state of the input terminal 215 and the output terminal 225. can be performed. Also, the receiver 200 may obtain a final offset compensation result in which the effect of the second offset is canceled by using the first offset compensation result and the second offset compensation result.

The up-down counter 250 may include flip-flops 251 and 252 , an arithmetic unit 253 and a multiplexer 254 . The flip-flops 251 and 252 may store a first count value according to the first offset correction and a second count value according to the second offset correction, and the operation unit 253 may store the first count value and the second count value Based on this, the final count value may be determined, and the multiplexer 254 may selectively output the first count value, the second count value, or the final count value. The count value output from the multiplexer 254 may be used to output a reference voltage Vref and compensation voltages VCP and VCN in the plurality of DACs 260 and 270 .

According to an embodiment of the present invention, the receiver 200 can more accurately compensate for the offset of the differential signal generator 110 using the boundary signals VBP and VBN.

10A to 10C are diagrams for explaining in detail an offset compensation method of a differential signal generator according to an embodiment of the present invention.

10A is a diagram for explaining an operation of the receiver 200 in an untwisted state of the input terminal 215 and the output terminal 225 of the boundary detector 220.

In the untwisted state, in the input terminal 215 of the boundary detector 220, the positive signal VSP may be input to the first terminal and the negative signal VSN may be input to the second terminal. Also, in the output terminal 225 of the boundary detector 200, the positive boundary signal VBP may be input to the first terminal and the negative boundary signal VBN may be input to the second terminal.

In the untwist state, the signal level difference between the boundary signals VBP and VBN may correspond to the sum of the first offset voltage Voff1 and the second offset voltage Voff2.

The receiver 200 may perform first offset compensation over several detection periods in an untwisted state. The up-down counter 250 increases or decreases the count value based on the offset result signal generated for each detection period, and outputs the counter value through the multiplexer 254, thereby generating the reference signal Vref and the compensation signals VCP and VCN. can be adjusted. The up-down counter 250 may perform first offset compensation until the signal level difference between the boundary signals VBP and VBN is offset. The up-down counter 250 may store a first count value after the first offset compensation is completed in the first flip-flop 251 .

10B is a diagram for explaining an operation of the receiver 200 in a twisted state of the input terminal 215 and the output terminal 225 of the boundary detector 220.

In the twisted state, at the input terminal 215 of the boundary detector 220, the negative signal VSN may be input to the first terminal and the positive signal may be input to the second terminal. Also, in the output terminal 225 of the boundary detector 200, the negative boundary signal VBN may be input to a first terminal, and the positive boundary signal VBP may be input to a second terminal.

In the twisted state, the signal level difference between the boundary signals VBP and VBN may correspond to a difference between the first offset voltage Voff1 and the second offset voltage Voff2.

The receiver 200 may perform secondary offset compensation over several detection periods in a twisted state. The up-down counter 250 increases or decreases the count value based on the offset result signal generated for each detection period, and outputs the counter value through the multiplexer 254, thereby generating the reference signal Vref and the compensation signals VCP and VCN. can be adjusted. The up-down counter 250 may perform secondary offset compensation until the difference between the boundary signals VBP and VBN is canceled. A second count value after the secondary offset compensation is completed may be stored in the second flip-flop 252 .

Since offsets between the boundary signals VBP and VBN may be different in the untwisted state and the twisted state, the first count value and the second count value may have different values. The receiver 200 may determine a final count value based on the first count value and the second count value.

10C is a diagram for explaining an operation in which the receiver 200 determines a final count value based on a first count value and a second count value.

The up-down counter 250 sums the first count value stored in the first flip-flop 251 and the second count value stored in the second flip-flop 252 using the arithmetic unit 253, and converts the summed value to '2'. ' to create the final count value. In the final count value, the influence of the second offset Voff2 may be offset. The up-down counter 250 may output the final count value through the multiplexer 254, and the plurality of DACs 260 and 270 generate the reference voltage Vref and compensation voltages VCP and VCN based on the final count value. ) can be output.

According to an embodiment of the present invention, when the receiver 200 performs offset compensation of the differential signals VSP and VSN, the effect of the second offset of the boundary detector 220 can be removed. Therefore, the noise margin of the differential signals VSP and VSN can be further improved.

Meanwhile, in FIGS. 1 to 10C , the present invention has been described taking a case in which a differential signal has two levels as an example, but the present invention is not limited thereto. For example, a receiver according to an embodiment of the present invention may perform offset compensation of a differential signal even when the differential signal is a signal having three or more levels, such as PAM-3 and PAM-4.

Hereinafter, an offset compensation method of a differential signal generator according to an embodiment of the present invention will be described with reference to FIGS. 11A to 11C.

11A is a graph showing the signal level of the single-ended signal VRX over time. In the example of FIG. 11A , the single-ended signal VRX may be a PAM-4 signal having four signal levels. For example, each of the four signal levels may be mapped to one of '00', '01', '10', and '11'. The single-ended signal VRX may have one level among the four signal levels in one cycle. That is, the single-ended signal VRX can transmit two bit signals in one cycle.

Even when the single-ended signal VRX is a PAM-4 signal, the differential signals VSP and VSN may be generated based on the single-ended signal VRX and the reference signal Vref.

11B is a graph showing signal levels of differential signals VSP and VSN with offsets over time. As described with reference to FIG. 2C , when there is an offset in the differential signal generator, an offset voltage may be generated in the differential signals VSP and VSN. In the example of FIG. 11B , the DC level of the positive signal VSP may be higher than that of the negative signal VSN, and the differential signals VSP and VSN may have positive offset voltages.

Even in the case of the differential signals VSP and VSN having three or more levels, the polarity of the offset voltage of the differential signals VSP and VSN may be determined based on the difference between the minimum levels VSP_min and VSN_min of the differential signals. According to an embodiment of the present invention, the receiver may determine whether the differential signals VSP and VSN have a positive offset voltage or a negative offset voltage using the boundary detector as described in FIGS. 4 and 5 there is. The receiver increases or decreases the count value of the counter according to whether the differential signals VSP and VSN have a positive offset voltage or a negative offset voltage, thereby determining the reference voltage Vref and the compensation voltages VCP and VCN. level can be adjusted.

11C is a graph illustrating the levels of a reference voltage (Vref) and compensation voltages (VCP, VCN) for compensating the offset of the differential signal generator. When the differential signals VSP and VSN have positive offset voltages, the offset voltage difference can be reduced by increasing the level of the reference voltage Vref. Alternatively, the offset voltage difference may be reduced by lowering the level of the positive compensation signal VCP and increasing the level of the negative compensation signal VCN.

12 to 13 are diagrams for explaining an effect of offset compensation according to an embodiment of the present invention.

12 illustrates an eye diagram of a PAM-4 signal. Referring to FIG. 12 , a PAM-4 signal may have one level among four signal levels (LV1-LV4) in one signal period (1 UI). The level of the PAM-4 signal in one signal period (1UI) can be determined by comparing the signal in the corresponding signal period with the reference voltages Vref1, Vref2, and Vref3. As the margin between adjacent signal levels increases and the margins become even, the signal and the reference voltages Vref1, Vref2, and Vref3 can be more accurately distinguished. The evenness of the margin between adjacent signal levels may be referred to as RLM (Ratio of Level Separation Mismatch).

13A to 13C are simulation data showing the effect of offset compensation according to an embodiment of the present invention.

13A shows the count value determined by the up-down counter according to the offset value ΔVth of the differential signal generator. In FIG. 13A , a positive offset value may generate a positive offset voltage in the differential signals VSP and VSN, and a negative offset value may generate a negative offset voltage in the differential signals VSP and VSN.

In the example of FIG. 13A , the count value may increase according to the offset value ΔVth of the differential signal generator. That is, as the offset value ΔVth has a larger value in the positive direction, the reference voltage Vref and the negative compensation voltage VCN are upwardly adjusted, and the positive compensation voltage VCP is downwardly adjusted so that the differential signals VSP and VSN are adjusted downward. ) can be compensated for.

13B shows RLM before and after offset compensation according to an embodiment of the present invention according to an offset value (ΔVth) of a differential signal generator.

The RLM before offset compensation has a maximum value when the offset value ΔVth has a specific value, and the RLM may greatly decrease when the offset value ΔVth deviate from the specific value. On the other hand, according to an embodiment of the present invention, since the reference voltage (Vref) and the compensation voltages (VCN, VCP) can be adjusted according to the offset value, RLM is high regardless of the offset value (ΔVth) of the differential signal generator. can be maintained as

13C shows margins before and after offset compensation according to an embodiment of the present invention according to an offset value (ΔVth) of a differential signal generator.

The margin before offset compensation has a maximum value when the offset value ΔVth has a specific value, and the RLM may greatly decrease when the offset value ΔVth deviate from the specific value. On the other hand, since the reference voltage Vref and the compensation voltages VCN and VCP can be adjusted according to the offset value, the margin can be maintained at a high level regardless of the offset value ΔVth of the differential signal generator.

In short, according to an embodiment of the present invention, the offset voltages of the differential signals VSP and VSN can be effectively reduced regardless of the offset value of the differential signal generator. That is, the offset of the differential signal generator can be compensated for, and the margin and RLM of the receiver can be improved.

The present invention is not limited by the above-described embodiments and accompanying drawings, but is intended to be limited by the appended claims. Therefore, various forms of substitution, modification, and change will be possible by those skilled in the art within the scope of the technical spirit of the present invention described in the claims, which also falls within the scope of the present invention. something to do.

100, 200: receiver
110, 210: differential signal generator
120, 220: boundary detector
130, 230: comparator
140, 240: boating unit
150, 250: up-down counter
160, 170, 260, 270: DAC

Claims (10)

In the receiver,
a differential signal generator for receiving a single ended signal and generating a differential signal based on the single ended signal, a reference signal and a pair of compensation signals;
a positive charging circuit for charging the first node to a power level during a logic high period of the clock signal;
a negative charging circuit for charging a second node to a power level during a logic high period of the clock signal;
a positive discharge circuit for discharging the first node according to a signal level of a positive signal included in the differential signal in a logic low period of the clock signal;
a negative discharge circuit for discharging the second node according to a signal level of a negative signal that is a complementary signal of the positive signal in a logic low period of the clock signal;
a comparator outputting an offset detection signal of the differential signal by comparing the signal level of the first node and the signal level of the second node; and
An offset compensator inputting a reference signal adjusted based on the offset detection signal obtained from the comparator and a pair of compensation signals to the differential signal generator.
A receiver comprising a.
According to claim 1,
The comparator
In the logic low period, a plurality of offset detection signals are output by comparing the signal level of the first node and the signal level of the second node a plurality of times.
receiving set.
According to claim 1,
The comparator
Outputting an offset detection signal indicating a positive offset voltage when the signal level of the first node is greater than the signal level of the second node.
receiving set.
According to claim 1,
A length of a logic low period of the clock signal is longer than a length of a signal period of the differential signal.
receiving set.
According to claim 4,
The positive discharge circuit discharges the first node over a plurality of signal periods of a differential signal having one level among two or more levels in one signal period in a logic low period of the clock signal;
The negative discharge circuit discharges the second node over a plurality of signal periods of the differential signal in a logic low period of the clock signal;
The difference between the signal levels of the first node and the second node at which discharge is terminated corresponds to the level difference between the positive signal and the negative signal.
receiving set.
According to claim 1,
The positive charging circuit
A first transistor that is a PMOS transistor having a gate connected to the clock signal, a source connected to a power signal, and a drain connected to the first node.
receiving set.
According to claim 6,
The positive discharge circuit
a second transistor that is an NMOS transistor having a gate connected to the clock signal and a source connected to ground;
a third transistor that is a PMOS transistor having a gate connected to the positive signal and a source connected to the first node;
Drains of the second transistor and the third transistor are connected to each other.
receiving set.
According to claim 7,
The second transistor is turned on when the clock signal is in a logic high state,
The third transistor is turned on when the level of the positive signal is less than the difference between the signal level of the first node and the threshold level of the third transistor.
receiving set.
In the receiver,
a differential signal generator for receiving a single ended signal and generating a differential signal based on the single ended signal, a reference signal and a pair of compensation signals;
First and second nodes are charged by receiving power supply voltage in a charging period, and in a discharging period after the charging period, the first node is discharged according to the level of a positive signal among the differential signals, and a negative signal among the differential signals is charged. a boundary detector that discharges the second node according to the level of , outputs the signal of the first node as a positive boundary signal, and outputs the signal of the second node as a negative boundary signal;
a comparator generating a plurality of offset detection signals within the discharge interval by comparing the level of the positive boundary signal and the level of the negative boundary signal;
a voting unit outputting a final offset signal representing the discharge interval using a plurality of offset detection signals obtained from the comparator;
an up-down counter that increments or decrements a count value based on the final offset signal; and
At least one DAC (Digital-Analog Converter) outputting the reference signal and a pair of compensation signals adjusted based on the count value
A receiver comprising a.
In the receiver,
a differential signal generator for receiving a single ended signal and generating a differential signal based on the single ended signal, a reference signal and a pair of compensation signals;
a boundary detector that periodically charges first and second nodes and discharges the charged first and second nodes based on the differential signal to output boundary signals corresponding to a minimum level of the differential signal;
a comparator generating an offset detection signal by comparing levels of the boundary signals;
a voting unit determining an offset polarity of the differential signal using the offset detection signals acquired from the comparator and outputting a final offset signal;
A first count value is determined by increasing or decreasing a count value according to the final offset signals output in an untwisted state of the input and output terminals of the boundary detector, and the input and output terminals of the boundary detector are twisted Determine the second count value by increasing or decreasing the count value according to the final offset signals output from the state, and based on the first count value and the second count value, the final count value in which the effect of the offset of the boundary detector is offset an up-down counter that outputs and
At least one DAC (Digital-Analog Converter) outputting the reference signal and a pair of compensation signals adjusted based on the final count value
A receiver comprising a.

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