KR20230077670A - Layer structures including dielectric layer, methods of manufacturing dielectric layer, electronic device including dielectric layer and electronic apparatus including electronic device - Google Patents

Abstract

Disclosed are a layer structure including a dielectric layer, a method for manufacturing the dielectric layer, an electronic device including the dielectric layer, and an electronic device including the electronic device. The dielectric layer according to an embodiment has a dielectric constant greater than that of silicon oxide, is provided to reinforce an undoped first layer and a rutile phase of the first layer, and is provided outside the first layer. It includes a second layer provided and a third layer provided to increase a band gap of the first layer and provided outside the first and second layers. A method of manufacturing a dielectric layer according to an embodiment includes a process of forming a dielectric layer having a permittivity greater than that of silicon oxide, a process of forming a phase stabilization layer for stabilizing a rutile phase of the dielectric layer, and a band gap of the dielectric layer. It includes a process of forming a high band gap layer for heightening.

Description

Layer structures including dielectric layer, methods of manufacturing dielectric layer, electronic device including dielectric layer and electronic apparatus including electronic device }

The present disclosure relates to a semiconductor material and an electronic device including the same, and more particularly, to a layer structure including a dielectric layer, a manufacturing method thereof, an electronic device including the dielectric layer, and an electronic device including the same.

In an environment where the degree of integration of semiconductor devices increases, line widths and thicknesses of layers constituting semiconductor devices are reduced. When the thickness of a dielectric layer used in a memory device (eg, DRAM) is thinned, leakage current characteristics may be lowered, and thus operational reliability of the memory device may be lowered. Therefore, in the case of a dielectric layer used in a memory device, an appropriate permittivity and low leakage current are required while maintaining a thin thickness.

Exemplary embodiments provide a dielectric layer capable of maintaining an appropriate permittivity even in a thin environment.

Exemplary embodiments provide a dielectric layer capable of preventing degradation of leakage current characteristics even in a highly integrated environment.

An exemplary embodiment provides a method for manufacturing such a dielectric layer.

An exemplary embodiment provides an electronic device including such a dielectric layer.

An exemplary embodiment provides an electronic device including such an electronic device.

The dielectric layer according to an exemplary embodiment has a dielectric constant greater than that of silicon oxide, is provided to reinforce an undoped first layer and a rutile phase of the first layer, and is provided outside the first layer. and a third layer provided to increase the band gap of the first layer and provided outside the first and second layers.

In one example, the first layer may be provided between the second layer and the third layer, and the three layers may be sequentially stacked.

In one example, the first layer is symmetrical about the second layer, and the third layer is on at least one side of the first side and the second side of the first laminate composed of the first and second layers. may be provided.

In one example, the first layer may be provided under and above the second layer and may be in contact with the second layer.

In one example, the first layer may be provided below and above the third layer and may be in contact with the third layer.

In one example, the second layer and the third layer are in contact with each other, and the first layer is on at least one side of a first side and a second side of a second laminate composed of the contacted second and third layers. may be provided.

In one example, a plurality of second layers may exist, and the first layer may be provided between the plurality of second layers.

In one example, a plurality of third layers may exist, and the first layer may be provided between the plurality of third layers.

In one example, one of the plurality of second layers and one of the plurality of third layers may be in contact with each other.

In one example, at least one of the second layer and the third layer may be embedded in the first layer.

In one example, the dielectric layer further includes a fourth layer provided to increase a band gap of the first layer, and the fourth layer is formed on the first side and the second layer of the third stack including the first to third layers. It may be provided on at least one side of the side. A plurality of second layers may exist, and the first layer may be provided between the plurality of second layers. A plurality of third layers may exist, and the first layer may be provided between the plurality of third layers.

A method of manufacturing a dielectric layer according to an exemplary embodiment includes forming a dielectric layer having a dielectric constant greater than that of silicon oxide, but forming it without doping, and a phase stabilization layer for stabilizing the rutile phase of the dielectric layer outside the dielectric layer. and forming a first high band gap layer outside the dielectric layer and the phase stabilization layer to increase the band gap of the dielectric layer.

In one example, the phase stabilization layer may be formed before forming the dielectric layer. The process of forming the dielectric layer, the process of forming the phase stabilization layer, and the process of forming the first high band gap layer may be sequentially performed. The dielectric layer may be formed by sequentially stacking a plurality of dielectric material layers. The phase stabilization layer and the first high band gap layer may be formed between the plurality of dielectric material layers. One layer and the other of the phase stabilization layer and the first high band gap layer may be sequentially formed and contact each other.

In one example, the phase stabilization layer and the first high band gap layer may be formed to be buried in the dielectric layer. At least one of the phase stabilization layer and the first high band gap layer may include a plurality of sequentially stacked layers, and the dielectric layer may also be formed between the plurality of layers.

In one example, the phase stabilization layer and the first high band gap layer may be alternately stacked repeatedly. A portion of the phase stabilization layer and a portion of the first high band gap layer may contact each other.

In one example, the forming of the first high band gap layer may include at least one of forming the first high band gap layer earlier than the other two processes and forming the first high band gap layer later than the other two processes. may include a course.

The manufacturing method may further include forming a second high band gap layer for increasing a band gap of the dielectric layer.

In one example, the process of forming the second high band gap layer may include at least one of forming the second high band gap layer earlier than the three processes and forming the second high band gap layer later than the three processes. may include a course.

The first high band gap layer and the second high band gap layer may be formed of different materials.

An electronic device including a dielectric layer according to an exemplary embodiment includes a substrate including first and second doped regions spaced apart from each other, a gate insulating layer provided on the substrate between the first and second doped regions, and and a gate electrode provided on the gate insulating layer, and the gate insulating layer includes the dielectric layer according to the exemplary embodiment.

The dielectric layer may further include a fourth layer provided to increase a band gap of the first layer.

A memory device including a dielectric layer according to an exemplary embodiment includes a transistor including a source, a drain, and a gate electrode, and a data storage element connected to the transistor, wherein the data storage element comprises the dielectric layer according to the exemplary embodiment. include

In one example, the data storage element may include a lower electrode connected to the transistor, an upper electrode facing the lower electrode, and the dielectric layer provided between the upper electrode and the lower electrode.

An electronic device according to an exemplary embodiment includes an electronic device provided to control the flow of an electrical signal, wherein the electronic device includes an electronic device including a dielectric layer according to the exemplary embodiment.

The disclosed dielectric layer includes a phase stabilization layer for stably maintaining a phase of the TiO2 layer as a rutile phase having a relatively high permittivity by using the TiO2 layer as a base layer, and preventing the leakage current characteristics of the TiO2 layer from deteriorating. and/or a material layer having a higher band gap than TiO2. The disclosed dielectric layer can be regarded as a composite dielectric layer, and by using such a dielectric layer, leakage current characteristics while maintaining the dielectric constant of the dielectric layer at a high dielectric constant even in a highly integrated environment in which the thickness of the dielectric layer is thin, for example, in an environment in which the thickness of the dielectric layer is thinned to 10 nm or less Deterioration can also be prevented.

Therefore, in the case of an electronic device and device to which the disclosed dielectric layer is applied, operation characteristics of the device can be stably maintained even in a high integration environment, and thus operation reliability of the device can be increased.

1 is a cross-sectional view showing a layer structure including a dielectric layer according to an embodiment.
2 to 7 are graphs showing simulation results performed to confirm electrical characteristics of a dielectric layer included in the layer structure of FIG. 1 .
8 to 31 are cross-sectional views illustrating various embodiments of the layer structure of FIG. 1 .
32 is a cross-sectional view of a first electronic device (first transistor) including a layer structure or a dielectric layer included in the layer structure according to an embodiment.
33 is a cross-sectional view of a memory device including a layer structure or a dielectric layer included in the layer structure according to an embodiment.
34 is a cross-sectional view of a second electronic device (second transistor) including a layer structure or a dielectric layer included in the layer structure according to an embodiment.
FIG. 35 is a cross-sectional view of FIG. 34 cut along the 35-35' direction.
FIG. 36 is a cross-sectional view of FIG. 34 cut in the direction 36-36'.
37 is a cross-sectional view of a third electronic device (third transistor) including a layer structure or a dielectric layer included in the layer structure according to an embodiment.
FIG. 38 is a cross-sectional view of FIG. 37 cut along the 38-38' direction.
FIG. 39 is a cross-sectional view of FIG. 37 cut in the direction 39-39'.
40 is a cross-sectional view of a fourth electronic device (fourth transistor) including a layer structure or a dielectric layer included in the layer structure according to an embodiment.
41 is a cross-sectional view of FIG. 40 cut in the direction 41-41'.
42 is a cross-sectional view of FIG. 40 cut in the direction 42-42'.
Fig. 43 is a schematic diagram illustrating an electronic device according to another exemplary embodiment.
Fig. 44 is a top plan view of an electronic device according to another exemplary embodiment.
Fig. 45 is a cross-sectional view taken along the line A-A' of Fig. 44;
46 is a schematic block diagram of a display device including a display driver IC (DDI) and an electronic element including a layer structure including a dielectric layer according to an exemplary embodiment.
47 is a circuit diagram of a CMOS inverter provided with an electronic device including a layer structure including a dielectric layer according to an exemplary embodiment.
48 is a circuit diagram of a CMOS SRAM device including an electronic device including a layer structure including a dielectric layer according to an exemplary embodiment.
49 is a circuit diagram of a CMOS NAND circuit with an electronic device including a layer structure with a dielectric layer according to an exemplary embodiment.
50 is a block diagram of an electronic system including an electronic device including a layer structure including a dielectric layer according to an exemplary embodiment.
51 is a block diagram of an electronic system including an electronic device including a layer structure including a dielectric layer according to an exemplary embodiment.
52 to 60 are cross-sectional views showing step-by-step methods of manufacturing a layer structure including a dielectric layer according to an exemplary embodiment.

Hereinafter, a layer structure including a dielectric layer according to an exemplary embodiment, a manufacturing method thereof, an electronic device including the dielectric layer, and an electronic device including the same will be described in detail with reference to the accompanying drawings. In the following description, thicknesses of layers or regions shown in drawings may be slightly exaggerated for clarity of the specification. In addition, the embodiments described below are merely illustrative, and various modifications are possible from these embodiments. In addition, in the layer structure described below, the expressions described as "upper part" or "upper part" may include not only what is directly on top of but also what is on top of non-contact. In the description below, like reference numerals in each drawing denote like members.

1 shows a first layer structure 100 including a dielectric layer according to an exemplary embodiment.

Referring to FIG. 1 , a layer structure 100 including a dielectric layer according to an embodiment includes a first material layer 120, a dielectric layer 130, and a second material layer 140 sequentially stacked.

In one example, the first material layer 120 may be or include a conductive layer, a layer including a semiconductor, or a semiconductor layer. The conductive layer may include a metal layer or a conductive metal oxide layer, or may include such a metal layer or metal oxide layer. In one example, the conductive layer is a RuO2 layer including a rutile phase, an IrO2 layer, a Ta doped SnO2 layer, a Nb doped SnO2 layer, a PtO2 layer, a PdO2 layer, a ReO2 layer, a MoO2 layer, a WO2 layer, a TaO2 layer. , NbO 2 layer and at least one of a TiN layer. For example, the first material layer 120 may be formed of one layer selected from among the material layers listed as the conductive layer, or may be formed by sequentially stacking two or three selected layers. The semiconductor layer may include a compound semiconductor layer or a non-compound semiconductor layer. The semiconductor layer may or may not be doped with a dopant. In one example, when the first material layer 120 includes a semiconductor layer, a channel or path for carrier movement may exist between the first material layer 120 and the dielectric layer 130 . In one example, the first material layer 120 may be used as an electrode layer.

The dielectric layer 130 may be a layered structure capable of reducing leakage current while stably maintaining a phase having a high dielectric constant or a composite dielectric layer having a layered structure. The phase having the high dielectric constant may be a rutile phase. The dielectric layer 130 is present on one surface of the first material layer 120 and may directly contact the one surface. The one surface of the first material layer 120 may be an upper surface, but depending on the viewpoint of the layer structure 100, the one surface may be a side surface, a lower surface, or an inclined surface. The dielectric layer 130 may include a given dielectric material, but may have a layer structure or layer configuration provided to have a band gap different from that of the given dielectric material. For example, the dielectric layer 130 is a composite dielectric layer including titanium oxide (TiO 2 ) as the given dielectric material, and may have a layer structure or layer configuration having a band gap larger than that of the titanium oxide. The dielectric layer 130 is the composite dielectric layer and may have a layer structure or layer structure including a material for lowering leakage current.

Accordingly, the dielectric layer 130 may have leakage current characteristics superior to those of the given dielectric material. That is, the leakage current of the dielectric layer 130 may be smaller than the leakage current of the given dielectric material.

In one example, the dielectric layer 130 may have a layer structure or a layered structure provided to have a rutile phase that is more stable than titanium oxide while having a high dielectric constant corresponding to the rutile phase of titanium oxide.

The layer structure of the dielectric layer 130 may include a plurality of layers. For example, the dielectric layer 130 may include seven sequentially stacked layers 13a, 13b, 13c, 13d, 13e, 13f, and 13g, but the number of layers may be increased or decreased.

In one example, the layer structure including the seven layers 13a, 13b, 13c, 13d, 13e 13f, and 13g has a second layer 13b on one side of the first layer 13a, and A third layer 13c is present on one side of the second layer 13b, a fourth layer 13d is present on one side of the third layer 13c, and one side of the fourth layer 13d is present. A fifth layer 13e is present on the top, a sixth layer 13f is present on one side of the fifth layer 13e, and a seventh layer 13g is on one side of the sixth layer 13f. This may include existing layer configurations.

In one example, the second layer 13b is outside the first layer 13a, may directly contact the one surface of the first layer 13a, and covers all or part of the one surface. It can be. In one example, the third layer 13c is outside the second layer 13b, may directly contact the one surface of the second layer 13b, and covers all or part of the one surface. It can be. In one example, the fourth layer 13d is outside the third layer 13c, may directly contact the one surface of the third layer 13c, and covers all or part of the one surface. It can be. In one example, the fifth layer 13e is outside the fourth layer 13d, may directly contact the one surface of the fourth layer 13d, and covers all or part of the one surface. It can be. In one example, the sixth layer 13f is outside the fifth layer 13e, can directly contact the one surface of the fifth layer 13e, and covers all or part of the one surface. It can be. In one example, the seventh layer 13g is outside the sixth layer 13f, can directly contact the one surface of the sixth layer 13f, and covers all or part of the one surface. It can be. In one example, the one surface of the first to seventh layers 13a to 13g may be an upper surface, but may also be a bottom surface, a side surface, or an inclined surface depending on a point of view.

The first layer 13a of the dielectric layer 130 may be formed on the one surface of the first material layer 120 and directly contact the one surface. The first layer 13a may cover all or part of the one surface of the first material layer 120 .

The first layer 13a may have a first thickness 4T1.

In one example, the first layer 13a may be a material layer (hereinafter referred to as a first high band gap layer) provided to increase the band gap of the dielectric layer 130 than the titanium oxide layer, or may include such a material layer. The first high band gap layer may have a band gap greater than that of the titanium oxide layer. The first high band gap layer may serve to increase a band gap of the dielectric layer 130 higher than that of the titanium oxide layer. The first high band gap layer may be a single layer or may include multiple layers made of different material layers. When the first high band gap layer is a plurality of layers, the layers may be sequentially and continuously stacked in contact with each other or sequentially stacked in non-contact with each other. In one example, the first high band gap layer is a material layer having a larger band gap than titanium oxide, and includes a hafnium oxide (HfO 2 ) layer, a zirconium oxide (ZrO 2 ) layer, and a mixed layer (Hf _x Zr _1-x O ₂ ) thereof. It may be one layer or may include such layers. The first high band gap layer may act as a layer that improves leakage current characteristics of the dielectric layer 130, that is, a layer that suppresses leakage current. Accordingly, the first high band gap layer may be referred to as a leakage current suppression layer or a leakage current reduction layer.

In one example, the first layer 13a may be a rutile-phase titanium oxide (eg, TiO2) layer having a high dielectric constant or may include such a titanium oxide layer. In this case, the first layer 13a may be undoped.

In one example, the first layer 13a may be or include another material layer (hereinafter referred to as a second high band gap layer) prepared to increase the band gap of the dielectric layer 130 than the titanium oxide layer. The second high band gap layer together with the first high band gap layer or alone may serve to increase the band gap of the dielectric layer 130 higher than that of the titanium oxide layer. The second high band gap layer may be a single layer or a plurality of layers, and in the case of a plurality of layers, may be sequentially stacked in contact with each other or sequentially stacked in non-contact with each other. For example, the second high band gap layer is a material layer having a larger band gap than the titanium oxide layer, and may include or include at least one of an Al2O3 layer, a Y2O3 layer, and a MgO layer, but is not limited to these layers. The first and second high band gap layers may be different material layers. Like the first high band gap layer, the second high band gap layer can also act as a layer that improves leakage current characteristics of the dielectric layer 130, that is, a layer that suppresses leakage current. Accordingly, the second high band gap layer may also be referred to as a leakage current suppression layer or a leakage current reduction layer.

In one example, the first layer 13a may be or include a layer provided to stabilize or reinforce the rutile phase of the titanium oxide layer (hereinafter referred to as a phase stabilization layer). The phase stabilization layer may also be expressed as a phase reinforcement layer. In one example, the first layer 13a may be one of material layers having a stable rutile phase, for example, or may include at least one of a SnO 2 layer, a GaO 2 layer, a GeO 2 layer, and a SiO 2 layer. there is. When the first layer 13a serves as a layer for stabilizing the rutile phase of the titanium oxide layer, a titanium oxide layer having a rutile phase may be directly formed on the first layer 13a.

The material composition of the second layer 13b may also vary depending on the role or function of the first layer 13a.

Also, the thickness 4T1 of the first layer 13a may vary according to the role or function of the first layer 13a. For example, when the first layer 13a is a rutile-phase titanium oxide layer having a high dielectric constant, the thickness 4T1 of the first layer 13a is greater than when the first layer 13a is used as a phase stabilization layer or a high band gap layer. They can all be thick.

The second layer 13b of the dielectric layer 130 has a second thickness 4T2. The second thickness 4T2 may be the same as or different from the first thickness 4T1. The second layer 13b may be one of a rutile-phase titanium oxide layer having a high dielectric constant, the phase stabilization layer, and the second high band gap layer. In one example, when the second layer 13b is a rutile-phase titanium oxide layer having a high dielectric constant, the second layer 13b may be undoped. The role or action of the second layer 13b may vary depending on the material layer used as the first layer 13a. In one example, when the first layer 13a is the first high band gap layer, the second layer 13b may be one of a rutile-phase titanium oxide layer, the phase stabilization layer, and the second high band gap layer. In one example, when the first layer 13a is a rutile-phase titanium oxide layer, the second layer 13b may be one of the rutile-phase titanium oxide layer, the phase stabilization layer, and the second high band gap layer. In one example, when the first layer 13a is the phase stabilization layer, the second layer 13b may be one of a rutile-phase titanium oxide layer and the second high band gap layer. In one example, when the first layer 13a is the second high band gap layer, the second layer 13b may be one of a rutile-phase titanium oxide layer and the phase stabilization layer. As such, the second thickness 4T2 of the second layer 13b may vary as the material properties of the second layer 13b vary. For example, the second thickness 4T2 when the second layer 13b is a rutile-phase titanium oxide layer may be greater than the thickness when the second layer 13b is a phase stabilization layer or a second high band gap layer.

The third layer 13c of the dielectric layer 130 has a third thickness 4T3. The third thickness 4T3 may be the same as or different from the second thickness 4T2. The third layer 13c may be one of a rutile-phase titanium oxide layer having a high dielectric constant, the phase stabilization layer, and the second high band gap layer. In one example, when the third layer 13c is a rutile-phase titanium oxide layer having a high dielectric constant, the third layer 13c may be undoped. The role or function of the third layer 13c may be different depending on the material properties of the second layer 13b. For example, when the second layer 13b is a rutile-phase titanium oxide layer, the third layer 13c may be one of the rutile-phase titanium oxide layer, the phase stabilization layer, and the second high band gap layer. In one example, when the second layer 13b is the phase stabilization layer, the third layer 13c may be one of a rutile-phase titanium oxide layer and the second high band gap layer. In one example, when the second layer 13b is the second high band gap layer, the third layer 13c may be one of a rutile-phase titanium oxide layer and the phase stabilization layer. In this way, as the material properties of the second layer 13b change, the third thickness 4T3 of the third layer 13c may also vary. For example, the third thickness 4T3 when the third layer 13c is a rutile-phase titanium oxide layer may be greater than the thickness when the third layer 13c is a phase stabilization layer or a second high band gap layer.

The fourth layer 13d of the dielectric layer 130 has a fourth thickness 4T4. The fourth layer 13d may be one of a rutile-phase titanium oxide layer having a high dielectric constant, the phase stabilization layer, and the second high band gap layer. In one example, when the fourth layer 13d is a rutile-phase titanium oxide layer having a high dielectric constant, the fourth layer 13d may be undoped. The role or function of the fourth layer 13d may vary depending on the material used for the third layer 13c. For example, when the third layer 13c is a rutile-phase titanium oxide layer, the fourth layer 13d may be one of the rutile-phase titanium oxide layer, the phase stabilization layer, and the second high band gap layer. In one example, when the third layer 13c is the phase stabilization layer, the fourth layer 13d may be one of a rutile-phase titanium oxide layer and the second high band gap layer. In one example, when the third layer 13c is the second high band gap layer, the fourth layer 13d may be one of a rutile-phase titanium oxide layer and the phase stabilization layer. As described above, the fourth thickness 4T4 of the fourth layer 13d may vary as the material properties of the fourth layer 13d vary. For example, the fourth thickness 4T4 when the fourth layer 13d is a rutile-phase titanium oxide layer may be greater than the thickness when the fourth layer 13d is a phase stabilization layer or a second high band gap layer.

The fifth layer 13e of the dielectric layer 130 has a fifth thickness 4T5.

The fifth layer 13e may be one of a rutile-phase titanium oxide layer having a high dielectric constant, the phase stabilization layer, and the second high band gap layer. In one example, when the fifth layer 13e is a rutile-phase titanium oxide layer having a high dielectric constant, the fifth layer 13e may be undoped. The role or action of the fifth layer 13e may vary depending on the material used for the fourth layer 13d. For example, when the fourth layer 13d is a rutile-phase titanium oxide layer, the fifth layer 13e is one of the rutile-phase titanium oxide layer, the phase stabilization layer, and the second high band gap layer, or the phase stabilization layer. and the second high band gap layer.

When the fourth layer 13d is the phase stabilization layer, the fifth layer 13e may be one of a rutile-phase titanium oxide layer and the second high band gap layer. In one example, when the fourth layer 13d is the second high band gap layer, the fifth layer 13e may be one of a rutile-phase titanium oxide layer and the phase stabilization layer. As such, when the material property of the fifth layer 13e is changed, the fifth thickness 4T5 of the fifth layer 13e may also be changed. For example, the fifth thickness 4T5 when the fifth layer 13e is a phase stabilization layer may be smaller than the thickness when the fifth layer 13e is a second high band gap layer.

The sixth layer 13f of the dielectric layer 130 has a sixth thickness 4T6.

The sixth layer 13f may be one of a rutile-phase titanium oxide layer having a high dielectric constant, the phase stabilization layer, and the second high band gap layer. In one example, when the sixth layer 13f is a rutile-phase titanium oxide layer having a high dielectric constant, the sixth layer 13f may be undoped. The role or action of the sixth layer 13f may vary depending on the material used for the fifth layer 13e. For example, when the fifth layer 13e is a rutile-phase titanium oxide layer, the sixth layer 13f is one of the rutile-phase titanium oxide layer, the phase stabilization layer, and the second high band gap layer, or the phase stabilization layer. and the second high band gap layer.

When the fifth layer 13e is the phase stabilization layer, the sixth layer 13f may be one of a rutile-phase titanium oxide layer and the second high band gap layer. In one example, when the fifth layer 13e is the second high band gap layer, the sixth layer 13f may be one of a rutile-phase titanium oxide layer and the phase stabilization layer. As such, when the material property of the sixth layer 13f is changed, the sixth thickness 4T6 of the sixth layer 13f may also be changed. For example, the sixth thickness 4T6 when the sixth layer 13f is a phase stabilization layer or a second high band gap layer may be smaller than a thickness when the sixth layer 13f is a rutile-phase titanium oxide layer.

The seventh layer 13g of the dielectric layer 130 has a seventh thickness 4T7.

The seventh layer 13g may have a high dielectric constant. The role or function of the seventh layer 13g may be determined in consideration of a material used as the sixth layer 13f. In one example, when the sixth layer 13f includes one of the rutile-on-titanium oxide layer, the phase stabilization layer, and the second high band gap layer, the seventh layer 13g includes a rutile-on-titanium oxide layer, the A phase stabilization layer, one of the first high band gap layer and the second high band gap layer may be included. The material of the sixth layer 13f and the material of the seventh layer 13g may be the same or different from each other. In one example, when the seventh layer 13g is a rutile-phase titanium oxide layer having a high dielectric constant, the seventh layer 13g may be undoped.

When the material property of the seventh layer 13g is changed, the seventh thickness 4T7 of the seventh layer 13g may also be changed. For example, the seventh thickness 4T7 when the seventh layer 13g is a rutile-phase titanium oxide layer or the first high band gap layer may be greater than a thickness when the seventh layer 13g is the phase stabilization layer. .

The total thickness T1 of the dielectric layer 130 may be determined in consideration of the degree of integration of an electronic device or electronic device to which the dielectric layer 130 or the layer structure 100 is applied. In one example, the thickness T1 of the dielectric layer 130 may be 100 Å (10 nm) or less or 60 Å (6 nm) or less, but may not be limited to this value. The thickness of the rutile-on-titanium oxide layer included in the dielectric layer 130, that is, the sum of the thicknesses of the rutile-on-titanium oxide layers included in each layer 13a, 13b, 13c, 13d, 13e, 13f, and 13g is the dielectric layer 130 may be smaller than the thickness T1 of In one example, the sum of the thicknesses of the rutile-phase titanium oxide layers included in each layer may be 40% or more or 50% or more of the thickness T1 of the dielectric layer 130 .

In the dielectric layer 130 , the phase stabilization layer and/or the second high band gap layer may be disposed between the titanium oxide layer of the rutile phase, or vice versa. In one example, a rutile-phase titanium oxide layer may be disposed between the phase stabilization layers, between the second high band gap layers, or between the phase stabilization layers and the second high band gap layers. In any case, the phase stabilization layer may be provided to directly contact the titanium oxide layer of the rutile phase.

In the material layer composed of the entire titanium oxide layer and the phase stabilization layer in the dielectric layer 130, the content of the main component (A1) of the phase stabilization layer [A1/(Ti+A1)] may be 5% or more and 20% or less, but this not limited to The main component (A1) may be a component except for oxygen in the phase stabilization layer. For example, when the phase stabilization layer is a SnO2 layer, the main component (A1) may be Sn.

The first to seventh layers 13a, 13b, 13c, 13d, 13e, 13f, and 13g included in the dielectric layer 130 may be formed by an atomic layer deposition (ALD) method, limited to this method. It doesn't work. Depending on the material properties, roles or functions of each layer 13a, 13b, 13c, 13d, 13e, 13f, or 13g, each layer may be formed with one or several ALD cycles, or may be formed with dozens or hundreds of ALD cycles. may be For example, when the second layer 13b is a titanium oxide layer, the second layer 13b may be formed by repeating an ALD cycle of forming titanium oxide tens to hundreds of times. For example, when the second layer 13b and the fourth layer 13d are titanium oxide layers and the third layer 13c is a phase stabilization layer (eg, SnO2), the third layer 13c is a SnO2 layer. The forming ALD cycle may be performed once or may be formed several times. Considering that the thickness of the phase stabilization layer formed by one ALD cycle corresponds to the thickness of one atomic layer, the thickness of the phase stabilization layer is negligibly thin compared to the thickness of the titanium oxide layer.

Considering this point, the phase stabilization layer in the dielectric layer 130 may be regarded as doped or buried in the titanium oxide layer. Accordingly, in the following description, the phase stabilization layer may be expressed as being doped or buried in the titanium oxide layer. In addition, the material layer composed of the phase stabilization layer and the titanium oxide layer may be expressed as a titanium oxide layer doped with the phase stabilization layer or a titanium oxide layer doped with major components of the phase stabilization layer. For example, when the phase stabilization layer is a SnO2 layer, the material layer including the phase stabilization layer and the titanium oxide layer may be referred to as “SnO2 doped titanium oxide layer” or “Sn doped titanium oxide layer”.

The second material layer 140 is provided to face the first material layer 120 with the dielectric layer 130 interposed therebetween. The second material layer 140 may be or include a conductive layer or a semiconductor layer. A material of the second material layer 140 may be the same as or different from that of the first material layer 120 . The second material layer 140 may be used as an electrode layer.

The layer structure 100 may be a structure in which a metal, an insulator, and a metal are sequentially stacked, that is, a metal-insulator-metal (MIM) structure. In one example, the layer structure 100 may be a capacitor as one of the data storage units.

2 is a graph showing a change in dielectric constant (a) and a rate of change in dielectric constant (b) of a titanium oxide layer according to the doping amount of SnO 2 , which is an example of a phase stabilization layer.

In (a) and (b) of FIG. 2, the first graphs G1 and G1' are for the [110] plane of the TiO2 layer, and the second graphs G2 and G2' are for the [001] plane. .

In (a) of FIG. 2, the horizontal axis represents the Sn doping amount (x) of the Sn-doped TiO2 (Sn(x)Ti(1-x)O2) layer, and the vertical axis represents the dielectric constant. In (b) of FIG. 2, the horizontal axis represents the Sn doping amount (x) of the Sn-doped titanium oxide, and the vertical axis represents the dielectric constant change ratio, respectively.

Referring to FIG. 2, the change in the dielectric constant of the TiO2 layer according to the Sn doping amount (x) varies depending on the crystal plane of the TiO2 layer, and the dielectric constant for the [110] plane is much larger than that for the [001] plane. you can see the big one In the case of the [110] plane, the dielectric constant starts around 200 and gradually increases until the Sn doping amount (x) reaches the first value (eg, x = 0.05, 5%), and the Sn doping amount (x) After exceeding the first value, the dielectric constant rapidly increases proportionally. This rapid increase is maintained until the Sn doping amount (x) reaches a second value between 0.1 (10%) and 0.15 (15%). As the Sn doping amount (x) passes the second value, the dielectric constant rapidly and proportionally decreases, and this decrease continues until the Sn doping amount (x) exceeds 0.2 (20%) and reaches 0.25 (25%). Continued. Even in the range where the dielectric constant decreases, the lowest value of the dielectric constant is greater than 200.

In the case of the [001] plane, the dielectric constant is smaller than that of the [110] plane, but the dielectric constant change pattern according to the Sn doping amount (x) is similar. Even in the case of the [001] plane, it can be seen that the dielectric constant when the Sn doping amount (x) is about 0.05 (5%) to 0.23 (23%) is larger than when Sn is not doped (x = 0.0).

3 is a graph showing the dielectric constant of a Sn-doped TiO2 layer when the doping amount (doping concentration) of SnO2, which is an example of a phase stabilization layer, is 5% or less.

In FIG. 3, the horizontal axis represents the Sn doping concentration [Sn/(Sn+Ti)], and the vertical axis represents the dielectric constant.

Referring to FIG. 3, it can be seen that the dielectric constant of the Sn-doped TiO2 layer is as high as 50 or more even at a Sn doping concentration of 0.5% to 5.0%.

2 and 3 show that a TiO2 layer doped (added) with a phase stabilization layer such as SnO2 also has a high dielectric constant (permittivity) of 50 or more.

4 shows leakage current characteristics of a TiO2 layer doped with SnO2 as an example of a phase stabilization layer in the dielectric layer 130, that is, a Sn-doped TiO2 layer at different first and second thicknesses.

In FIG. 4, the horizontal axis represents the equivalent oxide film thickness, and the vertical axis represents the leakage current.

In FIG. 4 , the first group 4G1 is a case where the Sn-doped TiO2 layer has a first thickness (55 Å), and the second group 4G2 is a case where the Sn-doped TiO2 layer has a second thickness (65 Å). The doping concentration of Sn in the Sn-doped TiO2 layers having the first and second thicknesses is about 0.5% to 4%. Therefore, even in the same group, the equivalent oxide thickness and leakage current of the Sn-doped TiO2 layer may be different.

In FIG. 4, in numbers representing ratios such as 29:1, 30:1, 52:1, and 43:1, the numbers on the left represent the number of ALD cycles required to form the TiO2 layer, and the numbers on the right represent the number of ALD cycles required to form the SnO2 layer. Indicates the number of cycles. For example, 69:1 means that 69 ALD cycles for forming the TiO2 layer and one ALD cycle for forming the SnO2 layer were performed until the Sn-doped TiO2 layer having the first thickness was formed. In other words, 69:1 means that the ALD cycle for forming the TiO2 layer was performed 69 times and the ALD cycle for forming the SnO2 layer was performed once to form the Sn-doped TiO2 layer having the first thickness.

Referring to FIG. 4 , the leakage current of the Sn-doped TiO 2 layer having a first thickness and the Sn-doped TiO 2 layer having a second thickness is less than 10 ^-2 and greater than 10 ^-4 .

FIG. 5 shows leakage current when Al2O3 is added as a layer for leakage current suppression to the Sn-doped TiO2 layer used to obtain the results of FIG. 4 . The Sn doping concentration of the Sn-doped TiO2 layer used to obtain the results shown in FIG. 5 was about 2.5%. And, in order to add Al2O3, an ALD cycle for forming an Al2O3 layer was performed once. As a result, FIG. 5 may be viewed as showing leakage current characteristics for the Sn _x Al _y Ti _(1-xy) O ₂ layer.

In FIG. 5, the horizontal axis represents the voltage applied to the Sn-doped TiO2 layer, and the vertical axis represents the leakage current.

Referring to FIG. 5 , the leakage current measured at about 1V is about 2x10 ^-6 A/cm 2 , which is much lower than that of FIG. 4 . As a result, the results of FIGS. 4 and 5 suggest that the leakage current is lowered by adding Al2O3 to the Sn-doped TiO2 layer. suggests that it has an inhibitory effect on

6 shows simulation results obtained by measuring leakage current characteristics of a titanium oxide layer and leakage current characteristics of a combination of a titanium oxide layer and a first high band gap layer.

In FIG. 6, the horizontal axis represents the equivalent oxide film thickness, and the vertical axis represents the leakage current.

In FIG. 6, a first graph 6G1 shows measurement results for the TiO2 layer. A second graph 6G2 shows measurement results for a combination of a ZrO2 layer and a TiO2 layer (sequentially stacked TiO2 layer/ZrO2 layer) as the first high band gap layer. A third graph 6G3 shows measurement results for the combination of the first high band gap layer, the HfO2 layer and the TiO2 layer (sequentially stacked TiO2 layer/HfO2 layer).

Comparing the first to third graphs 6G1 to 6G3, the leakage current decreases as the equivalent oxide film thickness increases in all of the TiO2 layer, the TiO2 layer/ZrO2 layer, and the TiO2 layer/HfO2 layer. However, the degree of leakage current reduction according to the increase in the equivalent oxide film thickness is different. Specifically, the leakage current reduction per unit equivalent oxide film thickness is greater in the case of the TiO2 /ZrO2 layer (6G2) and the TiO2 /HfO2 layer (6G3) than the case of the TiO2 layer (6G1), and the TiO2 /ZrO2 layer The TiO2 layer/HfO2 layer case (6G3) is larger than the case (6G2). Table 1 below is a numerical summary of these relationships.

a) ∂LKG/
∂t _film Thickness to reduce LKG 1-order (Å) b) ∂T _oxeq. /
∂t _film a)/b) c)∂LKG/
∂T _oxeq. TiO2 -0.034 ~29 0.059 -0.569 -0.508 TiO2/ZrO2 -0.098 ~10 0.131 -0.743 -0.605 TiO2/HfO2 -0.178 ~6 0.162 -1.098 -0.987

In Table 1, a) represents the change (decrease) of the leakage current (LKG) for the change in the actual thickness (t _film ) of the TiO2 layer, the TiO2 layer/ZrO2 layer, and the TiO2 layer/HfO2 layer, and b) is the TiO2 layer, TiO2 The ratio of the actual thickness (t _film ) and the equivalent oxide film thickness (T _oxeq ) of layer/ZrO2 layer and TiO2 layer/HfO2 layer is shown.

Referring to Table 1, in the case of the TiO2 layer, the leakage current reduction per unit equivalent oxide film thickness is about -0.508, and in the case of the TiO2/ZrO2 layer and the TiO2/HfO2 layer, it is about -0.605 and -0.987, respectively. As such, in the case of the TiO2 layer, in the case of the TiO2 layer/ZrO2 layer and in the case of the TiO2 layer/HfO2 layer, the amount of leakage current reduction according to the thickness change is different, so the actual amount required to lower the leakage current by about 1-order. The thickness is also different in each case. As summarized in Table 1, in the case of the TiO2 layer, the actual thickness required to lower the leakage current by 1 order is about ~29 Angstrom (2.9 nm), and in the case of the TiO2 layer/ZrO2 layer, it is about ~10 Angstrom (1.0 nm). , and in the case of the TiO2 layer/HfO2 layer, it is about ~6 angstroms (0.6 nm). As such, the actual thickness required to lower the leakage current by one order of magnitude is smaller in the case of the TiO2 layer/ZrO2 layer and the TiO2 layer/HfO2 layer than in the case of the TiO2 layer. Therefore, as a layer structure for lowering the leakage current at the same thickness, a TiO2 layer/ZrO2 layer or a TiO2 layer/HfO2 layer is more advantageous than the TiO2 layer.

7 shows simulation results of the relationship between the doping amount of the phase stabilization layer for the TiO2 layer and the stabilization of the rutile phase of the TiO2 layer.

In FIG. 7, the horizontal axis represents the doping amount or doping concentration of the phase stabilizing dopant doped into the TiO2 layer for phase stabilization, and the vertical axis represents which phase the TiO2 layer is in and the degree of phase stabilization. When the value of the vertical axis is greater than 0, the anatase phase is dominant in the TiO2 layer, and as the value increases, the anatase phase becomes thermodynamically more stable. When the value of the vertical axis is less than 0, that is, a negative value, the rutile phase is dominant in the TiO2 layer, and as the negative value increases, the rutile phase becomes thermodynamically more stable.

In the simulation conducted to obtain the results of FIG. 7 , SnO 2 layer, GeO 2 layer and SiO 2 layer having a rutile phase were used as the phase stabilization layer. In other words, Sn, Ge, and Si were used as dopants for phase stabilization in the simulations. The simulation was performed for the first to third doped TiO2 layers. The first doped TiO 2 layer is a phase stabilization layer in which a SiO 2 layer is used, and it can be regarded as being doped with Si. The second doped TiO 2 layer is a GeO 2 layer used as a phase stabilization layer, and can be regarded as being doped with Ge. The third doped TiO 2 layer is a phase stabilization layer in which a SnO 2 layer is used, and can be regarded as being doped with Sn.

In FIG. 7 , a first graph 7G1 represents a simulation result for the first doped TiO2 layer, and a second graph 7G2 represents a simulation result for the second doped TiO2 layer. And, a third graph 7G3 shows simulation results for the third doped TiO2 layer.

Referring to the first to third graphs 7G1 to 7G2, the first to third graphs 7G1 to 7G3, which were in an anatase phase-dominant region at the beginning of doping, are downward as the doping amount of the phase stabilizing material increases, and the rutile phase is dominant. It tends to fall deep into the region. This morphology suggests that the phase of the first to third doped TiO 2 layers is changed from the anatase phase to the stable rutile phase as the doping amount of the phase stabilizing material increases.

As a result, FIG. 7 suggests that a TiO 2 layer doped with a phase stabilization layer can have a stable rutile phase by adjusting the doping concentration.

FIG. 8 shows a first embodiment of the layer structure 100 of FIG. 1 .

Referring to FIG. 8, the dielectric layer 130 includes a first TiO2 layer 8A, a phase stabilization layer 8B, a second TiO2 layer 8C, a leakage current suppression layer 8D, and a third TiO2 layer sequentially stacked. (8E). The leakage current suppression layer 8D may be the second high band gap layer. Positions of the phase stabilization layer 8B and the leakage current suppression layer 8D may be interchanged. The first to third TiO2 layers 8A, 8C, and 8E may be the same TiO2 layers. In the first embodiment of FIG. 8, one of two spaced apart layers (eg, 13c and 13e) selected from the second to sixth layers 13b to 13f of the dielectric layer 130 of FIG. 1 is a phase stabilization layer, The other layer is a leakage current suppression layer, and all other layers except for the two selected layers in the dielectric layer 130 are TiO2 layers.

FIG. 9 shows a second embodiment of the layer structure 100 of FIG. 1 .

Referring to FIG. 9 , the dielectric layer 130 includes a first TiO 2 layer 9A, a phase stabilization layer 9B, a leakage current suppression layer 9C, and a second TiO 2 layer 9D sequentially stacked. Positions of the phase stabilization layer 9B and leakage current suppression layer 9C may be interchanged. The first and second TiO2 layers 9A and 9D may be the same TiO2 layers. In the second embodiment of FIG. 9, one of the two layers (eg, 13c and 13d) in contact with each other selected from the second to sixth layers 13b to 13f of the dielectric layer 130 of FIG. 1 is a phase stabilization layer, The other layer is a leakage current suppression layer, and all other layers except for the two selected layers in the dielectric layer 130 are TiO2 layers.

FIG. 10 shows a third embodiment of the layer structure 100 of FIG. 1 .

Referring to FIG. 10 , the dielectric layer 130 includes a first TiO 2 layer 10A, a phase stabilization layer 10B, a second TiO 2 layer 10C and a leakage current suppression layer 10D sequentially stacked. The leakage current suppression layer 10D may be the second high band gap layer. Positions of the phase stabilization layer 10B and the leakage current suppression layer 10D may be interchanged. The first and second TiO2 layers 10A and 10C may be the same TiO2 layer. In the third embodiment of FIG. 10, one of the seventh layer 13g of the dielectric layer 130 of FIG. 1 and one layer (eg, 13e) spaced apart from the seventh layer 13g is a phase stabilization layer, and the other The layer is a leakage current suppression layer, and all other layers of the dielectric layer 130 except for the two layers 13e and 13g are TiO2 layers.

FIG. 11 shows a fourth embodiment of the layer structure 100 of FIG. 1 .

Referring to FIG. 11 , the dielectric layer 130 includes a phase stabilization layer 11A, a first TiO 2 layer 11B, a leakage current suppression layer 11C, and a second TiO 2 layer 11D sequentially stacked. The leakage current suppression layer 11C may be the second high band gap layer. Positions of the phase stabilization layer 11A and the leakage current suppression layer 11C may be interchanged. The first and second TiO2 layers 11B and 11D may be the same TiO2 layers. In the fourth embodiment of FIG. 11, one of the first layer 13a of the dielectric layer 130 of FIG. 1 and another layer (eg, 13c) spaced apart from the first layer 13a is a phase stabilization layer, and the other layer is a phase stabilization layer. The layer is a leakage current suppression layer, and all other layers of the dielectric layer 130 are TiO2 layers.

FIG. 12 shows a fifth embodiment of the layer structure 100 of FIG. 1 .

Referring to FIG. 12 , the dielectric layer 130 includes a phase stabilization layer 12A, a TiO 2 layer 12B and a leakage current suppression layer 12C sequentially stacked. The leakage current suppression layer 12C may be the second high band gap layer. Positions of the phase stabilization layer 12A and the leakage current suppression layer 12C may be interchanged. In the fifth embodiment of FIG. 12, one of the first layer 13a and the seventh layer 13g of the dielectric layer 130 of FIG. 1 is a phase stabilization layer, the other layer is a leakage current suppression layer, and the dielectric layer 130 ) corresponds to the case where all the other layers are TiO2 layers.

FIG. 13 shows a sixth embodiment of the layer structure 100 of FIG. 1 .

Referring to FIG. 13, the dielectric layer 130 includes a sequentially stacked first TiO2 layer 13A1, a first phase stabilization layer 13A2, a second TiO2 layer 13A3, a second phase stabilization layer 13A4, and a second phase stabilization layer 13A4. 3 TiO2 layers 13A5, a leakage current suppression layer 13A6, and a fourth TiO2 layer 13A7. The leakage current suppression layer 13A6 may be the second high band gap layer. Positions of one of the first and second phase stabilization layers 13A2 and 13A4 and the leakage current suppression layer 13A6 may be interchanged. The first to fourth TiO2 layers 13A1, 13A3, 13A5, and 13A7 may be the same TiO2 layers. In the sixth embodiment of FIG. 13, one of the three spaced apart layers (eg, 13b, 13d, and 13f) selected from the second to sixth layers 13b to 13f of the dielectric layer 130 of FIG. 1 has leakage current. This corresponds to the case where the suppression layer, the remaining two layers are phase stabilization layers, and the rest of the dielectric layer 130 excluding the above three layers is a TiO2 layer.

FIG. 14 shows a seventh embodiment of the layer structure 100 of FIG. 1 .

Referring to FIG. 14, the dielectric layer 130 includes a first phase stabilization layer 14A, a first TiO 2 layer 14B, a leakage current suppression layer 14C, a second TiO 2 layer 14D, and a second TiO 2 layer 14D sequentially stacked. A phase stabilization layer 14E is included. Positions of one of the first and second phase stabilization layers 14A and 14E and the leakage current suppression layer 14C may be interchanged. The first and second TiO2 layers 14B and 14D may be the same TiO2 layers. The seventh embodiment of FIG. 14 includes two of the first and seventh layers 13a and 13g of the dielectric layer 130 of FIG. 1 and a layer (eg, 13d) spaced apart from the two layers 13a and 13g. This corresponds to the case where the phase stabilization layer, the other layer is a leakage current suppression layer, and the rest of the dielectric layer 130 excluding the above three layers is a TiO2 layer.

FIG. 15 shows an eighth embodiment of the layer structure 100 of FIG. 1 .

Referring to FIG. 15, the dielectric layer 130 is sequentially stacked with a first TiO2 layer 15A, a phase stabilization layer 15B, a second TiO2 layer 15C, a first leakage current suppression layer 15D, and a third TiO2 layer 15D. A TiO2 layer 15E, a second leakage current suppression layer 15F, and a fourth TiO2 layer 15G are included. Positions of one of the first and second leakage current suppression layers 15D and 15F and the phase stabilization layer 15B may be interchanged. The first to fourth TiO2 layers 15A, 15C, 15E, and 15G may be the same TiO2 layers. In the eighth embodiment of FIG. 15, one layer selected from among the second layer 13b, the fourth layer 13d, and the sixth layer 13f of the dielectric layer 130 of FIG. 1 is a phase stabilization layer, and the other two layers are It is a leakage current suppression layer, and the rest of the dielectric layer 130 except for the above three layers corresponds to the case of a TiO2 layer.

FIG. 16 shows a ninth embodiment of the layer structure 100 of FIG. 1 .

Referring to FIG. 16, the dielectric layer 130 includes a sequentially stacked first TiO 2 layer 16A, a first phase stabilization layer 16B, a second TiO 2 layer 16C, a second phase stabilization layer 16D, and a second phase stabilization layer 16D. 3 TiO2 layer 16E, a first leakage current suppression layer 16F, a fourth TiO2 layer 16G, a second leakage current suppression layer 16H, and a fifth TiO2 layer 16I.

Positions of at least one of the first and second phase stabilization layers 16B and 16D and at least one of the first and second leakage current suppression layers 16F and 16H may be interchanged. The first to fifth TiO2 layers 16A, 16C, 16E, 16G, and 16I may be the same TiO2 layers. In the ninth embodiment of FIG. 16, in the dielectric layer 130 of FIG. 1, the second layer 13b, the third layer 13c, the fifth layer 13e, and the sixth layer 13f are spaced apart from each other, A TiO2 layer is formed between the spaced layers, two of the four layers 13b, 13c, 13e, and 13f are formed as phase stabilization layers, and the other two are formed as leakage current suppression layers. Except for the layers 13b, 13c, 13e, and 13f, the rest corresponds to the case where the TiO2 layer is formed.

FIG. 17 shows a tenth embodiment for the layer structure 100 of FIG. 1 .

Referring to FIG. 17, the dielectric layer 130 includes a sequentially stacked first TiO 2 layer 17A, a first phase stabilization layer 17B, a second TiO 2 layer 17C, a second phase stabilization layer 17D, and a second phase stabilization layer 17D. 1 leakage current suppression layer 17E, a third TiO2 layer 17F, a second leakage current suppression layer 17G, and a fourth TiO2 layer 17H. The second phase stabilization layer 17D and the first leakage current suppression layer 17E are in contact with each other.

The dielectric layer 130 of FIG. 17 corresponds to the case in which the second phase stabilization layer 16D and the first leakage current suppression layer 16F are in contact with each other in FIG. 16 .

FIG. 18 shows an eleventh embodiment of the layer structure 100 of FIG. 1 .

Referring to FIG. 18 , the dielectric layer 130 includes a first high band gap layer 18A, a first TiO 2 layer 18B, a phase stabilization layer 18C, and a second TiO 2 layer 18D sequentially stacked. Positions of the phase stabilization layer 18C and the first TiO2 layer 18B may be interchanged. That is, the phase stabilization layer 18C may be positioned between the first high band gap layer 18A and the first TiO 2 layer 18B, and may contact both layers. In the eleventh embodiment of FIG. 18, the first layer 13a of the dielectric layer 130 of FIG. 1 is a first high band gap layer, the seventh layer 13g is a TiO2 layer, and the second layers 13b to the sixth This corresponds to the case where one of the layers 13f is a phase stabilization layer and the others are TiO2 layers.

FIG. 19 shows a twelfth embodiment of the layer structure 100 of FIG. 1 .

Referring to FIG. 19 , the dielectric layer 130 includes a first TiO 2 layer 19A, a phase stabilization layer 19B, a second TiO 2 layer 19C, and a first high band gap layer 19D sequentially stacked. In the twelfth embodiment of FIG. 19, one of the second to sixth layers 13b, 13c, 13d, 13e, and 13f of the dielectric layer 130 of FIG. 1 is a phase stabilization layer, and the seventh layer 13g is the second embodiment. 1 is a high band gap layer, and the remaining layers are TiO2 layers.

FIG. 20 shows a thirteenth embodiment of the layer structure 100 of FIG. 1 .

Referring to FIG. 20 , the dielectric layer 130 includes a first high band gap layer 20A, a first TiO 2 layer 20B, a phase stabilization layer 20C, a second TiO 2 layer 20D, and a second high band gap layer 20A, which are sequentially stacked. A band gap layer 20E is included. In the thirteenth embodiment of FIG. 20, the first layer 13a and the seventh layer 13g of the dielectric layer 130 of FIG. 1 are high band gap layers, and the second to sixth layers 13b, 13c, 13d, 13e, 13f) corresponds to the case where one layer is a phase stabilization layer and the other layer is a TiO2 layer.

FIG. 21 shows a fourteenth embodiment of the layer structure 100 of FIG. 1 .

Referring to FIG. 21 , the dielectric layer 130 includes a first high band gap layer 21A, a phase stabilization layer 21B, and a TiO 2 layer 21C sequentially stacked. In the fourteenth embodiment of FIG. 21, the first layer 13a of the dielectric layer 130 of FIG. 1 is a high band gap layer, the second layer 13b is a phase stabilization layer, and the third to seventh layers 13c, 13d, 13e, 13f, 13g) correspond to the TiO2 layer.

FIG. 22 shows a fifteenth embodiment of the layer structure 100 of FIG. 1 .

Referring to FIG. 22, the dielectric layer 130 includes a sequentially stacked high band gap layer 22A, a first TiO 2 layer 22B, a phase stabilization layer 22C, a second TiO 2 layer 22D, and a leakage current suppression layer ( 22E) and a third TiO2 layer 22F. The first to third TiO2 layers may be TiO2 layers that are physically the same as each other. In the fifteenth embodiment of FIG. 22, the first layer 13a of the dielectric layer 130 of FIG. 1 is a high band gap layer, one of the second and third layers 13b and 13c is a phase stabilization layer, and the fifth layer and a case in which one of the sixth layers 13e and 13f is a leakage current suppression layer and the other layer is a TiO2 layer.

FIG. 23 shows a sixteenth embodiment of the layer structure 100 of FIG. 1 .

Referring to FIG. 23, the dielectric layer 130 is sequentially stacked with a high band gap layer 23A, a first TiO 2 layer 23B, a phase stabilization layer 23C, a leakage current suppression layer 23D, and a second TiO 2 layer ( 23E). The first and second TiO2 layers may be TiO2 layers that are physically the same as each other. In the sixteenth embodiment of FIG. 23, the first layer 13a of the dielectric layer 130 of FIG. 1 is a high band gap layer, and one of the two adjacent layers selected from the third to sixth layers 13c to 13f is phase stabilized. layer, the other layer is a leakage current suppression layer, and the remaining layers of the dielectric layer 130 are TiO2 layers.

FIG. 24 shows a seventeenth embodiment of the layer structure 100 of FIG. 1 .

Referring to FIG. 24, the dielectric layer 130 is sequentially stacked with a high band gap layer 24A, a phase stabilization layer 24B, a first TiO 2 layer 24B, a leakage current suppression layer 24D, and a second TiO 2 layer ( 24E).

The first and second TiO2 layers 24B and 24E may be TiO2 layers that are physically the same as each other. In the 17th embodiment of FIG. 24, the first layer 13a of the dielectric layer 130 of FIG. 1 is a high band gap layer, the second layer 13b is a phase stabilization layer, and the fourth to sixth layers 13d-13f ) corresponds to a case in which one layer is a leakage current suppression layer and the remaining layers of the dielectric layer 130 are TiO2 layers.

FIG. 25 shows an eighteenth embodiment of the layer structure 100 of FIG. 1 .

Referring to FIG. 25, the dielectric layer 130 is sequentially stacked with a high band gap layer 25A, a first TiO 2 layer 25B, a phase stabilization layer 25C, a second TiO 2 layer 25D, and a leakage current suppression layer ( 25E).

The first and second TiO2 layers 25B and 25D may be materially the same TiO2 layers. In the eighteenth embodiment of FIG. 25, the first layer 13a of the dielectric layer 130 of FIG. 1 is a high band gap layer, the seventh layer 13g is a leakage current suppression layer, and the third to fifth layers 13c- 13e) corresponds to a case in which one layer is a phase stabilization layer and the remaining layers of the dielectric layer 130 are TiO2 layers.

FIG. 26 shows a nineteenth embodiment of the layer structure 100 of FIG. 1 .

Referring to FIG. 26 , the dielectric layer 130 includes a high band gap layer 26A, a phase stabilization layer 26B, a TiO 2 layer 26C, and a leakage current suppression layer 26D sequentially stacked.

In the 19th embodiment of FIG. 26, the first layer 13a of the dielectric layer 130 of FIG. 1 is a high band gap layer, and one of the second layer 13b and the seventh layer 13g is a leakage current suppression layer. , the other layer is a phase stabilization layer, and the remaining layers of the dielectric layer 130 are TiO2 layers.

FIG. 27 shows a twentieth embodiment of the layer structure 100 of FIG. 1 .

Referring to FIG. 27 , the dielectric layer 130 includes a high band gap layer 27A, a phase stabilization layer 27B, a leakage current suppression layer 27C, and a TiO 2 layer 27D sequentially stacked.

In the twentieth embodiment of FIG. 27, the first layer 13a of the dielectric layer 130 of FIG. 1 is a high band gap layer, and one of the second layer 13b and the third layer 13c is a leakage current suppression layer. , the other layer is a phase stabilization layer, and the remaining layers of the dielectric layer 130 are TiO2 layers.

FIG. 28 shows a twenty-first embodiment of the layer structure 100 of FIG. 1 .

Referring to FIG. 28, the dielectric layer 130 is sequentially stacked with a first TiO2 layer 28A, a phase stabilization layer 28B, a second TiO2 layer 28C, a leakage current suppression layer 28D, and a third TiO2 layer. (28E) and a high band gap layer (28F). The first to third TiO2 layers 28A, 28C, and 28E may be TiO2 layers that are physically identical to each other. In the twenty-first embodiment of FIG. 28, the seventh layer 13g of the dielectric layer 130 of FIG. 1 is a high band gap layer, and one of the third layer 13c and the fifth layer 13e is a leakage current suppression layer. , the other layer is a phase stabilization layer, and the remaining layers of the dielectric layer 130 are TiO2 layers.

FIG. 29 shows a twenty-second embodiment of the layer structure 100 of FIG. 1 .

Referring to FIG. 29, the dielectric layer 130 is sequentially stacked with a first high band gap layer 29A, a first TiO 2 layer 29B, a phase stabilization layer 29C, a second TiO 2 layer 29D, and leakage current suppression. layer 29E, a third TiO2 layer 29F and a second high band gap layer 29G. The first to third TiO2 layers 29B, 29D, and 29F may be TiO2 layers that are physically identical to each other. In the twenty-second embodiment of FIG. 29, the first and seventh layers 13a and 13g of the dielectric layer 130 of FIG. 1 are high band gap layers, and one of the third layer 13c and the fifth layer 13e is This corresponds to the case where the leakage current suppression layer, the other layer is a phase stabilization layer, and the remaining layers of the dielectric layer 130 are TiO2 layers.

FIG. 30 shows a twenty-third embodiment of the layer structure 100 of FIG. 1 .

Referring to FIG. 30, the dielectric layer 130 is sequentially stacked with a first high band gap layer 30A, a first TiO 2 layer 30B, a phase stabilization layer 30C, a second TiO 2 layer 30D, and leakage current suppression. layer 30E and a second high band gap layer 30F. The first and second TiO 2 layers 30B and 30D may be physically the same TiO 2 layers. The leakage current suppression layer 30E is buried in the second TiO2 layer 30D. Accordingly, the leakage current suppression layer 30E does not contact the second high band gap layer 30F. Positions of the leakage current suppression layer 30E and the phase stabilization layer 30C may be interchanged. Such a buried structure may be formed as follows. That is, a partial thickness of the second TiO 2 layer 30D is first formed, then masking is performed so that only a part of the TiO 2 layer formed first is exposed, and a leakage current suppression layer 30E is formed on the exposed portion, and then the leakage current suppression layer By forming the remaining thickness of the second TiO 2 layer so that 30E is completely covered, the buried structure can be formed.

In the twenty-third embodiment of FIG. 30, the first and seventh layers 13a and 13g of the dielectric layer 130 of FIG. 1 are high band gap layers, and one of the third layer 13c and the fifth layer 13e is In the case where the leakage current suppression layer, the other layer is a phase stabilization layer, and the remaining layer of the dielectric layer 130 is a TiO2 layer, the width of the fifth layer 13e is equal to that of the adjacent fourth and sixth layers 13d and 13f. It is shorter than the width, corresponding to the case where the fifth layer 13e is completely surrounded by the fourth layer 13d and the sixth layer 13f.

FIG. 31 shows a twenty-fourth embodiment of the layer structure 100 of FIG. 1 .

Referring to FIG. 31 , the dielectric layer 130 includes a first high band gap layer 31A, a TiO 2 layer 31B, a phase stabilization layer 31C, a leakage current suppression layer 31D and a second high band gap layer sequentially stacked. (31E). The phase stabilization layer 31C and the leakage current suppression layer 31D are buried in the TiO2 layer 31B. The phase stabilization layer 31C and the leakage current suppression layer 31D are spaced apart from each other in a buried state. The leakage current suppression layer 31D and the phase stabilization layer 31C do not contact the first and second high band gap layers 31A and 31E. Positions of the leakage current suppression layer 31D and the phase stabilization layer 31C may be interchanged. The layer structure in which the phase stabilization layer 31C and the leakage current suppression layer 31D are buried may be formed by applying the method of forming the layer structure in which the leakage current suppression layer 30E is buried in FIG. 30 .

In the twenty-fourth embodiment of FIG. 31, the first and seventh layers 13a and 13g of the dielectric layer 130 of FIG. 1 are high band gap layers, and one of the third layer 13c and the fifth layer 13e is In the case where the leakage current suppression layer, the other layer is a phase stabilization layer, and the remaining layer of the dielectric layer 130 is a TiO2 layer, the widths of the third and fifth layers 13c and 13e are adjacent to the second, fourth and sixth layers. This corresponds to the case where the third and fifth layers 13c and 13e are shorter than the widths of the layers 13b, 13d and 13f and are completely surrounded by the second, fourth and sixth layers 13b, 13d and 13f.

8 to 31, when the dielectric layer 130 includes a phase stabilization layer (eg, 8B, 22C) and a leakage current suppression layer (eg, a first high band gap layer) (eg, 8D, 22E) , The phase stabilization layer and the leakage current suppression layer may each include two or more layers, and the phase stabilization layer and the leakage current suppression layer may be alternately stacked repeatedly.

32 shows a first electronic device 2200 including a layered structure according to an exemplary embodiment. The first electronic device 2200 may include a field effect transistor.

Referring to FIG. 32 , the first electronic device 2200 includes a substrate 2210 having first and second doped regions 22S and 22D spaced apart from each other, and a gap between the first and second doped regions 22S and 22D. A gate insulating layer 2220 provided on the substrate 2210 and a gate electrode 2230 provided on the gate insulating layer 2220 are included. The substrate 2210 may include a semiconductor substrate doped with at least a first type impurity, and the first and second doped regions 22S and 22D may be provided on the semiconductor substrate. In one example, the substrate 2210 may be a P-type semiconductor substrate or an N-type semiconductor substrate doped with P-type or N-type conductive impurities as the first-type impurity. A non-semiconductor layer may be further provided below the semiconductor substrate. In one example, the non-semiconductor layer may include an insulating layer. The first and second doped regions 22S and 22D may be regions doped with second type impurities. The second type impurity may be an impurity opposite to the first type impurity. For example, when the first-type impurity is a P-type conductive impurity, the second-type impurity may be an N-type conductive impurity. One of the first and second doped regions 22S and 22D may be a source region, and the other may be a drain region. The gate insulating layer 2220 is formed on the upper surface of the substrate 2210 between the first and second doped regions 22S and 22D, covers the entire upper surface, and may directly contact the upper surface. . The substrate 2210 under the gate insulating layer 2220 between the first and second doped regions 22S and 22D may provide a channel. When the first electronic device 2200 is operated, carriers may move between the first and second doped regions 22S and 22D through the channel. The carrier may include electrons or holes. The gate insulating layer 2220 may contact the first and second doped regions 22S and 22D. The gate insulating layer 2220 may have a single layer or a multi-layer structure. The gate insulating layer 2220 may extend over portions of the first and second doped regions 22S and 22D. In one example, the gate insulating layer 2220 may be the dielectric layer 130 described in FIG. 1 or include the dielectric layer 130, but is not limited thereto. Considering the materials of the substrate 2210, the gate insulating layer 2220, and the gate electrode 2230, the layer structure including the substrate 2210, the gate insulating layer 2220, and the gate electrode 2230 is the layer of FIG. It may correspond to structure 100.

The gate insulating layer 2220 and the gate electrode 2230 may be collectively referred to as a gate stack.

33 shows a memory device 2300 including a layered structure according to an exemplary embodiment.

Referring to FIG. 33 , the memory device 2300 includes a substrate 2210, first and second doped regions 22S and 22D formed on the substrate 2210, and a gap between the first and second doped regions 22S and 22D. A gate insulating layer 2220 and a gate electrode 2230 sequentially stacked on the substrate 2210, and a data storage element 2750 connected to the second doped region 22D are included.

An interlayer insulating layer 2730 covering the first and second doped regions 22S and 22D and the gate electrode 2230 is formed on the substrate 2210 . The interlayer insulating layer 2730 includes a via hole H1 exposing a part of the second doped region 22D. The via hole H1 is filled with a conductive plug 2740. The conductive plug 2740 covers the entire exposed portion of the second doped region 22D. The data storage element 2750 is provided on the interlayer insulating layer 2730, covers the upper surface of the conductive plug 2740, and may directly contact the upper surface. The data storage element 2750 may include memory cells disposed in storage nodes of various memory devices. For example, the data storage element 2750 may include one of memory cells disposed on one of a DRAM storage node, a FRAM storage node, an SRAM storage node, an MRAM storage node, and a PRAM storage node; not limited to The memory cell may include a configuration capable of storing data '1' or '0'. The memory cell may include the dielectric layer 130 of FIG. 1 . For example, the memory cell may include a DRAM capacitor. As is known, the capacitor of the DRAM includes a lower electrode, a dielectric layer, and an upper electrode. In one example, the dielectric layer of the capacitor may be the dielectric layer 130 described in FIG. 1 or include the dielectric layer 130 .

34 shows a second electronic device 2800 including a layer structure according to an exemplary embodiment. The second electronic device 2800 may be a FinFET.

Referring to FIG. 34 , a semiconductor layer 2820 is aligned in a first direction on a substrate 2810 . A gate stacked structure GS1 is provided on a partial region of the semiconductor layer 2820 . The gate stack GS1 may be provided to cover the upper surface and both side surfaces of the semiconductor layer 2820 . The substrate 2810 may be an insulating substrate. In one example, the substrate 2810 may be a substrate including an insulating layer on one surface on which the semiconductor layer 2820 and the gate stack GS1 are formed. The one surface may be an upper surface of the substrate 2810. The first direction may be parallel to the one surface of the substrate 2810 or the X axis. The semiconductor layer 2820 may include a P-type or N-type semiconductor layer. One part of the one side and the other side of the semiconductor layer 2820 around the gate stack GS1 may be a source or source electrode, and the other part may be a drain or drain electrode. An aspect ratio of each of the semiconductor layer 2820 and the gate stack GS1 may be greater than 1, but is not limited thereto. In one example, the height of each of the semiconductor layer 2820 and the gate stack GS1 in the Z-axis direction may be greater than, equal to, or smaller than the width in the Y-axis direction. A height of the gate stack structure GS1 may be greater than a height of the semiconductor layer 2820 .

FIG. 35 shows a cross section of FIG. 34 cut along the 35-35' direction.

Referring to FIG. 35 , a semiconductor layer 2820 is formed on a substrate 2810 . The aspect ratio of the semiconductor layer 2820 may be greater than 1, but the aspect ratio may be 1 or less than 1. A surface of the semiconductor layer 2820 may become a channel layer.

Both sides and an upper surface of the semiconductor layer 2820 are covered with a gate insulating layer 2830 . The thickness of the gate insulating layer 2830 formed on the semiconductor layer 2820 may be constant or substantially constant. A thickness of the gate insulating layer 2830 may be smaller than that of the semiconductor layer 2820 . The gate insulating layer 2830 may be the dielectric layer 130 of FIG. 1 or include the dielectric layer 130 . A gate electrode 2850 is stacked on the side surface and top surface of the gate insulating layer 2830 . Top and side surfaces of the gate electrode 2850 may be parallel to the top and side surfaces of the gate insulating layer 2830 .

FIG. 36 shows a cross section of FIG. 34 cut along the 36-36' direction.

Referring to FIG. 36 , a semiconductor layer 2820 is formed on one surface of a substrate 2810 . A gate insulating layer 2830 and a gate electrode 2850 are sequentially stacked on a partial region of the upper surface of the semiconductor layer 2820 . A layer structure including a sequentially stacked semiconductor layer 2820 , a gate insulating layer 2830 , and a gate electrode 2850 may correspond to the layer structure 100 shown in FIG. 1 .

A left portion and a right portion of the gate stack GS1 in the semiconductor layer 2820 may be doped with the same dopant. In one example, the dopant may include an N-type or P-type impurity. Depending on the dopant, the second electronic device 2800 may be an N-type device or a P-type device. One of the left and right portions of the semiconductor layer 2820 may serve as a source region and the other may serve as a drain region. A region under the gate stack GS1 in the semiconductor layer 2820 may be a channel. The second electronic device 2800 may be a top gate FinFET in which a gate electrode 2850 is disposed above the channel.

37 shows a third electronic device 3100 including a layer structure according to an exemplary embodiment.

Referring to FIG. 37 , a semiconductor layer 2820 is provided on a substrate 2810 in a direction parallel to the X axis. The aspect ratio of the semiconductor layer 2820 may be greater than 1, may be equal to or less than 1.

FIG. 38 shows a cross section of FIG. 37 cut along the 38-38′ direction.

Referring to FIG. 38 , a gate electrode 2850 is formed on a substrate 2810 . The aspect ratio of the gate electrode 2850 may be greater than 1, may be 1, or may be less than 1. A gate insulating layer 2830 and a semiconductor layer 2820 are sequentially stacked on the upper surface and both side surfaces of the gate electrode 2850 . The semiconductor layer 2820 may be formed to be thicker than the gate insulating layer 2830 . The gate insulating layer 2830 may correspond to the dielectric layer 130 of FIG. 1 . A region of the semiconductor layer 2820 contacting the gate insulating layer 2830 may become a channel. A layer structure of the sequentially stacked semiconductor layer 2820 , the gate insulating layer 2830 , and the gate electrode 2850 may correspond to the layer structure 100 of FIG. 1 .

FIG. 39 shows a cross section of FIG. 37 cut in the 39-39′ direction.

Referring to FIG. 39 , a gate electrode 2850 is present on a partial region of an upper surface of a substrate 2810 . A gate insulating layer 2830 covering the gate electrode 2850 is formed on the upper surface of the substrate 2810 . The gate insulating layer 2830 may be formed to cover the top surface of the substrate 2810 around the gate electrode 2850 and to cover the top surface and both side surfaces of the gate electrode 2850 . An upper surface of the gate insulating layer 2830 is formed flat. A portion of the gate insulating layer 2830 formed on the upper surface of the gate electrode 2850 may be formed to a certain thickness. A portion of the gate insulating layer 2830 formed on both sides of the gate electrode 2850 may be thicker than a portion formed on the upper surface of the gate electrode 2850 . A semiconductor layer 2820 is formed on the gate insulating layer 2830 . The semiconductor layer 2820 may be formed to cover the entire upper surface of the gate insulating layer 2830 . A portion of the semiconductor layer 2820 corresponding to the upper surface of the gate electrode 2850 may include a channel. Left and right portions of the gate electrode 2850 in the semiconductor layer 2820 may be regions doped with an N-type or P-type dopant. One of the left part and the right part may be a source region, and the other may be a drain region. A semiconductor layer 2820 including a channel is disposed on the gate electrode 2850 . That is, the semiconductor layer 2820 may be provided to face the gate electrode 2850 with the gate insulating layer 2830 interposed therebetween. The semiconductor layer 2820 may be formed to cover the entire upper surface of the gate insulating layer 2830 . The third electronic device 3100 may be a bottom gate FinFET in which the gate electrode 2850 is disposed below the channel.

40 is a three-dimensional view of a fourth electronic device 3400 including a layer structure including a dielectric layer according to an exemplary embodiment.

Referring to FIG. 40 , a first electrode 33E1 , a gate electrode 1320 , and a second electrode 33E2 are sequentially aligned in a direction parallel to the X axis on a substrate 1310 . The substrate 1310 may be an insulating substrate. In one example, the substrate 1310 may be a semiconductor substrate on which an insulating layer is formed. In this case, the semiconductor substrate may include, for example, Si, Ge, SiGe, or a III-V group semiconductor material. The substrate 1310 may be, for example, a silicon substrate on which silicon oxide is formed, but is not limited thereto. The aspect ratio of each of the first electrode 33E1 , the gate electrode 1320 , and the second electrode 33E2 may be greater than or equal to 1, but may be less than 1. The first and second electrodes 33E1 and 33E2 may be N-type or P-type semiconductor layers. In one example, the material of the first and second electrodes 33E1 and 33E2 may be the same as the semiconductor layer used as the substrate 102 of FIG. 1 . In one example, the gate electrode 1320 may have a single layer or a multi-layer structure.

A channel layer 1340 and a gate insulating layer 1370 are sequentially formed between the first electrode 33E1 and the gate electrode 1320 in a direction from the first electrode 33E1 to the gate electrode 1320 . A gate insulating layer 1370 and a channel layer 1340 are sequentially formed between the gate electrode 1320 and the second electrode 33E2 in a direction from the gate electrode 1320 to the second electrode 33E2 . The gate insulating layer 1370 may be the dielectric layer 130 of FIG. 1 or include the dielectric layer 130 . The channel layer 1340 may include a semiconductor layer doped with P-type or N-type impurities. In one example, a semiconductor material used as the channel layer 1340 may be the same as that of the first and second electrodes 33E1 and 33E2. One of the first and second electrodes 33E1 and 33E2 may be a source electrode, and the other may be a drain electrode. The heights of the first and second electrodes 33E1 and 33E2 in a direction perpendicular to the substrate 1310 (Z-axis direction) may be the same as the height of the gate electrode 1320, but are not limited thereto.

FIG. 41 shows a cross section of FIG. 40 cut along the 41-41′ direction.

FIG. 42 shows a cross section of FIG. 40 cut along the 42-42' direction.

The cross section shown in FIG. 41 is a first cross section cut from the first electrode 33E1 to the second electrode 33E2 in a direction perpendicular to the substrate 1310 (Z direction in the drawing) (X direction in the drawing). can indicate The cross section shown in FIG. 42 is a second cross section cut across the first electrode 33E1 and the second electrode 33E2 in a direction perpendicular to the substrate 1310 (Z direction in the drawing) (Y direction in the drawing). can represent Here, since the substrate 1310 may not be perfectly flat, the vertical direction may include a substantially vertical direction as well as a substantially vertical direction. In this specification, the definitions described above for the first cross section and the second cross section are jointly used.

Referring to FIG. 41 , the channel layer 1340 may include a first channel 1341 having a hollow closed cross-sectional structure in a first cross-section. The hollow closed-type cross-sectional structure may include, for example, a closed loop shape including a rectangular, circular, elliptical, or irregular shape. The first channel 1341 is connected to, for example, the sheet portion 1341a across and connected between the first electrode 33E1 and the second electrode 33E2, and the first electrode 33E1 and the second electrode 33E2. A contact portion 1341b that makes contact may be included. The sheet portion 1341a may be referred to as a horizontal portion because it is parallel or substantially parallel to the substrate 1310 . Since the contact portion 1341b is perpendicular or substantially perpendicular to the substrate 1310, it may also be referred to as a vertical portion. The first channel 1341 may include two sheet portions 1341a. The contact portion 1341b may support the two sheet portions 1341a and may define a gap between the two sheet portions 1341a.

A plurality of first channels 1341 may be provided, and the first channels 1341 may be spaced apart from each other in a direction perpendicular to the substrate 1310 (Z direction). In other words, the neighboring first channels 1341 and the first channels 1341 may be arranged to be separated from each other. Meanwhile, the channel layer 1340 may include a second channel 1342 having an open cross-sectional structure or a sheet-like structure at at least one of an upper end and a lower end in the first cross-section. The channel layer 1340 may be connected between the first electrode 33E1 and the second electrode 33E2 to become a passage through which current flows between the first electrode 33E1 and the second electrode 33E2. The channel layer 1340 may directly contact the first electrode 33E1 and the second electrode 33E2. In one example, the channel layer 1340 may be connected to the first electrode 33E1 and the second electrode 33E2 through another medium.

Since the first channel 1341 has a hollow closed cross-sectional structure, the first channel 1341 can make surface contact with the first electrode 33E1 and the second electrode 33E2, and the The contact area can be widened by adjusting the thickness of the hollow. That is, by adjusting the length of the spacer portion 1341b of the first channel 1341, the contact area between the first channel 1341 and the first electrode 33E1 and the contact area between the first channel 1341 and the second electrode 33E2 are reduced. The contact area can be adjusted. For example, the length of the spacer portion 1341b may have a range of 100 nm or less. In one example, the length of the spacer portion 1341b may range from 50 nm or less. In one example, the length of the spacer portion 1341b may range from 20 nm or less. In one example, the length of the spacer portion 1341b may range from 10 nm or less.

In one example, the thickness d of the sheet portion 1341a connected between the first electrode 33E1 and the second electrode 33E2 in the first channel 1341 may be 20 nm or less. In one example, the sheet portion 1341a of the first channel 1341 may be 10 nm or less. In one example, the thickness d of the sheet portion 1341a of the first channel 1341 may be 5 nm or less. In one example, the thickness d of the sheet portion 1341a of the first channel 1341 may be 1 nm or less. In one example, the distance between the first electrode 33E1 and the second electrode 33E2 may have a range of 100 nm or less. In one example, the distance between the first electrode 33E1 and the second electrode 33E2 may have a range of 50 nm or less. In one example, a distance between the first electrode 33E1 and the second electrode 33E2 may have a range of 20 nm or less.

A gate insulating layer 1370 may be provided on inner surfaces of the first channel 1341 and the second channel 1342 . The gate insulating layer 1370 may be formed to cover entire inner surfaces of the first and second channels 1341 and 1342 . A gate electrode 1320 may be provided inside the gate insulating layer 1370 . The gate insulating layer 1370 may directly contact the first and second channels 1341 and 1342 .

In the first cross section, the first channel 1341 and the gate insulating layer 1370 may have a structure surrounding the entire gate electrode 1320 . Accordingly, the gate electrode 1320 may correspond to the entire inner surface of the first channel 1341 with the gate insulating layer 1370 interposed therebetween. A layer structure including a channel layer 1340 , a gate insulating layer 1370 , and a gate electrode 1320 sequentially stacked in a given direction may correspond to the first layer structure 100 described with reference to FIG. 1 . Accordingly, the fourth electronic device 3400 may also have the characteristics of having the first layer structure 100 of FIG. 1 .

Although not shown, in one example, a buffer layer may be further provided between the channel layer 1340 and the gate insulating layer 1370 .

Meanwhile, an insulating layer 1380 may be further provided between adjacent first channels 1341 and between the first channel 1341 and the second channel 1342 . The insulating layer 1380 may be disposed across between the first electrode 33E1 and the second electrode 33E2. The insulating layer 1380 may directly contact the first electrode 33E1 and the second electrode 33E2. The insulating layer 1380 may insulate between channels and serve as a support layer for depositing the channels in a manufacturing process. In one example, the insulating layer 1380 may have a thickness in a range of greater than zero and less than or equal to 100 nm. In one example, the insulating layer 1380 may have a thickness in a range of greater than zero and less than or equal to 20 nm. The insulating layer 1380 may include at least one of low-doped silicon, SiO2, Al2O3, HfO2, or Si3N4.

In this embodiment, the first channel 1341 may have a hollow, closed cross-sectional structure, and may be connected with a multi-bridge structure between the first electrode 33E1 and the second electrode 33E2. On the substrate 1310, the first electrode 33E1 and the second electrode 33E2 are spaced apart from each other along the first direction, and a first channel 1341 is formed between the first electrode 33E1 and the second electrode 33E2. The substrate 1310 may be spaced apart from each other along a second direction perpendicular to the substrate 1310 . The first direction may be the X direction, and the second direction may be the Z direction.

Referring to FIG. 42 , the channel layer 1340 may include a first channel 1341 having a hollow closed cross-sectional structure in a second cross-section. A plurality of first channels 1341 may be provided and spaced apart from each other. A gate insulating layer 1370 is provided between the first channel 1341 and the gate electrode 1320 . A gate electrode 1320 may be provided around the gate insulating layer 1370 to surround the gate insulating layer 1370 . In the second cross section, the first channels 1341 are spaced apart from each other in the height direction of the fourth electronic device 3400, that is, in a direction (Z direction) perpendicular to the substrate 1310, and the outer side of the first channel 1341 A gate insulating layer 1370 may be provided, and the gate insulating layer 1370 and the gate electrode 1320 may be provided in a form surrounding the first channel 1341 . That is, the gate insulating layer 1370 surrounds the entire first channel 1341 . The gate electrode 1320 surrounds the entire side of the first channel 1341 . Accordingly, the present embodiment may have a so-called all-around gate structure. The first channel 1341 in the first cross section and the first channel 1341 in the second cross section may be provided alternately in a direction perpendicular to the substrate 1310 . The insulating layer 1380 may be provided inside the first channel 1341 , and the inside of the first channel 1341 may be filled with the insulating layer 1380 .

As shown in FIG. 42 , the gate electrode 1320 may be spaced apart from the first channel layer 1341 with the gate insulating layer 1370 interposed therebetween. The gate electrode 1320 may have a shape surrounding the first channel 1341 in a closed path. Since the gate insulating layer 1370 includes the dielectric layer 130 of FIG. 1 , leakage current characteristics of the gate insulating layer 1370 may not deteriorate even when the thickness is less than 10 nm. Accordingly, leakage current through the gate insulating layer 1370 can be suppressed.

In addition, the fourth electronic device 3400 according to an exemplary embodiment is a field effect transistor, and has a multi-bridge type channel, thereby suppressing the short channel effect and effectively reducing the thickness and length of the channel. In addition, since the fourth electronic device 3400 has a subminiature size and excellent electrical performance, it is suitable for application to an integrated circuit device having a high degree of integration.

43 shows an electronic device according to another exemplary embodiment.

Referring to FIG. 43 , the electronic device 1002 may include a structure in which the capacitor CA2 and the transistor TR are electrically connected by a contact 21 .

The transistor TR is disposed on a semiconductor substrate SU having a source region SR, a drain region DR, and a channel region CH, and is disposed on the semiconductor substrate SU to face the channel region CH, and has a gate insulation. A gate stack GS2 including a layer GI and a gate electrode GA is included.

The interlayer insulating layer 35 may be provided on the semiconductor substrate SU to cover the gate stack GS2. The interlayer insulating layer 35 may include an insulating material. For example, the interlayer insulating layer 35 may include Si oxide (eg, SiO ₂ ), Al oxide (eg, Al ₂ O ₃ ), or a high dielectric material (eg, HfO ₂ ). there is. The contact 21 penetrates the interlayer insulating layer 35 and electrically connects the transistor TR and the capacitor CA2.

The capacitor CA2 includes a lower electrode 202 , an upper electrode 402 , and a dielectric thin film 302 provided between the lower electrode 202 and the upper electrode 402 . The lower electrode 202 and the upper electrode 402 are presented in a shape that can maximize the contact area with the dielectric thin film 302 .

In one example, a layer structure including the sequentially stacked lower electrode 202 , dielectric thin film 302 , and upper electrode 202 may correspond to the layer structure 100 of FIG. 1 . The dielectric thin film 302 may be the dielectric layer 130 described in FIG. 1 or may include the dielectric layer 130 . As an example, the dielectric thin film 302 may include one of various implementations of the dielectric layer 130 illustrated in FIGS. 8 to 31 .

In one example, the material of the lower electrode 202 may be selected to ensure conductivity as an electrode and to maintain stable capacitance performance even after a high-temperature process in manufacturing the capacitor CA2.

The upper electrode 402 includes a conductive material, and the material is not particularly limited. Like the lower electrode 202, the upper electrode 402 may have a rutile phase, but may include various conductive materials having a different phase. The upper electrode 402 may include a metal, a metal nitride, a metal oxide, or a combination thereof. For example, the upper electrode 402 is TiN, MoN, CoN, TaN, W, Ru, RuO ₂ , SrRuO ₃ , Ir, IrO ₂ , Pt, PtO, SRO(SrRuO ₃ ), BSRO((Ba,Sr) RuO ₃ ), CRO (CaRuO ₃ ), LSCO ((La,Sr)CoO ₃ ), or combinations thereof.

Fig. 44 is a top plan view of an electronic device according to another exemplary embodiment.

Referring to FIG. 44 , an electronic device 1003 may include a structure in which a plurality of capacitors and a plurality of field effect transistors are repeatedly arranged. The electronic device 1003 is formed on a semiconductor substrate 41' including a source, a drain, and a channel, and a field effect transistor including a gate stack 42 and a semiconductor substrate 41' so as not to overlap the gate stack 42. A bit line structure 43 including a contact structure 50' disposed on the contact structure 50' and a capacitor CA3 disposed on the contact structure 50' and electrically connecting a plurality of field effect transistors may be further included. there is.

Although FIG. 44 illustrates a form in which both the contact structure 50' and the capacitor CA3 are repeatedly arranged along the X and Y directions, it is not limited thereto. For example, the contact structures 50' may be arranged along the X and Y directions, and the capacitor CA3 may be arranged in a hexagonal shape such as a honeycomb structure.

Fig. 45 is a cross-sectional view taken along the line A-A' of Fig. 44;

Referring to FIG. 45 , a semiconductor substrate 41 ′ may have a shallow trench isolation (STI) structure including a device isolation film 44 . The device isolation film 44 may be a single layer made of one kind of insulating film or a multi-layer made of a combination of two or more kinds of insulating films. The device isolation layer 44 may include a device isolation trench 44T in the semiconductor substrate 41', and the device isolation trench 44T may be filled with an insulating material. The insulating material is FSG (fluoride silicate glass), USG (undoped silicate glass), BPSG (boro-phospho-silicate glass), PSG (phospho-silicate glass), FOX (flowable oxide), PE-TEOS (plasma enhanced tetra-ethyl -ortho-silicate), and at least one of tonen silazene (TOSZ), but is not limited thereto.

The semiconductor substrate 41' further includes a channel region CH defined by the device isolation layer 44 and a gate line trench 42T disposed parallel to an upper surface of the semiconductor substrate 41' and extending along the X direction. can do. The channel region CH may have a relatively long island shape having short and long axes. As illustratively shown in FIG. 44 , the long axis of the channel region CH may be arranged along a direction D3 parallel to the upper surface of the semiconductor substrate 41'.

The gate line trench 42T may be disposed to cross the channel region CH or within the channel region CH at a predetermined depth from the upper surface of the semiconductor substrate 41 ′. The gate line trench 42T may also be disposed inside the device isolation trench 44T, and the bottom of the gate line trench 42T inside the device isolation trench 44T is lower than that of the gate line trench 42T of the channel region CH. can have sides. The first source/drain 41'ab and the second source/drain 41"ab may be disposed in an upper portion of the channel region CH positioned on both sides of the gate line trench 42T.

A gate stack 42 may be disposed inside the gate line trench 42T. Specifically, the gate insulating layer 42a, the gate electrode 42b, and the gate capping layer 42c may be sequentially disposed inside the gate line trench 42T.

The gate electrode 42b may include at least one of metal, metal nitride, metal carbide, and polysilicon. For example, the metal may include at least one of aluminum (Al), tungsten (W), molybdenum (Mo), titanium (Ti), and tantalum (Ta), and the metal nitride film may include a titanium nitride film (TiN film) and It may include at least one of a tantalum nitride film (TaN film). The metal carbide may include at least one of aluminum and silicon-doped (or containing) metal carbide, and may include TiAlC, TaAlC, TiSiC, or TaSiC as specific examples.

In one example, the gate electrode 42b may have a structure in which a plurality of materials are stacked, for example, a metal nitride layer/metal layer structure such as TiN/Al or a metal nitride layer such as TiN/TiAlC/W. /metal carbide layer/metal layer may have a laminated structure. However, the materials mentioned above are merely illustrative.

In one example, the gate insulating layer 42a may include a paraelectric material or a high-k dielectric material, and may have a dielectric constant of approximately 20 to 70.

In one example, the gate insulating layer 42a may include silicon oxide, silicon nitride, aluminum oxide, hafnium oxide, zirconium oxide, or the like, or may include a 2D insulator such as h-BN (hexagonal boron nitride). there is. For example, the gate insulating layer 42a may include silicon oxide (SiO ₂ ), silicon nitride (SiN _x ), and the like, hafnium oxide (HfO ₂ ), hafnium silicon oxide (HfSiO ₄ ), lanthanum oxide ( La ₂ O ₃ ), lanthanum aluminum oxide (LaAlO ₃ ), zirconium oxide (ZrO ₂ ), hafnium zirconium oxide (HfZrO ₂ ), zirconium silicon oxide (ZrSiO ₄ ), tantalum oxide (Ta ₂ O ₅ ), titanium oxide (TiO ₂ ), strontium titanium oxide (SrTiO ₃ ), yttrium oxide (Y ₂ O ₃ ), aluminum oxide (Al ₂ O ₃ ), red scandium tantalum oxide (PbSc _0.5 Ta _0.5 O ₃ ), red zinc niobate (PbZnNbO ₃ ) etc. may be included. In addition, the gate insulating layer 42a is made of aluminum oxynitride (AlON), zirconium oxynitride (ZrON), hafnium oxynitride (HfON), lanthanum oxynitride (LaON), yttrium oxynitride (YON), and the like. It may include a metal nitride oxide such as ZrSiON, HfSiON, YSiON, LaSiON, etc., or an aluminate such as ZrAlON, HfAlON, etc.

In one example, the gate insulating layer 42a may include one of the implementations of the dielectric layer 130 of FIG. 1 and the dielectric layer 130 illustrated in FIGS. 8 to 31 .

In one example, the gate capping layer 42c may include at least one of silicon oxide, silicon oxynitride, and silicon nitride. A gate capping layer 42c may be disposed on the gate electrode 42b to fill the remaining portion of the gate line trench 42T.

Subsequently, the bit line structure 13 may be disposed on the first source/drain 41'ab. The bit line structure 43 may be disposed parallel to the upper surface of the semiconductor substrate 41' and extend along the Y direction. The bit line structure 43 is electrically connected to the first source/drain 41'ab, and a bit line contact 43a, a bit line 43b, and a bit line capping layer 43c are sequentially formed on the substrate. can include For example, the bit line contact 43a may include polysilicon, the bit line 43b may include a metal material, and the bit line capping layer 43c may include an insulating material such as silicon nitride or silicon oxynitride. may contain substances.

45 illustrates a case where the bit line contact 43a has a bottom surface at the same level as the top surface of the semiconductor substrate 41', but this is exemplary and is not limited thereto. For example, in another embodiment, a recess formed to a predetermined depth from the upper surface of the semiconductor substrate 41' is further provided, and the bit line contact 43a extends into the recess to form a bit line contact 43a. The bottom surface of may be formed lower than the top surface of the semiconductor substrate 41'.

The bit line structure 43 may further include a bit line intermediate layer (not shown) between the bit line contact 43a and the bit line 43b. The bit line interlayer may include a metal silicide such as tungsten silicide or a metal nitride such as tungsten nitride. Also, bit line spacers (not shown) may be further formed on sidewalls of the bit line structure 43 . The bit line spacer may have a single-layer structure or a multi-layer structure, and may include an insulating material such as silicon oxide, silicon oxynitride, or silicon nitride. Also, the bit line spacer may further include an air space (not shown).

The contact structure 50' may be disposed on the second source/drain 41"ab. The contact structure 50' and the bit line structure 43 may be disposed on different sources/drains on the substrate. In the contact structure 50', a lower contact pattern (not shown), a metal silicide layer (not shown), and an upper contact pattern (not shown) are sequentially stacked on the second source/drain 41"ab. may be a rescue. The contact structure 50' may further include a barrier layer (not shown) surrounding side surfaces and a bottom surface of the upper contact pattern. For example, the lower contact pattern may include polysilicon, the upper contact pattern may include a metal material, and the barrier layer may include a conductive metal nitride.

The capacitor CA3 may be electrically connected to the contact structure 50' and disposed on the semiconductor substrate 41'. Specifically, the capacitor CA3 includes a lower electrode 203 electrically connected to the contact structure 50', an upper electrode 403 spaced apart from the lower electrode 203, and the lower electrode 203 and the upper electrode 403. ) and a dielectric thin film 303 disposed between them. The lower electrode 203 may have a cylindrical shape or a cup shape with an inner space closed at the bottom. The upper electrode 403 may have a comb shape having comb teeth extending into an inner space formed by the lower electrode 203 and a region between adjacent lower electrodes 203 . The dielectric thin film 303 may be disposed between the lower electrode 203 and the upper electrode 403 so as to be parallel to these surfaces.

In one example, materials of the lower electrode 203, the dielectric thin film 303, and the upper electrode 403 constituting the capacitor CA3 may be substantially the same as those of the capacitor CA2 described above with reference to FIG. omit explanation.

An interlayer insulating layer 45 may be further disposed between the capacitor CA3 and the semiconductor substrate 41'. The interlayer insulating layer 45 may be disposed in a space between the capacitor CA3 where no other structure is disposed and the semiconductor substrate 41'. Specifically, the interlayer insulating layer 45 may be disposed to cover wiring and/or electrode structures such as the bit line structure 43 , the contact structure 50 ′, and the gate stack 42 on the substrate. For example, the interlayer insulating layer 45 may surround a wall of the contact structure 50'. The interlayer insulating film 45 includes a first interlayer insulating film 45a surrounding the bit line contact 43a and a second interlayer insulating film covering side surfaces and/or top surfaces of the bit line 43b and the bit line capping layer 43c 45b) may be included.

The lower electrode 203 of the capacitor CA3 may be disposed on the interlayer insulating layer 45 , specifically, on the second interlayer insulating layer 45b. Also, when the plurality of capacitors CA3 are disposed, bottom surfaces of the plurality of lower electrodes 203 may be separated by the etch stop layer 46 . In other words, the etch stop layer 46 may include an opening 46T, and the bottom surface of the lower electrode 203 of the capacitor CA3 may be disposed in the opening 46T. As shown, the lower electrode 203 may have a cylindrical shape or a cup shape with an inner space closed at the bottom. The capacitor CA3 may further include a support portion (not shown) that prevents the lower electrode 203 from tilting or falling, and the support portion may be disposed on a sidewall of the lower electrode 203 .

Electronic devices according to the above-described exemplary embodiments may constitute transistors constituting a digital circuit or an analog circuit. In some embodiments, the example electronics may be used as high voltage transistors or low voltage transistors. For example, the electronic device of the exemplary embodiment may constitute a high voltage transistor constituting a peripheral circuit of a flash memory device or an electrically erasable and programmable read only memory (EEPROM) device, which is a non-volatile memory device operating at a high voltage. Alternatively, an exemplary embodiment is an IC device for LCD (liquid crystal display) requiring an operating voltage of 10 V or more, for example, an operating voltage of 20 V to 30 V, or a PDP (plasma display panel) requiring an operating voltage of 100 V. ) can constitute a transistor included in an IC chip used in the

46 is a schematic block diagram of a display device 1420 including a display driver IC (DDI) 3700 and the DDI 3700 according to an exemplary embodiment.

Referring to FIG. 46, the DDI 3700 includes a controller 1402, a power supply circuit 1404, a driver block 1406, and a memory block 1408. ) may be included. The control unit 1402 receives and decodes a command applied from the main processing unit (MPU) 1422, and controls each block of the DDI 3700 to implement an operation according to the command. The power supply circuit unit 1404 generates a driving voltage in response to the control of the control unit 1402 . The driver block 1406 drives the display panel 1424 using the driving voltage generated by the power supply circuit 1404 in response to the control of the controller 1402 . The display panel 1424 may be a liquid crystal display panel or a plasma display panel. The memory block 1408 temporarily stores commands input to the controller 1402 or control signals output from the controller 1402 or stores necessary data, and may include memory such as RAM and ROM. The power supply circuit unit 1404 and the driver block 1406 may include electronic devices according to the above-described exemplary embodiments.

Fig. 47 is a circuit diagram of a CMOS inverter 3800 according to an exemplary embodiment.

The CMOS inverter 3800 includes a CMOS transistor 1510. The CMOS transistor 1510 includes a PMOS transistor 1520 and an NMOS transistor 1530 connected between the power terminal Vdd and the ground terminal. The CMOS transistor 1510 may include an electronic device according to the exemplary embodiment described above.

48 is a circuit diagram of a CMOS SRAM device 3900 according to an exemplary embodiment.

The CMOS SRAM device 3900 includes a pair of driving transistors 1610. The pair of driving transistors 1610 includes a PMOS transistor 1620 and an NMOS transistor 1630 connected between the power terminal Vdd and the ground terminal, respectively. The CMOS SRAM device 3900 may further include a pair of transfer transistors 1640. A source of the transfer transistor 1640 is cross-connected to a common node of the PMOS transistor 1620 and the NMOS transistor 1630 constituting the driving transistor 1610 . The power terminal Vdd is connected to the source of the PMOS transistor 1620, and the ground terminal is connected to the source of the NMOS transistor 1630. A word line WL may be connected to a gate of the pair of transfer transistors 1640 , and a bit line BL and an inverted bit line may be connected to drains of the pair of transfer transistors 1640 , respectively.

At least one of the driving transistor 1610 and the transfer transistor 1640 of the CMOS SRAM device 3900 may include an electronic device according to the exemplary embodiment described above.

49 is a circuit diagram of a CMOS NAND circuit 4000 according to an exemplary embodiment.

The CMOS NAND circuit 4000 includes a pair of CMOS transistors to which different input signals are delivered. The CMOS NAND circuit 4000 may include electronic devices according to the exemplary embodiments described above.

50 is a block diagram illustrating an electronic system 4100 according to an illustrative embodiment.

The electronic system 4100 includes a memory 1810 and a memory controller 1820 . The memory controller 1820 may control the memory 1810 to read data from and/or write data to the memory 1810 in response to a request from the host 1830 . At least one of the memory 1810 and the memory controller 1820 may include an electronic device according to the exemplary embodiment described above.

51 is a block diagram of an electronic system 4200 according to an illustrative embodiment.

The electronic system 4200 may configure a wireless communication device or a device capable of transmitting and/or receiving information in a wireless environment. The electronic system 4200 includes a controller 1910, an input/output device (I/O) 1920, a memory 1930, and a wireless interface 1940, which are interconnected through a bus 1950, respectively.

The controller 1910 may include at least one of a microprocessor, a digital signal processor, or a processing device similar thereto. The input/output device 1920 may include at least one of a keypad, keyboard, or display. Memory 1930 may be used to store instructions executed by controller 1910 . For example, the memory 1930 may be used to store user data. Electronic system 4200 can use air interface 1940 to transmit/receive data over a wireless communications network. The air interface 1940 may include an antenna and/or a wireless transceiver. In some embodiments, the electronic system 4200 may be a variety of communication systems, such as code division multiple access (CDMA), global system for mobile communications (GSM), north American digital cellular (NADC), extended- time division multiple access), and/or wide band code division multiple access (WCDMA). The electronic system 4200 may include an electronic device according to the exemplary embodiment described above as a field effect transistor.

An electronic device including a layered structure according to an exemplary embodiment may exhibit good electrical performance with a subminiature structure, and thus may be applied to an integrated circuit device, and may realize miniaturization, low power consumption, and high performance.

Next, a method of manufacturing a layer structure including a dielectric layer according to an exemplary embodiment will be described with reference to FIGS. 52 to 58. In this process, the same reference numerals as those mentioned above denote the same members, and description thereof will be omitted.

Referring to FIG. 52 , a first layer L1 is formed on one surface of the first material layer 120 . The first layer L1 may directly contact the one surface of the first material layer 120 and may be formed to cover all or part of the one surface. The first layer L1 may be formed to have a first thickness 5T1. The first thickness 5T1 may vary according to the role or function of the first layer L1. The first layer L1 may be formed by an ALD method, but is not limited to this method. The first layer L1 may be formed to correspond to the first layer 13a of FIG. 1 in material and composition. The formed first layer L1 may have one surface (eg, an upper surface) parallel or substantially parallel to the one surface of the substrate 120 .

After forming the first layer (L1), as shown in FIG. 53, a second layer (L2) is formed on the one surface of the formed first layer (L1). The second layer L2 may be directly formed on the one surface of the first layer L1 and may be formed to cover all or part of the one surface. The formed second layer L2 may have one surface (eg, an upper surface) parallel or substantially parallel to the one surface of the first material layer 120 or the one surface of the first layer L1. The second layer L2 may be formed to have a second thickness 5T2. The first and second thicknesses 5T1 and 5T2 may be the same as or different from each other. The second layer L2 may be formed by an ALD method, but is not limited to this method. Materially or functionally, the second layer L2 may be different from the first layer L1. During the formation process using ALD, the number of formation cycles of the first and second layers L1 and L2 may be different from each other. The material and configuration of the second layer L2 may correspond to one of the second layer 13b to the sixth layer 13f of FIG. 1 .

After forming the second layer L2, as shown in FIG. 54, a third layer L3 is formed on the one surface of the second layer L2. The third layer L3 may be directly formed on the one surface of the second layer L2 and may be formed to cover all or part of the one surface. The formed third layer L3 may have one surface (eg, an upper surface) parallel or substantially parallel to the one surface of the first material layer 120 or the one surface of the second layer L2. The third layer L3 may be formed by an ALD method and may have a third thickness 5T3, but is not limited to this method. The third thickness 5T3 may be the same as or different from the second thickness 5T2. The third layer L3 may be materially or functionally different from the first and second layers L1 and L2. For example, one of the first to third layers L1, L2, and L3 may be a TiO2 layer, another layer may be a phase stabilization layer, and the other layer may be a leakage current suppression layer. Alternatively, one of the first to third layers L1, L2, and L3 may be a TiO2 layer, another layer may be a phase stabilization layer, and the other layer may be a high band gap layer. In one example, the material and configuration of the third layer L3 may correspond to the seventh layer 13g of FIG. 1 or one of the second to sixth layers 13b to 13f. .

A second material layer 140 may be formed on the third layer L3.

In one example, as shown in FIG. 55 , a first TiO 2 layer LT1 may be further formed between the first and second layers L1 and L2. In this case, the first TiO 2 layer LT1 may be directly formed on the one surface of the first layer L1 and may be formed to cover all or part of the one surface. The formed first TiO2 layer LT1 may have one surface (eg, an upper surface) parallel or substantially parallel to the one surface of the first material layer 120 or the one surface of the first layer L1. can After the first TiO 2 layer LT1 is completely formed, the second layer L2 may be directly formed on the one surface of the first TiO 2 layer LT1 and may be formed to cover all or part of the one surface. can In other words, the first TiO2 layer LT1 and the second layer L2 are in direct contact with the first TiO2 layer LT1 on the other surface (eg, the bottom surface) opposite to the one surface of the second layer L2. The first TiO2 layer LT1 may be formed to contact all or part of the other surface of the second layer L2. The formed second layer L2 may have one surface (eg, an upper surface) parallel or substantially parallel to the one surface of the first material layer 120 or the one surface of the first TiO2 layer LT1. .

The first TiO2 layer LT1 may be formed by an ALD method, but is not limited to this method. The first TiO2 layer (LT1) may be formed to have a fourth thickness (5T4), and among the first to third layers (L1-L3), a layer used as a phase stabilization layer and a leakage current suppression layer (or a high band gap layer) may be formed thicker than the layer used as In the ALD process of forming the first TiO2 layer LT1, the number of formation cycles is greater than the number of cycles of formation of the layer used as the phase stabilization layer and the number of cycles of formation of the layer used as the leakage current suppression layer (or high band gap layer). There can be many.

In one example, as shown in FIG. 56, a second TiO2 layer LT2 may be further formed between the second and third layers L2 and L3. In this case, the second TiO 2 layer LT2 may be directly formed on the one surface of the second layer L2 and may be formed to cover all or part of the one surface. The formed second TiO2 layer LT2 may have one surface (eg, an upper surface) parallel or substantially parallel to the one surface of the first material layer 120 or the one surface of the second layer L2. can After the second TiO2 layer LT2 is completely formed, the third layer L3 may be formed directly on the one surface of the second TiO2 layer LT2 and cover all or part of the one surface. can In other words, the second TiO2 layer (LT2) and the third layer (L3) have the second TiO2 layer (LT2) opposite (facing) the one surface of the third layer (L3) to the other surface (eg, bottom surface). The second TiO2 layer LT2 may be formed to contact all or part of the other surface of the third layer L3. The formed third layer L3 may have one surface (eg, an upper surface) parallel or substantially parallel to the one surface of the first material layer 120 or the one surface of the second TiO2 layer LT2. .

The second TiO2 layer LT2 may be formed by an ALD method, but is not limited to this method. The second TiO2 layer (LT2) may be formed to have a fifth thickness (5T5), and among the first to third layers (L1-L3), a layer used as a phase stabilization layer and a leakage current suppression layer (or a high band gap layer) may be formed thicker than the layer used as In the ALD process for forming the second TiO2 layer LT2, the number of formation cycles is greater than the number of cycles of formation of the layer used as the phase stabilization layer and the number of cycles of formation of the layer used as the leakage current suppression layer (or high band gap layer). There can be many.

As an example, the first TiO 2 layer LT1 of FIG. 55 may be applied to FIG. 56 . That is, in the layer structure shown in FIG. 56, a TiO2 layer may be formed between the first and second layers L1 and L2.

In one example, the second layer L2 may be formed as a single layer, but may be formed as a plurality of layers as shown in FIG. 57 .

Referring to FIG. 57 , the second layer L2 may be formed by sequentially stacking the first to fifth sub-material layers L2a, L2b, L2c, L2d, and L2e, but is not limited thereto. That is, the second layer L2 may be formed by sequentially stacking 5 or more or 5 or less sub-material layers. Each of the first to fifth sub-material layers L2a to L2e is one of a phase stabilization layer, a first leakage current suppression layer, and a TiO2 layer, and two adjacent sub-material layers may be different from each other. For example, the first and second sub-material layers L2a and L2b may be formed by sequentially stacking a phase stabilization layer and a first leakage current layer or stacking the phase stabilization layer and the TiO2 layer sequentially. It may be formed by stacking or stacking in reverse order, and may be formed by stacking the first leakage current suppression layer and the TiO 2 layer sequentially or stacking in reverse order.

In this case, the TiO2 layer can be formed to be thicker than the phase stabilization layer and the first leakage current suppression layer. To this end, the TiO2 layer can be formed with more ALD formation cycles than the phase stabilization layer and the second leakage current suppression layer. The phase stabilization layer and the second leakage current suppression layer may be formed in less than 10 ALD formation cycles, and in one example, may be formed in one ALD formation cycle.

FIG. 58 shows an example of the second layer L2 of FIG. 57 . In FIG. 58 , the first and third sub-material layers L2a and L2c are phase stabilization layers, the fifth sub-material layer L2e may be the first leakage current suppression layer or vice versa, and the second and fourth sub-material layers L2e may be the same. The material layers L2b and L2d may be TiO2 layers thicker than the first, third, and fifth sub-material layers L2a, L2c, and L2e.

In one example, as shown in FIG. 59 , a fourth layer L4 may be formed to a sixth thickness 5T6 between the first material layer 120 and the first layer L1. In this case, the fourth layer L4 may be directly formed on the one surface of the first material layer 120 . One surface (eg, upper surface) of the fourth layer L4 may be parallel or substantially parallel to the one surface of the first material layer 120 . After the fourth layer L4 is formed, the first layer L1 may be directly formed on the one surface of the fourth layer L4 and may be formed to cover all or part of the one surface. The formed first layer L1 may have one surface parallel to or substantially parallel to the one surface of the first material layer 120 or the one surface of the fourth layer L4 . From another point of view, the fourth layer (L4) is formed to directly contact the other surface (eg, the bottom surface) on the opposite side of the one surface of the first layer (L1), and covers all or part of the other surface. catalog is formed.

The fourth layer L4 may be formed using an ALD device, but is not limited thereto. The fourth layer L4 may be formed of the high band gap layer described in FIG. 1 , and the number of ALD formation cycles may be smaller than the number of ALD formation cycles for forming the TiO 2 layer. In FIG. 59 , the first layer L1 may correspond to one of the second to sixth layers 13b to 13f of FIG. 1 . For example, the first layer L1 may be any one of a TiO2 layer, a phase stabilization layer, and a leakage current suppression layer.

In one example, as shown in FIG. 59 , a fifth layer L5 may be formed with a seventh thickness 5T7 between the second material layer 140 and the third layer L3. In this case, the fifth layer L5 may be directly formed on the one surface of the third layer L3 and may be formed to cover all or part of the one surface. One surface (eg, upper surface) of the formed fifth layer L5 may be parallel or substantially parallel to the one surface of the first material layer 120 or the one surface of the third layer L3. After the fifth layer L5 is formed, the second material layer 140 may be formed directly on the one surface of the fifth layer L5, or may be formed to cover all or part of the one surface. From another point of view, the fifth layer L5 is directly formed on a surface (eg, a bottom surface) of the second material layer 140 facing the first material layer 120 and covers all or part of the bottom surface. can be formed

The fifth layer L5 may be formed using an ALD device, but is not limited thereto. The fifth layer L5 may be formed of the high band gap layer described in FIG. 1 , and the number of ALD formation cycles may be smaller than the number of ALD formation cycles for forming the TiO 2 layer. When the fifth layer L5 is formed, the third layer L3 may correspond to one of the second to sixth layers 13b to 13f of FIG. 1 .

In one example, only a selected layer of the fourth and fifth layers L4 and L5 may be formed, or both layers may be formed.

The technical ideas of FIGS. 55 and/or 56 may be applied to the layer structure of FIG. 59 . For example, between the first and second layers L1 and L2, between the second and third layers L2 and L3, between the first and fourth layers L1 and L4, and between the third and fifth layers L3 , L5), a TiO2 layer may be formed between at least one of them. FIG. 60 shows a case where a third TiO 2 layer LT3 is formed between the first layer L1 and the fourth layer L4 in FIG. 59 .

In this case, the third TiO2 layer LT3 may be directly formed on the one surface of the fourth layer L4 and cover all or part of the one surface. The formed third TiO2 layer LT3 may have one surface (eg, an upper surface) parallel or substantially parallel to the one surface of the first material layer 120 or the one surface of the fourth layer L4. . Also, the first layer L1 may be directly formed on the one surface of the third TiO 2 layer LT3 and cover all or part of the one surface. As a result, the third TiO2 layer LT3 may directly contact all or part of the lower surface of the first layer L1. The first layer L1 may have one surface (eg, an upper surface) parallel or substantially parallel to the one surface of the third TiO2 layer LT3.

The third TiO2 layer LT3 may be formed by an ALD method, but is not limited to this method. The third TiO2 layer (LT3) is formed with a thickness (5T8) thicker than the layer used as the phase stabilization layer, the layer used as the leakage current suppression layer, and the layer formed of the high band gap layer, and the ALD formation cycle of the third TiO2 layer The number of times may also be greater than the number of ALD formation cycles of the layer used as the phase stabilization layer, the layer used as the leakage current suppression layer, and the layer formed as the high band gap layer.

Although many matters are specifically described in the above description, they should be interpreted as examples of preferred embodiments rather than limiting the scope of the invention. Therefore, the scope of the present invention should not be determined by the described embodiments, but should be determined by the technical idea described in the claims.

4T1-4T7: first to seventh thicknesses 5T1-5T8: first to eighth thicknesses
8A, 8C and 8E: first to third TiO2 layers
8B, 9B, 10B, 11A, 12A, 15B, 18C, 19B, 20C, 21B, 22C, 23C, 24B, 25C, 26B, 27B, 28B, 29C, 30C, 31C: phase stabilization layer
8D, 9C, 10D, 11C, 12C, 14C, 13A6, 22E, 23D, 24D, 25E, 26D, 27C, 28D, 29E, 30E, 31D: leakage current suppression layer
9A, 9D: first and second TiO2 layers 10A, 10C: first and second TiO2 layers
11B, 11D: First and second TiO2 layers 12B, 21C, 26C, 27D, 31B: TiO2 layers
13a to 13g: first to seventh layers 13A2, 13A4: first and second phase stabilization layers
13A1, 13A3, 13A5, 13A7: first to fourth TiO2 layers
14A, 14E: first and second phase stabilization layers 14B, 14D: first to second TiO2 layers
15A, 15C, 15E and 15G: first to fourth TiO2 layers
15D, 15F: first and second leakage current suppression layers
16A, 16C, 16E, 16G and 16I: first to fifth TiO2 layers
16B, 16D: first and second phase stabilization layers 16F, 16H: first and second leakage current suppression layers
17A, 17C, 17F and 17H: first to fourth TiO2 layers
17B, 17D: first and second phase stabilization layers 17E, 17G: first and second leakage current suppression layers
18A, 19D, 21A, 22A, 23A, 24A, 25A, 26A, 27A, 28F: high band gap layer
18B and 18D: first and second TiO2 layers 19A and 19C: first and second TiO2 layers
20A, 20E: first and second high band gap layers 20B and 20D: first and second TiO2 layers
22B, 22D and 22F: first to third TiO2 layers 22S, 22D: first and second doped regions
23B and 23E: first and second TiO2 layers 24C and 24E: first and second TiO2 layers
25B and 25D: first and second TiO2 layers 28A, 28C and 28E: first to third TiO2 layers
29A, 29G: first and second high band gap layers 29B, 29D and 29F: first to third TiO2 layers
30A, 30F: first and second high band gap layers 30B, 30D: first and second TiO2 layers
31A, 31E: first and second high band gap layers 41': semiconductor substrate
41'ab: first source/drain 41 "ab: second source/drain
42: gate stack 42a: gate insulating layer
42b: gate electrode 42c: capping layer
42T: gate line trench 43: bit line structure
43a: bit line contact 43b: bit line
43c: bit line capping layer 44: device isolation film
44T: element isolation trench 45: interlayer insulating film
45a: first interlayer insulating film 45b: second interlayer insulating film
46: etch stop layer 46T: opening
50': contact structure 100: layer structure
120, 140: first and second material layers 130: dielectric layer
202, 203: lower electrode 302, 303: dielectric thin film
402, 403: upper electrode 1002, 1003: electronic device
2220: gate insulating layer 1370, 2220, 2830: gate insulating layer
1341, 1342: first and second channels 1341a: seat portion (horizontal portion)
1341b: contact portion (vertical portion) 1420: display device
1402: control unit 1404: power supply circuit unit
1406: driver block 1408: memory block
1422: central processing unit 1424: display panel
1510: CMOS transistor 1520, 1620: PMOS transistor
1530, 1630: NMOS transistor 1610: driving transistor
1640: transfer transistor 1810, 1930: memory
1820: memory controller 1830: host
1910: controller 1920: I/O device
1940: wireless interface 1950: bus
2640, 2850: gate electrode
2600, 2800, 3100, 3400: first to fourth electronic elements
2300: memory element 2720: gate stack
2730 Interlayer insulating layer 2740 Conductive plug
2750: data storage element 2820: semiconductor layer
3700: Display Driving Integrated Circuit (DDI) 3800: CMOS Inverter
3900: CMOS SRAM device 4000: CMOS NAND circuit
4100, 4200: electronic system CA2, CA3: capacitor
CH: channel region GS1: gate stack
H1: via hole L1-L5: first to fifth layers
L2a-L2e: 1st to 5th sub-material layers LT1-LT3: 1st to 3rd TiO2 layers
T1: thickness of dielectric layer TR: transistor

Claims (39)

an undoped first layer having a dielectric constant greater than that of silicon oxide;
a second layer provided to reinforce a rutile phase of the first layer and provided outside the first layer; and
A dielectric layer including a third layer provided to increase a band gap of the first layer and provided outside the first and second layers. According to claim 1,
The first layer is provided between the second layer and the third layer, the three layers are sequentially stacked dielectric layer. According to claim 2,
The first layer is symmetric about the second layer,
The third layer is a dielectric layer provided on at least one side of the first side and the second side of the first laminate formed of the first and second layers. According to claim 1,
The first layer is provided under and above the second layer, the dielectric layer in contact with the second layer. According to claim 1,
The first layer is provided under and above the third layer, the dielectric layer in contact with the third layer. According to claim 4,
The first layer is provided under and above the third layer, the dielectric layer in contact with the third layer. According to claim 1,
The second layer and the third layer are in contact with each other, and the first layer is provided on at least one side of a first side and a second side of a second laminate composed of the contacted second and third layers. According to any one of claims 1 to 7,
A plurality of the second layers are present,
A dielectric layer provided with the first layer between the plurality of second layers. According to any one of claims 1 to 7,
A plurality of the third layers are present,
A dielectric layer including the first layer between the plurality of third layers. According to claim 8,
A plurality of the third layers are present,
A dielectric layer including the first layer between the plurality of third layers. According to claim 10,
A dielectric layer in which one of the plurality of second layers and one of the plurality of third layers are in contact with each other. According to claim 1,
At least one of the second layer and the third layer is a dielectric layer buried in the first layer. According to any one of claims 1 to 7,
Further comprising a fourth layer provided to increase the band gap of the first layer,
The fourth layer is a dielectric layer provided on at least one side of the first side and the second side of the third laminate comprising the first to third layers. According to claim 13,
A plurality of the second layers are present,
A dielectric layer provided with the first layer between the plurality of second layers. According to claim 13,
A plurality of the third layers are present,
A dielectric layer including the first layer between the plurality of third layers. 15. The method of claim 14,
A plurality of the third layers are present,
A dielectric layer including the first layer between the plurality of third layers. According to claim 1,
The first layer is a TiO2 dielectric layer. According to claim 1,
The second layer is a dielectric layer including at least one of SnO2, GeO2, GaO2 and SiO2. According to claim 1 or 3,
The third layer is a dielectric layer including at least one of Al2O3, Y2O3 and MgO. According to claim 1 or 3,
The third layer is a dielectric layer containing HfO2 or ZrO2. Forming a dielectric layer having a dielectric constant greater than that of silicon oxide, but forming it without doping;
forming a phase stabilization layer outside the dielectric layer to stabilize the rutile phase of the dielectric layer; and
Forming a first high band gap layer outside the dielectric layer and the phase stabilization layer to increase the band gap of the dielectric layer; According to claim 21,
The phase stabilization layer is a method of manufacturing a dielectric layer formed before forming the dielectric layer. According to claim 21,
Forming the dielectric layer, forming the phase stabilization layer, and forming the first high band gap layer are sequentially performed. According to claim 21,
The dielectric layer is a method of manufacturing a dielectric layer formed by sequentially stacking a plurality of dielectric material layers. 25. The method of claim 24,
The phase stabilization layer and the first high band gap layer are formed between the plurality of dielectric material layers. 26. The method of claim 25,
A method of manufacturing a dielectric layer in which one layer and the other of the phase stabilization layer and the first high band gap layer are sequentially formed and contacted with each other. According to claim 21,
The phase stabilization layer and the first high band gap layer are formed to be buried in the dielectric layer. According to claim 21,
At least one of the phase stabilization layer and the first high band gap layer includes a plurality of layers sequentially stacked, and the dielectric layer is formed between the plurality of layers. 29. The method of claim 28,
The phase stabilization layer and the first high band gap layer are repeatedly and alternately stacked. 29. The method of claim 28,
A method of manufacturing a dielectric layer in which a portion of the phase stabilization layer and a portion of the first high band gap layer are in contact with each other. According to claim 21,
Forming the first high band gap layer,
A method of manufacturing a dielectric layer comprising at least one step of forming the first high band gap layer before the other two steps and forming the first high band gap layer later than the other two steps. According to claim 21,
The method of manufacturing a dielectric layer further comprising forming a second high band gap layer for increasing the band gap of the dielectric layer. 33. The method of claim 32,
Forming the second high band gap layer,
A method of manufacturing a dielectric layer comprising at least one step of forming the second high band gap layer earlier than the three steps and forming the second high band gap layer later than the three steps. 33. The method of claim 32,
The first high band gap layer and the second high band gap layer are formed of different materials. a substrate including first and second doped regions spaced apart from each other;
a gate insulating layer provided on the substrate between the first and second doped regions; and
A gate electrode provided on the gate insulating layer; includes,
The gate insulating layer is an electronic device comprising the dielectric layer of claim 1. 36. The method of claim 35,
The dielectric layer further includes a fourth layer provided to increase a band gap of the first layer. a transistor including source, drain and gate electrodes; and
a data storage element coupled to the transistor;
The data storage element is a memory device comprising the dielectric layer of claim 1. 38. The method of claim 37,
The data storage element,
a lower electrode connected to the transistor;
an upper electrode facing the lower electrode; and
The memory device including a; the dielectric layer provided between the upper electrode and the lower electrode. In an electronic device including an electronic element provided to regulate the flow of an electrical signal,
The electronic device includes the electronic device of claim 35.

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