KR20230077587A - Semiconductor device - Google Patents

Abstract

A semiconductor device according to an exemplary embodiment of the present invention includes a plurality of word lines stacked on a substrate, at least one ground selection line disposed between the plurality of word lines and the substrate, and a plurality of word lines. and a cell region including a plurality of channel structures penetrating the at least one ground selection line, and a peripheral circuit region including peripheral circuits controlling the cell region, wherein the peripheral circuit region comprises: the plurality of words; During a first program time during which a first program voltage is input to a program word line selected from among lines, a first ground select bias voltage is input to the at least one ground select line, and a voltage different from the first program voltage is applied to the program word line. During a second program time during which the second program voltage is input, a second ground select bias voltage having a different magnitude from the first ground select bias voltage is input to the at least one ground select line.

Description

Semiconductor device {SEMICONDUCTOR DEVICE}

The present invention relates to semiconductor devices.

A semiconductor device may provide a function of writing and erasing data or reading recorded data. Semiconductor devices can be classified into non-volatile memory devices and volatile memory devices, and recorded data in the non-volatile memory device can be maintained even when power is cut off. The data storage capacity required for semiconductor devices is continuously increasing, and accordingly, the number of memory cells included in semiconductor devices is gradually increasing, and accordingly, various methods for securing stable operation of semiconductor devices are actively proposed. It is becoming.

One of the problems to be achieved by the technical idea of the present invention is to determine the level of a bias voltage input to a ground selection line, a source region, etc. according to the size of a program voltage input to a program word line and the position of the program word line during a program operation. By changing, it is intended to provide a semiconductor device that can operate stably.

A semiconductor device according to an exemplary embodiment of the present invention includes a plurality of word lines stacked on a substrate, at least one ground select line disposed between the plurality of word lines and the substrate, and a first line perpendicular to the substrate. a cell region including a plurality of channel structures extending in one direction and penetrating the plurality of word lines and the at least one ground selection line; and peripheral circuits controlling the cell region, wherein the plurality of word lines and a peripheral circuit region to which program voltages are input in order of approaching the substrate in the first direction, wherein the peripheral circuit region is connected to a program word line selected from among the plurality of word lines. During a first program time during which a program voltage is input, a first ground select bias voltage is input to the at least one ground select line, and a second program voltage having a magnitude different from that of the first program voltage is input to the program word line. A second ground selection bias voltage having a different magnitude from the first ground selection bias voltage is input to the at least one ground selection line during two program times.

A semiconductor device according to an exemplary embodiment of the present invention includes a plurality of word lines stacked on a substrate, at least one ground selection line disposed between the plurality of word lines and the substrate, and a first line perpendicular to the substrate. a cell including a plurality of channel structures extending in a direction and penetrating the plurality of word lines and the at least one ground selection line, and a source region formed on the substrate and electrically connected to the plurality of channel structures. and a peripheral circuit area including peripheral circuits controlling the cell area, wherein the peripheral circuit area is configured in a first program operation for a first program word line positioned at a first height in the first direction. , A second program word line positioned at a second height lower than the first height and sequentially inputting a first level voltage and a second level voltage different from the first level to the at least one ground selection line. In the second program operation for , a voltage of a third level lower than the first level and a voltage of a fourth level lower than the second level are sequentially input to the at least one ground selection line.

A semiconductor device according to an embodiment of the present invention includes ground select transistors connected to a common source line and a ground select line, string select transistors connected to bit lines and at least one string select line, and the ground select transistors. and memory cells connected in series between the string select transistors and connected to word lines, and a row decoder controlling the ground select transistors, the string select transistors, and the memory cells, wherein the The row decoder inputs a first program voltage during a first program time to a program word line connected to a selected memory cell among the memory cells, and inputs a second program voltage during a second program time after the first program time. The row decoder determines the absolute values of the voltages input to the ground selection line and the common source line at each of the first program time and the second program time, respectively, as magnitudes of the first program voltage and the second program voltage. decide based on

According to one embodiment of the present invention, a semiconductor device may sequentially input a first program voltage and a second program voltage to one program word line connected to a selected memory cell in a program operation. Depending on the difference between the first program voltage and the second program voltage, the voltage input to the ground select line, the source region, etc. may vary, and the threshold voltage of unselected memory cells connected to the program word line may change unintentionally. It is possible to minimize disturb and improve the performance of the semiconductor device. In addition, the stable operation of the semiconductor device can be secured by changing the level of the voltage input to the ground selection line, the source region, etc. according to the position of the program word line.

Various advantageous advantages and effects of the present invention are not limited to the above description, and will be more easily understood in the process of describing specific embodiments of the present invention.

1 is a schematic block diagram of a system including a semiconductor device according to an exemplary embodiment of the present invention.
2 is a schematic block diagram of a semiconductor device according to an exemplary embodiment of the present invention.
3 is a schematic circuit diagram of a semiconductor device according to an exemplary embodiment of the present invention.
4A to 4D are diagrams provided to explain the operation of a semiconductor device according to an exemplary embodiment of the present invention.
5 and 6 are diagrams schematically illustrating a semiconductor device according to an exemplary embodiment of the present invention.
7 to 9 are diagrams schematically illustrating a semiconductor device according to an exemplary embodiment of the present invention.
10 is a diagram provided to describe an operation of a semiconductor device according to an exemplary embodiment.
11 to 13 are diagrams provided to explain the operation of a semiconductor device according to an exemplary embodiment of the present invention.
14 to 19 are diagrams provided to explain the operation of a semiconductor device according to an exemplary embodiment of the present invention.
20 and 21 are diagrams schematically illustrating a semiconductor device according to an exemplary embodiment of the present invention.
22 and 23 are diagrams schematically illustrating a semiconductor device according to an exemplary embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

1 is a schematic block diagram of a system including a semiconductor device according to an exemplary embodiment of the present invention.

Referring to FIG. 1 , a system 1 may include a semiconductor device 10 provided as a memory device and a memory controller 20 . The system 1 may support a plurality of channels CH1 to CHm, and the semiconductor device 10 and the memory controller 20 may be connected through the plurality of channels CH1 to CHm. For example, the system 1 may be implemented as a storage device such as a solid state drive (SSD).

The semiconductor device 10 may include a plurality of memory chips NVM11 to NVMmn. Each of the memory chips NVM11 to NVMmn may be connected to one of the plurality of channels CH1 to CHm through a corresponding way. For example, the memory devices NVM11 to NVM1n are connected to the first channel CH1 through ways W11 to W1n, and the memory devices NVM21 to NVM2n are connected to the first channel CH1 through ways W21 to W2n. It may be connected to the second channel CH2. In an exemplary embodiment, each of the memory chips NVM11 to NVMmn may be implemented as an arbitrary memory unit capable of operating according to individual commands from the memory controller 20 . For example, each of the memory chips NVM11 to NVMmn may be implemented as a chip or die, but the present invention is not limited thereto.

The memory controller 20 may transmit and receive signals to and from the semiconductor device 10 through a plurality of channels CH1 to CHm. For example, the memory controller 20 transmits commands CMDa to CMDm, addresses ADDRa to ADDRm, and data DATAa to DATAm to the semiconductor device 10 through channels CH1 to CHm. Data DATAa to DATAm may be transmitted to the device 10 or received from the semiconductor device 10 .

The memory controller 20 may select one of nonvolatile memory devices connected to a corresponding channel through each channel and transmit/receive signals to and from the selected nonvolatile memory device. For example, the memory controller 20 may select the nonvolatile memory device NVM11 from among the memory devices NVM11 to NVM1n connected to the first channel CH1 . The memory controller 20 transmits the command CMDa, address ADDRa, and data DATAa to the selected memory device NVM11 through the first channel CH1, or transmits data DATAa from the selected memory device NVM11. ) can be received.

The memory controller 20 may transmit and receive signals to and from the semiconductor device 10 in parallel through different channels. For example, the memory controller 20 transmits the command CMDa to the semiconductor device 10 through the second channel CH2 while transmitting the command CMDa to the semiconductor device 10 through the first channel CH1. can transmit. For example, the memory controller 20 receives data DATAb from the semiconductor device 10 through a second channel CH2 while receiving data DATAa from the semiconductor device 10 through a first channel CH1. can receive

The memory controller 20 may control overall operations of the semiconductor device 10 . The memory controller 20 may control each of the memory chips NVM11 to NVMmn connected to the channels CH1 to CHm by transmitting signals to the channels CH1 to CHm. For example, the memory controller 20 may transmit the command CMDa and the address ADDRa through the first channel CH1 to control the selected one of the memory devices NVM11 to NVM1n.

Each of the memory chips NVM11 to NVMmn may operate under the control of the memory controller 20 . For example, the memory device NVM11 may program data DATAa according to the command CMDa, address ADDRa, and data DATAa provided through the first channel CH1. For example, the memory device NVM21 reads data DATAb according to the command CMDb and address ADDRb provided through the second channel CH2, and transfers the read data DATAb to the memory controller 20. can be sent to

1 shows that the semiconductor device 10 communicates with the memory controller 20 through m channels and includes n nonvolatile memory devices corresponding to each channel, but the channels The number and number of nonvolatile memory devices connected to one channel may be variously changed.

2 is a schematic block diagram of a semiconductor device according to an exemplary embodiment of the present invention.

Referring to FIG. 2 , the semiconductor device 30 may include a control logic circuit 32 , a cell region 33 , a page buffer unit 34 , a voltage generator 35 , and a row decoder 36 . The semiconductor device 30 may further include an interface circuit 31 and may further include a column logic, a pre-decoder, a temperature sensor, a command decoder, an address decoder, a source driver, and the like. The semiconductor device 30 may be a memory device that stores data, and may be, for example, a non-volatile memory device that retains stored data even when power is cut off.

The control logic circuit 32 may generally control various operations within the semiconductor device 30 . The control logic circuit 32 may output various control signals in response to the command CMD and/or the address ADDR received by the interface circuit 31 . For example, the control logic circuit 32 may output a voltage control signal CTRL_vol, a row address X-ADDR, and a column address Y-ADDR.

The cell area 33 may include a plurality of memory blocks BLK1 -BLKz (z is a positive integer), and each of the plurality of memory blocks BLK1 -BLKz may include a plurality of memory cells. . In an embodiment, the plurality of memory blocks BLK1 -BLKz may be separated from each other by first isolation regions including an insulating material, and inside each of the plurality of memory blocks BLK1 -BLKz, a first separation region may be formed. Second separation regions different from the separation regions may be disposed. For example, each of the second separation regions may have a structure different from that of the first separation regions.

For example, the plurality of memory blocks BLK1 to BLKz may include main blocks for storing data and at least one spare block for storing data necessary for the operation of the semiconductor device 30 . The cell region 33 may be connected to the page buffer unit 34 through bit lines BL, and may be connected to the page buffer unit 34 through word lines WL, string select lines SSL, and ground select lines GSL. It may be connected to the row decoder 36.

In an exemplary embodiment, the cell region 33 may include a 3D memory cell array, and the 3D memory cell array may include a plurality of NAND strings. Each NAND string may include memory cells respectively connected to word lines vertically stacked on a substrate. U.S. Patent Publication No. 7,679,133, U.S. Patent Publication No. 8,553,466, U.S. Patent Publication No. 8,654,587, U.S. Patent Publication No. 8,559,235, and U.S. Patent Application Publication No. 2011/0233648 are incorporated herein by reference. are combined In an exemplary embodiment, the cell region 33 may include a 2D memory cell array, and the 2D memory cell array may include a plurality of NAND strings disposed along row and column directions.

The page buffer unit 34 may include a plurality of page buffers PB1 - PBn (n is an integer greater than or equal to 3), and the plurality of page buffers PB1 - PBn may include a plurality of bit lines BL. It may be connected to each of the memory cells through. The page buffer unit 34 may select at least one bit line from among the bit lines BL in response to the column address Y-ADDR. The page buffer unit 34 may operate as a write driver or a sense amplifier according to an operation mode. For example, during a program operation, the page buffer unit 34 may apply a bit line voltage corresponding to data to be programmed to the selected bit line. During a read operation, the page buffer unit 34 may detect data stored in a memory cell by sensing a current or voltage of a selected bit line. Data to be programmed into the cell area 33 through a program operation and data read from the cell area 33 through a read operation may be input/output through the interface circuit 31 .

The voltage generator 35 may generate various types of voltages for performing program, read, and erase operations based on the voltage control signal CTRL_vol. For example, the voltage generator 35 may generate a program voltage, a read voltage, a pass voltage, a program verify voltage, an erase voltage, and the like. In one embodiment, the control logic circuit 32 may control the voltage generator 35 to generate voltages for executing program, read, and erase operations using data stored in the spare block. Some of the voltages generated by the voltage generator 35 may be input to the word lines WL as word line voltages VWL by the row decoder 36, and some may be input to the common source line by the source driver. It could be.

The row decoder 36 may select one of a plurality of word lines WL and select one of a plurality of string select lines SSL in response to the row address X-ADDR. For example, during a program operation, the row decoder 36 may apply a program voltage and a program verify voltage to a selected word line, and may apply a read voltage to a selected word line during a read operation.

3 is a schematic circuit diagram of a semiconductor device according to an exemplary embodiment of the present invention.

The memory block BLK shown in FIG. 3 represents a three-dimensional memory block formed in a three-dimensional structure on a substrate. For example, a plurality of NAND strings included in the memory block BLK may be formed in a direction perpendicular to the substrate.

Referring to FIG. 3 , the memory block BLK may include a plurality of NAND strings NS11 to NS43 connected between the bit lines BL1 to BL3 and the common source line CSL. Each of the plurality of NAND strings NS11 to NS43 may include a string select transistor SST, a plurality of memory cells MC1 to MC8, and a ground select transistor GST. 3 illustrates that each of the plurality of memory NAND strings NS11 to NS43 includes eight memory cells MC1 to MC8, but is not necessarily limited thereto.

The string select transistor SST may be connected to corresponding string select lines SSL1 to SSL4. The plurality of memory cells MC1 to MC8 may be connected to corresponding word lines WL1 to WL8, respectively. According to example embodiments, at least one of the word lines WL1 to WL8 may be provided as a dummy word line. The ground select transistor GST may be connected to corresponding ground select lines GSL1 - GSL2 . The string select transistor SST may be connected to corresponding bit lines BL1 - BL3 , and the ground select transistor GST may be connected to the common source line CSL.

Word lines (eg, WL1) having the same height may be connected in common, and at least some of the ground select lines GSL1 to GSL2 and the string select lines SSL1 to SSL4 may be separated from each other. For example, referring to FIG. 3 , the string select lines SSL1 to SSL4 disposed at the same height may be separated from each other, and some of the ground select lines GSL1 to GSL2 disposed at the same height may be connected to each other. Accordingly, in the embodiment shown in FIG. 3 , two of the two string select lines SSL1 to SSL4 may be disposed on each of the ground select lines GSL1 to GSL2 . Although the memory block BLK is illustrated in FIG. 3 as being connected to eight word lines WL1 to WL8 and three bit lines BL1 to BL3, it is not necessarily limited thereto.

4A to 4D are diagrams provided to explain the operation of a semiconductor device according to an exemplary embodiment of the present invention.

4A to 4D may be diagrams illustrating distribution of threshold voltages of memory cells according to the number of bits of data stored in each of the memory cells included in the memory device. First, FIG. 4A may be a diagram illustrating threshold voltage distribution of memory cells storing 1-bit data.

Referring to FIG. 4A , memory cells may have one of a first state S1 and a second state S2. The first state S1 may have a lower voltage than the second state S2. In the embodiment shown in FIG. 6 , the read voltage V _RD input to word lines by the memory controller for a read operation may be a voltage between the first state S1 and the second state S2. .

FIG. 4B may be a diagram illustrating threshold voltage distribution of memory cells in memory cells each capable of storing 2-bit data. In the embodiment shown in FIG. 4B , the memory cells may have any one of the first to fourth states S1 to S4. The memory controller may perform a read operation by inputting the first to third read voltages V _RD1 -V _RD3 between the first to fourth states S1 to S4 to word lines. Also, 2-bit data may be stored in each of the memory cells through a plurality of program operations.

FIG. 4C may be a diagram illustrating threshold voltage distribution of memory cells in memory cells each capable of storing 3-bit data. In the embodiment shown in FIG. 4C , the memory cells may have any one of the first to eighth states S1 to S8. The memory controller may perform a read operation by inputting the first to seventh read voltages V _RD1 -V _RD7 between the first to eighth states S1 to S8 to word lines.

4D may be a diagram illustrating threshold voltage distribution of memory cells each capable of storing 4-bit data. In the embodiment shown in FIG. 4D , the memory cells may have any one of the first to sixteenth states S1 to S16. The memory controller may perform a read operation by inputting the first to fifteenth read voltages V _RD1 -V _RD15 between the first to sixteenth states S1 to S16 to word lines.

As described with reference to FIGS. 4A to 4D , the semiconductor device according to an exemplary embodiment of the present invention may program or delete data by changing threshold voltages of memory cells. When the threshold voltage of each memory cell maintains the voltage immediately after the program operation, the semiconductor device can accurately read data of each memory cell.

However, as described above with reference to FIG. 3 , in the semiconductor device according to an embodiment of the present invention, some memory cells may be connected to the same word line and/or bit line, and thus, non-selected memory that is not selected in a program operation. A predetermined voltage is inevitably applied to the cells as well. When threshold voltages of unselected memory cells are changed during a program operation on a selected memory cell, data of the unselected memory cells may be damaged, which may lead to deterioration in performance and reliability of the semiconductor device.

In one embodiment of the present invention, in a program operation, a string selection line connected to a NAND string including a selected memory cell and a The level of the voltage input to the ground selection line and the common source line can be adjusted. Accordingly, a threshold voltage change that may occur in unselected memory cells during a program operation may be minimized, and performance and reliability of the semiconductor device may be improved.

5 and 6 are diagrams schematically illustrating a semiconductor device according to an exemplary embodiment of the present invention.

Referring first to FIG. 5 , a semiconductor device 40 according to an exemplary embodiment may include a plurality of mats 41 to 44 and a logic circuit 45 . For example, each of the plurality of mats 41 to 44 may include the cell area 33, the page buffer unit 35, and the row decoder 36 described with reference to FIG. 2, and the logic circuit 45 ) may include a control logic circuit 32 and a voltage generator 35 and the like.

According to embodiments, each of the plurality of mats 41 to 44 may operate independently of each other. For example, while the first mat 41 executes a program operation of writing data received from an external memory controller, etc., the logic circuit 45 reads data stored in the second mat 42 and outputs it to the outside. can do.

Next, FIG. 6 may be a diagram showing the arrangement of a cell region and a peripheral circuit region in one of the mats included in the semiconductor device 50 according to an embodiment of the present invention. Referring to FIG. 6 , a peripheral circuit area is disposed around the cell areas 51A and 51B, and for example, a row decoder 52 may be disposed on both sides of each of the cell areas 51A and 51B. Meanwhile, the page buffer units 53A and 53B may be disposed on one side of the cell regions 51A and 51B, respectively. A direction in which each of the cell regions 51A and 51B and the row decoder 52 are adjacent may cross a direction in which each of the cell regions 51A and 51B is adjacent to the page buffer units 53A and 53B. The row decoder 52 and the page buffer units 53A and 53B may be connected to a logic circuit that controls overall operations of the semiconductor device 50 and an input/output interface that communicates with an external device through the input/output circuits 54A and 54B. there is.

For example, word lines, string selection lines, and ground selection lines included in each of the cell regions 51A and 51B extend in the horizontal direction of FIG. 6 and are adjacent to the cell regions 51A and 51B. 52) can be linked. Meanwhile, bit lines connected to the channel layers in each of the cell regions 51A and 51B extend in a vertical direction and are connected to page buffer units 53A and 53B disposed on one side of each of the cell regions 51A and 51B. can 6, the cell regions 51A and 51B, the row decoder 52, the page buffer units 53A and 53B, and the input/output circuits 54A and 54B are formed on one substrate. It can be.

7 to 9 are diagrams schematically illustrating a semiconductor device according to an exemplary embodiment of the present invention.

7 may be a top plan view of a portion of the semiconductor device 100 according to an exemplary embodiment. Referring to FIG. 7 , the semiconductor device 100 may include a cell region CELL and a peripheral circuit region PERI, and the cell region CELL may include a cell array region CAR and a cell contact region CTR. can For example, the cell array area CAR may be an area where the channel structures CH are disposed, and the cell contact area CTR may be an area where the cell contacts CMC are disposed. In the embodiment shown in FIG. 7 , the cell contact region CTR may be disposed between the cell array region CAR and the peripheral circuit region PERI.

A plurality of gate electrode layers stacked in a first direction (Z-axis direction) and a plurality of channel structures CH extending in the first direction and penetrating the plurality of gate electrode layers may be disposed in the cell region CELL. . The plurality of gate electrode layers may be formed of a conductive material such as metal or metal silicide, and each of the plurality of channel structures CH may include a channel layer, a charge storage layer, a tunneling layer, and the like.

A plurality of devices LVTR and HVTR are disposed in the peripheral circuit area PERI, and the plurality of devices LVTR and HVTR have a first well region WA1 and a second well region WA2 having different impurity characteristics. ) can be formed. For example, low voltage devices LVTR may be formed in the first well area WA1 , and high voltage devices HVTR may be formed in the second well area WA2 . 7 , at least some of the elements LVTR and HVTR adjacent to the cell region CELL in the second direction (X-axis direction) are cell contacts CMC of the cell contact region CTR. ) may be elements included in a row decoder connected to.

As shown in FIG. 7 , the cell area CELL includes a plurality of blocks BLK, and the plurality of blocks BLK extends in the second direction in a plurality of first separation regions DA1. separated from each other by, and may be arranged along the third direction (Y-axis direction). Each of the plurality of first separation regions DA1 may extend along the second direction, cross the cell region CELL, and may include an insulating material. For example, each of the plurality of first separation regions DA1 may be formed of silicon oxide, silicon nitride, or the like.

Meanwhile, at least one of the plurality of second separation regions DA2 may be disposed in each of the plurality of blocks BLK. The plurality of second separation regions DA2 extends in the second direction like the plurality of first separation regions DA1 , but are not a boundary between the plurality of blocks BLK, but form a boundary between the plurality of blocks BLK. It can be placed inside one of them. In the embodiment shown in FIG. 5 , each of the plurality of blocks BLK is illustrated as including two second separation regions DA2, but the second separation included in each of the plurality of blocks BLK. The number of regions DA2 may vary according to embodiments.

Referring to FIG. 7 , each of the plurality of second separation regions DA2 disposed inside each of the plurality of blocks BLK has a first line DL1 and a second line DL1 in the second direction (X-axis direction). can be separated by line DL2. The first line DL1 and the second line DL2 may be separated from each other in the second direction. Accordingly, some of the plurality of gate electrode layers may be connected as one layer in each of the plurality of blocks BLK through the first line DL1 and the second line DL2 .

For example, gate electrode layers providing a plurality of word lines among a plurality of gate electrode layers may be connected to each other between the first line DL1 and the second line DL2 . For example, the gate electrode layer disposed at the first height and providing one of the word lines may be connected to each other between the first line DL1 and the second line DL2, and each of the plurality of blocks BLK may not be divided into a plurality of regions along the third direction (Y-axis direction) within the region.

On the other hand, the gate electrode layers providing the string selection line may be divided into a plurality of regions in the third direction by the first line DL1 and the upper separation layer SC in each of the plurality of blocks BLK. Meanwhile, portions of the gate electrode layers providing the ground selection line may be connected to each other within each of the plurality of blocks BLK. In one embodiment, under the pair of gate electrode layers providing a pair of string selection lines separated from each other by the upper separation layer SC, a pair of gate electrode layers providing a ground selection line may be connected to each other. . In this case, the number of string selection lines arranged in one block BLK may be greater than the number of ground selection lines.

FIG. 8 is a view showing a cross section in the direction II′ of FIG. 7 . 7 and 8 together, the semiconductor device 100 includes a plurality of gate electrode layers 110 and a plurality of insulating layers stacked in a first direction (Z-axis direction) perpendicular to the upper surface of the substrate 101. 120 , and channel structures CH extending in the first direction and penetrating the gate electrode layers 110 and the insulating layers 120 . Each of the channel structures CH includes a channel layer 132 connected to the substrate 101, a gate dielectric layer 131 disposed between the channel layer 132 and the gate electrode layers 110, and a channel layer 132 inside the channel layer 132. The buried insulating layer 133 and the drain region 134 over the channel layer 132 may be included. An interlayer insulating layer 150 may be disposed on the plurality of gate electrode layers 110 .

The gate dielectric layer 131 may include a tunneling layer, a charge storage layer, a blocking layer, and the like. For example, at least one of the tunneling layer, the charge storage layer, and the blocking layer may be formed to surround the gate electrode layers 110 . The drain region 134 is connected to at least one of the bit lines BL through the bit line contact 135, and the bit lines BL may be connected to a page buffer formed in the peripheral circuit area PERI. The bit lines BL may extend in the third direction (Y-axis direction).

9 may be a diagram simply illustrating the semiconductor device 200 according to an exemplary embodiment. Referring to FIG. 9 , the semiconductor device 200 includes a plurality of word lines WL stacked on a substrate 201 and a plurality of string select lines SSL1 disposed on the plurality of word lines WL. SSL2), a ground select line GSL disposed between the plurality of word lines WL and the substrate 201, and the like. In the embodiment shown in FIG. 9, the first string selection line SSL1 and the second string selection line SSL2 are stacked in a first direction (Z-axis direction), but a plurality of string selection lines SSL1 , SSL2) may vary depending on the embodiment.

The plurality of channel structures CH extends in the first direction and penetrates the plurality of word lines WL, the plurality of string select lines SSL1 and SSL2, and the ground select line GSL to form the substrate 201. and may be connected to the bit lines BL1 and BL2 through upper channel contacts CHCNT. The plurality of word lines WL, the plurality of string selection lines SSL1 and SSL2, and the ground selection line GSL are formed in the third direction by the separation area DA extending in the second direction (X-axis direction). (Y-axis direction) can be separated from each other.

The plurality of word lines WL may provide memory cells together with a plurality of channel structures CH. The number of memory cells may be determined according to the number of word lines WL and the number of channel structures CH.

In one embodiment of the present invention, a program operation of writing data into a plurality of memory cells is performed in a first direction from a word line disposed above to a word line disposed below among a plurality of word lines WL. can be executed For example, in the embodiment shown in FIG. 9 , a program operation for the first memory cell MC1 connected to the first word line WL1 is executed first, and the second memory cell MC1 connected to the second word line WL2 is executed first. A program operation for the memory cell MC2 may be executed last. Accordingly, the program voltage may be input to the first word line W1L first, and the program voltage may be input to the second word line WL2 last.

As shown in FIG. 9 , since the program voltage is input to each of the plurality of word lines WL as a unit, while the program voltage is input to the first word line WL1, not the first memory cell MC1. , the program voltage may also be applied to other memory cells connected to the first word line WL1. Accordingly, data of memory cells other than the first memory cell MC1 may be unintentionally changed. For example, unlike the first memory cell MC1 , data of memory cells provided by the channel structures CH connected to the first bit line BL1 and connected to the first word line WL1 may be unintentionally transmitted. can be changed.

In one embodiment of the present invention, the above problem can be solved by boosting the voltage of the channel layer in unselected memory cells. When the channel layer voltages of memory cells not selected in the program operation are boosted, a difference between a program voltage input through a word line and a channel layer voltage may decrease. Accordingly, it is possible to minimize unintentional programming of unselected memory cells.

For example, the semiconductor device 200 may perform a channel initialization operation or the like prior to applying a program voltage to a program word line selected from among a plurality of word lines WL in order to perform a program. In one embodiment of the present invention, while the channel initialization operation is being executed, the magnitude of the voltage input to the ground selection line (GSL) and/or the common source line formed on the substrate 201 and connected to the channel structures (CH). The voltage of the channel layer of non-selected memory cells may be boosted as necessary by varying V according to the size of the program voltage and/or the position of the program word line. For example, the position of the program word line may be a position of the program word line among the plurality of word lines WL along the first direction.

10 is a diagram provided to describe an operation of a semiconductor device according to an exemplary embodiment.

Referring to FIG. 10 , a program voltage may be input to a peripheral circuit region of a semiconductor device according to an embodiment of the present invention by selecting one program word line PGM WL among a plurality of word lines. As shown in FIG. 10 , during the program operation, the peripheral circuit area may input the program voltage to the program word line PGM WL two or more times. For example, the row decoder of the peripheral circuit area inputs a first program voltage (V _PGM1 ) to the program word line (PGM WL) during a first program time, and programs a second program voltage (V _PGM2 ) during a second program time. It can be input to the word line (PGM WL). The first program voltage (V _PGM1 ) and the second program voltage (V _PGM2 ) may have different sizes. In the embodiment shown in FIG. 10 , the first program voltage (V PGM1 ) is the second program voltage (V _PGM1 ). _PGM2 ) may be smaller.

Each of the first program time and the second program time may include a channel initialization time, a program execution time, a program recovery time, and the like. During the channel initialization time, the semiconductor device may set the voltage of the channel layer by controlling the row decoder. The program execution time may be a time when the program voltage is input to the program word line PGM WL, and the program recovery time may be a time when the program voltage or the like is discharged.

First, during the channel initialization time of the first program time, the peripheral circuit area may input the selection voltage V _SEL to the string selection line SEL SSL connected to the same NAND string as the selected memory cell. Meanwhile, the unselect voltage V _UNSEL may be input to the string select line UNSEL SSL connected to a NAND string different from the selected memory cell. As an example, the selection voltage (V _SEL ) may be a voltage greater than the threshold voltage of the string selection transistor connected to the string selection line, and the non-selection voltage (V _UNSEL ) is a voltage less than the threshold voltage of the string selection transistor connected to the string selection line can be

Meanwhile, the peripheral circuit region may input the first ground selection bias voltage V _GB1 to the ground selection line GSL and the first source bias voltage V _CB1 to the common source line CSL. The common source line CSL is electrically connected to a source region formed on a substrate in a cell region of a semiconductor device, and thus, NAND strings of a block in which a selected memory cell is disposed may be connected in common to one common source line CSL. there is.

When the channel initialization time elapses, the first ground selection bias voltage (V _GB1 ) is discharged, and the levels of the first source bias voltage (V _CB1 ) and the selected voltage (V _SEL ) and the unselected voltage (V _UNSEL ) are maintained. can During program execution time, the first program voltage V _PGM1 may be input to the program word line PGM WL connected to the selected memory cell. It may first be discharged before the first ground selection bias voltage V _GB1 and the first program voltage V _PGM1 are input. On the other hand, the first source bias voltage V _CB1 input to the source region through the common source line CSL may be maintained while the first program voltage V _PGM1 is input.

Charges may be trapped in the charge storage layer of the selected memory cell by a difference between the first program voltage V _PGM1 input to the program word line PGM WL and the channel voltage of the NAND string including the selected memory cell. During program execution time, a pass voltage lower than the first program voltage V _PGM1 may be input to word lines other than the program word line PGM WL.

During the first program time, a ground voltage is input to a bit line connected to a selected NAND string including a selected memory cell, and a voltage higher than the ground voltage is input to bit lines connected to a non-select NAND string not including a selected memory cell. It can be. Accordingly, the voltage of the channel layer of the unselected NAND string may be relatively higher than that of the channel layer of the selected NAND string, and data of memory cells included in the unselected NAND string may be prevented from being changed unintentionally. For example, data change of unselected memory cells connected to the program word line PGM WL in the unselected NAND string may be prevented.

However, in the second program operation in which the second program voltage (V _PGM2 ) relatively higher than the first program voltage (V _PGM1 ) is input, the unselected memory cell connected to the program word line (PGM WL) in the unselected NAND string The probability that the data of is changed may increase. In one embodiment of the present invention, the magnitude of the second ground selection bias voltage V _GB2 input to the ground selection line GSL in the second program operation is greater than the magnitude of the first ground selection bias voltage V _GB1 . can Also, in the second program operation, the level of the second source bias voltage V _CB2 input to the common source line CSL may be greater than the level of the first source bias voltage VCB1 . In other words, the absolute value of the voltage input to the ground select line GSL and the common source line CSL may vary according to the magnitude of the program voltage input to the program word line PGM WL. Therefore, the voltage of the channel layer of the unselected NAND string may have a relatively higher level in the second program operation than in the first program operation, and data of unselected memory cells are unintentionally changed in the second program operation. can be effectively prevented.

11 to 13 are diagrams provided to explain the operation of a semiconductor device according to an exemplary embodiment of the present invention.

Referring to FIGS. 11 to 13 , the semiconductor device 300 may include a plurality of NAND strings NS1 to NS4 . A plurality of NAND strings NS1 to NS4 are included in one block, and thus may share word lines WL1 to WL3. The first and second NAND strings NS1 and NS2 are commonly connected to the first bit line BL1, and the third and fourth NAND strings NS3 and NS4 are connected to the second bit line BL2 in common. can be connected to

In addition, the first and third NAND strings NS1 and NS3 are commonly connected to the first string selection line SSL1, and the second and fourth NAND strings NS2 and NS4 are connected to the second string selection line (SSL1). SSL2) can be commonly connected. The plurality of NAND strings NS1 to NS4 may share one ground select line GSL and one common source line CSL. In one embodiment described with reference to FIGS. 11 to 13 , the selected memory cell A is included in the first NAND string NS1 and may be connected to the second word line WL2 .

First, FIG. 11 may be a diagram illustrating bias voltages input to the plurality of NAND strings NS1 to NS4 during channel initialization time. Referring to FIG. 11 , during channel initialization time, a ground voltage is input to the first bit line BL1, which is a selected bit line, and a power supply voltage VCC higher than the ground voltage is applied to a second bit line BL2, which is an unselected bit line. ) can be entered. Meanwhile, the power supply voltage VCC may be input to the first string select line SSL1 connected to the first NAND string NS1 , and the ground voltage may be input to the second string select line SSL2 . A ground voltage may be input to the word lines WL1 to WL3.

Meanwhile, during the channel initialization time, the first ground selection bias voltage V _GB1 may be input to the ground selection line GSL, and the first source bias voltage V _CB1 may be input to the common source line CSL. The ground select transistor connected to the ground select line GSL1 may be turned on by the first ground select bias voltage V _GB1 , and thus the voltage of the channel layer of the NAND strings NS1 to NS4 may be set to the first source bias voltage. (V _CB1 ). However, the voltage of the channel layer of the first NAND string NS1 including the selected memory cell A is changed by the ground voltage input to the first bit line BL1 to the third and fourth NAND strings NS3, NS4) may be boosted to a level smaller than the voltage of the channel layer.

Meanwhile, the channel layer of the second NAND string NS2 connected to the first bit line BL1 and including the unselected memory cell B is controlled by the ground voltage input to the second string select line SSL2. 1 may not be electrically connected to the bit line BL1. Accordingly, the voltage of the channel layer of the second NAND string NS2 may also be boosted by the first source bias voltage V _CB1 .

12, during program execution time, the first program voltage V _PGM1 is input to the second word line WL2, which is the program word line, and the pass voltage V PGM1 is applied to the remaining word lines WL1 and WL3. _PASS ) can be input. Since the voltages of the channel layers of the first and second NAND strings NS1 and NS2 are boosted to a level lower than the voltages of the channel layers of the third and fourth NAND strings NS3 and NS4, the selected memory cell A ), charges may move from the channel layer and be trapped in the charge storage layer due to a voltage difference between the first program voltage V _PGM1 and the channel layer. On the other hand, in the unselected memory cells B, C, and D, charges may not be trapped in the charge storage layer due to the voltage of the channel layer boosted to a relatively high level.

13 may be a diagram illustrating bias voltages input to the plurality of NAND strings NS1 to NS4 during the program recovery time. During the program recovery time, bias voltages input to the plurality of NAND strings NS1 to NS4 may be discharged.

11 to 13 may be diagrams illustrating bias voltages input to the plurality of NAND strings NS1 to NS4 during the first program time described above with reference to FIG. 10 . The second program time after the first program time may also include a channel initialization time, a program execution time, and a program recovery time. However, as described with reference to FIG. 10 , during the program execution time of the second program time, the second program voltage having a higher level than the first program voltage V _PGM1 is applied to the second word line WL2 that is the program word line. (V _PGM2 ) can be input.

Accordingly, when the voltages of the channel layers of the second to fourth NAND strings NS2 to NS4 including the unselected memory cells B, C, and D are not sufficiently boosted, the unselected memory cells B, C, and D are not sufficiently boosted. Charges may be trapped in the charge storage layer of D). In an embodiment of the present invention, the second ground selection bias voltage (V) greater than the first ground selection bias voltage (V _GB1 ) is applied to the ground selection line (GSL) during the second program time so that the above problem does not occur. _GB2 ), and a second source bias voltage (V _CB2 ) greater than the first source bias voltage (V _CB1 ) may be input to the common source line (CSL).

As described above, the voltage of the channel layer of the second to fourth NAND strings NS2 to NS4 is controlled by increasing the level of the bias voltage input to the ground selection line GSL and the common source line CSL. Compared to 1 program time, boosting may be performed to a higher level in the second program time. Therefore, even though the second program voltage V _PGM2 higher than the first program voltage V _PGM1 is input to the second word line WL2 during the second program time, the unselected memory cells B, C, and D ) can effectively prevent charges from being trapped in the charge trap layer.

14 to 19 are diagrams provided to explain the operation of a semiconductor device according to an exemplary embodiment of the present invention.

Referring first to FIG. 14 , similarly to the description with reference to FIG. 10 , during a program operation, the peripheral circuit area may input a program voltage to the program word line PGM WL two or more times. For example, the row decoder of the peripheral circuit area inputs a first program voltage (V _PGM1 ) to the program word line (PGM WL) during a first program time, and programs a second program voltage (V _PGM2 ) during a second program time. It can be input to the word line (PGM WL). In the embodiment shown in FIG. 14 , the first program voltage V _PGM1 may be greater than the second program voltage V _PGM2 .

A bias voltage input to each of the string select lines SEL SSL and UNSEL SSL may be similar to that described above with reference to FIG. 10 . However, in the embodiment shown in FIG. 14 , the level of the first ground selection bias voltage (V _GB1 ) input to the ground selection line (GSL) during the first program time is It may be greater than the magnitude of the second ground selection bias voltage (V _GB2 ) input to .

In addition, the magnitude of the first source bias voltage (V _CB1 ) input to the common source line (CSL) during the first program time is equal to the second source bias voltage (V CB1 ) input to the common source line (CSL) during the second program time. _CB2 ) may be larger than the size of This may be because the first program voltage V _PGM1 is greater than the second program voltage V _PGM2 .

Next, referring to FIG. 15 , the first program voltage V _PGM1 may be lower than the second program voltage V _PGM2 . During the program operation, the peripheral circuit area may input the program voltage to the program word line PGM WL two or more times, and may not perform the channel initialization operation after the first program time. In the embodiment shown in FIG. 15 , channel initialization is not performed during the second program time, and therefore, the second source bias voltage V _CB2 input to the common source line CSL during the second program time is the ground voltage may have a level corresponding to

When channel initialization is not performed during the second program time, leakage from the channel layer boosted to a predetermined level during the previous first program time to the common source line (CSL) receiving the second source bias voltage (V _CB2 ) current can flow. In an embodiment of the present invention, a negative voltage may be input to the ground select line GSL in order to block leakage current flowing from the channel layer to the common source line CSL during the second program time. Referring to FIG. 15 , after the second program time starts, the second ground selection bias voltage V _GB2 , which is a negative voltage, may be input to the ground selection line GSL.

16 and 17 , the voltage of the common source line CSL may not be discharged during the program recovery time of the first program time. First, referring to FIG. 16 , unlike the first ground selection bias voltage (V _GB1 ) discharged after the channel initialization time of the first program time and the first program voltage (V _PGM1 ) discharged during the program recovery time, the common source line The voltage of (CSL) may be maintained at the first source bias voltage (V _CB1 ).

When the second program time starts and the second ground selection bias voltage V _GB2 is input to the ground selection line GSL, the ground selection transistor connected to the ground selection line GSL is turned on and the second source bias voltage ( V _CB2 ) may be input to a channel layer of NAND strings. Accordingly, a channel initialization operation for boosting the voltage of the channel layer may be performed. Since the voltage of the common source line CSL is maintained without being discharged, the second source bias voltage V _CB2 may have the same level as the first source bias voltage V _CB1 .

Meanwhile, in the embodiment shown in FIG. 17 , the voltage of the common source line CSL may not be discharged during the program recovery time of the first program time. Also, during the channel initialization time of the second program time, the voltage of the common source line CSL may increase from the first source bias voltage V _CB1 to the second source bias voltage V _CB2 . At the same time, a channel initialization operation for boosting a channel voltage may be performed while the ground select transistor is turned on by the second ground select bias voltage V _GB2 input to the ground select line GSL during the channel initialization time.

During the second program time, a second program voltage V _PGM2 higher than the first program voltage V _PGM1 may be input to the program word line PGM WL. As shown in FIG. 17, by inputting a second source bias voltage (V _CB2 ) greater than the first source bias voltage (V _CB1 ) to the common source line (CSL) during the channel initialization time of the second program time, non-selection Channel layer voltages of NAND strings including memory cells may be boosted to a higher level during the second program time than during the first program time. Accordingly, even though the second program voltage V _PGM2 higher than the first program voltage V _PGM1 is input to the program word line PGM WL, charges are transferred in unselected memory cells connected to the program word line PGM WL. This occurrence can be minimized.

Operations according to the embodiments described with reference to FIGS. 16 and 17 may be applied even when the first program voltage V _PGM1 is smaller than the second program voltage V _PGM2 . For example, when the first program voltage V _PGM1 is lower than the second program voltage V _PGM2 , the voltage input to the common source line CSL is maintained without being discharged during the program recovery time of the first program time. can Alternatively, during the first program time, the voltage of the common source line (CSL) is maintained at the first source bias voltage (V _CB1 ) without discharging, and when the second program time starts, the voltage of the common source line (CSL) is reduced to the first source bias voltage (V CB1 ). The bias voltage V _CB1 may be reduced to the second source bias voltage V _CB2 .

In the semiconductor device according to an embodiment of the present invention, among a plurality of word lines, memory cells disposed relatively far from the substrate are first selected and programmed, and memory cells disposed relatively close to the substrate are later selected and programmed. there is. In terms of word lines, the peripheral circuit area of the semiconductor device first selects a word line disposed at a high position in a first direction perpendicular to the substrate as a program word line, and a word line disposed at a low position in the first direction is relatively can be selected as a late program word line. For example, when a total of N word lines are stacked on a substrate, a first word line from an N th word line may be sequentially selected as a program word line.

Since the word line close to the substrate is selected later, at the time of selecting the word line close to the substrate as the program word line and executing the program operation, the voltage of the channel layer is relatively higher due to the program operation on the memory cells selected first. You can have a high level. Therefore, in a program operation in which a word line close to the substrate is selected as a program word line, leakage current from the channel layer to the common source line may relatively increase.

In an embodiment of the present invention, the above problem can be solved by differently setting the magnitude of the bias voltage input to at least one of the ground select line and the common source line according to the position of the program word line. In one example, as the program word line is closer to the substrate, that is, as the number of other memory cells connected between the select memory cell connected to the program word line and the string select transistor increases, the row decoder may select at least one of the ground select line and the common source line. The magnitude of the bias voltage input to can be reduced. Alternatively, the row decoder may reduce the magnitude of the bias voltage input to at least one of the ground selection line and the common source line as the order in which the program word lines are selected is later than the location of the program word lines. Hereinafter, it will be described in more detail with reference to FIGS. 18 and 19 .

Referring to FIGS. 18 and 19 , during a program operation, the peripheral circuit area may input a program voltage to the program word line PGM WL two or more times. For example, the row decoder of the peripheral circuit area inputs a first program voltage (V _PGM1 ) to the program word line (PGM WL) during a first program time, and programs a second program voltage (V _PGM2 ) during a second program time. It can be input to the word line (PGM WL). In the embodiments described with reference to FIGS. 18 and 19 , it is assumed that the first program voltage V _PGM1 is smaller than the second program voltage V _PGM2 . However, the first program voltage V _PGM1 may be greater than the second program voltage V _PGM2 .

Bias voltages input to each of the string select lines SEL SSL and UNSEL SSL, the ground select line GSL, and the common source line CSL may be similar to those described above. For example, the first ground selection bias voltage V GB1 is input to the ground selection line GSL during the first program time, and the first ground selection bias voltage V _GB1 is applied to the ground selection line _GSL during the second program time. ) _may be input. In addition, a first source bias voltage V CB1 is input to the common source line _CSL during the first program time, and a voltage higher than the first source bias voltage V _CB1 is applied to the common source line CSL during the second program time. A second source bias voltage (V _CB2 ) may be input. This sufficiently boosts the voltage of the channel layer during the second program time when the second program voltage (V _PGM2 ) greater than the first program voltage (V _PGM1 ) is input, so that charges are unintentionally moved in unselected memory cells and data It may be to prevent a phenomenon in which is changed.

In the embodiments shown in FIGS. 18 and 19 , the first ground selection bias voltage V GB1 and the second ground selection bias voltage V _GB2 , the first ground selection bias voltage V _GB2 according to the position of the program word line PGM WL, Levels of the source bias voltage V _CB1 and the second source bias voltage V _CB2 may be determined differently.

Referring first to FIG. 18 , when a first word line among a plurality of word lines is selected as a program word line, the magnitude of the first ground selection bias voltage V _GB1 is the first level V1 and the second ground The size of the selection bias voltage V _GB2 may be determined as the second level V2. As described above, the second level V2 may be greater than the first level V1.

Meanwhile, when a second word line closer to the substrate than the first word line is selected as the program word line among the plurality of word lines, the level of the first ground selection bias voltage (V _GB1 ) is at the third level (V3), The level of the 2 ground selection bias voltage V _GB2 may be determined as the fourth level V4. The fourth level V4 may be greater than the third level V3. Also, the third level V3 may be smaller than the first level V1, and the fourth level V4 may be smaller than the second level V2.

In addition, the voltage of the common source line CSL as well as the voltage of the ground select line GSL may vary depending on the position of the program word line. When a first word line among a plurality of word lines is selected as a program word line, the first source bias voltage (V _CB1 ) has a fifth level (V5), and the second source bias voltage (V _CB2 ) has a level may be determined as the sixth level (V6). The sixth level V6 may be greater than the fifth level V5.

Next, when the second word line closer to the substrate than the first word line is selected as the program word line, the magnitude of the first source bias voltage V _CB1 is at the seventh level V7 and the second source bias voltage V The size of _CB2 ) may be determined as the eighth level (V8). The eighth level V8 may be greater than the seventh level V7. Also, the seventh level V7 may be smaller than the fifth level V5, and the eighth level V8 may be smaller than the sixth level V6.

The second word line is disposed closer to the substrate than the first word line, and for example, the second word line may be disposed between the first word line and the substrate in a direction perpendicular to a top surface of the substrate. Also, the second word line may be selected as a program word line later than the first word line. Prior to selecting the second word line as the program word line, since at least one other word line including the first word line is preselected as the program word line, in the program operation in which the second word line is selected as the program word line, The voltage of the channel layer may be boosted to a relatively higher level than the executed program operation. As the voltage of the channel layer is boosted to a higher level, leakage current from the channel layer to the common source line CSL may relatively increase when the second word line is selected as the program word line.

Therefore, as shown in FIG. 18, as the program word line is closer to the substrate, the first ground selection bias voltage V _GB1 and the second ground selection bias voltage V _GB2 input to the ground selection line GSL, and the common The influence of the leakage current may be reduced by reducing the magnitudes of the first source bias voltage V _CB1 and the second source bias voltage V _CB2 input to the source line CSL. Depending on embodiments, only the bias voltage input to the ground selection line GSL or the bias voltage input to the common source line CSL may be set differently according to the position of the program word line.

19, in a program operation after the first program operation, for example, in the second program operation, a ground voltage is input to the common source line CSL and a negative voltage is applied to the ground select line GSL. can be entered. Accordingly, in the embodiment shown in FIG. 19, the channel initialization operation may not be executed in the second program operation.

Referring to FIG. 19 , when a first word line among a plurality of word lines is selected as a program word line, the magnitude of the first ground selection bias voltage V _GB1 is the first level V1 and the second ground selection The magnitude of the bias voltage V _GB2 may be determined as the second level V2. Since the channel initialization operation is not performed in the second program operation, the second level V2 may be a negative voltage level less than zero.

If the second word line, which is closer to the substrate than the first word line, among the plurality of word lines is selected as the program word line later than the first word line, the magnitude of the first ground selection bias voltage (V _GB1 ) increases to the third level (V3). ), the magnitude of the second ground selection bias voltage V _GB2 may be determined as the fourth level V4. The third level V3 may be smaller than the first level V1, and the fourth level V4 may be smaller than the second level V2. As shown in FIG. 19 , the fourth level V4 may be a negative voltage, and an absolute value of the fourth level V4 may be greater than an absolute value of the second level V2 .

The voltage of the common source line CSL may also vary according to the position of the program word line. When the first word line is selected as the program word line, the magnitude of the first source bias voltage V _CB1 may be determined as the fifth level V5 and the magnitude of the second source bias voltage V _CB2 may be determined as the ground voltage. there is. Next, when the second word line closer to the substrate than the first word line is selected as the program word line, the magnitude of the first source bias voltage V _CB1 is reduced to a seventh level V7 smaller than the fifth level V5. , the magnitude of the second source bias voltage (V _CB2 ) may be determined as a ground voltage.

A voltage of the channel layer when the second word line is selected as the program word line may be greater than a voltage of the channel layer when the first word line is selected as the program word line, and a voltage from the channel layer toward the common source line (CSL) Leakage current may increase. In the embodiment shown in FIG. 19 , when the second word line is selected, a negative voltage having a larger absolute value is input to the ground selection line GSL as the second ground selection bias voltage V _GB2 , thereby channel In the second program operation in which initialization is not performed, the influence of leakage current may be reduced.

In an embodiment in which the levels of voltages input to the ground selection line (GSL) and the common source line (CSL) are differently determined according to the position of a program word line among a plurality of word lines, the voltage of the common source line (CSL) is discharged. It can also be applied to embodiments that do not. For example, in the embodiments described with reference to FIGS. 16 and 17 , when the first word line is selected as the program word line, the magnitudes of the voltages input to the ground selection line GSL and the common source line CSL are When the second word line closer to the substrate than the word line is selected as the program word line, voltages input to the ground selection line GSL and the common source line CSL may be greater than voltages.

20 and 21 are diagrams schematically illustrating a semiconductor device according to an exemplary embodiment of the present invention.

Referring to FIG. 20 , the semiconductor device 400 may include a first region 410 and a second region 420 stacked in a first direction (Z-axis direction). The first region 410 may be a cell region, and the second region 420 may be a peripheral circuit region. The first area 410 may include memory cell arrays MCA and first and second through wire areas TB1 and TB2 formed on the first substrate. Through wires connecting the first region 410 and the second region 420 and extending in the first direction (Z-axis direction) may be disposed in each of the first and second through wire regions TB1 and TB2. there is.

Each of the memory cell arrays MCA may include a plurality of blocks BLK. The plurality of blocks BLK may extend in a second direction (X-axis direction) and may be arranged in a third direction (Y-axis direction). The plurality of blocks BLK may be divided by a plurality of first separation regions extending in the second direction, and a plurality of second separation regions may be disposed inside each of the plurality of blocks BLK. .

According to example embodiments, the plurality of blocks BLK may include at least one dummy block and at least one spare block. Memory cells that store data in the semiconductor device 400 may not be disposed in the dummy block. The spare block includes a memory cell like the other blocks BLK, and may store data when characteristics of the other blocks BLK deteriorate or a deterioration compensation operation for the blocks BLK is executed.

The second region 420 may include a row decoder (DEC), a page buffer (PB), and a peripheral circuit (PC) formed on the second substrate. For example, the peripheral circuit PC may include a voltage generator, a source driver, an input/output circuit, and the like. The row decoder DEC and the page buffer PB may be connected to the first region 410 through the first and second through wire regions TB1 and TB2 .

The row decoder DEC may be connected to the memory cell array MCA through word lines, string select lines, ground select lines, and a common source line. The page buffer PB may be connected to the memory cell array MCA through bit lines. As described above, in the program operation, the row decoder DEC may select a program word line from among word lines and input a program voltage thereto. Also, the row decoder DEC may differently determine the magnitude of the voltage input to the ground selection lines and the common source line according to the magnitude of the program voltage.

In addition, the row decoder DEC may determine the magnitude of the voltage input to the ground selection lines and the common source line differently according to the position of the word line selected as the program word line or the order in which the corresponding word line is selected as the program word line. . For example, when the row decoder (DEC) inputs a program voltage to a word line selected later as a program word line within a block, it may input a relatively small voltage to the ground select lines and the common source line. can

FIG. 21 may be a cross-sectional view illustrating a partial region of the semiconductor device 500 having the same structure as the exemplary embodiment illustrated in FIG. 20 . Referring to FIG. 21 , in the cell region CELL, a plurality of gate electrode layers 510 and a plurality of insulating layers 520 are alternately stacked in a first direction (Z-axis direction) and extend in the first direction. A plurality of channel structures CH passing through the plurality of gate electrode layers 510 may be disposed. A first interlayer insulating layer 550 may be disposed on the plurality of gate electrode layers 510 and the plurality of channel structures CH.

The plurality of channel structures CH may extend to a depth where a portion of the first substrate 501 of the cell region CELL is recessed. The plurality of gate electrode layers 510 are formed of a conductive material such as metal or metal silicide, and each of the plurality of channel structures CH includes a gate dielectric layer 531, a channel layer 532, a buried insulating layer 533, and the like. A drain region 534 and the like may be included. The drain region 534 of each of the plurality of channel structures CH may be connected to the bit lines BL through the channel contact 535 inside the first interlayer insulating layer 550 .

The cell area CELL includes a plurality of blocks BLK, and the plurality of blocks BLK are divided by a plurality of first separation regions DA1 extending in the second direction (X-axis direction), They may be arranged in a third direction (Y-axis direction). Each of the plurality of first separation regions DA1 may extend along the second direction to cross the cell region CELL and may be formed of an insulating material. For example, each of the plurality of first separation regions DA1 may be formed of silicon oxide, silicon nitride, or the like.

A plurality of second separation regions DA2 and an upper separation layer SC may be disposed inside each of the plurality of blocks BLK. The plurality of second separation regions DA2 and the upper separation layer SC may extend in the second direction like the plurality of first separation regions DA1. Unlike the plurality of first isolation regions DA1 and the plurality of second isolation regions DA2, the upper separation layer SC includes some gate electrode layers disposed on the upper portion in the first direction to provide string select lines. Only 510 can be divided into a plurality of regions. Accordingly, in the embodiment shown in FIG. 21 , the number of string selection lines included in one block may be greater than the number of ground selection lines.

A plurality of elements 570 , a plurality of element contacts 561 connected to the plurality of elements 570 , and a plurality of wiring patterns 563 may be formed in the peripheral circuit area PERI. The plurality of devices 570 are formed on the second substrate 560, and the plurality of devices 570, the plurality of device contacts 561, and the plurality of wiring patterns 563 are formed on the second interlayer insulating layer ( 565) can be covered. The first substrate 501 of the cell region CELL may be disposed on the upper surface of the second interlayer insulating layer 565 . Each of the plurality of devices 570 includes a source/drain region 571 and a gate structure 575, and the gate structure 575 includes a gate spacer 572, a gate insulating layer 573, and a gate conductive layer 574. ) and the like.

22 and 23 are diagrams schematically illustrating a semiconductor device according to an exemplary embodiment of the present invention.

Referring to FIG. 22 , the semiconductor device 600 may include a first region 610 and a second region 620 stacked in a first direction (Z-axis direction). The first region 610 may be a cell region, and the second region 620 may be a peripheral circuit region. A configuration of each of the first region 610 and the second region 620 may be similar to that described above with reference to FIG. 20 .

However, unlike the embodiment described above with reference to FIG. 20 , in the embodiment shown in FIG. 22 , the second region 620 including the peripheral circuit region may be combined with the first region 610 in an inverted state. there is. Accordingly, the elements included in the first region 610 and providing the row decoder DEC, the page buffer PB, and the peripheral circuit PC, and the gate electrode layers and the channel included in the second region 620 Structures, bit lines, and the like may be disposed between a first substrate in the first region 610 and a second substrate in the second region 620 in a first direction.

The row decoder (DEC) is connected to the memory cell array (MCA) through word lines, string select lines, ground select lines, and a common source line, and the page buffer (PB) is connected to the memory cell array (MCA) through bit lines. MCA) can be connected. In the program operation, the row decoder DEC may select a program word line from among word lines and input a program voltage thereto. In addition, the row decoder DEC determines the voltage input to the ground selection lines and the common source line according to the size of the program voltage, the position of the word line selected as the program word line, and the order in which the corresponding word line is selected as the program word line. Size can be determined differently.

For example, the row decoder DEC may increase a voltage input to the ground selection lines and the common source line as the program voltage increases. Alternatively, as the word line is selected later as the program word line, the magnitude of the voltage input to the ground selection lines and the common source line may be reduced. In one embodiment, when the upper word line is first selected as the program word line and the lower word line is later selected as the program word line, when the lower word line is selected as the program word line, the ground select lines and the common source line are input. The influence of the leakage current flowing from the channel layer to the common source line may be reduced by reducing the magnitude of the voltage.

Next, referring to FIG. 23 , the semiconductor device 700 may include a cell region CELL and a peripheral circuit region PERI stacked in a first direction (Z-axis direction). As described above with reference to FIG. 22 , the peripheral circuit area PERI may be stacked with the cell area CELL in an inverted state. Therefore, between the first substrate 701 of the cell area CELL and the second substrate 760 of the peripheral circuit area PERI, the elements 770 of the peripheral circuit area PERI and the Gate electrode layers 710 and channel structures CH may be disposed.

For example, the semiconductor device 700 may have a chip to chip (C2C) structure. In the C2C structure, after fabricating a first chip including a cell region (CELL) on a first wafer and fabricating a second chip including a peripheral circuit region (PERI) on a second wafer different from the first wafer, It may refer to a structure in which the first chip and the second chip are connected to each other by a bonding method. For example, the bonding method may refer to a method of physically and electrically connecting a bonding pad formed on the uppermost wiring pattern layer of the first chip and a bonding pad formed on the uppermost wiring pattern layer of the second chip. For example, when the bonding pad is formed of copper (Cu), the bonding method may be a Cu-Cu bonding method, and the bonding pad may also be formed of aluminum or tungsten.

The cell region CELL includes a plurality of gate electrode layers 710 , a plurality of insulating layers 720 , and a plurality of gate electrode layers 710 that are alternately stacked in a first direction perpendicular to the upper surface of the first substrate 701 . ) and a plurality of channel structures CH passing through the plurality of insulating layers 720 . Each of the plurality of channel structures CH includes a gate dielectric layer 731, a channel layer 732, a buried insulating layer 733, a drain region 734, and the like, and the drain region 734 is a channel contact 735 It may be connected to the bit lines BL through. The bit lines BL may be electrically connected to at least one of the elements 770 of the peripheral circuit area PERI through a first bonding pad 757 formed on the first interlayer insulating layer 750. The device 770 connected to the raw bit lines BL may be one of devices providing a page buffer.

The peripheral circuit area PERI may include a plurality of devices 770 formed on the second substrate 760 and a plurality of wiring patterns 763 connected to the plurality of devices 770 . The plurality of wiring patterns 763 may be connected to the plurality of elements 770 through the element contact 761, and the plurality of elements 770 and the plurality of wiring patterns 763 may be connected to the second interlayer insulating layer. (765) can be placed inside. The plurality of wiring patterns 763 may be physically and electrically connected to the first bonding pad 757 of the cell region CELL through the second bonding pad 767 formed on the second interlayer insulating layer 765. there is.

In order to efficiently connect the peripheral circuit area PERI and the cell area CELL, arrangements of circuits included in the peripheral circuit area PERI may be determined according to the structure of the cell area CELL. For example, among the plurality of elements 770 , elements providing a page buffer may be disposed in the peripheral circuit area PERI so as to be positioned above the plurality of channel structures CH. In addition, among the plurality of devices 770 of the peripheral circuit area PERI, devices providing a row decoder may be located on cell contacts connected to the plurality of gate electrode layers 710 . can be placed within.

The present invention is not limited by the above-described embodiments and accompanying drawings, but is intended to be limited by the appended claims. Therefore, various forms of substitution, modification, and change will be possible by those skilled in the art within the scope of the technical spirit of the present invention described in the claims, which also falls within the scope of the present invention. something to do.

30, 40, 50, 100, 200, 300, 400, 500, 600, 700: semiconductor device
SSL: string select line
WL: word line
PGM WL: Program word line
GSL: Ground select line
CSL: Common Source Line

Claims (20)

A plurality of word lines stacked on a substrate, at least one ground selection line disposed between the plurality of word lines and the substrate, and extending in a first direction perpendicular to the substrate to the plurality of word lines and a cell region including a plurality of channel structures penetrating the at least one ground selection line; and
a peripheral circuit area including peripheral circuits for controlling the cell area and inputting program voltages to at least some of the plurality of word lines in order of approaching the substrate in the first direction; Including,
The peripheral circuit region inputs a first ground selection bias voltage to the at least one ground selection line during a first program time during which a first program voltage is input to a program word line selected from among the plurality of word lines;
A second ground select bias voltage having a different level from the first ground select bias voltage on the at least one ground select line during a second program time during which a second program voltage having a different level than the first program voltage is input to the program word line. , the semiconductor device.
According to claim 1,
The semiconductor device of claim 1 , wherein the magnitude of the first program voltage is smaller than that of the second program voltage, and the magnitude of the first ground selection bias voltage is smaller than that of the second ground selection bias voltage.
According to claim 1,
The semiconductor device of claim 1 , wherein the magnitude of the first program voltage is greater than that of the second program voltage, and the magnitude of the first ground selection bias voltage is greater than that of the second ground selection bias voltage.
According to claim 1,
When a first word line among the plurality of word lines is selected as the program word line, the peripheral circuit area determines the magnitude of the first ground selection bias voltage as a first level during the first program time; The semiconductor device of claim 1 , wherein a magnitude of the second ground selection bias voltage is determined to be a second level during a second program time.
According to claim 4,
In the peripheral circuit area, when a second word line closer to the substrate than the first word line in the first direction is selected as the program word line among the plurality of word lines, the first word line during the first program time. determining the level of the ground selection bias voltage as a third level less than the first level, and determining the level of the second ground selection bias voltage as a fourth level less than the second level during the second program time. Device.
According to claim 1,
The cell region further includes a source region formed on the substrate and electrically connected to the plurality of channel structures,
The peripheral circuit region inputs a first source bias voltage to the source region during the first program time, and applies a second source bias voltage having a different magnitude from the first source bias voltage to the source region during the second program time. Input, semiconductor device.
According to claim 6,
When the magnitude of the first program voltage is smaller than the magnitude of the second program voltage, the magnitude of the first source bias voltage is smaller than the magnitude of the second source bias voltage;
and when the first program voltage is greater than the second program voltage, the first source bias voltage is greater than the second source bias voltage.
According to claim 6,
The second source bias voltage is a ground voltage.
According to claim 8,
The semiconductor device of claim 1 , wherein the second ground selection bias voltage is a negative voltage.
According to claim 6,
During the first program time, a time for which the first ground select bias voltage is input to the at least one ground select line is shorter than a time for which the first source bias voltage is input to the source region;
A time period during which the second ground selection bias voltage is input to the at least one ground selection line is shorter than a time period during which the second source bias voltage is input to the source region during the second program time.
According to claim 6,
Each of the first program time and the second program time includes a channel initialization time, a program execution time, and a program recovery time,
The semiconductor device of claim 1 , wherein the first ground selection bias voltage and the second ground selection bias voltage are discharged during the program execution time.
According to claim 11,
The semiconductor device of claim 1 , wherein the first source bias voltage and the second source bias voltage are discharged during the program recovery time.
According to claim 6,
When a first word line among the plurality of word lines is selected as the program word line, the peripheral circuit area determines the magnitude of the first source bias voltage as a fifth level during the first program time, and The semiconductor device of claim 1 , wherein the magnitude of the first ground selection bias voltage is determined to be a sixth level different from the fifth level during two program times.
According to claim 13,
In the peripheral circuit area, when a second word line closer to the substrate than the first word line in the first direction is selected as the program word line among the plurality of word lines, the first word line during the first program time. determining a level of the source bias voltage as a seventh level less than the fifth level, and determining a level of the second ground selection bias voltage as an eighth level less than the sixth level during the second program time. .
A plurality of word lines stacked on a substrate, at least one ground selection line disposed between the plurality of word lines and the substrate, extending in a first direction perpendicular to the substrate and extending between the plurality of word lines and the substrate. a cell region including a plurality of channel structures penetrating at least one ground selection line, and a source region formed on the substrate and electrically connected to the plurality of channel structures; and
a peripheral circuit area including peripheral circuits controlling the cell area; Including,
The peripheral circuit area may include a voltage of a first level and a voltage of the first level on the at least one ground select line during a first program operation on a first program word line located at a first height in the first direction. Sequentially inputting voltages of different second levels,
In a second program operation on a second program word line positioned at a second height lower than the first height, a voltage of a third level lower than the first level and a voltage higher than the second level are applied to the at least one ground select line. A semiconductor device in which voltages of a small fourth level are sequentially input.
According to claim 15,
wherein each of the second level and the fourth level is a negative level, and an absolute value of the second level is smaller than an absolute value of the fourth level.
According to claim 16,
The peripheral circuit area inputs a ground voltage to the source area while the second level voltage is input to the ground select line in the first program operation, and the fourth level voltage in the second program operation. A ground voltage is input to the source region while a voltage is input to the ground selection line.
According to claim 15,
In the peripheral circuit area, after the voltage input to the at least one ground selection line is discharged in each of the first program operation and the second program operation, the first program word line and the second program word line respectively A semiconductor device to which a program voltage is input.
According to claim 18,
The semiconductor device of claim 1 , wherein, in the peripheral circuit region, a voltage higher than a ground voltage is input to the source region while a program voltage is input to each of the first program word line and the second program word line.
ground select transistors connected to the common source line and the ground select line;
string select transistors coupled to the bit lines and to at least one string select line;
memory cells connected in series between the ground select transistors and the string select transistors and connected to word lines; and
a row decoder controlling the ground select transistors, the string select transistors, and the memory cells; Including,
The row decoder inputs a first program voltage during a first program time to a program word line connected to a selected memory cell among the memory cells, and inputs a second program voltage during a second program time after the first program time;
The row decoder determines an absolute value of a voltage input to the ground selection line and the common source line at each of the first program time and the second program time, respectively, as a value of each of the first program voltage and the second program voltage. A semiconductor device determined based on size.

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