KR20230076083A - Image sensor and method of fabricating the same - Google Patents

Abstract

A substrate including a pixel area and an optical black area and having first and second surfaces opposite to each other, color filters disposed on the second surface of the substrate in the pixel area, and An image sensor including a first optical black pattern disposed in a first recess provided on the second surface of the substrate, wherein the first optical black pattern includes the same material as any one of the color filters; , upper surfaces of the color filters and upper surfaces of the first optical black pattern may be provided at the same level.

Description

Image sensor and its manufacturing method

The present invention relates to an image sensor and a manufacturing method thereof.

An image sensor is a semiconductor device that converts an optical image into an electrical signal. The image sensor may be classified into a charge coupled device (CCD) type and a complementary metal oxide semiconductor (CMOS) type. The CMOS image sensor is abbreviated as CIS (CMOS image sensor). The CIS includes a plurality of pixels two-dimensionally arranged. Each of the pixels includes a photodiode (PD). The photodiode serves to convert incident light into an electrical signal.

An object to be solved by the present invention is to provide an image sensor with improved structural stability and a manufacturing method thereof.

Another problem to be solved by the present invention is to provide a method for manufacturing an image sensor with less defects and an image sensor manufactured through the method.

The problem to be solved by the present invention is not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the description below.

An image sensor according to embodiments of the present invention for solving the above technical problems includes a substrate including a pixel area and an optical black area and having a first surface and a second surface facing each other, and a substrate in the pixel area. It may include color filters disposed on the second surface, and a first optical black pattern disposed in a first recess provided in the second surface of the substrate in the optical black region. The first optical black pattern may include the same material as any one of the color filters. Upper surfaces of the color filters and upper surfaces of the first optical black pattern may be provided at the same level.

An image sensor according to embodiments of the present invention for solving the above technical problems includes a substrate including a pixel area, an optical black area, and a pad area, and a first recess provided on an upper surface of the substrate in the optical black area. , a second recess provided on the upper surface of the substrate in the pad area, a plurality of color filters disposed on the substrate in the pixel area, and a bottom surface and an inner surface of the first recess in the optical black area. a first optical black pattern conformally covering the first optical black pattern, a second optical black pattern filling a remainder of the first recess in the optical black region, and a conductive pad disposed on the substrate in the pad region. can The first optical black pattern may include the same material as any one of the color filters. The second optical black pattern may include a material different from that of the first optical black pattern and the color filters.

An image sensor according to embodiments of the present invention for solving the above technical problems is a substrate including a pixel area and an optical black area, color filters disposed on an upper surface of the substrate in the pixel area, and the optical black area. a first optical black pattern disposed in a recess provided on the upper surface of the substrate in an area, provided on the pixel area and the optical black area, the color filters and the first optical black pattern on the upper surface of the substrate; A passivation layer covering the black pattern, and a color separation lens array layer provided on the passivation layer may be included. The color separation lens array layer may have regions corresponding to the color filters and provided with nano posts, and the nano posts may be arranged to branch light of different wavelengths included in incident light toward the color filters. . The first optical black pattern may include the same material as any one of the color filters. Upper surfaces of the color filters and upper surfaces of the first optical black pattern may be provided on one plane.

A method of manufacturing an image sensor according to embodiments of the present invention for solving the above technical problems includes providing a substrate including a pixel area, an optical black area, and a pad area, and performing an etching process on the upper surface of the substrate. to form a first recess on the optical black region and a second recess on the pad region, and the top surface of the substrate, the first recess and the second recess in the optical black region and the pad region. forming a first optical black pattern conformally covering the recess, forming a conductive pad filling the rest of the second recess on the pad area, and forming color filters on the pixel area. and forming a second optical black pattern filling a remainder of the first recess on the optical black region. The second optical black pattern may be formed together in a process of forming one of the color filters. Upper surfaces of the second optical black pattern may be provided at the same level as upper surfaces of the color filters.

In the image sensor according to example embodiments, the top surfaces of the color filters in the pixel area and the top surface of the second optical black pattern in the optical black area may be provided on the same plane. Accordingly, there may be no step difference between the color filters and the second optical black pattern near the boundary between the pixel area and the optical black area, and an upper end of the image sensor may be substantially flat on the pixel area and the optical black area. Accordingly, structural stability of the image sensor may be improved.

Since there is no step between the color filters and the second optical black pattern in the vicinity of the boundary between the pixel region and the optical black region, the shapes of the color filters and the second optical black pattern can be accurately formed. In a process after forming the color filters and the second optical black pattern, a defect that may occur due to a step difference between the first color filters and the second optical black pattern may be prevented.

1 is a block diagram illustrating an image sensor according to example embodiments.
2 is a circuit diagram of an active pixel sensor array of an image sensor according to embodiments of the present invention.
3 to 8 are cross-sectional views illustrating image sensors according to example embodiments.
9 to 17 are cross-sectional views illustrating a method of manufacturing an image sensor according to example embodiments.

An image sensor according to the concept of the present invention will be described with reference to the drawings.

1 is a block diagram illustrating an image sensor according to example embodiments.

Referring to FIG. 1 , an image sensor includes an active pixel sensor array (1001), a row decoder (1002), a row driver (1003), a column decoder (1004), and timing. It may include a timing generator (1005), a Correlated Double Sampler (CDS) 1006, an Analog to Digital Converter (ADC) 1007, and an I/O buffer (1008). .

The active pixel sensor array 1001 includes a plurality of two-dimensionally arranged unit pixels, and can convert an optical signal into an electrical signal. The active pixel sensor array 1001 may be driven by a plurality of driving signals such as a pixel selection signal, a reset signal, and a charge transfer signal from the row driver 1003 . Also, the converted electrical signal may be provided to the correlated double sampler 1006.

The row driver 1003 may provide a plurality of driving signals for driving a plurality of unit pixels to the active pixel sensor array 1001 according to a result decoded by the row decoder 1002 . When unit pixels are arranged in a matrix form, driving signals may be provided for each row.

Timing generator 1005 can provide timing and control signals to row decoder 1002 and column decoder 1004 .

A correlated double sampler (CDS) 1006 may receive, hold, and sample an electrical signal generated by the active pixel sensor array 1001 . The correlated double sampler 1006 may double sample a specific noise level and a signal level caused by an electrical signal, and output a difference level corresponding to a difference between the noise level and the signal level.

The analog-to-digital converter (ADC) 1007 may convert an analog signal corresponding to a difference level output from the correlated double sampler 1006 into a digital signal and output the converted digital signal.

The input/output buffer 1008 may latch digital signals, and the latched signals may sequentially output digital signals to an image signal processing unit (not shown) according to decoding results in the column decoder 1004 .

2 is a circuit diagram of an active pixel sensor array of an image sensor according to embodiments of the present invention.

Referring to FIGS. 1 and 2 , the sensor array 1001 includes a plurality of unit pixel areas PX, and the unit pixel areas PX may be arranged in a matrix form. Each of the unit pixel regions PX may include a transfer transistor TX and logic transistors RX, SX, and DX. Logic transistors may include a reset transistor RX, a select transistor SX, and a source follower transistor DX. The transfer transistor TX may include a transfer gate electrode TG. Each of the unit pixel regions PX may further include a photoelectric conversion element PD and a floating diffusion region FD.

The photoelectric conversion device PD may generate and accumulate photocharges in proportion to the amount of light incident from the outside. The photoelectric conversion device PD may include a photodiode, a phototransistor, a photogate, a pinned photodiode, and a combination thereof. The transfer transistor TX may transfer charges generated by the photoelectric conversion element PD to the floating diffusion region FD. The floating diffusion region FD may receive and accumulate charges generated by the photoelectric conversion element PD. The source follower transistor DX may be controlled according to the amount of photocharges accumulated in the floating diffusion region FD.

The reset transistor RX may periodically reset charges accumulated in the floating diffusion region FD. A drain electrode of the reset transistor RX may be connected to the floating diffusion region FD, and a source electrode of the reset transistor RX may be connected to the power supply voltage VDD. When the reset transistor RX is turned on, the power supply voltage VDD connected to the source electrode of the reset transistor RX may be applied to the floating diffusion region FD. Accordingly, when the reset transistor RX is turned on, the charges accumulated in the floating diffusion region FD are discharged to reset the floating diffusion region FD.

The source follower transistor DX may serve as a source follower buffer amplifier. The source follower transistor DX may amplify a potential change in the floating diffusion region FD and output it to the output line Vout.

The selection transistor SX may select unit pixel regions PX to be read in units of rows. When the selection transistor SX is turned on, the power supply voltage VDD may be applied to the drain electrode of the source follower transistor DX.

3 to 6 are cross-sectional views illustrating image sensors according to example embodiments.

Referring to FIG. 3 , a substrate 10 including a pixel area AP, an optical black area OB, and a pad area PR is provided. The substrate 10 includes a first surface 10a and a second surface 10b that are opposed to each other. The substrate 10 may include a semiconductor substrate. For example, the substrate 10 may be a silicon single crystal wafer, a silicon epitaxial layer, or a silicon on insulator (SOI) substrate. The substrate 10 may be doped with impurities of the first conductivity type. For example, the first conductivity type may be a P type.

The pixel area AP may include a plurality of unit pixels UP. For example, a pixel separator 31 may be disposed in the pixel area AP of the substrate 10 to separate a plurality of unit pixels UP. The pixel separator 31 may serve to prevent cross talk between adjacent unit pixels UP. The pixel separator 31 may pass through the substrate 10 from the first surface 10a of the substrate 10 and reach the second surface 10b of the substrate 10 . The pixel separator 31 may have a mesh structure in which lines cross each other in a plan view. A part of the pixel separator 31 may be located on the optical black area OB. Unlike shown, the width of the pixel separator 31 may be greater in the optical black area OB than in the pixel area AP.

The pixel separator 31 may include an isolation conductive pattern 33 and an isolation insulating layer 35 . The separation conductive pattern 33 may vertically penetrate the substrate 10 . The separation insulating layer 35 may be interposed between the separation conductive pattern 33 and the substrate 10 . The separation conductive pattern 33 may include, for example, doped-poly Si and/or metal. The isolation insulating layer 35 may include, for example, silicon oxide (SiO).

A photoelectric converter 13 may be disposed within the substrate 10 in each of the unit pixels UP. A photoelectric converter 13 may also be disposed within the substrate 10 in the optical black region OB. The photoelectric converter 13 may be doped with impurities of a second conductivity type opposite to the first conductivity type. The second conductivity type may be, for example, N-type. N-type impurities doped in the photoelectric conversion unit 13 form a P-N junction with P-type impurities doped in the substrate 10 to provide a photodiode.

Light may be incident into the substrate 10 through the second surface 10b of the substrate 10 . Electron-hole pairs may be formed at the P-N junction by incident light. Although not shown, transfer transistors, reset transistors, source follower transistors, and selection transistors for transmitting electrons generated by incident light are provided on the first surface 10a of the substrate 10 in the pixel area AP. can be placed. That is, the image sensor may be a rear light receiving image sensor.

A first recess RS1 and a second recess RS2 may be provided on the second surface 10b of the substrate 10 . The first recess RS1 may be positioned on the optical black area OB. The second recess RS2 may be located on the pad area PR. The first and second recesses RS1 and RS2 may be formed from the second surface 10b of the substrate 10 toward the first surface 10a of the substrate 10 . The first recess RS1 may be spaced upward from the photoelectric converter 13 of the optical black area OB. The first recess RS1 may be an area in which the optical black patterns OBP1 and OBP2 are provided on the optical black area OB. The second recess RS2 may be an area where the conductive pad 90 is provided on the pad area PR. A bottom surface of the first recess RS1 and a bottom surface of the second recess RS2 may be positioned at the same level as each other. Alternatively, as shown in FIG. 4 , the bottom surface of the first recess RS1 may be provided at a higher level than the bottom surface of the second recess RS2 . Hereinafter, the description will continue based on the embodiment of FIG. 3 .

An element isolation pattern 17 may be disposed adjacent to the first surface 10a of the substrate 10 . The device isolation pattern 17 may define active regions in each unit pixel UP of the pixel area AP. The device isolation pattern 17 may include, for example, a single layer structure or a multilayer structure of at least one of silicon oxide (SiO), silicon nitride (SiN), and silicon oxynitride (SiON). A transfer gate electrode TG may be disposed in some of the active regions. The transfer gate electrode TG may correspond to the gate of the transfer transistor TX of FIG. 2 .

A portion of the transfer gate electrode TG may be inserted into the substrate 10 . Another portion of the transfer gate electrode TG protrudes outside the first surface 10a of the substrate 10 and may cover the first surface 10a. The transfer gate electrode TG may be a 'vertical type gate'. A floating diffusion region FD may be disposed next to the transfer gate electrode TG in the active region. The floating diffusion region FD may be disposed within the substrate 10 . The floating diffusion region FD may be doped with impurities of the second conductivity type, for example.

Although not shown, circuit gate electrodes may be disposed in other portions of the active regions. For example, a circuit gate electrode (not shown) may be disposed in another part of the active regions, and the circuit gate electrode is a reset gate of the reset transistor RX of FIG. 2 and a source of the source follower transistor DX. It may correspond to one of the follower gate and the selection gate of the selection transistor SX. A plurality of unit pixels UP adjacent to each other share at least one of the reset gate of the reset transistor RX, the source follower gate of the source follower transistor DX, and the selection gate of the selection transistor SX. so that charge can be transferred.

The circuit gate electrode may not be inserted into the substrate 10 . The circuit gate electrode is positioned on the first surface 10a of the substrate 10 and may be a 'Planar type gate'. Source/drain regions may be disposed on both sides of the circuit gate electrode in another part of the active region where the circuit gate electrode is disposed. For example, impurities of the second conductivity type may be doped in the source/drain regions.

A gate insulating layer GI may be interposed between the transfer gate electrode TG and the substrate 10 and between the circuit gate electrode and the substrate 10 . The gate insulating layer GI may include, for example, silicon oxide (SiO) or silicon nitride (SiN).

A wiring layer 40 may be disposed on the first surface 10a of the substrate 10 . The wiring layer 40 may include an upper wiring layer 41 and a lower wiring layer 45 .

The upper wiring layer 41 may include a first interlayer insulating layer 42 and first wirings 43 . The first surface 10a of the substrate 10 may be covered with a first interlayer insulating layer 42 . The first interlayer insulating layer 42 may cover the transfer gate electrode TG and the circuit gate electrode on the first surface 10a of the substrate 10 . The first interlayer insulating film 42 is, for example, selected from silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), TEOS (Tetra Ethyl Ortho Silicate), and a porous insulator. It may include at least one multilayer structure. Multi-layered first wirings 43 may be disposed in the first interlayer insulating layer 42 . The first wire 43 may be positioned on the pixel area AP. The floating diffusion region FD may be connected to the first wire 43 through the contact plug 44 . The contact plug 44 may pass through the first interlayer insulating layer 42 in the pixel area AP. A part of the first wiring 43 may also be disposed on the optical black area OB. More specifically, the first wire 43 may be disposed below the photoelectric converter 13 in the pixel area AP and the optical black area OB. However, the present invention is not limited thereto, and the first wire 43 may be disposed in various positions as needed.

A lower wiring layer 45 may be disposed below the upper wiring layer 41 . The lower wiring layer 45 may include a second interlayer insulating layer 46 and second wirings 47 . A lower surface of the upper wiring layer 41 may be covered with a second interlayer insulating layer 46 . The second interlayer insulating film 46 is, for example, selected from silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), TEOS (Tetra Ethyl Ortho Silicate), and a porous insulator. It may include at least one multilayer structure. Multi-layered second wires 47 may be disposed in the second interlayer insulating layer 46 . The second wires 47 may be positioned on the pad area PR. Some of the second wires 47 may also be disposed on the optical black area OB. More specifically, the second wires 47 may be disposed on the pad area PR, and may be disposed below an area in the optical black area OB where the photoelectric converter 13 is not provided. . However, the present invention is not limited thereto, and the second wires 47 may be disposed in various positions as needed.

The lower wiring layer 45 may be covered with a first passivation layer 48 . The first protective layer 48 may include, for example, silicon oxide (SiO) or polyimide.

A first fixed charge layer 24 may be disposed on the second surface 10b of the substrate 10 . The second surface 10b may contact the first fixed charge layer 24 . The first fixed charge layer 24 may cover the second surface 10b of the substrate 10 on the pixel area AP, and may cover the second surface 10b of the substrate 10 on the optical black area OB. and may conformally cover the inner surface of the first recess RS1, cover the second surface 10b of the substrate 10 on the pad region PR, and cover the inner surface of the second recess RS2. It can be covered conformally. The first fixed charge layer 24 may be formed of a single layer or a multilayer of a metal oxide layer or a metal fluoride layer containing oxygen or fluorine in an amount less than the stoichiometric ratio. Accordingly, the fixed charge layer may have a negative fixed charge. The first fixed charge film 24 is selected from the group consisting of hafnium (Hf), zirconium (Zr), aluminum (Al), tantalum (Ta), titanium (Ti), yttrium (Y) and lanthanoid. It may be made of a single layer or multiple layers of metal oxide or metal fluoride including at least one metal. As a specific example, the first fixed charge layer 24 may include a hafnium oxide layer (HfO) and/or an aluminum oxide layer (Al2O3). Dark current and white spots can be improved by the first fixed charge layer 24 .

A second fixed charge layer 26 and a second passivation layer 28 may be sequentially stacked on the first fixed charge layer 24 . The second fixed charge layer 26 and the second passivation layer 28 are formed on the pixel area AP, the optical black area OB, and the pad area PR so that the first fixed charge layer 24 is conformal. can cover The second fixed charge layer 26 may include a single layer or multiple layers of metal oxide or metal fluoride. The second fixed charge layer 26 may include, for example, a hafnium oxide layer (HfO) and/or an aluminum oxide layer (Al2O3). The second fixed charge layer 26 may reinforce the first fixed charge layer 24 or function as an adhesive layer. The second passivation layer 28 may include at least one of PETEOS, silicon oxide (SiO), silicon nitride (SiN), silicon carbonitride (SiCN), hafnium oxide (HfO), and aluminum oxide (Al2O3). The second passivation layer 28 may function as an antireflection layer and/or a planarization layer.

A light blocking grid pattern 56 may be disposed on the second passivation layer 28 in the pixel area AP. The light-blocking grid pattern 56 may overlap the pixel separator 31 and may have a net shape in plan view. The light blocking grid pattern 56 may include, for example, a metal such as titanium (Ti) or tungsten (W). Although not shown, a low refractive index pattern may be disposed on the light blocking grid pattern 56 . The low refractive index pattern may have the same planar shape as the light blocking grid pattern 56 . For example, sidewalls of the low refractive index pattern may be aligned with sidewalls of the light blocking grid pattern 56 . The low refractive index pattern may include an organic material. The low refractive index pattern may have a lower refractive index than color filters CF1 and CF2 described later. For example, the low refractive pattern may have a refractive index of about 1.3 or less. The light blocking grid pattern 56 and the low refractive index pattern may prevent crosstalk between adjacent unit pixels UP. Although FIG. 3 shows that the light blocking grid pattern 56 is provided only on the pixel area AP, the present invention is not limited thereto. According to other embodiments, a portion of the light blocking grid pattern 56 may be located on the optical black area OB. In this case, the light blocking grid pattern 56 may not extend into the first recess RS1. Hereinafter, the description will continue based on the embodiment of FIG. 3 .

Color filters CF1 and CF2 may be disposed between the light blocking grid pattern 56 in the pixel area AP. Each of the color filters CF1 and CF2 may have one color among blue, green, and red. The color filters CF1 and CF2 may be arranged in a Bayer pattern, a 2x2 Tetra pattern, or a 3x3 Nona pattern. Alternatively, the color filters CF1 and CF2 may include other colors such as cyan, magenta, or yellow. Upper surfaces of the color filters CF1 and CF2 may be positioned at a higher level than the upper surface of the light blocking grid pattern 56 . For example, the color filters CF1 and CF2 adjacent to each other may contact each other on the light blocking grid pattern 56 therebetween. Alternatively, as shown in FIG. 5 , the upper surfaces of the color filters CF1 and CF2 may be positioned at the same level as the upper surface of the light blocking grid pattern 56 . That is, the color filters CF1 and CF2 may be provided only within a region defined by the light blocking grid pattern 56 . Hereinafter, the description will continue based on the embodiment of FIG. 3 .

A micro lens array layer ML may be disposed on the color filters CF1 and CF2 in the pixel area AP. The micro lens array layer ML may include convex lens parts overlapping each of the unit pixels UP.

The first connection structure 120 , the connection contact 80 , and the optical black patterns OBP1 and OBP2 may be provided on the substrate 10 in the optical black area OB.

The first connection structure 120 connects the first optical black pattern OBP1 to be described later with the first wirings 43 of the upper wiring layer 41 and/or the second wirings 47 of the lower wiring layer 45. It may be a via plug that does. The first connection structure 120 may fill the first trench TR1 formed in the substrate 10 in the optical black region OB. The first trench TR1 may be formed inside the first recess RS1 when viewed in plan view. That is, the first trench TR1 may extend from the bottom surface of the first recess RS1 into the substrate 10 . At this time, the first trench TR1 penetrates the first fixed charge layer 24, the second fixed charge layer 26, and the second passivation layer 28 inside the first recess RS1 to pass through the inside of the substrate 10. can be extended to The first trench TR1 may pass through the substrate 10 and the upper wiring layer 41 to expose top and/or side surfaces of some of the first wirings 43 . A portion of the first trench TR1 penetrates the substrate 10, the upper wiring layer 41, and the lower wiring layer 45 from one side of the partial first wirings 43 to the top surface of some of the second wirings 47. can expose. The first connection structure 120 may include a first conductive pattern 121 , a first insulating pattern 123 , and a first capping pattern 125 .

The first conductive pattern 121 may conformally cover the inner wall of the first trench TR1 . The first conductive pattern 121 may pass through the substrate 10 and the upper wiring layer 41 to connect the substrate 10 and the wiring layer 40 . The first conductive pattern 121 may contact wires in the upper wiring layer 41 and the lower wiring layer 45 . For example, the first conductive pattern 121 may contact some of the first wires 43 and some of the second wires 47 exposed by the first trench TR1 . Accordingly, the first conductive pattern 121 may be electrically connected to the wirings 43 and 47 in the wiring layer 40 . The first conductive pattern 121 may include, for example, a metal material such as tungsten (W).

The first insulating pattern 123 may fill the remaining portion of the first trench TR1. The first insulating pattern 123 may entirely or partially penetrate the substrate 10 and the wiring layer 40 . A first capping pattern 125 may be provided on an upper surface of the first insulating pattern 123 . A first capping pattern 125 may be provided on the first insulating pattern 123 .

The connection contact 80 may fill the second trench TR2 formed in the substrate 10 in the optical black region OB. The second trench TR2 may be formed inside the first recess RS1 when viewed in plan view. That is, the second trench TR2 may extend from the bottom surface of the first recess RS1 into the substrate 10 . The second trench TR2 may be horizontally spaced apart from the first trench TR1. The second trench TR2 may be formed on the pixel separator 31 of the optical black region OB. In this case, the second trench TR2 may pass through the first fixed charge layer 24 , the second fixed charge layer 26 , and the second passivation layer 28 inside the first recess RS1 . The second trench TR2 may pass through the substrate 10 to expose the isolation conductive pattern 33 of the pixel isolation unit 31 .

The connection contact 80 penetrates the first fixed charge layer 24, the second fixed charge layer 26, the second passivation layer 28, and a portion of the substrate 10 to form a separation conductive pattern of the pixel separator 31. (33) can be encountered. The connection contact 80 includes a first contact pattern 82 that conformally covers the inner sidewall and bottom surface of the second trench TR2 and fills the second trench TR2 on the first contact pattern 82 . A second contact pattern 84 may be included. The first contact pattern 82 may include, for example, tungsten (W). The second contact pattern 84 may include, for example, aluminum (Al).

A first optical black pattern OBP1 may be provided on the second passivation layer 28 in the optical black area OB. More specifically, the first optical black pattern OBP1 may conformally cover the second passivation layer 28 within the first recess RS1. For example, the first optical black pattern OBP1 may extend along the bottom surface and inner wall of the first recess RS1 on the second passivation layer 28 . As the first connection structure 120 and the connection contact 80 are provided to penetrate the first fixed charge layer 24, the second fixed charge layer 26, and the second passivation layer 28, the first recess ( On the bottom surface of RS1), the first conductive pattern 121 of the first connection structure 120 and the first contact pattern 82 of the connection contact 80 may be connected to the first optical black pattern OBP1. That is, the connection contact 80 may be connected to the wiring layer 40 through the first optical black pattern OBP1 and the first connection structure 120 . In this case, the first optical black pattern OBP1 , the first conductive pattern 121 , and the first contact pattern 82 may include the same material and may be integrated. The first optical black pattern OBP1 , the first conductive pattern 121 , and the first contact pattern 82 may have the same thickness as each other. In other words, the first conductive pattern 121 of the first connection structure 120 and the first contact pattern 82 of the connection contact 80 are formed on the second passivation layer 28 of the first recess RS1. It may extend along a bottom surface and the inner wall, and may be connected to each other on the bottom surface of the first recess RS1. At this time, a part of the first conductive pattern 121 and a part of the first contact pattern 82 positioned on the bottom surface and the inner wall of the first recess RS1 are formed as the first optical black pattern OBP1. can be defined Also, the first optical black pattern OBP1 may include a material different from that of the color filters CF1 and CF2 and the second optical black pattern OBP2 described later. For example, the first optical black pattern OBP1 , the first conductive pattern 121 , and the first contact pattern 82 may include tungsten (W).

In the optical black area OB, the first optical black pattern OBP1 may serve to block light. The amount of charge detected in the optical black area OB where light is blocked may be determined as the reference charge amount. That is, the unit pixel charge amount sensed from the unit pixels UP is compared with the reference charge amount, and differences between the unit pixel charge amount and the reference charge amount are calculated to calculate the electrical signal magnitude sensed from each unit pixel UP. can do.

A second optical black pattern OBP2 may be disposed on the first optical black pattern OBP1 in the optical black area OB. The second optical black pattern OBP2 may overlap the first optical black pattern OBP1. The second optical black pattern OBP2 may fill the remainder of the first recess RS1. Accordingly, the first optical black pattern OBP1 may cover the lower and side surfaces of the second optical black pattern OBP2. The upper surface of the second optical black pattern OBP2 may be located at the same level as the upper surfaces of the color filters CF1 and CF2. The upper surface of the second optical black pattern OBP2 may be substantially flat. That is, the upper surface of the second optical black pattern OBP2 and the upper surfaces of the color filters CF1 and CF2 may be positioned on the same plane. According to other embodiments, as shown in FIG. 5 , when the top surfaces of the color filters CF1 and CF2 are provided at the same level as the top surface of the light blocking grid pattern 56, the second optical black pattern OBP2 An upper surface of the light blocking grid pattern 56 may also be located at the same level as the upper surface of the light blocking grid pattern 56 .

According to positions of the top surfaces of the color filters CF1 and CF2 , the top surface of the second optical black pattern OBP2 may be positioned at the same level as or higher than the top surface of the second passivation layer 28 . When the top surface of the second optical black pattern OBP2 is located at a level higher than the top surface of the second passivation layer 28, the first optical black pattern OBP1 is formed on the side surface of the second optical black pattern OBP2. Only the lower part can be covered. Alternatively, when the upper surface of the second optical black pattern OBP2 is located at the same level as the uppermost surface of the second passivation layer 28, the first optical black pattern OBP1 is the second optical black pattern OBP2 can cover the entire side of the That is, the top of the first optical black pattern OBP1 may be located at the same level as or lower than the upper surface of the second optical black pattern OBP2.

The second optical black pattern OBP2 may include the same material as any one of the color filters CF1 and CF2. For example, the second optical black pattern OBP2 may be blue. The second optical black pattern OBP2 may be a photo resist pattern including a blue pigment. Like the first optical black pattern OBP1, the second optical black pattern OBP2 also serves to block light. The second optical black pattern OBP2 may supplement a light blocking function that may be lacking only in the first optical black pattern OBP1.

According to example embodiments, the top surfaces of the color filters CF1 and CF2 of the pixel area AP and the top surface of the second optical black pattern OBP2 of the optical black area OB are on the same plane. can be provided. Accordingly, there may be no step between the color filters CF1 and CF2 and the second optical black pattern OBP2 near the boundary between the pixel area AP and the optical black area OB, and the top of the image sensor is the pixel area. Area AP and optical black area OB may be substantially flat. Accordingly, structural stability of the image sensor may be improved. In addition, since there is no step between the color filters CF1 and CF2 and the second optical black pattern OBP2 near the boundary between the pixel area AP and the optical black area OB, the color filters CF1 and CF2 A process after forming the second optical black pattern OBP2 may be easier. This will be described in more detail along with a manufacturing method of the image sensor.

Still referring to FIG. 3 , although not shown, a passivation layer may be interposed between the first optical black pattern OBP1 and the second optical black pattern OBP2 .

A second connection structure 130 and a conductive pad 90 may be provided on the substrate 10 in the pad region PR.

The second connection structure 130 may be a via plug connecting the conductive pad 90 and the second wires 47 of the lower wiring layer 45 . The second connection structure 130 may fill the third trench TR3 formed in the substrate 10 in the pad region PR. The pad region PR may extend into the substrate 10 from the second surface 10b of the substrate 10 . In this case, the third trench TR3 may pass through the first fixed charge layer 24 , the second fixed charge layer 26 , and the second passivation layer 28 . The third trench TR3 may pass through the substrate 10 , the upper wiring layer 41 , and the lower wiring layer 45 to expose a portion of the upper surface of the second wiring 47 . The second connection structure 130 may include a second conductive pattern 131 , a second insulating pattern 133 , and a second capping pattern 135 .

The second conductive pattern 131 may conformally cover the inner wall of the third trench TR3 . The second conductive pattern 131 may pass through the substrate 10 and the upper wiring layer 41 to connect the substrate 10 and the wiring layer 40 . The second conductive pattern 131 may contact wires in the upper wiring layer 41 and the lower wiring layer 45 . For example, the second conductive pattern 131 may contact some of the second wires 47 exposed by the third trench TR3. Accordingly, the second conductive pattern 131 may be electrically connected to wires in the wiring layer 40 . The second conductive pattern 131 may include, for example, a metal material such as tungsten (W).

The second insulating pattern 133 may fill the remaining portion of the third trench TR3. The second insulating pattern 133 may entirely or partially penetrate the substrate 10 and the wiring layer 40 . A second capping pattern 135 may be provided on an upper surface of the second insulating pattern 133 . A second capping pattern 135 may be provided on the second insulating pattern 133 .

A conductive pad 90 may be provided on the second passivation layer 28 in the pad region PR. More specifically, the conductive pad 90 may fill the second recess RS2 on the second passivation layer 28 . A lower surface of the conductive pad 90 may be positioned at the same level as a lower surface of the first optical black pattern OBP1 . Here, the lower surface of the first optical black pattern OBP1 means a surface positioned on the bottom surface of the first recess RS1 among the downward facing surfaces of the first optical black pattern OBP1, and It is independent of the lower surfaces of the first conductive pattern 121 and the first contact pattern 82 connected to the first optical black pattern OBP1. According to other embodiments, as shown in FIG. 4 , when the bottom surface of the second recess RS2 is provided lower than the bottom surface of the first recess RS1, the lower surface of the conductive pad 90 may be located at a level lower than the lower surface of the first optical black pattern OBP1. However, the present invention is not limited thereto, and the depth of the second recess RS2 may be provided in various ways according to the resistance of the conductive pad 90 . Hereinafter, the description will continue based on the embodiment of FIG. 3 .

The conductive pad 90 conformally covers the inner sidewall and bottom surface of the second recess RS2 and the second recess RS2 on the first pad pattern 92. It may include a second pad pattern 94 filling the . The first pad pattern 92 may include, for example, tungsten (W). The second pad pattern 94 may include, for example, aluminum (Al).

The conductive pad 90 may be electrically connected to the second connection structure 130 . More specifically, the first pad pattern 92 of the conductive pad 90 and the second conductive pattern 131 of the second connection structure 130 may extend onto the second surface 10b of the substrate 10. and may be connected to each other on the second surface 10b. In this case, the first pad pattern 92 and the second conductive pattern 131 may include the same material and may be integrated. The first pad pattern 92 and the second conductive pattern 131 may have the same thickness as each other.

The first pad pattern 92 of the conductive pad 90 may extend to another area to form an electrical connection. For example, the first pad pattern 92 of the conductive pad 90 may extend to the optical black area OB, and the first optical black pattern OBP1 may extend to the pad area PR and be connected to each other.

According to other embodiments, as shown in FIG. 6 , the first connection structure 120 may not be provided. In this case, the conductive pad 90 may be connected to the lower wiring layer 45 through the second connection structure 130, and the first pad pattern 92 and the first pad pattern extending onto the optical black region OB It may be connected to the upper wiring layer 41 through the connection contact 80 connected to (92). Hereinafter, the description will continue based on the embodiment of FIG. 3 .

A planarization pattern 70 may be disposed between the micro lens array layer ML and the second passivation layer 28 . The color filters CF1 and CF2 may be positioned between the flattening pattern 70 and the micro lens array layer ML. The second optical black pattern OBP2 may be positioned between the planarization pattern 70 and the second passivation layer 28 . That is, the planarization pattern 70 may cover the color filters CF1 and CF2 and the second optical black pattern OBP2 on the second passivation layer 28 . The height of the top surface of the second optical black pattern OBP2 may be the same as the heights of the top surfaces of the color filters CF1 and CF2 . Accordingly, the top surface of the flattening pattern 70 may be flat in the pixel area AP and the optical black area OB. The planarization pattern 70 may have an opening exposing the conductive pad 90 on the pad region PR. The planarization pattern 70 may be formed of a transparent photoresist material identical to/similar to that of the micro lens array layer ML or a transparent thermosetting resin. In other embodiments, the planarization pattern 70 may not be provided as needed.

7 and 8 are cross-sectional views illustrating image sensors according to example embodiments. In FIGS. 7 and 8 , the configuration of the pad region PR is omitted for convenience of description. In the following embodiments, components described with reference to FIGS. 1 to 6 use the same reference numerals, and descriptions thereof are omitted or briefly described for convenience of description. That is, differences between the embodiments of FIGS. 1 to 6 and the following embodiments will be mainly described.

Referring to FIG. 7 , a first recess RS1 may be provided on the second surface 10b of the substrate 10 . The first recess RS1 may be positioned on the optical black area OB. The first recess RS1 may be formed from the second surface 10b of the substrate 10 toward the first surface 10a of the substrate 10 .

A first fixed charge layer 24 may be disposed on the second surface 10b of the substrate 10 . The second surface 10b may contact the first fixed charge layer 24 . The first fixed charge layer 24 may cover the second surface 10b of the substrate 10 on the pixel area AP, and may cover the second surface 10b of the substrate 10 on the optical black area OB. and may cover the inner surface of the first recess RS1 in a conformal manner. A second fixed charge layer 26 and a second passivation layer 28 may be sequentially stacked on the first fixed charge layer 24 . The second fixed charge layer 26 and the second passivation layer 28 may conformally cover the first fixed charge layer 24 on the pixel area AP and the optical black area OB.

A light blocking grid pattern 56 may be disposed on the second passivation layer 28 in the pixel area AP. The light-blocking grid pattern 56 may overlap the pixel separator 31 and may have a net shape in plan view. Color filters CF1 and CF2 may be disposed between the light blocking grid pattern 56 in the pixel area AP.

The first connection structure 120 , the connection contact 80 , and the optical black patterns OBP1 and OBP2 may be provided on the substrate 10 in the optical black area OB.

The first connection structure 120 includes vias connecting the first optical black pattern OBP1 to the first wires 43 of the upper wiring layer 41 and/or the second wires 47 of the lower wiring layer 45. It may be a via plug. The first connection structure 120 may fill the first trench TR1 formed in the substrate 10 in the optical black region OB. The first trench TR1 extends into the substrate 10 through the first fixed charge layer 24 , the second fixed charge layer 26 , and the second passivation layer 28 inside the first recess RS1 . It can be. The first connection structure 120 may include a first conductive pattern 121 , a first insulating pattern 123 , and a first capping pattern 125 .

The connection contact 80 may fill the second trench TR2 formed in the substrate 10 in the optical black region OB. The second trench TR2 may pass through the first fixed charge layer 24 , the second fixed charge layer 26 , and the second passivation layer 28 inside the first recess RS1 . The second trench TR2 may be horizontally spaced apart from the first trench TR1. The connection contact 80 penetrates the first fixed charge layer 24, the second fixed charge layer 26, the second passivation layer 28, and a portion of the substrate 10 to form a separation conductive pattern of the pixel separator 31. (33) can be encountered. The connection contact 80 may include a first contact pattern 82 and a second contact pattern 84 .

A first optical black pattern OBP1 may be provided on the second passivation layer 28 in the optical black area OB. The first optical black pattern OBP1 may conformally cover the second passivation layer 28 in the first recess RS1. On the bottom surface of the first recess RS1, the first conductive pattern 121 of the first connection structure 120 and the first contact pattern 82 of the connection contact 80 form the first optical black pattern OBP1 and can be connected The first optical black pattern OBP1 may include a material different from that of the color filters CF1 and CF2 and the second optical black pattern OBP2 described later.

A second optical black pattern OBP2 may be disposed on the first optical black pattern OBP1 in the optical black area OB. The second optical black pattern OBP2 may overlap the first optical black pattern OBP1. The second optical black pattern OBP2 may fill the remainder of the first recess RS1. The upper surface of the second optical black pattern OBP2 may be located at the same level as the upper surfaces of the color filters CF1 and CF2. The upper surface of the second optical black pattern OBP2 and the upper surfaces of the color filters CF1 and CF2 may be positioned on the same plane. The second optical black pattern OBP2 may include the same material as any one of the color filters CF1 and CF2.

A planarization pattern 70 may be disposed on the second passivation layer 28 . The planarization pattern 70 may cover the color filters CF1 and CF2 and the second optical black pattern OBP2 on the second passivation layer 28 . The height of the top surface of the second optical black pattern OBP2 may be the same as the heights of the top surfaces of the color filters CF1 and CF2 . Accordingly, the top surface of the flattening pattern 70 may be flat in the pixel area AP and the optical black area OB. The flattening pattern 70 has a refractive index lower than that of the first nano-posts 66 of the color separation lens array layer 60 described later, such as silicon oxide (SiO) or siloxane-based spin on glass (SOG). It may be made of a dielectric material having a refractive index and low absorption in the visible light band.

A color separation lens array layer 60 may be provided on the flattening pattern 70 . The color separation lens array layer 60 may include a third passivation layer 62 , a first dielectric layer 64 , and first nano posts 66 .

The third passivation layer 62 may cover the planarization pattern 70 . An upper surface of the third passivation layer 62 may be flat. The third passivation layer 62 may include aluminum oxide (Al2O3).

First nano-posts 66 may be disposed on the third passivation layer 62 in the pixel area AP. The first nano-posts 66 may not be provided in the optical black area OB. The first nano-posts 66 may be arranged in a predetermined rule on the third passivation layer 62 . Here, the rule is applied to parameters such as shape, size (eg, width, height, etc.), spacing, and arrangement of the first nano-posts 66, and the color separation lens array layer ( 60) may be determined according to the target phase distribution to be implemented. The target phase distribution may be determined in consideration of a target region in which the wavelength of the incident light is to be separated and focused. The target phase distribution is the position immediately after the incident light passes through the color separation lens array layer 60, for example, the phase at the lower surface of the color separation lens array layer 60 or the upper surface of the third protective film 62. means distribution.

The color separation lens array layer 60 may have regions respectively positioned on the color filters CF1 and CF2. For example, the regions of the color separation lens array layer 60 may correspond to the color filters CF1 and CF2 in one-to-one correspondence. Each of the regions may include one or a plurality of first nano-posts 66 . Although FIG. 7 shows three first nano-posts 66 overlapping the regions, the present invention is not limited thereto. In addition, the first nano-posts 66 may be disposed at the boundary between the regions as shown in FIG. 7, or the first nano-posts 66 may be located entirely within the regions unlike shown. can

The first nano-posts 66 may form a phase distribution in which light of different wavelengths included in the incident light is diverted and condensed in different directions. For example, the first nano-posts are distributed in the regions such that light of a first wavelength included in the incident light has a first phase distribution and light of a second wavelength has a second phase distribution. The shape, size, arrangement, etc., of the slabs 66 may be determined. According to the target phase distribution, the array of first nano-posts 66 and the target positions (eg, color filters CF1 and CF2 or the photoelectric conversion unit 13, etc.) Light of one wavelength and light of the second wavelength may be condensed. Wavelengths of the lights diverged by the first nano-posts 66 may correspond to target wavelengths of the color filters CF1 and CF2 condensing the lights. Rules for arranging the first nano-posts 66 in the regions may be different. The first nano-posts 66 may have a size smaller than that of a wavelength band to be diverged. For example, when the incident light is visible light, the size (eg, width or height) of the first nano-posts 66 may be smaller than 400 nm.

The first nano-posts 66 may be made of a material having a higher refractive index than that of the third passivation layer 62 or the first dielectric layer 64 . For example, the first nano-posts 66 may include c-Si, p-Si, a-Si, and III-V compound semiconductors (GaP, GaN, GaAs, etc.), SiC, TiO2, SiN, and/or combinations thereof. can be made with The first nano-posts 66 having a refractive index different from that of the third passivation layer 62 or the first dielectric layer 64 may change the phase of passing light.

According to example embodiments, the top surfaces of the color filters CF1 and CF2 of the pixel area AP and the top surface of the second optical black pattern OBP2 of the optical black area OB are on the same plane. There may be no step difference between the color filters CF1 and CF2 and the second optical black pattern OBP2 near the boundary between the pixel area AP and the optical black area OB. Accordingly, the flattening pattern 70 may be formed to be more flat, and the color separation lens array layer 60 formed on the flattening pattern 70 may also be formed to be flat. Accordingly, the arrangement or arrangement rules of the first nano-posts 66 may be formed more regularly, and optical characteristics of the image sensor may be improved. In addition, it may be easier than forming the color separation lens array layer 60 formed on the flattening pattern 70 .

With continued reference to FIG. 7 , a first dielectric layer 64 may be provided on the third passivation layer 62 . The first dielectric layer 64 may cover the first nano-posts 66 on the third passivation layer 62 . The first dielectric layer 64 may include a dielectric material having a lower refractive index than the first nano-posts 66 . The first dielectric layer 64 may include the same material as the third passivation layer 62 . For example, the first dielectric layer 64 may be made of SiO2 or air.

Although the single-layer color separation lens array layer 60 is disclosed in FIG. 7, the present invention is not limited thereto. The color separation lens array layer may have at least a multi-layer configuration. Referring to FIG. 8 , the two-layer color separation lens array layer 60 will be described as an example. However, the present invention is not limited thereto, and a color separation lens array layer having a multi-layer configuration of three or more may be provided.

Referring to FIG. 8 , the color separation lens array layer 60 includes a third passivation layer 62-1, a first dielectric layer 64-1, first nano-posts 66-1, and a fourth passivation layer 62-1. 2), a second dielectric layer 64-2 and second nano-posts 66-2. The third passivation layer 62-1, the first dielectric layer 64-1, and the first nano-posts 66-1 constitute the first layer 60-1 of the color separation lens array layer 60, The fourth passivation layer 62-2, the second dielectric layer 64-2, and the second nano-posts 66-2 may constitute the second layer 60-2 of the color separation lens array layer 60. there is.

A first layer 60 - 1 of the color separation lens array layer 60 may be provided on the flattening pattern 70 . The third passivation layer 62 - 1 may cover the planarization pattern 70 . First nano posts 66 - 1 may be disposed on the third passivation layer 62 - 1 in the pixel area AP. A first dielectric layer 64-1 may be provided on the third passivation layer 62-1.

A second layer 60-2 of the color separation lens array layer 60 may be provided on the first layer 60-1. The fourth passivation layer 62-2 may cover the first dielectric layer 64-1. Second nano posts 66 - 2 may be disposed on the fourth passivation layer 62 - 2 in the pixel area AP. A second dielectric layer 64-2 may be provided on the fourth passivation layer 62-2.

The third passivation layer 62-1 and the fourth passivation layer 62-2 may have structures substantially the same as or similar to those of the third passivation layer 62 described with reference to FIG. 7 .

The first dielectric layer 64-1 and the second dielectric layer 64-2 may have structures substantially the same as or similar to those of the first dielectric layer 64 described with reference to FIG. 7 . The first dielectric layer 64-1 and the second dielectric layer 64-2 may surround the first nano-posts 66-1 and the second nano-posts 66-2, respectively. At this time, the first nano-posts 66-1 and the second nano-posts 66-2 are exposed to the upper surface of the first dielectric layer 64-1 and the upper surface of the second dielectric layer 64-2, respectively. It can be. However, the present invention is not limited thereto, and the first dielectric layer 64-1 and the second dielectric layer 64-2 include first nano-posts 66-1 and second nano-posts 66-2, respectively. ) can be completely covered.

The first nano-posts 66-1 and the second nano-posts 66-2 may have structures similar to those of the first nano-posts 66 described with reference to FIG. 7 . However, the first nano-posts 66-1 of the first layer 60-1 and the second nano-posts 66-2 of the second layer 60-2 have different positions in a plan view. can be arranged For example, the first nano-posts 66-1 and the second nano-posts 66-2 may be horizontally shifted. More specifically, shift directions of the first nano-posts 66-1 and the second nano-posts 66-2 may follow the inclined direction of the incident light. For example, when light incident on the image sensor is inclined from right to left, the second nano-posts 66-2 may be shifted to the right relative to the first nano-posts 66-1. Conversely, when light incident on the image sensor is inclined from left to right, the second nano-posts 66-2 may be shifted to the left with respect to the first nano-posts 66-1.

Although not shown, when considering the chief ray angle of incident light, the second nano-posts 66-2 may be shifted toward the center of the image sensor relative to the first nano-posts 66-1. For example, the second nano-posts 66-2 are further shifted to the right with respect to the first nano-posts 66-1 from the center to the left edge of the image sensor, and the center of the image sensor The second nano-posts 66-2 may be further shifted to the left with respect to the first nano-posts 66-1 toward the right edge from .

A fifth passivation layer 68 may be provided on the color separation lens array layer 60 . The fifth passivation layer 68 may cover the second dielectric layer 64-2 and the second nano-posts 66-2. The fifth passivation layer 68 may include silicon nitride (SiN).

9 to 17 are cross-sectional views illustrating a method of manufacturing an image sensor according to example embodiments.

Referring to FIG. 9 , a substrate 10 having a first surface 10a and a second surface 10b facing each other may be provided. The substrate 10 may include a pixel area AP, an optical black area OB, and a pad area PR. The substrate 10 may include a semiconductor substrate. The substrate 10 may be doped with impurities of the first conductivity type.

A device isolation pattern 17 may be formed on the first surface 10a of the substrate 10 . The device isolation pattern 17 may define active regions.

Referring to FIG. 10 , a trench may be formed on the pixel area AP and the optical black area OB by performing an etching process on the first surface 10a of the substrate 10 . The width of the trench may gradually decrease from the first surface 10a to the second surface 10b of the substrate 10 . When viewed from a plan view, the trench may have a lattice structure. A plurality of unit pixels UP may be defined in the pixel area AP by the trench.

A pixel separator 31 filling the trench may be formed. The pixel separator 31 may include an isolation conductive pattern 33 and an isolation insulating layer 35 . Forming the isolation conductive pattern 33 and the isolation insulating film 35 includes forming an insulating film partially filling the trench in a conformal manner, forming a conductive film filling the trench on the insulating film, and A planarization process may be performed on the insulating layer and the conductive layer until the first surface 10a of the substrate 10 is exposed. For example, the isolation insulating layer 35 may include a silicon oxide layer (SiO), a silicon oxynitride layer (SiON), or a silicon nitride layer (SiN). The isolation conductive pattern 33 may include n-type or p-type doped polysilicon.

Referring to FIG. 11 , photoelectric conversion units 13 are formed in the substrate 10 in the unit pixels UP of the pixel area AP by injecting impurities of a conductivity type opposite to that of the substrate 10 . can form

A floating diffusion region FD may be formed by doping impurities into each of the active regions. Transfer transistors TX and logic transistors RX, SX, and DX described above with reference to FIG. 2 may be formed on the active patterns.

A wiring layer 40 may be formed on the substrate 10 . A first interlayer insulating layer 42 may be formed on the first surface 10a of the substrate 10 . First interconnections 43 may be formed in the first interlayer insulating layer 42 , and contact plugs 44 connected to the first interconnections 43 may be formed. A second interlayer insulating layer 46 may be formed on the first interlayer insulating layer 42 . Second wires 47 may be formed in the second interlayer insulating layer 46 .

Referring to FIG. 12 , a planarization process may be performed on the second surface 10b of the substrate 10 to expose the pixel separator 31 . The planarization process may include a chemical mechanical polishing (CMP) process. A portion of the substrate 10 may be removed by the planarization process, and an upper surface of the pixel separator 31 may be exposed. In this case, both the upper surface of the separation conductive pattern 33 and the upper surface of the separation insulating layer 35 of the pixel separator 31 may be exposed.

Referring to FIG. 13 , a first recess RS1 and a second recess RS2 may be formed on the substrate 10 . More specifically, after forming a mask pattern on the second surface 10b of the substrate 10, an etching process using the mask pattern as an etching mask is performed to form a first recess ( RS1) and the second recess RS2 may be formed on the pad region PR. Since the first recess RS1 and the second recess RS2 are formed through the same etching process, the depth of the first recess RS1 and the depth of the second recess RS2 may be substantially the same. can Alternatively, the first recess RS1 and the second recess RS2 may be individually formed through separate processes. In this case, the depth of the first recess RS1 and the depth of the second recess RS2 may be formed differently. For example, as in the embodiment of FIG. 4 , the second recess RS2 The depth of may be formed to be greater than the depth of the first recess RS1.

The first fixed charge layer 24 may be formed conformally on the second surface 10b of the substrate 10 . The second fixed charge layer 26 may be formed conformally on the first fixed charge layer 24 . A second passivation layer 28 may be formed conformally on the second fixed charge layer 26 . At this time, the first fixed charge layer 24, the second fixed charge layer 26, and the second passivation layer 28 are formed along the bottom surface and inner walls of the first recess RS1 on the optical black area OB. and may be formed along the bottom surface and inner walls of the second recess RS2 on the pad region PR. In addition, the first fixed charge layer 24, the second fixed charge layer 26, and the second passivation layer 28 may cover the pixel separator 31 on the pixel area AP and the optical black area OB. . The first fixed charge film 24 is selected from the group consisting of hafnium (Hf), zirconium (Zr), aluminum (Al), tantalum (Ta), titanium (Ti), yttrium (Y) and lanthanoid. It may be formed of a metal oxide or metal fluoride containing at least one metal. The second passivation layer 28 may include at least one selected from PETEOS, silicon oxide (SiO), silicon nitride (SiN), silicon carbonitride (SiCN), hafnium oxide (HfO), and aluminum oxide (Al2O3).

Referring to FIG. 14 , a first trench TR1 , a second trench TR2 , and a third trench TR3 may be formed on the substrate 10 . More specifically, after forming a mask pattern on the second surface 10b of the substrate 10, an etching process using the mask pattern as an etching mask is performed on the substrate 10, thereby forming an image on the optical black area OB. A third trench TR3 may be formed on the first trench TR1 and the second trench TR2 and the pad region PR.

The first trench TR1 may be formed to extend from the bottom surface of the first recess RS1 into the substrate 10 . In this case, the first trench TR1 may pass through the first fixed charge layer 24 , the second fixed charge layer 26 , and the second passivation layer 28 inside the first recess RS1 . The first trench TR1 may pass through the substrate 10 and the upper wiring layer 41 to expose upper surfaces of some of the first wirings 43 . A portion of the first trench TR1 penetrates the substrate 10, the upper wiring layer 41, and the lower wiring layer 45 from one side of the partial first wirings 43 to the top surface of some of the second wirings 47. can expose.

The second trench TR2 may extend from the bottom surface of the first recess RS1 into the substrate 10 . The second trench TR2 may be formed on the pixel separator 31 of the optical black region OB. In this case, the second trench TR2 may pass through the first fixed charge layer 24 , the second fixed charge layer 26 , and the second passivation layer 28 inside the first recess RS1 . The second trench TR2 may pass through the substrate 10 to expose the isolation conductive pattern 33 of the pixel isolation unit 31 .

The third trench TR3 may be formed to extend into the substrate 10 from the second surface 10b of the substrate 10 . The third trench TR3 may pass through the first fixed charge layer 24 , the second fixed charge layer 26 , and the second passivation layer 28 . The third trench TR3 may pass through the substrate 10 , the upper wiring layer 41 , and the lower wiring layer 45 to expose a portion of the upper surface of the second wiring 47 .

Referring to FIG. 15 , the first conductive layer ML1 may be conformally formed on the second passivation layer 28 . For example, the first conductive layer ML1 may cover the second passivation layer 28 on the pixel area AP, cover the second passivation layer 28 on the optical black area OB, and cover the first recess (RS1), may be formed along inner sides of the first trench (TR1) and the second trench (TR2), to cover the second passivation layer 28 on the pad region (PR) and the second recess (RS2 and It may be formed along the inside of the third trench TR3. The first conductive layer ML1 may include, for example, tungsten (W). A part of the first conductive layer ML1 positioned in the first trench TR1 on the optical black region OB may constitute the first conductive pattern 121, and the first conductive layer ML1 positioned in the second trench TR2 may be formed. A portion of the conductive layer ML1 may constitute the first contact pattern 82, and the first conductive layer (which is located in the first recess RS1 and on the second surface 10b of the substrate 10) A part of ML1) may constitute the first optical black pattern OBP1. A part of the first conductive layer ML1 located in the third trench TR3 on the pad region PR may constitute the second conductive pattern 131, and the first conductive layer ML1 located in the second recess RS2 A portion of the conductive layer ML1 may constitute the first pad pattern 92 .

The second contact pattern 84 may be formed by filling the remainder of the second trench TR2 with a conductive material, and the second pad pattern 94 may be formed by filling the remainder of the second recess RS2 with a conductive material. can

Referring to FIG. 16 , an insulating layer (not shown) may be formed on the second surface 10b of the substrate 10 . The insulating layer may fill the remainder of the first trench TR1 and the remainder of the third trench TR3. Thereafter, an etching process such as wet etching may be performed on the insulating layer. Accordingly, the insulating layer may remain only in the first trench TR1 and the third trench TR3, and a portion of the insulating layer in the first trench TR1 may form the first insulating pattern 123. , and a portion of the insulating layer in the third trench TR3 may form the second insulating pattern 133 .

A first capping pattern 125 and a second capping pattern 135 may be formed on the first insulating pattern 123 and the second insulating pattern 133 , respectively. For example, the first capping pattern 125 may be formed by filling the remaining portion of the first trench TR1 with an insulating material, and the second capping pattern 135 may be formed by filling the remaining portion of the third trench TR3 with an insulating material. can be formed. Unlike this, in the process of forming the color filters CF1 and CF2 to be described later, insulating materials constituting the color filters CF1 and CF2 fill the remainder of the first trench TR1 and the third trench TR3 to make the second trench TR1 and TR3. A first capping pattern 125 and a second capping pattern 135 may be formed.

Thereafter, the first conductive layer ML1 may be removed from the pixel area AP by patterning the first conductive layer ML1. Accordingly, the second passivation layer 28 may be exposed on the pixel area AP.

Referring to FIG. 17 , a second conductive layer (not shown) may be formed conformally on the second passivation layer 28 in the pixel area AP. The second conductive layer may include, for example, tungsten (W). A light blocking grid pattern 56 exposing the second passivation layer 28 on the photoelectric conversion unit 13 may be formed by patterning the second conductive layer. Although the light blocking grid pattern 56 is formed separately from the first optical black pattern OBP1 in the exemplary embodiments, the present invention is not limited thereto. According to other embodiments, the light blocking grid pattern 56 may be formed on the result of FIG. 14 by patterning the first conductive layer ML1 positioned on the pixel area AP.

A photo lithography process may be performed several times to form the color filters CF1 and CF2 and the second optical black pattern OBP2 on the substrate 10 . For example, the first color filters CF1 and the second optical black pattern OBP2 may be simultaneously formed by performing a first photolithography process. To this end, a first photosensitive thermosetting resin solution containing a blue dye may be coated on the second surface 10b of the substrate 10 . At this time, the first optical black pattern OBP1 is formed on the second passivation layer 28 on the optical black area OB, and no separate structure is formed on the second passivation layer 28 on the pixel area AP. can However, as the first recess RS1 is formed in the substrate 10 on the optical black area OB and the first optical black pattern OBP1 is formed in the first recess RS1, the first optical black pattern A step difference between the pixel area AP and the optical black area OB caused by OBP1 may not occur or may be minimized. Accordingly, the first photosensitive thermosetting resin liquid may be coated with a uniform thickness, and streaking defects may not occur or be minimized. A first photoresist film may be formed by heating and curing the first photosensitive thermosetting resin solution. An exposure process and a developing process may be performed to form the first color filters CF1 and the second optical black pattern OBP2 . As a result, the shapes of the first color filters CF1 and the second optical black pattern OBP2 can be accurately formed. In addition, as the step difference between the pixel area AP and the optical black area OB does not occur or is minimized, the upper surfaces of the first color filters CF1 and the upper surfaces of the second optical black pattern OBP2 are It can be formed to be positioned at the same level, and a defect that may occur due to a step between the first color filters CF1 and the second optical black pattern OBP2 in a subsequent process can be prevented. Subsequently, the same/similar second and third photolithography processes may be sequentially performed to form the second and third color filters CF2 , respectively.

Referring back to FIG. 3 , a planarization pattern 70 may be formed on the substrate 10 . As the step difference between the first color filters CF1 and the second optical black pattern OBP2 does not occur or is minimized, the upper surface of the flattening pattern 70 may be substantially flat. ) may be formed with a thin thickness, it may be easy to form the upper surface of the planarization pattern 70 flat.

Thereafter, a micro lens array layer ML may be formed on the planarization pattern 70 .

Although the embodiments of the present invention have been described with reference to the accompanying drawings, those skilled in the art can implement the present invention in other specific forms without changing its technical spirit or essential features. You will understand that there is Therefore, the embodiments described above should be understood as illustrative in all respects and not limiting.

10: substrate
AP: pixel area OB: optical black area
PR: pad area
13: photoelectric conversion unit 17: element separation pattern
31: pixel separation unit 40: wiring layer
56: shading grid pattern 70: flattening pattern
80: connection contact 90: conductive pad
120: first connection structure 130: second connection structure
CF1, CF2: color filter OBP1: first optical black pattern
OBP2: second optical black pattern

Claims (10)

a substrate including a pixel area and an optical black area and having first and second surfaces facing each other;
color filters disposed on the second surface of the substrate in the pixel area; and
a first optical black pattern disposed in a first recess provided on the second surface of the substrate in the optical black region;
Including,
The first optical black pattern includes the same material as any one of the color filters,
Upper surfaces of the color filters and upper surfaces of the first optical black pattern are provided at the same level.
According to claim 1,
Further comprising a second optical black pattern interposed between the first optical black pattern and the substrate in the optical black region,
The second optical black pattern covers side surfaces and a lower surface of the first optical black pattern in the first recess. According to claim 2,
The second optical black pattern includes a material different from that of the first optical black pattern and the color filters. According to claim 1,
The substrate further includes a pad region,
The image sensor further comprises a conductive pad disposed in a second recess provided on the second surface of the substrate in the pad area. According to claim 4,
Further comprising a second optical black pattern interposed between the first optical black pattern and the substrate in the optical black region,
The second optical black pattern extends over the pad area, and covers side surfaces and lower surfaces of the conductive pad within the second recess.

a substrate including a pixel area, an optical black area, and a pad area;
a first recess provided on an upper surface of the substrate in the optical black region;
a second recess provided on an upper surface of the substrate in the pad area;
a plurality of color filters disposed on the substrate in the pixel area;
a first optical black pattern conformally covering bottom and inner surfaces of the first recess in the optical black region;
a second optical black pattern filling a remainder of the first recess in the optical black region; and
a conductive pad disposed on the substrate in the pad area;
Including,
The first optical black pattern includes the same material as any one of the color filters,
The second optical black pattern includes a material different from that of the first optical black pattern and the color filters.
According to claim 6,
Upper surfaces of the color filters and upper surfaces of the second optical black pattern are positioned on the same level. According to claim 6,
The bottom surface of the first recess and the bottom surface of the second recess are located at substantially the same level as the image sensor. According to claim 6,
An uppermost end of the first optical black pattern is positioned at the same level as or lower than an upper surface of the second optical black pattern.
a substrate including a pixel area and an optical black area;
color filters disposed on an upper surface of the substrate in the pixel area;
a first optical black pattern disposed in a recess provided in the upper surface of the substrate in the optical black region;
a passivation layer provided on the pixel area and the optical black area and covering the color filters and the first optical black pattern on an upper surface of the substrate; and
a color separation lens array layer provided on the passivation layer;
Including,
the color separation lens array layer has regions respectively corresponding to the color filters and provided with nano posts, the nano posts being arranged to branch light of different wavelengths included in incident light toward the color filters;
The first optical black pattern includes the same material as any one of the color filters,
The upper surface of the color filters and the upper surface of the first optical black pattern are provided on one plane.

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