KR20230068957A - System on chip for perporming scan test, and design method therefor - Google Patents

Abstract

A system on chip (SoC), according to the present invention, comprises: an OTP memory storing secured data; an OTP controller containing at least one shadow register which reads the secured data from the OTP memory and stores the secured data; a power management unit which receives an operation mode signal from an external device and outputs test mode information indicating whether an operation mode is a test mode according to the operation mode signal and a test validation signal corresponding to the secured data; and a test circuit which receives the test mode information from the power management unit, test data from the external device, and outputs a scan mode signal and a test mode signal according to the test data and a test inactivating signal. The test inactivating signal corresponds to development status data indicating a chip development status in the secured data. Accordingly, the present invention can provide an SoC improving the availability of a scan test.

Description

System on chip performing scan test, and method of designing it

The present invention relates to a system on a chip that performs a scan test, and a method for designing the same.

In general, SoC (System on Chip) means that a system having several functions is implemented as a single semiconductor chip. A design for test (DFT) technique is used to test logic circuits included in the SoC. Among the DFT techniques, a scan test is a technique for testing a logic circuit by checking output data based on input scan pattern data. Based on the scan test, a stuck fault, a transition delay fault, and the like of the logic circuit may be determined.

An object of the present invention is to provide a system on a chip that improves the availability of a scan test, and a method for designing the same.

An object of the present invention is to provide a system-on-chip that improves DFT (Design for Test) verification performance, and a method for designing the same.

A system on a chip according to an embodiment of the present invention includes an OTP memory for storing security data; an OTP controller including at least one shadow register for reading the security data from the OTP memory and storing the security data; a power management unit that receives an operation mode signal from an external device and outputs test mode information indicating whether an operation mode is a test mode according to the operation mode signal and a test valid signal corresponding to the secure data; and a test circuit that receives the test mode information from the power management unit, receives test data from the external device, and outputs a scan mode signal and a test mode signal according to the test data and a test inactivation signal. The deactivation signal is characterized in that it corresponds to development state data indicating a chip development state among the security data.

A system on a chip according to another embodiment of the present invention includes a first combinational logic; second combinatorial logic; third combinatorial logic; first scan flip-flops coupled between the first combinational logic and the second combinational logic; second scan flip-flops connected between the second combinational logic and the third combinational logic; a scan control flip-flop that receives output data of the second combinational logic and transfers the output data to the third combinational logic; a scan chain configured to receive scan data and to include the first scan flip-flops and the second scan flip-flops; and a multiplexer outputting one of an output signal of the scan chain and an output signal of the third combinational logic in response to a scan mode signal, wherein the scan control flip-flop affects a scan operation when the output data is in the scan mode. It is characterized in that it is designed not to give.

A method for designing a system on a chip according to an embodiment of the present invention includes defining One Time Programming (OTP) data in a specification; Determining whether the OTP data has an effect on testing or debugging access; and designing a shadow register using scan control flip-flops to store the OTP data when the OTP data affects the test or debugging access, each of the scan control flip-flops in a scan mode. It is characterized in that the output data is designed not to affect the scan operation.

A system on a chip and a method for designing the system according to an embodiment of the present invention can improve test usability by maintaining a value of a specific register in a scan mode.

A system-on-chip and a method for designing the system according to an embodiment of the present invention can improve DFT verification performance by maintaining a value of a specific register in a scan mode.

The accompanying drawings are provided to aid understanding of the present embodiment, and provide examples along with detailed descriptions.
1 is a diagram showing a scan chain circuit of a general system-on-chip by way of example.
2 is a diagram showing a system on chip 100 according to an embodiment of the present invention.
3 is a diagram showing an OTP controller 120 according to an embodiment of the present invention by way of example.
4 is a diagram exemplarily showing a scan control flip-flop according to an embodiment of the present invention.
5 is a diagram exemplarily showing a scan control flip-flop according to another embodiment of the present invention.
6 is a diagram exemplarily showing a scan chain circuit according to an embodiment of the present invention.
7 is a flowchart exemplarily showing a method of designing an OTP controller according to an embodiment of the present invention.
8 is a block diagram showing a computing device driving an EDA according to an embodiment of the present invention.
9 is a diagram showing a computing system 1000 according to an embodiment of the present invention by way of example.
10 is a block diagram showing a vehicle control system 2000 according to an exemplary embodiment of the present invention.

In the following, the content of the present invention will be described clearly and in detail to the extent that a person skilled in the art can easily practice using the drawings.

In general, a System on Chip (SoC) includes a One Time Programmable (OTP) memory to safely store values used therein. The security data stored in the OTP memory includes a security key for booting, trim information for sensor value correction, information for a memory repair system, development status data, and the like. Here, the development state data is used to classify the development state of the SoC, for example, a development stage, a test stage, and a mass production stage. The SoC can use development state data to switch operating modes. In general, the operation mode of SoC is divided into a function mode and a test mode. Here, the test mode is used for DFT (Design For Test). For secure DFT, operation mode conversion must be performed after data in the OTP memory is actually loaded. Such operation mode conversion may be determined as a valid signal output from the OTP controller. On the other hand, during a scan test, when the development state data is shaken, it is switched to an unintended mode, and thus test efficiency may be lowered.

1 is a diagram showing a scan chain circuit of a general system-on-chip by way of example. Referring to FIG. 1, when synthesizing a design, flip-flops that may have an effect are excluded from the scan chain. However, the data of the flip-flop may still be shaken by combinational logic during the 'update' process of the scan test. In general, the process of reading and writing data in the OTP memory in software takes quite a long time. For this reason, when booting the SoC, a process of copying OTP data to a shadow register (sensing) is performed. The data of these shadow registers are used for SoC operations (boot-related operations, security-related operations, recovery-related operations, etc.).

As schemes for DFT (Design for Test), such as IEEE 1149.1, are strengthened, a scan test for testing defects in flip-flops and gates (AND, OR, XOR, etc.) is inevitably required. First, a flip-flop test is performed by connecting all flip-flops in a chain, applying random data to the first input terminal, and then extracting data applied from the output terminal to compare the data. After data is first applied to the connected scan chain, the scan chain is released and operated in a functional mode (update), thereby confirming whether the gate operates according to the logic intended by the designer.

The shadow register of OTP is composed of a number of flip-flops. For this reason, scan tests are inevitably performed. However, among the shadow registers, certain registers (registers that store data used to classify the development status) should not be connected to the scan chain. This is because the flip-flop is tested using random data, so even though it is in the development stage, it can be set to make testing impossible by recognizing it for mass production. Also, when testing a gate as well as a scan chain, a problem in which a specific register is overwritten with unintended data may occur due to combinational logic. These problems can degrade DFT verification performance and lead to problems such as security holes. This makes DFT verification difficult and becomes a potential factor that makes security weak. To solve this problem, a function ECO (Engineering Change Order) is usually performed to exclude the corresponding flip-flop from the scan chain. However, the test coverage can be remarkably reduced by using only the vector for fixing the data so that the data is not shaken in the SCAN capture operation.

The present invention discloses a system on a chip that improves DFT verification performance/test usability, an electronic device having the same, and a method of operating the same. In particular, the system-on-chip according to an embodiment of the present invention may be implemented (designed) so that flip-flop data, which may affect a test, is not shaken during a test operation. For example, the system-on-chip of the present invention uses a feedback loop flip-flop or a gating clock flip-flop, and the like, so that a specific register (eg, a combinational logic) is used during a scan test operation. For example, it may be implemented so that data in a shadow register) is not updated. In addition, the system-on-chip according to an embodiment of the present invention may be designed so that a flip-flop that may affect a test is not connected to a scan chain when a design is synthesized.

The system-on-a-chip according to an embodiment of the present invention enables a stable test by preventing specific data from being updated by an 'update' item (combinational logic test) during a scan test. In addition, the system-on-chip according to an embodiment of the present invention enables a stable test by preventing data of a specific flip-flop from being updated by a 'shifting' item during a scan test.

A system-on-chip according to an embodiment of the present invention and a method for designing the same cause an unintended problem by excluding OTP data affecting a design for test (DFT)/debugging element from a scan test. In addition, it can be implemented to perform secure DFT control so that specific data is not updated due to the operation of combinatorial logic in the scan chain.

2 is a diagram showing a system on chip 100 according to an embodiment of the present invention. Referring to FIG. 2 , the system on chip 100 may include an OTP memory 110, an OTP controller 120, a power management unit 130 (PMU), and a test circuit 140 (JTAG TOP).

OTP memory 110 may be implemented to store secure data. Here, security data may include a booting key, trim information, recovery information, or development state data. The OTP memory 110 may include a plurality of memory cells connected to word lines and bit lines. Here, the plurality of memory cells may have irreversible characteristics in which programmed data is not lost and cannot be programmed again even if power is cut off. For example, each of the memory cells may be implemented as a fuse or an antifuse.

The OTP controller 120 may be implemented to control the OTP memory 110 . OTP controller 120 may include at least one shadow register 122 . Data constituting the secure DFT may be loaded into the shadow register 122 of the OTP controller 120. During the scan test, the OTP controller 120 may be implemented as a scan control flip-flop 124 in which data of the shadow register 122 is not toggled so that the DFT environment is not deactivated. For example, data in the shadow register 122 may be controlled using clock gating or a feedback loop.

In an embodiment, DFT/Debug access may be controlled according to life-cycle data of the OTP memory 110 without clock gating or a feedback loop in normal mode. In order to distinguish the normal mode from the test mode, it is possible to switch to the test mode by receiving a valid signal (JTAG_VALID) indicating that data output from the OTP memory 110 is valid.

Also, the OTP controller 120 may read security data from the OTP memory 110. For example, the OTP controller 120 may be implemented to output a valid signal (JTAG_VALID) when security data related to JTAG (DFT)/debugging is read.

The power management unit 130 may receive power from an external device and supply internal power to the SoC 100 . In addition, the power management unit 130 receives an operation mode signal (XOM) and a reset signal (XnRESET) from an external device, receives a test valid signal (JTAG_VALID) from the shadow register 122 of the OTP controller 120, Test mode information can be output.

In an embodiment, the sequence for DFT is as follows. The power management unit 130 may receive a value for the test mode using the operation mode signal XOM, which is an external input. The OM (Operation Mode) decoder 131 of the power management unit 130 receives the mode signal XOM and the reset signal XnRESET, interprets the received mode signal XOM, and prepares for the test mode TEST_MODE. can confirm that it has been The power management unit 130 may include a logic circuit 132 that performs an AND operation on the output signal of the OM decoder 131 and the test valid signal JTAG_VALID from the shadow register 122 and outputs test mode information.

In addition, the AND operation circuit 132 of the power management unit 130 performs an 'AND' operation on the valid signal (JTAG_VALID) received from the OTP controller 120 and the signal received from the OM decoder 131, so that the operation mode is the test mode. It can be output that it has been converted to .

The test circuit (JTAG TOP module 140) may receive test data from an external JTAG interface using the JTAG MUX 141. Also, the test circuit 140 may determine each test mode according to the received data. For example, the test circuit 140 receives test mode information from the power management unit 130, receives a test disable signal (JTAG_DISABLE) from the shadow register 122 of the OTP controller 120, and tests from the JTAG interface. Data may be received, and a scan mode signal (SCAN_MODE) and a test mode signal (TEST_MODE) may be output. Here, the scan mode signal SCAN_MODE includes a value indicative of a scan operation, and the test mode signal TEST_MODE includes a value indicative of a test operation.

In general, security data such as the test disable signal (JTAG_DISABLE) stored in the OTP memory can distinguish the development status of the SoC. In the development stage, a test mode exists for system-on-chip debugging. In the actual mass production stage, conversion to the test mode may be impossible. In the test mode, the internal data of the SoC can be processed. This is because key data related to security can be read. Among these test items, there is a scan test that tests flip-flops and gates, which are elements that make up the SoC. The SoC is tested using random data, and at this time, the flip-flop storing the test disable signal (JTAG_DISABLE) may change to '1' even though it is in the development stage. As a result, the scan chain may be released. This makes the circuit untestable. In order to prevent this, the OTP controller 120 according to an embodiment of the present invention replaces the flip-flop storing related data in the shadow register 122 with a feedback flip-flop, or a secure DFT control circuit using clock gating, that is, , can be implemented with the scan control flip-flop 124.

In general, OTP memory stores data representing development stages (Life-cycle). In the booting phase of the product, OTP data is loaded into the shadow register. During the scan test, there is a possibility that the data of the shadow register may be toggled. This can turn off the DFT/Debug function.

The system-on-chip 100 according to an embodiment of the present invention improves the usability of test operations by providing a scan control flip-flop 124 that turns on/off or controls DFT/Debug-related functions for each stage of product development. can make it In addition, the system-on-a-chip 100 according to an embodiment of the present invention may fix security data of a shadow register by using a clock gating method or a feedback loop method in the OTP controller 120 .

3 is a diagram showing an OTP controller 120 according to an embodiment of the present invention by way of example. Referring to FIG. 3 , the OTP controller 120 may include a function register 121 and a shadow register 122 .

The function register 121 may include at least one flip-flop that stores data for performing a function of the OTP controller 120 .

The shadow register 122 may include at least one flip-flop 123 that stores trim information and at least one scan control flip-flop 124 that stores DFT information.

As shown in FIG. 3 , the OTP controller 120 may be implemented by applying a scan control flip-flop 124 in the shadow register 122 to data that may affect DFT (Debug) access. In a typical OTP controller, only flip-flops exist between combinational logics. Accordingly, during a scan test, when data is updated by the combinational logic, the data of the flip-flops may also be updated. On the other hand, in the embodiment of the present invention The OTP controller 120 according to the above may include a shadow register 122 (see FIG. 1) implemented as a scan control flip-flop whose data is not updated by combinatorial logic.

4 is a diagram exemplarily showing a scan control flip-flop according to an embodiment of the present invention. Referring to FIG. 4 , the scan control flip-flop 400 may include a flip-flop 410 and a multiplexer 420 . In an embodiment, the scan control flip-flop 400 may receive an output of the first combinational logic 401 and transmit an input to the second combinational logic 402 . By placing the 2x1 multiplexer 420 in front of the flip-flop 410, it is possible to be affected by the combinational logic 401 when operating in a mode other than the scan chain. When operating as a scan chain, a feedback loop may be formed by connecting the output of the flip-flop 410 to the input. As a result, current data of the flip-flop 410 may be maintained. As a result, the data of flip-flop 410 is not arbitrarily updated.

5 is a diagram exemplarily showing a scan control flip-flop according to another embodiment of the present invention. Referring to FIG. 5 , the scan control flip-flop 500 may include a flip-flop 510 and an AND gate circuit 520 .

As shown in FIG. 5 , by disposing the AND gate circuit 520 at the clock terminal applied to the flip-flop 510, a common clock signal can be used when operating in a mode other than the scan chain. In addition, current data of the flip-flop 510 may be maintained by gating a clock signal when operating as a scan chain. That is, during the scan chain, data in the flip-flop 510 is not arbitrarily updated.

6 is a diagram exemplarily showing a scan chain circuit according to an embodiment of the present invention. Referring to FIG. 6, the scan chain circuit includes a first combinational logic 601, a second combinational logic 602, a third combinational logic 603, scan flip-flops (SFFs), scan control flip-flops 610, and A multiplexer 620 may be included.

The scan flip-flops (SFFs) may include first scan flip-flops and second scan flip-flops forming a scan chain. Here, the first scan flip-flops may be connected between the first combinational logic 601 and the second combinational logic 602 . Also, the second scan flip-flops may be connected between the second combinational logic 603 and the third combinational logic 603 . Here, the scan chain may receive scan data during a scan operation and output corresponding data.

The scan control flip-flop 610 may be implemented to receive output data of the second combinational logic 602 and pass the output data to the third combinational logic 603 . The scan control flip-flop 610 can be excluded from the scan chain as shown in FIG. 6 . In an embodiment, as described in FIGS. 2 to 6 , the scan control flip-flop 610 may be designed so that output data of combinational logic does not affect a scan operation in a scan mode.

The multiplexer 620 may be implemented to output one of the output signal of the scan chain and the output signal of the third combinational logic 603 in response to the scan mode signal SCAN_MODE.

As shown in FIG. 6, in the case of a flip-flop that may affect the test, it can be excluded from the scan chain as before. In addition, by replacing the flip-flop 610 using a feedback loop, a stable test is possible.

7 is a flowchart exemplarily showing a method of designing an OTP controller according to an embodiment of the present invention. Referring to FIG. 7 , a method of designing an OTP controller may proceed as follows. Specifications of data to be stored in the OTP memory (110, see FIG. 2) may be defined (S110). It can be determined whether the corresponding data affects JTAG/Debug access (S120). If the corresponding data is data affecting JTAG/Debug access, the shadow register 122 (see FIG. 2) may be designed using scan control flip-flops 124 (see FIG. 2) (S130). On the other hand, when the corresponding data is data that does not affect JTAG/Debug access, the shadow register 122 may be designed by flip-flops (S135). By repeating the above process, the OTP controller (120, see FIG. 2) can be designed.

In an embodiment, the scan control flip-flops 124 may be excluded from the scan chain. In an embodiment, each of the scan control flip-flops 124 may be implemented as a feedback loop flip-flop 400 shown in FIG. 4 or a gating clock flip-flop 500 shown in FIG. 5 . .

General digital hardware design proceeds with RTL (Register Transfer Level) design according to specifications, proceeds with netlist design, proceeds with layout design, manufactures chips using layout data, and testing is in progress. In general, a specification describes requirements for each function of hardware. The functions described in the specification are described using HDL (Hardware Description Language) such as Verilog or VHDL (Very High-Speed Integrated Circuit Hardware Description Language). In the register transfer level (RTL) design stage, hardware components with modularity and flexibility can be designed. Each of the components is linked to a description library with timing constraints related to voltage and environmental factors. In the netlist design stage, by verifying the equivalence of the RTL design and the netlist design, it is verified that the designed function is not modified by synthesis. In addition, timing between components is verified using Static Timing Analysis (STA). Each component of the technology library is mapped to an analog model described using layers (eg, silicon-based semiconductors). After this, all components are placed in a predetermined area and routed (interconnected) to the metal layer. In the layout design stage, the entire layout is compared to the netlist design through layout-to-schematic (LVS) verification. In addition, it is verified whether the designed layout can be manufactured through DRC (Design Rule Check). Then, a chip is manufactured according to the designed layout, i.e., layout data. After that, the test proceeds. On the other hand, a custom design may proceed according to a similar process after gate unit circuit completion. A high level design (HLD) of a memory device may be performed using a computing device. A circuit designed by HLD can be expressed more concretely by RTL coding or simulation. Codes generated by RTL coding can be converted into a netlist and arranged and synthesized into an entire semiconductor memory. The synthesized schematic circuit is verified by a simulation tool, and an adjustment process may be accompanied according to the verification result.

Generally, Electronic Design Automation (EDA) is a software application available to designers/manufacturers to design electronic devices. Many software applications are available for designing, simulating, analyzing and verifying electronic devices prior to fabrication on integrated circuits or semiconductor substrates.

8 is a block diagram showing a computing device driving an EDA according to an embodiment of the present invention. Referring to FIG. 8 , a computing device 800 may include at least one processor 810, a working memory 820, an input/output device 830, and a storage device 840. Here, the computing device 800 may be provided as a dedicated device for designing. Computing device 800 may be configured to run various design and verification simulation programs.

The processor 810 may be implemented to execute software to be executed on the computing device 800 . The processor 810 may execute an operating system (OS) loaded into the working memory 820 . The processor 810 may execute various application programs to be driven based on an operating system (OS). In an embodiment, the processor 810 may execute an EDA tool. Here, EDA tools may include RTL synthesis tools, batch tools, clock tree synthesis tools, routing tools, verification tools, netlist simulation tools, or CDC tools. In particular, the EDA tool may include the secure DFT control (scan control flip-flop) algorithm described in FIGS. 2-7.

The working memory 820 may load an operating system (OS) or application programs. When the computing device 800 boots, the OS image stored in the storage device 840 may be loaded into the working memory 820 according to a booting sequence. All input/output operations of the computing device 800 may be supported by an operating system (OS). Additionally, the EDA tool 822 may be loaded into the working memory 820 from the storage device 840 .

Also, the working memory 820 may include volatile memory such as static random access memory (SRAM) or dynamic random access memory (DRAM). Meanwhile, the working memory 820 is not limited thereto, and may include non-volatile memory such as phase-change RAM (PRAM), magnetic RAM (MRAM), resistance RAM (ReRAM), ferroelectric RAM (FRAM), and flash memory. there is.

The input/output device 830 may be implemented to control user input and output from user interface devices. For example, the input/output device 830 may receive information from a designer using a keyboard or a monitor. Using the input/output device 830, a designer may receive information about semiconductor regions or data paths requiring adjusted operating characteristics. In addition, through the input/output device 830, processing processes and processing results of the simulation tool and the CDSC tool may be output so as to be displayed.

The storage device 840 may be provided as a storage medium of the computing device 800 . The storage device 840 may store application programs (AP), operating system images, and various data. The storage device 840 may be provided as a memory card (multimedia card (MMC), embedded MMC (eMMC), secure digital (SD), MicroSD, etc.) or a hard disk drive (HDD). The storage device 840 may include a NAND-type flash memory having a mass storage function. Alternatively, the storage device 840 may include a next-generation non-volatile memory such as PRAM, MRAM, ReRAM, FRAM, or NOR flash memory.

The system bus 801 may provide a network within the computing device 800 . At least one processor 810, a working memory 820, an input/output device 850, and a storage device 840 are electrically connected through the system bus 801 and may exchange data with each other.

The computer program product for automating electronic design in SoC design according to an embodiment of the present invention, when designing an OTP controller, excludes data affecting scan test operation from the scan chain or outputs the corresponding data. A Secure DFT control algorithm may be provided to secure the flip-flop.

A method for designing an OTP controller of an SoC according to an embodiment of the present invention enables efficient DFT control by designing a scan control circuit. The design method of the present invention enables a stable test by using a feedback loop flip-flop or a gating clock flip-flop in a scan test among DFT items. In addition, safe and fast test mode conversion is possible without reading all OTP data by using a valid signal (JTAG_VALID) to determine whether OTP data related to mode conversion has actually been detected. As a result, the speed of SoC development can be shortened. In addition, the flip-flop that affects DFT (Debug) is a potential risk factor that is difficult to detect during scan testing, and the risk factor can be reduced in advance by designing with this in mind at the RTL (Register Transfer Level) level.

Meanwhile, the SoC according to an embodiment of the present invention can be applied to a computing system.

9 is a diagram showing a computing system 1000 according to an embodiment of the present invention by way of example. Referring to FIG. 9 , the computing system 1000 may include a main processor 1100, memories 1200a and 1200b, and storage devices 1300a and 1300b, and additionally includes an image capturing device. 2410, user input device 2420, sensor 2430, communication device 2440, display 2450, speaker 2460, power supplying device 2470 and connections It may include one or more of the connecting interfaces 2480.

The main processor 1100 may control the overall operation of the system 1000, and more specifically, the operation of other components constituting the system 1000. The main processor 1100 may be implemented as a general-purpose processor, a dedicated processor, or an application processor. The main processor 1100 may include an OTP controller implemented with the scan control flip-flop described in FIGS. 1 to 8 .

The main processor 1100 may include one or more CPU cores 1110 and may further include a controller 1120 for controlling the memories 1200a and 1200b or the storage devices 1300a and 1300b. In an embodiment, the main processor 1100 may further include an accelerator block 1130 that is a dedicated circuit for high-speed data operation such as artificial intelligence (AI) data operation. Such an accelerator block 1130 may include a graphics processing unit (GPU), a neural processing unit (NPU), or a data processing unit (DPU), and is physically independent from other components of the main processor 1100. It may be implemented as a chip of.

The memories 1200a and 1200b may be used as main memory devices of the system 1000 and may include volatile memories such as SRAM or DRAM, but may also include non-volatile memories such as flash memory, PRAM, or RRAM. The memories 1200a and 1200b may also be implemented in the same package as the main processor 1100 .

The storage devices 1300a and 1300b may function as non-volatile storage devices that store data regardless of whether or not power is supplied, and may have a relatively large storage capacity compared to the memories 1200a and 1200b. The storage devices 1300a and 1300b may include storage controllers 1310a and 1310b and non-volatile memory (NVM) storage 1320a and 1320b for storing data under the control of the storage controllers 1310a and 1310b. can The non-volatile memories 1320a and 1320b may include V-NAND flash memory of a 2-dimensional (2D) structure or a 7-dimensional (3D) structure, but may include other types of non-volatile memories such as PRAM or RRAM. may be

The storage devices 1300a and 1300b may be included in the system 1000 in a state physically separated from the main processor 1100 or may be implemented in the same package as the main processor 1100 . In addition, the storage devices 1300a and 1300b have a form such as a solid state device (SSD) or a memory card, so that other components of the system 1000 can be accessed through an interface such as a connection interface 2480 to be described later. It may also be coupled to be detachable with the . The storage devices 1300a and 1300b may be devices to which standard protocols such as universal flash storage (UFS), embedded multi-media card (eMMC), or non-volatile memory express (NVMe) are applied, but are not necessarily limited thereto. It's not.

The photographing device 1410 may capture a still image or a moving image, and may be a camera, a camcorder, or a webcam. The user input device 1420 may receive various types of data input from a user of the system 1000, and may use a touch pad, a keypad, a keyboard, a mouse, or a microphone ( microphone), etc. The sensor 1430 can detect various types of physical quantities that can be acquired from the outside of the system 1000 and convert the detected physical quantities into electrical signals. Such a sensor 1430 may be a temperature sensor, a pressure sensor, an illuminance sensor, a position sensor, an acceleration sensor, a biosensor, or a gyroscope.

The communication device 1440 may transmit and receive signals with other devices outside the system 1000 according to various communication protocols. Such a communication device 2440 may be implemented by including an antenna, a transceiver, or a modem (MODEM). The display 1450 and the speaker 1460 may function as output devices that output visual information and auditory information to the user of the system 1000, respectively. The power supply device 1470 may appropriately convert power supplied from a battery built in the system 1000 or an external power source and supply the power to each component of the system 1000 .

The connection interface 1480 may provide a connection between the system 1000 and an external device connected to the system 1000 and capable of exchanging data with the system 1000 . The connectivity interface 2480 includes Advanced Technology Attachment (ATA), Serial ATA (SATA), external SATA (e-SATA), Small Computer Small Interface (SCSI), Serial Attached SCSI (SAS), Peripheral Component Interconnection (PCI), PCIe (PCI express), NVMe (NVM express), IEEE 1394, USB (universal serial bus), SD (secure digital) card, MMC (multi-media card), eMMC (embedded multi-media card), UFS (Universal Flash Storage) ), embedded universal flash storage (eUFS), and compact flash (CF) card interface.

On the other hand, as the SoC test scheme becomes important, the design method can be applied to product groups emphasizing secure DFT, including automotive products.

10 is a block diagram showing a vehicle control system 2000 according to an exemplary embodiment of the present invention. Referring to FIG. 10, the vehicle control system 2000 for autonomous driving includes a sensor information collection device 2100, a navigation information collection device 2200, an electronic control unit 2300 (ECU) for autonomous driving, a central processing unit ( 2400) and a memory device 2500. Also, the electronic control unit 2300 for autonomous driving may include a neural network device 2310 and a crypto device 2320. The electronic control unit 2300 may include an OTP controller implemented as an OTP memory for storing secure data and a scan control flip-flop for maintaining secure data in test/debugging operations as described in FIGS. 1 to 8 .

The neural network device 2310 may perform a neural network operation using various types of video information and audio information, and generate information signals such as video recognition results and voice recognition results based on the performance results.

The sensor information collection device 2100 includes devices capable of collecting various kinds of video information and audio information, such as a camera or a microphone, and may provide them to the electronic control unit 2300 for autonomous driving. The navigation information collection device 2200 may provide various types of information (eg, location information) related to vehicle operation to the electronic control unit 2300 for autonomous driving. The neural network device 2310 may generate an information signal by executing various types of neural network models by taking information from the sensor information collection device 2100 or the navigation information collection device 2200 as an input. When the sensor information collection device 2100 includes a camera or a microphone, the crypto device 2320 of the autonomous driving module 2300 performs security processing on voice data or image data from the sensor information collection device 2100, and the A decoding operation and an ECC operation may be performed. As described above, the crypto device 2320 may store encrypted data and metadata/ECC data in the memory device 2500 .

Meanwhile, in FIG. 10 , an example in which an embodiment of the present invention is applied to an autonomous driving system is described. However, embodiments of the present invention can be applied to products requiring a security function in a camera sensor, such as IoT, surveillance cameras, and the like.

The design method of controlling DFT/Debug-related functions for each product development stage is to prevent important information from being leaked through SCAN while the assembly stage of the essential element product required by custom SoC customers is carried out by an external company Secure For DFT configuration, OTP is generally used. DFT/Debug access is controlled according to this data. During the scan test of the OTP Controller, the related data is toggled to an unintended value and is controlled so that it does not affect the test. Depending on the operation mode of the product, there is a difference in the secure DFT control method. In normal mode, data intended to control the DFT/Debug function according to the development stage of the product is stored in the OTP. That is, control is possible according to OTP data without clock gating and feedback loop circuit. In SCAN Mode, after reading OTP data, data is maintained only when DFT/Debug related functions are enabled. In addition to excluding it from the SCAN chain, additional logic design of clock gating or feedback loop keeps data during scan test. In designing a secure DFT according to the life-cycle of a product using an OTP controller, the OTP controller can be designed to maintain data in the case of a flip-flop that affects the scan test.

On the other hand, the above-described content of the present invention is only specific embodiments for carrying out the invention. The present invention will include technical ideas, which are abstract and conceptual ideas that can be utilized as technology in the future, as well as concrete and practically usable means themselves.

100: system on chip
110: OTP memory
120: OTP controller
122: shadow register
124: scan control flip-flop
130: power management unit
131: operation mode decoder
140: test circuit

Claims (10)

OTP (One Time Programming) memory for storing security data;
an OTP controller including at least one shadow register for reading the security data from the OTP memory and storing the security data;
a power management unit that receives an operation mode signal from an external device and outputs test mode information indicating whether an operation mode is a test mode according to the operation mode signal and a test valid signal corresponding to the secure data; and
a test circuit that receives the test mode information from the power management unit, receives test data from the external device, and outputs a scan mode signal and a test mode signal according to the test data and a test inactivation signal;
Wherein the test deactivation signal corresponds to development state data indicating a chip development state among the security data. According to claim 1,
The system-on-a-chip, characterized in that the security data includes a security key, trim data, recovery data and the development state data. According to claim 1,
The at least one shadow register includes at least one scan control flip-flop for storing data that does not affect a scan test. According to claim 3,
Wherein the at least one scan control flip-flop is implemented as a feedback loop flip-flop. According to claim 4,
The feedback loop flip-flop,
a flip-flop outputting the data in response to a clock; and
A system-on-chip comprising a multiplexer that outputs one of a combinational logic signal and an output signal of the flip-flop in response to a scan mode signal. According to claim 3,
Wherein the at least one scan control flip-flop is implemented as a gating clock flip-flop. According to claim 6,
The gating clock flip-flop,
a flip-flop that outputs output data of combinational logic in response to a gating clock; and
and an AND operation circuit that receives a scan mode signal and a clock and outputs the gating clock. According to claim 1,
The power management unit,
an operation mode decoder that receives the operation mode signal and the reset signal and determines an operation mode corresponding to the operation mode signal; and
and an arithmetic circuit outputting the test mode information by performing an AND operation on the test valid signal and the output signal of the operation mode decoder. first combinatorial logic;
second combinatorial logic;
third combinatorial logic;
first scan flip-flops coupled between the first combinational logic and the second combinational logic;
second scan flip-flops connected between the second combinational logic and the third combinational logic;
a scan control flip-flop that receives output data of the second combinational logic and transfers the output data to the third combinational logic;
a scan chain configured to receive scan data and to include the first scan flip-flops and the second scan flip-flops; and
A multiplexer outputting one of an output signal of the scan chain and an output signal of the third combinational logic in response to a scan mode signal;
The system-on-chip, characterized in that the scan control flip-flop is designed so that the output data does not affect the scan operation in the scan mode. In the system-on-chip design method,
Defining OTP (One Time Programming) data in the specification;
Determining whether the OTP data has an effect on testing or debugging access; and
designing a shadow register using scan control flip-flops to store the OTP data when the OTP data affects the test or debugging access;
Each of the scan control flip-flops is designed so that output data does not affect a scan operation in a scan mode.

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