KR20230068263A - Memory system using host memory buffer and operation method thereof - Google Patents

Abstract

The present invention relates to a memory system, and more particularly, to a memory system using a host memory buffer and an operating method thereof. A method of operating a memory system including a host and a storage device according to an embodiment of the present invention includes allocating a portion of a host memory included in the host as a host memory buffer for use by a controller of the storage device; Setting a set characteristic command to activate a memory buffer, setting a retention command including information about a response speed of the host memory buffer, and selecting an operating mode of the host memory buffer based on the retention command. It includes a selection step. The memory system according to the exemplary embodiment of the present invention selects an optimal mode among operation modes of the host memory buffer based on the response speed of the host memory buffer, thereby improving overall performance of the memory system.

Description

Memory system using host memory buffer and its operating method {MEMORY SYSTEM USING HOST MEMORY BUFFER AND OPERATION METHOD THEREOF}

The present invention relates to a memory system, and more particularly, to a memory system using a host memory buffer and an operating method thereof.

As an example of a flash memory-based mass storage device, a solid state drive (hereinafter referred to as SSD) is a representative example. Along with the explosive increase in demand for SSD, its uses are diversifying. For example, uses may be subdivided into SSDs for servers, SSDs for clients, and SSDs for data centers. The SSD's interface must be able to provide optimal speed and reliability for each of these uses. To meet these demands, SATA, PCIe, and SAS are being applied as optimal SSD interfaces. In particular, in recent years, PCIe-based NVMe or UFS-based Unified Memory Extension (UME) has been actively researched and applied to storage devices. These interfaces provide a memory sharing function between devices. For example, a host may allocate a portion of a memory area within the host to a storage device, and the allocated memory area may be referred to as a host memory buffer (HMB).

In this memory sharing technique, a demand for a technique for a storage device to efficiently use a host memory buffer (HMB) is increasing. This is because the host memory buffer (HMB) is located in the host, but utilization of the host memory buffer (HMB) is performed by the storage device. In particular, according to the prior art, the host transmits only an enable signal or a disable signal for whether or not the host memory buffer (HMB) is available to the storage device, and the response speed of the host memory buffer (HMB). do not transmit information In this case, the storage device operates by accessing the host memory buffer (HMB) regardless of the response speed of the host memory buffer (HMB), which causes performance degradation of the overall memory system.

An object of the present invention is to provide a memory system capable of varying the operation of a host memory buffer according to the response speed of the host memory buffer.

A method of operating a memory system including a host and a storage device according to an embodiment of the present invention includes allocating a portion of a host memory included in the host as a host memory buffer for use by a controller of the storage device; setting a set characteristic command to activate the host memory buffer; setting a retention command including information about response speed of the host memory buffer; selecting an operation mode of the host memory buffer based on the retention command; and selecting one of a plurality of power states supported by the controller based on a performance objective of an operation mode of the host memory buffer.

A method of operating a memory system including a host and a storage device according to an embodiment of the present invention includes allocating a portion of a host memory included in the host as a host memory buffer for use by a controller of the storage device; setting a set characteristic command to activate the host memory buffer; setting a retention command including information about response speed of the host memory buffer; and selecting an operation mode of the host memory buffer based on the retention command.

A storage device sharing a host memory of a host according to an embodiment of the present invention includes an interface for using a portion of the host memory as a host memory buffer of the storage device; and selecting one of first to third modes as an operation mode for the host memory buffer based on the response speed of the host memory buffer when a retention occurs in which a response speed of the host memory buffer becomes slow. and a storage device, wherein when the first mode is selected, access to the host memory buffer of the storage device is allowed, and when the second mode is selected, access to the host memory buffer of the storage device is allowed. The storage retrieves and stores frequently used data among data stored in the host memory buffer, and when the third mode is selected, access of the storage device to the host memory buffer is not permitted.

A memory system according to an exemplary embodiment of the present invention selects an optimal mode among operation modes of the host memory buffer based on the response speed of the host memory buffer and operates the host memory buffer according to the selected mode. Accordingly, performance of the entire memory system may be improved.

1 is a block diagram illustrating a memory system according to an exemplary embodiment of the inventive concept.
FIG. 2 is a block diagram showing an example of the host memory of FIG. 1 .
FIG. 3 is a block diagram showing the configuration of the storage controller of FIG. 1 as an example.
4 is a diagram showing an example of a retention command by way of example.
5 is a flowchart illustrating an example of an operation of the memory system of FIG. 1 .
6 is a flowchart illustrating an example of step S120 of FIG. 5 in which the host sets a retention command.
7 is a flowchart illustrating an example of step S140 of FIG. 5 in which the storage device selects an operation mode.
8 and 9 are diagrams for explaining in detail an operation of transmitting a command between a host and a storage controller when retention occurs.
10 is a block diagram showing an example of a memory system according to an exemplary embodiment, and FIG. 11 is a block diagram showing an example of a storage controller of FIG. 10 .
12A to 12E are diagrams illustrating an example of a command transmission operation between the host of FIG. 10 and the storage controller.

Hereinafter, embodiments of the present invention will be described clearly and in detail to the extent that those skilled in the art can easily practice the present invention.

1 is a block diagram illustrating a memory system 1000A according to an exemplary embodiment of the inventive concept. Referring to FIG. 1 , a memory system 1000A according to an embodiment of the present invention includes a host 1100 and a storage device 1200 .

The memory system 1000A according to an embodiment of the present invention supports a host memory buffer function that shares a partial area of the host memory 1130 with the storage device 1200 . In addition, when retention occurs, the response speed of the host memory buffer 1120 allocated to the storage device 1200 is delayed compared to the normal speed, the host 1100 sends a retention command to the storage device. Send to (1200). The storage device 1200 selects a mode exhibiting optimal performance among a plurality of modes based on the retention command and operates the host memory buffer 1120 according to the selected mode. Accordingly, overall performance of the memory system 1000A may be improved.

More specifically, the host 1100 writes data into the storage device 1200 or reads data stored in the storage device 1200 . To this end, the host 1100 may transmit a command CMD and an address ADDR for writing data to the storage device 1200 . Also, the host 1100 may transfer a command CMD and an address ADDR for reading data stored in the storage device 1200 to the storage device 1200 . The host 1100 includes a processor 1110 , a host memory 1130 , and an interface circuit 1150 .

Application programs, file systems, device drivers, and the like may be loaded into the host memory 1130 . In addition, various software or data driven by the host 1100 may be loaded into the host memory 1130 . In particular, the host 1100 may allocate a portion of the host memory 1130 as the host memory buffer 1120 serving as a buffer of the storage device 1200 .

The host memory buffer 1120 is an area of the host memory 1130 allocated to the storage device 1200 so that the storage device 1200 can use it. For example, when the host memory buffer 1120 is allocated to the storage device 1200, the host memory buffer 1120 is provided for exclusive use by the storage device 1200. At this time, the host 1100 may delete the host memory buffer 1120 from the host memory descriptor list.

Retention may occur in the host memory buffer 1120 . Here, retention means a state in which the response speed of the host memory buffer 1120 is slowed compared to a normal case. For example, it is assumed that the host memory 1130 is set to be activated at intervals of 200 ms in a power saving mode. If the host 1100 enters the power saving mode, a retention occurs in which the response speed of the host memory buffer 1120 becomes slower than normal. In addition, retention may occur due to various causes, such as deterioration of memory cells of the host memory buffer 1120 and performance of a replacement operation for defective memory cells.

When retention occurs in the host memory buffer 1120 , the host 1100 transmits a retention command to the storage device 1200 . Here, the retention command includes the address of the host memory buffer 1120 where retention occurs and a retention level corresponding to the delayed response speed. In an embodiment, the host memory buffer 1120 is divided into a plurality of HMB areas, and retention may occur in at least one HMB area among the plurality of HMB areas. In this case, the host 1100 may transmit an address and a retention level corresponding to the HMB area where retention occurs to the storage device 1200 .

The interface circuit 1150 provides a physical connection between the host 1100 and the storage device 1200 . That is, the interface circuit 1150 converts commands, addresses, data, etc. corresponding to various requests issued by the host 1100 into an interfacing method with the storage device 1200 . Protocols of the interface circuit 1150 include Universal Serial Bus (USB), Small Computer System Interface (SCSI), PCI express, ATA, Parallel ATA (PATA), Serial ATA (SATA), Serial Attached SCSI (SAS), UFS ( Universal Flash Storage) may be at least one of them.

The storage device 1200 may also be referred to as an NVM subsystem and is provided as data storage for the host 1100 . In addition, the storage device 1200 may allocate a portion of the host memory 1130 of the host 1100 as the host memory buffer 1120 and use the host memory buffer 1120 identically to the internal buffer. The storage device 1200 includes a host interface 1220 , a storage controller 1240 , and a nonvolatile memory device 1260 .

The host interface 1220 is provided as a physical communication channel of the storage device 1200 for data exchange with the host 1100 . The host interface 1220 may have an interfacing protocol through which the host memory buffer 1120 may support the buffer function of the storage device 1200 . That is, the host interface 1220 may be an interfacing method for mutually sharing memory resources of the host 1100 and memory resources of the storage device 2100 . For example, the storage controller 1240 may manage the host memory buffer 1120 and an internal buffer of the storage device 1200 as one memory map through the host interface 1220 .

The storage controller 1240 controls overall operations of the storage device 1200 . The storage controller 1240 includes an operation mode controller 1243 that selects an operation mode of the host memory buffer 1120 based on a retention command received from the host 1100 .

The operation mode controller 1243 receives a retention command from the host 1100 and checks the retention level of the host memory buffer 1120 where retention occurs based on the retention command. In addition, the operation mode controller 1243 selects a mode that exhibits optimal performance among operation modes for the host memory buffer 1120 based on the retention level, and the host memory buffer in which retention occurs according to the selected mode ( 1120) can be operated.

For example, the operation mode controller 1243 may select a mode allowing or blocking access to the host memory buffer 1120 of the storage device 1200 according to the retention level. Also, the operation mode controller 1243 may select a mode for retrieving some of the data stored in the host memory buffer 1120 according to the retention level and storing the retrieved data in the storage device 1200 . In this way, by changing the operation mode of the host memory buffer 1120 in which retention occurs according to the retention level, overall performance of the memory system 1000A may be improved.

The nonvolatile memory device 1260 is provided as a storage medium of the storage device 1200 . The nonvolatile memory device 1260 may include nonvolatile memory such as flash memory, PRAM, MRAM, ReRAM, FRAM, and a magnetic disk.

As described above, the memory system 1000A according to an embodiment of the present invention selects an optimal mode among operation modes for the host memory buffer 1120 based on the retention level, and selects the host memory buffer 1120 according to the selected mode. Operate the buffer 1120. In this way, by varying the operation of the host memory buffer 1120 according to the retention level, overall performance of the memory system 1000A may be improved.

FIG. 2 is a block diagram showing an example of the host memory 1130 of FIG. 1 . In FIG. 2 , for convenience of description, it is assumed that the host memory buffer 1120 is divided into first to third HMB areas 1122 , 1124 , and 1126 .

The host memory 1130 is a memory included in the host 1100 . The host memory 1130 may store or output data requested by the host 1100 . For example, the host memory 1130 may be implemented with volatile memory such as DRAM or SRAM. However, the host memory 1130 may be implemented in various ways according to purposes, and may also be implemented as a non-volatile memory.

The host memory buffer 1120 is an area in which a portion of the host memory 1130 is allocated to the storage device 1200 so that it can be used as a buffer of the storage device 1200 . That is, the storage device 1200 may use the host memory buffer 1120 as an internal buffer. In the case of an internal buffer provided in the storage device 1200, it may be difficult to provide sufficient capacity due to various issues such as cost, device size, and design limitations. However, since the host 1100 according to an embodiment of the present invention allocates a portion of the host memory 1130 to the storage device 1200 for use by the storage device 1200, the storage device 1200 has sufficient buffer capacity. can be obtained.

The host memory buffer 1120 may be divided into a plurality of HMB areas 1122, 1124, and 1126 according to various criteria.

In one embodiment, the host memory buffer 1120 may be divided into a plurality of HMB areas 1122, 1124, and 1126 according to the access frequency of stored data. For example, data with high access frequency of the storage device 1200 is stored in the first HMB area 1122, and data with medium access frequency of the storage device 1200 is stored in the second HMB area 1124. In the third HMB area 1126 , data with a low access frequency of the storage device 1200 may be stored.

Also, according to an embodiment, the host memory buffer 1120 may be divided into a plurality of HMB areas 1122, 1124, and 1126 according to the type of data to be stored. For example, mapping data of the storage device 1200 is stored in the first HMB area 1122 , user data is stored in the second HMB area 1124 , and storage device 1200 is stored in the third HMB area 1126 . ) Management data for managing the may be stored. Meanwhile, the host memory buffer 1120 may be divided into a plurality of HMB areas 1122, 1124, and 1126 according to various criteria, such as the degree of deterioration of memory cells, in addition to attributes of stored data.

Retention may occur in some of the plurality of HMB areas 1122 , 1124 , and 1126 of the host memory buffer 1120 . In this case, the host 1100 may transmit a retention command for an HMB area in which retention occurs among the plurality of HMB areas 1122 , 1124 , and 1126 to the storage device 1200 (see FIG. 1 ). The storage device 1200 may receive a retention command for the HMB area, and the operation mode controller 1243 (see FIG. 1 ) may select an operation mode for the HMB area where retention occurs based on the retention command.

FIG. 3 is a block diagram showing the configuration of the storage controller 1240 of FIG. 1 as an example. Referring to FIG. 3 , the storage controller 1240 includes a CPU 1241 , an operation mode controller 1243 , and a flash interface 1245 .

The CPU 1241 may control overall operations of the storage device 1100 . For example, the CPU 1241 uses a flash interface 1245 to write data to the nonvolatile memory device 1260 or to read data stored in the nonvolatile memory device 1260 in response to a command from the host 1100. can control.

The operation mode controller 1243 receives a retention command for the host memory buffer 1120 through the host interface 1220 (refer to FIG. 1). The operation mode controller 1243 checks the retention level of the host memory buffer 1120 and selects an optimal mode among a plurality of operation modes for the host memory buffer 1120 based on this. To this end, the operation mode controller 1243 may include a retention level check module 1242 and an operation mode determination module 1244 .

The retention level checking module 1242 checks the retention level of the host memory buffer 1120 included in the retention command. For example, when the host memory buffer 1120 is divided into a plurality of HMB areas, the retention level checking module 1242 may check the retention level of the HMB area where retention occurs among the plurality of HMB areas. .

The operation mode determination module 1244 selects an optimal mode among operation modes for the host memory buffer 1120 based on the retention level, and operates the host memory buffer 1120 in which retention occurs according to the selected mode. can

For example, as described below, the operation mode determination module 1244 may select one of the first to third modes (Mode1 to Mode3) according to the retention level. When the first mode (Mode1) is selected, the operation mode determination module 1244 may allow the storage device 1200 to access the host memory buffer 1120 where retention occurs. When the second mode (Mode2) is selected, the operation mode determination module 1244 allows the storage device 1200 to access the host memory buffer 1120 where retention occurs, but frequently uses data where retention occurs. Data may be retrieved from the host memory buffer 1120 and stored in the storage device 1200 . When the third mode (Mode 3) is selected, the operation mode determination module 1244 may not allow the storage device 1200 to access the host memory buffer 1120 where retention occurs.

4 is a diagram showing an example of a retention command by way of example. For convenience of explanation, in FIG. 4 , the host memory buffer 1120 (see FIG. 1 ) is divided into first to third HMB areas HMB1 to HMB3 , respectively, to the first to third HMB areas HMB1 to HMB3 . It is assumed that retention occurs.

Referring to FIG. 4 , the retention command includes an address ADDR of the host memory buffer 1120 where retention occurs and a retention level.

The retention level may be divided into a plurality of levels according to the degree of delay in response speed. The host 1100 (refer to FIG. 1 ) may determine a retention level of the host memory buffer 1120 where retention occurs, based on the degree of delay of the response speed of the host memory buffer 1120 .

For example, as shown in FIG. 4 , it is assumed that the expected response times of the first to third HMB areas HMB1 to HMB3 are 500 ms, 200 ms, and 90 ms, respectively. Also, assume that the first and second reference response times TH1 and TH2 are 90 ms and 300 ms, respectively.

The expected response time of the first HMB area HMB1 is 500 ms, which is greater than the second standard response time TH2 of 300 ms. In this case, the host 1100 may determine that the response speed of the first HMB area HMB1 is very slow, and may determine the retention level of the first HMB area HMB1 as 'X'. Here, the retention level of 'X' may indicate that the host memory buffer is in an unusable state. When the retention level is 'X', the operation mode determination module 1244 (see FIG. 3 ) may select a third mode (Mode3) as an operation mode of the first HMB area HMB1. Accordingly, access of the storage device 1200 to the first HMB area HMB1 may be blocked.

The expected response time of the second HMB area HMB2 is 200 ms, which is greater than the first standard response time TH1 of 100 ms and less than the second standard response time TH2 of 300 ms. In this case, the host 1100 may determine that the response speed of the second HMB area HMB2 is medium slow, and may determine the retention level of the second HMB area HMB2 as '1'. When the retention level is '1', the operation mode determination module 1244 may select the second mode (Mode2) as an operation mode of the second HMB area HMB2. Accordingly, the storage device 1200 is allowed to access the second HMB area HMB2, but frequently used data can be retrieved from the second HMB area HMB2 and stored in the storage device 1200.

The expected response time of the third HMB area HMB3 is 90 ms, which is smaller than the first reference response time TH1 of 100 ms. In this case, the host 1100 may determine that the response speed of the third HMB area HMB3 is slightly slow, and may determine the retention level of the third HMB area HMB3 as '2'. When the retention level is '2', the operation mode determination module 1244 may select the first mode (Mode1) as an operation mode of the third HMB area HMB3. Accordingly, the storage device 1200 is allowed to access the third HMB area HMB3, and the third HMB area HMB3 can be continuously used as an internal buffer regardless of whether or not retention occurs.

As described above, the host 1100 according to an embodiment of the present invention may set the retention level of the host memory buffer 1120 according to the degree of delay in response speed. In addition, the operation mode controller 1243 may select an optimal operation mode for the host memory buffer 1120 based on the retention level.

FIG. 5 is a flowchart illustrating an example of an operation of the memory system 1000A of FIG. 1 .

In step S110, the host 1100 allocates a portion of the host memory 1130 as the host memory buffer 1120 for use by the storage device 1200.

In step S120, the host 1100 sets a retention command based on the response speed of the host memory buffer 1120 where retention occurs.

In step S130 , the host 1100 transmits a retention command to the storage device 1200 .

In operation S140 , the storage device 1200 receives a retention command and selects an operation mode for the host memory buffer 1120 based on the received retention command.

In step S150 , the storage device 1200 receives a retention recovery command from the host 1100 . Accordingly, the operation of using the host memory buffer 1120 as an internal buffer of the storage device 1200 resumes.

6 is a flowchart illustrating an example of step S120 of FIG. 5 in which the host 1100 sets a retention command. For convenience of description, it is assumed in FIG. 6 that the retention level is set based on the first and second reference response times TH1 and TH2 as in FIG. 4 .

In step S121, the host 1100 checks the expected response time of the host memory buffer 1120 where retention occurs.

In step S122, the host 1100 checks whether the expected response time is greater than the first reference response time TH1.

If the expected response time is less than the first reference response time TH1, the host 1100 sets the retention level of the host memory buffer 1120 to '2' (step S123). Conversely, if the expected response time is greater than the first reference response time TH1, the host 1100 checks whether the expected response time is greater than the second reference response time TH2 (step S124).

If the expected response time is less than the second reference response time TH2, the host 1100 sets the retention level of the host memory buffer 1120 to '1' (step S125). Conversely, if the expected response time is greater than the second reference response time TH2, the host 1100 sets the retention level of the host memory buffer 1120 to 'X' (step S126).

As described above, the host 1100 may set the retention level according to the response speed of the host memory buffer 1120 where retention occurs.

FIG. 7 is a flowchart illustrating an example of step S140 of FIG. 5 in which the storage device 1200 selects an operation mode. For convenience of explanation, it is assumed in FIG. 7 that retention commands having retention levels of '2', '1', and 'X' are received.

In step S141 , the storage device 1200 checks the retention level of the host memory buffer 1120 . If the retention level is '2', step S142 of selecting the first mode (Mode1) is performed. If the retention level is '1', step S143 of selecting the second mode (Mode2) is performed. If the retention level is 'X', step S144 of selecting the third mode (Mode1) is performed.

In step S142, the storage device 1200 selects the first mode (Mode1). In this case, the storage device 1200 may access the host memory buffer 1120 where retention occurs. That is, since the decrease in response speed due to retention has little effect on overall performance, the storage device 1200 may continue to use the host memory buffer 1120 as an internal buffer regardless of whether or not retention occurs.

In step S143, the storage device 1200 selects the second mode (Mode2). In this case, the storage device 1200 may access the host memory buffer 1120 where retention occurs, but access to the host memory buffer 1120 may be minimized for smooth operation. To this end, the storage device 1200 may retrieve frequently used data from the host memory buffer 1120 and store it.

More specifically, in step S143_1, the storage device 1200 may access the host memory buffer 1120. In step S143_2 , the storage device 1200 may retrieve frequently used data from the host memory buffer 1120 and store it therein. In step S143_3, the storage device 1200 may perform various background operations using the retrieved data. Also, if necessary, the storage device 1200 may access the host memory buffer 1120 again and further retrieve necessary data.

Meanwhile, in step S144, the storage device 1200 selects the third mode (Mode3). In this case, the storage device 1200 is not permitted to access the host memory buffer 1120 where retention occurs. However, depending on whether data necessary for the background operation needs to be recovered, blocking access to the host memory buffer 1120 of the storage device 1200 may be executed after necessary data is recovered.

More specifically, in step S144_1, the storage device 1200 determines whether there is data necessary for a background operation or the like in the host memory buffer 1120.

If there is no required data, the storage device 1200 is not allowed to access the host memory buffer 1120 (step S144_6). In this case, the storage device 1200 may enter a deep sleep state or perform a background operation using previously stored data.

Conversely, if necessary data exists, the storage device 1200 accesses the host memory buffer 1120 (step S144_2). Thereafter, the storage device 1200 retrieves data necessary for a background operation from the host memory buffer 1120 and stores the data therein (step S144_3). Thereafter, access of the storage device 1200 to the host memory buffer 1120 is blocked (step S144_4), and the storage device 1200 may perform a background operation using the retrieved data.

As described above, the storage device 1200 selects an optimal mode among operating modes of the host memory buffer 1120 based on the retention level of the host memory buffer 1200, and the host memory buffer 1200 selects an optimal mode according to the selected mode. The buffer 1120 may be operated.

8 and 9 are diagrams for explaining in detail an operation of transmitting a command between a host and a storage controller when retention occurs. For a clear explanation, in FIG. 8, a command transmission operation between a general host and a storage controller is described, and in FIG. 9, a host 1100 (see FIG. 1) and a storage controller 1240 (see FIG. 1) according to an embodiment of the present invention A command transmission operation between will be described.

First, referring to FIG. 8 , in step S10, the host sets bits of an enable host memory (EHM) command and a memory return (MR) command to '1', respectively. Accordingly, an operation for returning the host memory buffer to the host is performed while the host memory buffer is activated.

In step S20, before the host memory buffer is deactivated, the storage controller retrieves data stored in the host memory buffer.

In step S30, the host sets bits of the EHM command and the MR command to '0' and '1', respectively. Accordingly, the host memory buffer is deactivated and the host memory buffer is returned.

In step S40, the storage controller enters a deep sleep state or performs a background operation. At this time, since the host memory buffer has already been returned, the storage controller cannot use data stored in the host memory buffer.

In step S50, the host memory buffer is recovered from retention. In this case, the host sets bits of the EHM command and the MR command to '1' and '0', respectively. Accordingly, the host reallocates the host memory buffer to the storage controller, and the host memory buffer is activated.

In step S60, the storage controller performs a rebuilding operation to store necessary data in the host memory buffer again.

As described above, general memory systems only provide set feature commands such as the EHM command and the MR command, but do not provide a retention command like the present invention. Accordingly, when retention occurs, in which the response speed of the host memory buffer becomes slower than the normal speed, a general memory system deactivates the host memory buffer and returns the host memory buffer in which retention occurs.

In this case, a typical memory system must retrieve all data stored in the host memory buffer before the host memory buffer is deactivated. Accordingly, a time delay (latency) occurs accordingly. In addition, upon recovery from retention, a general memory system must perform a rebuilding operation of allocating a host memory buffer again and storing data in the host memory buffer again. Accordingly, a time delay accordingly occurs again.

9A is a diagram illustrating an example of a command transmission operation between the host 1100 and the storage controller 1240 according to an embodiment of the present invention. In FIG. 9A , a command transmission operation in the first mode (Mode1) described in FIG. 7 will be described as an example.

In step S1110, the host 1100 sets bits of the EHM command and the MR command to '1' and '0', respectively. Accordingly, the following operation may be performed in a state in which the host memory buffer HMB is enabled. In addition, the host memory buffer (HMB) is not returned.

In step S1120, the host 1100 transmits a retention command to the storage controller 1240. The retention command includes the address of the host memory buffer (HMB) where retention occurs and the retention level. For example, as shown in FIG. 7 , assume that the retention level is '2'. In this case, the storage controller 1240 confirms that the retention level is '2' and selects the first mode (Mode1) as an operation mode of the host memory buffer (HMB). Accordingly, the storage controller 1240 continues to use the host memory buffer (HMB) as an internal buffer regardless of whether retention occurs.

In step S1130, the host 1100 transmits an I/O command to the storage controller 1240.

In step S1140 , the storage controller 1240 processes the I/O command received from the host 1100 . At this time, the storage controller 1240 can freely access the host memory buffer (HMB).

In step S1150, the host 1100 transmits a retention recovery command to the storage controller 1240.

As described above, in the first mode (Mode1), the storage controller 1240 according to an embodiment of the present invention does not return the host memory buffer (HMB) and continues to use it as an internal buffer. Therefore, unlike the general memory system of FIG. 8 , the storage controller 1240 according to an embodiment of the present invention does not need to perform an operation to retrieve data stored in the host memory buffer (ie, step S20 of FIG. 8 ). As a result, time delay caused by retrieving data from the host memory buffer (HMB) can be prevented.

In addition, since the host memory buffer (HMB) is continuously used as an internal buffer, the storage controller 1240 according to an embodiment of the present invention rebuilds the host memory buffer (HMB) (ie, step S60 of FIG. 8) do not need to be performed. Accordingly, a time delay caused by rebuilding the host memory buffer (HMB) can also be prevented.

9B is a diagram illustrating an example of a command transmission operation between the host 1100 and the storage controller 1240 according to an embodiment of the present invention. In FIG. 9B , an example of a command transmission operation in the second mode (Mode2) described in FIG. 7 will be described.

In step S1210, the host 1100 sets bits of the EHM command and the MR command to '1' and '0', respectively. Accordingly, the following operation may be performed in a state in which the host memory buffer (HMB) is activated.

In step S1220, the host 1100 transmits a retention command to the storage controller 1240. For example, as shown in FIG. 7 , assume that the retention level is '1'. In this case, the storage controller 1240 may confirm that the retention level is '1' and select a second mode (Mode2) corresponding to the retention level as an operation mode of the host memory buffer (HMB).

In step S1230 , the storage controller 1240 retrieves frequently used data from the host memory buffer (HMB) and stores it in the storage device 1200 .

In step S1240, the storage controller 1240 performs a background operation using the retrieved data. At this time, if necessary for the background operation, the storage controller 1240 may access the host memory buffer (HMB) again to retrieve more necessary data. However, since frequently used data has already been retrieved in step S1230, access to the host memory buffer (HMB) of the storage controller 1240 can be minimized.

In step S1250, the host 1100 transmits a retention recovery command to the storage controller 1240.

In step S1260, the storage controller 1240 updates the contents of the host memory buffer (HMB).

As described above, in the second mode (Mode2), the storage controller 1240 according to an embodiment of the present invention may operate to minimize access to the host memory buffer (HMB) where retention occurs. In particular, while the general storage controller of FIG. 8 retrieves all data stored in the host memory buffer, the storage controller 1240 according to an embodiment of the present invention can retrieve only frequently used data from the host memory buffer (HMB). . Thus, time delay due to data retrieval can be reduced.

In addition, the host 1100 according to an embodiment of the present invention continuously sets the bit of the MR command to '0'. Therefore, the host memory buffer HMB is not returned, and the data stored in the host memory buffer HMB is continuously maintained. Accordingly, the storage controller 1240 according to an embodiment of the present invention may update only changed data, compared to the general storage controller of FIG. 8 having to store all data again in the newly allocated host memory buffer. As a result, the time required for the resume operation of the host memory buffer HMB may be reduced.

9C is a diagram showing an example of a command transmission operation between the host 1100 and the storage controller 1240 according to an embodiment of the present invention. In FIG. 9C , another example of a command transmission operation in the second mode (Mode2) described in FIG. 7 will be described. The operation described in FIG. 9C is similar to that of FIG. 9B. Therefore, redundant descriptions will be omitted below.

In step S1310, the host 1100 sets bits of the EHM command and the MR command to '1' and '0', respectively.

In step S1320, the host 1100 transmits a retention command to the storage controller 1240. For example, let's assume that the retention level is '1'. In this case, the storage controller 1240 selects the second mode (Mode2).

In step S1330 , the storage controller 1240 retrieves frequently used data from the host memory buffer (HMB) and stores it in the storage device 1200 .

In step S1340, the host 1100 transmits an I/O command to the storage controller 1240.

In step S1350, the storage controller 1240 processes an I/O command using the retrieved data. At this time, if necessary to process the I/O command, the storage controller 1240 may re-access the host memory buffer (HMB) to further retrieve necessary data. However, since frequently used data has already been retrieved in step S1330, access to the host memory buffer (HMB) of the storage controller 1240 can be minimized.

In step S1360 , the host 1100 transmits a retention recovery command to the storage controller 1240 .

In step S1370, the storage controller 1240 updates the host memory buffer (HMB).

As described above, in the second mode (Mode2), the storage controller 1240 according to an embodiment of the present invention minimizes access to the host memory buffer (HMB) where retention occurs and commands I/O commands. can handle

9D is a diagram illustrating an example of a command transmission operation between the host 1100 and the storage controller 1240 according to an embodiment of the present invention. In FIG. 9D , an example of a command transmission operation in the third mode (Mode3) described in FIG. 7 will be described.

In step S1410, the host 1100 sets bits of the EHM command and the MR command to '1' and '0', respectively.

In step S1420, the host 1100 transmits a retention command to the storage controller 1240. For example, as shown in FIG. 7 , assume that the retention level is 'X'. In this case, the storage controller 1240 selects the third mode (Mode3).

In step S1430 , the storage controller 1240 retrieves data necessary for a background operation from the host memory buffer (HMB) and stores it in the storage device 1200 .

In step S1440, the storage controller 1240 transmits an acknowledgment signal (ACK) notifying the host 1100 that recovery of necessary data has been completed. After that, access of the storage device 1200 to the host memory buffer 1120 is blocked.

In step S1450, the storage controller 1240 performs a background operation. At this time, the storage controller 1240 is not allowed to access the host memory buffer 1120, and the storage controller 1240 performs a background operation using only retrieved data or previously stored data.

In step S1460, the host 1100 transmits a retention recovery command to the storage controller 1240.

In step S1470, the storage controller 1240 updates the contents of the host memory buffer (HMB).

As described above, in the third mode (Mode3), the retention command set by the host 1100 according to an embodiment of the present invention blocks the storage controller 1240 from accessing the host memory buffer HMB. function as an option.

In general, when the host enters a power saving mode, the storage controller's access to the host memory buffer may cause the host to wake-up. This becomes a factor that halves the effect of the power saving mode. However, the retention command according to an embodiment of the present invention functions as an option to block access to the host memory buffer (HMB) of the storage controller 1240. Accordingly, when the host 1100 enters the power saving mode, the host 1100 may prevent unwanted wake-up from occurring in advance by setting the retention level of the retention command to 'X'.

In addition, since the host 1100 according to an embodiment of the present invention does not return the host memory buffer (HMB), the time required to restart the host memory buffer (HMB) can be reduced.

9E is a diagram illustrating an example of a command transmission operation between the host 1100 and the storage controller 1240 according to an embodiment of the present invention. In FIG. 9E , another example of a command transmission operation in the third mode (Mode3) described in FIG. 7 will be described. The operation described in FIG. 9E is similar to that of FIG. 9D. Therefore, redundant descriptions will be omitted below.

In step S1510, the host 1100 sets bits of the EHM command and the MR command to '1' and '0', respectively.

In step S1520, the host 1100 transmits a retention command to the storage controller 1240. For example, suppose the retention level is 'X'. In this case, the storage controller 1240 selects the third mode (Mode3).

In step S1530, access to the host memory buffer (HMB) of the storage controller 1240 is blocked. Accordingly, the storage controller 1240 may enter an idle state or perform a background operation using data previously stored in the storage device 1200 .

In step S1540, the host 1100 transmits a retention recovery command to the storage controller 1240.

In step S1550, the storage controller 1240 updates the contents of the host memory buffer (HMB).

As described above, in the third mode (Mode3), the retention command may immediately block access of the storage controller 1240 to the host memory buffer HMB.

On the other hand, the above description is exemplary, and the technical spirit of the present invention can be modified and applied in various ways. In the following, application examples of the present invention will continue to be described.

FIG. 10 is a block diagram showing an example of a memory system 1000B according to an embodiment of the present invention, and FIG. 11 is a block diagram showing an example of a storage controller 1240_1 of FIG. 10 . The memory system 1000B of FIG. 10 is similar to the memory system 1000A of FIG. 1 , and the storage controller 1240_1 of FIG. 11 is similar to the storage controller 1240 of FIG. 3 . Therefore, the same or similar elements are denoted using the same or similar reference numerals, and redundant descriptions will be omitted below.

The memory system 1000B of FIG. 10 may additionally support a power management function. For example, the memory system 1000B may support a dynamic power management function, and the host 1100_1 adjusts power states so that the storage device 1200_1 can exhibit the best performance. can be modified. To this end, the host 1100_1 may include a power manager 1140 , and the operation mode controller 1243_1 may include a power state descriptor table 1246 .

The power manager 1140 receives information about performance statistics from the storage device 1200_1. For example, the power manager 1140 may receive information about performance statistics for each of a plurality of power states supported by the storage controller 1240 . Information on performance statistics is provided for Maximum Power (MP), Entry Latency (ENLAT), Exit Latency (EXLAT), Relative Read Throughput (RRT), Relative Read Latency (RRL), Relative Write Throughput (RWT), Relative Write Latency (RWL) ) may contain information about

The power manager 1140 may select a power state capable of maximizing performance of the storage device 1200_1 based on performance statistics for each of a plurality of power states. In particular, the power manager 1140 according to an embodiment of the present invention may select a power state based on the operation mode of the host memory buffer 1120 . In this case, the operation mode of the host memory buffer 1120 may be provided to the power manager 1140 as a performance objective. Also, as another example, the power manager 1140 may select a power state based on the retention level of the host memory buffer 1120 . In this case, the retention command set by the host 1100_1 may be provided to the power manager 1140 as a performance target.

The power state descriptor table 1246 manages information about performance statistics for each of a plurality of power states supported by the storage controller 1200_1 . For example, the storage controller 1200_1 can support up to 32 power states, and the power state descriptor table 1246 can manage performance statistics such as MP for each of the 32 power states.

As described above, the memory system 1000B according to an embodiment of the present invention additionally supports a power management function. In particular, the power manager 1140 may select an optimal power state from among a plurality of power states based on the retention level of the host memory buffer 1120 in which retention occurs and/or the operating mode of the host memory buffer 1120. there is. As a result, the host 1100_1 according to an embodiment of the present invention can more accurately control the storage device 1200_1, and thus the overall performance of the memory system 1000B can be improved.

12A to 12E are diagrams illustrating an example of a command transmission operation between the host 1100_1 and the storage controller 1240_1 of FIG. 10 . Operations of FIGS. 12A to 12E are similar to those of FIGS. 9A to 9E except that a power state command is additionally transmitted from the host 1100_1 to the storage controller 1240_1 . Therefore, redundant descriptions will be omitted below.

12A is a diagram illustrating an example of a command transmission operation between the host 1100_1 and the storage controller 1240_1 in the first mode (Mode1).

In step S2110, the host 1100_1 sets bits of the EHM command and the MR command to '1' and '0', respectively.

In step S2120, the host 1100_1 transmits a retention command to the storage controller 1240_1. For example, suppose that the retention level of the host memory buffer (HMB) where retention occurs is '2'. In this case, the storage controller 1240_1 selects the first mode (Mode1) as an operation mode of the host memory buffer (HMB). Accordingly, the storage controller 1240_1 can freely access the host memory buffer HMB.

In step S2130, the host 1100_1 sets an active power state based on the retention level (ie, '2') of the host memory buffer (HMB) and/or the operation mode (ie, the first mode). is selected and transmitted to the storage controller 1240_1. Here, the active power state refers to a power state in which the storage controller 1240_1 supports performing various operations including processing I/O commands.

In step S2140, the host 1100_1 transmits an I/O command to the storage controller 1240_1.

In step S2150, the storage controller 1240_1 processes the I/O command received from the host 1100_1. At this time, the storage controller 1240_1 may freely access the host memory buffer (HMB) to obtain data required for an I/O command.

In step S2160, the host 1100_1 transmits a retention recovery command to the storage controller 1240_1.

As described above, the memory system 1000B according to an embodiment of the present invention selects the operation mode of the host memory buffer (HMB) in consideration of the retention level, as well as the storage controller ( The power state of 1240_1) can be determined. Accordingly, accurate control of the storage device 1240_1 is possible, and as a result, overall performance of the memory system 1000B may be improved.

12B is a diagram illustrating an example of a command transmission operation between the host 1100_1 and the storage controller 1240_1 in the second mode (Mode2).

In step S2210, the host 1100_1 sets bits of the EHM command and the MR command to '1' and '0', respectively.

In step S2220, the host 1100_1 transmits a retention command to the storage controller 1240_1. For example, suppose the retention level is '1'. In this case, the storage controller 1240_1 selects the second mode (Mode2) as an operation mode of the host memory buffer (HMB).

In step S2230, the host 1100_1 enters the power state based on the retention level (ie, '1') and/or operation mode (ie, the second mode) of the host memory buffer (HMB). Select Non-Operational Power State (NOPS).

In step S2240, the storage controller 1240_1 retrieves frequently used data from the host memory buffer (HMB) and stores it in the storage device 1200_1.

In step S2250, the storage controller 1240_1 uses the retrieved data to perform operations allowed in a non-operating power state. For example, in a non-operating power state, the storage controller 1200_1 may perform a Persistent Memory Region (PMR) access operation, a Controller Memory Buffer (CMB) access operation, a background operation, and the like, but an I/O command processing operation can't do

At this time, if necessary, the storage controller 1240_1 may access the host memory buffer (HMB) again to retrieve more necessary data. However, since frequently used data has already been retrieved in step S2240, access to the host memory buffer HMB of the storage controller 1240_1 may be minimized.

In step S2260, the host 1100_1 transmits a retention recovery command to the storage controller 1240_1.

In step S2270, the storage controller 1240_1 updates the contents of the host memory buffer (HMB).

As described above, in the second mode (Mode2), the storage controller 1240 according to an embodiment of the present invention may operate to minimize access to the host memory buffer (HMB) where retention occurs. In addition, the host 1100_1 according to an embodiment of the present invention may cause the storage controller 1200_1 to operate in a non-operating power state.

12C is a diagram showing another example of a command transmission operation between the host 1100 and the storage controller 1240 in the second mode (Mode2).

In step S2310, the host 1100_1 sets bits of the EHM command and the MR command to '1' and '0', respectively.

In step S2320, the host 1100_1 transmits a retention command to the storage controller 1240. For example, suppose the retention level is '1'. In this case, the storage controller 1240_1 selects the second mode (Mode2) as an operation mode of the host memory buffer (HMB).

In step S2330, the host 1100_1 selects an active power state as a power state suitable for the storage controller 1200_1.

In step S2340, the storage controller 1240_1 retrieves frequently used data from the host memory buffer (HMB) and stores it in the storage device 1200_1.

In step S2350, the host 1100_1 transmits an I/O command to the storage controller 1240_1.

In step S2360, the storage controller 1240_1 processes an I/O command using the retrieved data. At this time, if necessary to process the I/O command, the storage controller 1240_1 may re-access the host memory buffer (HMB) to retrieve more necessary data. However, since frequently used data has already been retrieved in step S2340, access to the host memory buffer HMB of the storage controller 1240_1 can be minimized.

In step S2370, the host 1100_1 transmits a retention recovery command to the storage controller 1240_1.

In step S2380, the storage controller 1240_1 updates the contents of the host memory buffer (HMB).

As described above, in the second mode (Mode2), the storage controller 1240 may process an I/O command while minimizing access to the host memory buffer (HMB) where retention occurs. The host 1100_1 may select an active power state as a power state suitable for the storage controller 1200_1.

12D is a diagram showing an example of a command transmission operation between the host 1100 and the storage controller 1240 in the third mode (Mode3).

In step S2410, the host 1100_1 sets bits of the EHM command and the MR command to '1' and '0', respectively.

In step S2420, the host 1100_1 transmits a retention command to the storage controller 1240_1. For example, suppose the retention level is 'X'. In this case, the storage controller 1240 selects the third mode (Mode3).

In step S2430, the host 1100_1 determines the power state of the storage controller 1240_1 based on the retention level (ie, 'X') and/or operation mode (ie, the third mode) of the host memory buffer (HMB). to select a non-operating power state (NOPS).

In step S2440, the storage controller 1240_1 retrieves necessary data from the host memory buffer (HMB) in a non-operating power state and stores it in the storage device 1200_1.

In step S2450, the storage controller 1240_1 transmits an acknowledgment signal (ACK) notifying the host 1100_1 that collection of necessary data has been completed. After that, the storage device 1200_1 is blocked from accessing the host memory buffer HMB.

In step S2460, the storage controller 1240_1 performs an operation allowed in a non-operating power state by using the retrieved data.

In step S2470, the host 1100_1 transmits a retention recovery command to the storage controller 1240_1.

In step S2480, the storage controller 1240_1 updates the contents of the host memory buffer (HMB).

As described above, in the third mode (Mode3), the retention command may function as an option blocking access of the storage controller 1240_1 to the host memory buffer HMB. In addition, the host 1100_1 may select a non-operating power state as a power state suitable for the storage controller 1200_1.

12E is a diagram showing an example of a command transmission operation between the host 1100 and the storage controller 1240 in the third mode (Mode3).

In step S2510, the host 1100_1 sets bits of the EHM command and the MR command to '1' and '0', respectively.

In step S2520, the host 1100_1 transmits a retention command to the storage controller 1240_1. For example, suppose the retention level is 'X'. In this case, the storage controller 1240 selects the third mode (Mode3) as an operation mode of the host memory buffer (HMB).

In step S2430, the host 1100_1 determines the power state of the storage controller 1240_1 based on the retention level (ie, 'X') and/or operation mode (ie, the third mode) of the host memory buffer (HMB). to select a non-operating power state (NOPS).

In step S2540, the storage controller 1240_1 is not permitted to access the host memory buffer 1120_1. In this case, the storage controller 1240_1 may perform permitted operations in a non-operating state by using data previously stored in the storage device 1200 .

In step S2550, the host 1100_1 transmits a retention recovery command to the storage controller 1240_1.

In step S2560, the storage controller 1240_1 updates the contents stored in the host memory buffer (HMB).

As described above, in the third mode (Mode3), the storage controller 1240 is immediately blocked from accessing the host memory buffer (HMB) and operates in a non-operating power state.

Meanwhile, in the above description, the EHM command and the retention command have been described as independent three-characteristic commands. However, this is an example, and the retention command may replace the EHM command. For example, bit '1' of the EHM command may be replaced with a retention level 'X' of the retention command. In addition, bit '1' of the EHM command may be replaced with other retention levels (ie, retention levels '1', '2', etc.) except for the retention level 'X'. As a result, in the above embodiments, the EHM command may be replaced by a retention command.

Meanwhile, the above descriptions are specific examples for carrying out the present invention. In addition to the above-described embodiments, the present invention will also include embodiments that can be simply or easily changed in design. In addition, the present invention will also include techniques that can be easily modified and practiced using the embodiments. Therefore, the scope of the present invention should not be limited to the above-described embodiments and should not be defined, and should be defined by those equivalent to the claims of this invention as well as the claims to be described later.

EHM: Enable Host Memory
MR: Memory Return
HMB: Host Memory Buffer
NOPS: Non-Operational Power States
CMD: command
ADDR: address

Claims (20)

In the operating method of a memory system including a host and a storage device:
allocating a portion of a host memory included in the host as a host memory buffer for use by a controller of the storage device;
setting a set characteristic command to activate the host memory buffer;
setting a retention command including information about response speed of the host memory buffer;
selecting an operation mode of the host memory buffer based on the retention command; and
and selecting one of a plurality of power states supported by the controller based on a performance objective of an operation mode of the host memory buffer. According to claim 1,
The host selects a non-operating power state as the power state of the controller. According to claim 2,
and retrieving, by the controller, at least a portion of data stored in the host memory buffer to perform an operation permitted in the non-operating power state. According to claim 3,
The controller further comprises transmitting a confirmation signal notifying that the step of retrieving at least a portion of the data stored in the host memory buffer is completed to the host,
After the confirmation signal is transmitted, the access of the controller to the host memory buffer is not allowed. According to claim 2,
After the non-operating power state is selected, access of the controller to the host memory buffer is not allowed. According to claim 5,
The retention command functions as an option for blocking access of the controller to the host memory buffer. According to claim 1,
When the expected response time of the host memory buffer is less than a reference response time, the controller is allowed to access the host memory buffer. According to claim 7,
Where the controller is allowed to access the host memory buffer, the host selects an active power state as the power state of the controller. According to claim 1,
The host memory buffer includes at least two areas, and the retention command includes response speed information for each of the at least two areas. According to claim 1,
receiving, by the controller, a retention recovery command from the host; and
and updating data stored in the storage device to the host memory buffer. In the operating method of a memory system including a host and a storage device:
allocating a portion of a host memory included in the host as a host memory buffer for use by a controller of the storage device;
setting a set characteristic command to activate the host memory buffer;
setting a retention command including information about response speed of the host memory buffer; and
and selecting an operation mode of the host memory buffer based on the retention command. According to claim 11,
The method of operating the memory system further comprising the step of recovering at least a portion of the data stored in the host memory buffer and storing it in the storage device. According to claim 12,
The controller further comprises transmitting a confirmation signal notifying that the step of retrieving at least a portion of the data stored in the host memory buffer is completed to the host,
After the confirmation signal is transmitted, the access of the controller to the host memory buffer is not allowed. According to claim 11,
The retention command functions as an option that does not allow the controller to access the host memory buffer. According to claim 11,
The retention command includes an address and a retention level of the host memory buffer, and the retention level is generated by comparing an expected response time of the host memory buffer with at least one reference response time. According to claim 15,
The controller selects an operating mode of the host memory buffer according to the retention level included in the retention command. According to claim 15,
The host memory buffer includes at least two areas, and the retention command includes a retention level for each of the at least two areas. According to claim 11,
receiving, by the controller, a retention recovery command from the host; and
and updating data stored in the storage device to the host memory buffer. For storage devices that share the host memory of the host:
an interface for using a partial area of the host memory as a host memory buffer of the storage device; and
Storage for selecting one of the first to third modes as an operating mode for the host memory buffer based on the response speed of the host memory buffer when retention occurs, which slows down the response speed of the host memory buffer. includes a device;
When the first mode is selected, access to the host memory buffer of the storage device is allowed;
When the second mode is selected, access to the host memory buffer of the storage device is allowed, and the storage retrieves and stores frequently used data among data stored in the host memory buffer,
When the third mode is selected, access to the host memory buffer of the storage device is not allowed. According to claim 19,
While access to the host memory buffer of the storage device is not allowed in the third mode, the EHM command for activating the host memory buffer is active, and the MR command for returning the host memory buffer is inactive. A storage device that is in state.

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