KR20230063540A - High-speed decision feedback equalizer including a plurality of cascaded latches - Google Patents

Abstract

으로 표시되는 신호 De_n을 상기 제1 래치(LE₁)의 입력단에 인가하는 제1 가산기;

으로 표시되는 신호 Do_n을 상기 제1 래치(LO₁)의 입력단에 인가하는 제2 가산기; 및 상기 제1 래치(LE₁) 내지 제N 래치(LE_N) 중 짝수번째 래치(LE₂, LE₄, …)와 상기 제1 래치(LO₁) 내지 제N 래치(LO_N) 중 홀수번째 래치(LO₁, LO₃, …)의 클럭 입력단(EN)에 각각 클럭 신호(CLK)를 인가하고, 상기 제1 래치(LE₁) 내지 제N 래치(LE_N) 중 홀수번째 래치(LE₁, LE₃, …)와 상기 제1 래치(LO₁) 내지 제N 래치(LO_N) 중 짝수번째 래치(LO₂, LO₄, …)의 클럭 입력단(EN)에 각각 반전 클럭 신호(CLKB)를 인가하는 클럭 신호 생성기(CLK_GEN)를 포함하는 것을 특징으로 한다(단, X_n은 수신된 신호이며, N은 1 이상의 자연수).The present invention relates to a decision feedback equalizer. The decision feedback equalizer according to the present invention includes first latches (LE ₁ ) to N-th latches (LE _N ) connected in a cascade form; First multipliers ME 1 to Nth multipliers (ME ₁ ) to generate output signals (ME _{1_OUT} ) to output signals (ME _{N_OUT} ) by amplifying the output signals of the first latch (LE 1 ) to the Nth latch (LE _N ) _, respectively. multiplier (ME _N ); a first latch (LO ₁ ) to an N-th latch (LO _N ) connected in a cascade form; First multipliers (MO ₁ ) to N-th multipliers (MO 1 ) to generate output signals (MO _{1_OUT} ) to (MO _{N_OUT} ) by amplifying the output signals of the first to N-th latches (LO ₁ ) to (LO _N ), respectively. multiplier (MO _N );

a first adder for applying a signal De _n represented by ? to an input terminal of the first latch LE ₁ ;

a second adder for applying the signal Don _n represented by ? to an input terminal of the first latch LO ₁ ; and even-numbered latches LE ₂ , LE ₄ , ... among the first to N-th latches LE ₁ to LE _N , and odd-numbered latches among the first to N-th latches LO ₁ to LO _N . The clock signal CLK is applied to clock input terminals EN of the latches LO ₁ , LO ₃ , ..., respectively, and the odd-numbered latches LE ₁ among the first to N-th latches LE ₁ to LE _N . , LE ₃ , ...) and the clock input terminal EN of the even-numbered latches LO ₂ , LO ₄ , ... among the first latches LO ₁ to N-th latches LO _N , respectively, an inverted clock signal CLKB is provided. It is characterized in that it includes a clock signal generator (CLK_GEN) for applying (provided that X _n is a received signal and N is a natural number greater than or equal to 1).

Description

High-speed decision feedback equalizer including a plurality of latches connected in cascade form

The present invention relates to a high-speed decision-feedback equalizer including a plurality of latches connected in a cascade form. .

1 is a schematic diagram showing the distortion of a waveform. Referring to FIG. 1 , when a pulse having a length of T _b is transmitted through a LOSSY CHAMMEL (eg, a signal transmission cable, etc.), a distorted signal (x _n ) is received at the receiving end. For example, the received signal (x _n ) gradually rises from t=-T _b and reaches C ₀ (Main Cursor) at t=0 due to the low-pass filter characteristics of the lossy channel. The signal (x _n ) gradually descends from t=0 and reaches C ₁ (Post Cursor) at t=T _b and C ₂ (Post Cursor) at t=2T _b . That is, the signal (x _n ) does not reach 0 even when t=2T _b .

This phenomenon is called Inter-Symbol Interference (ISI), and ISI causes a previous data bit to affect a current data bit.

To solve ISI, a decision feedback equalizer (DFE) has been proposed.

2 is a block diagram showing a 1-tap decision feedback equalizer (1-tap DFE) according to the prior art.

Referring to FIG. 2 , the 1-tap decision feedback equalizer includes an adder 10 , a slicer 20 , a flip-flop (FF) 30 and a multiplier 40 .

As shown in FIG. 1 , the level of the signal (x _n ) received through the lossy channel is determined by the slicer 20 . The signal whose level is determined is delayed by the FF 30 and fed back through the multiplier 40. At this time, the feedback signal (d _F ) removes the post cursor of the signal (x _n ).

A more detailed description of this is as follows.

First, ignoring the influence of the initial value of the signal d _F , the signal x _n is the signal d _n . The slicer 20 removes amplitude noise of the signal d _n and outputs the signal ds _n . Here, signal d _n is substantially an analog signal due to the lossy channel, but signal ds _n is a digital signal. That is, the signal ds _n is “0” or “1”. In addition, since the signal ds _n can mean the sign of the signal d _n , ds _n =sgn(d _n ). That is, the signal ds _n may be referred to as a sign ds _n , and may have a value of “+1” or “−1”. In the following, it is assumed that ds _n =+1 or ds _n =-1.

The signal ds _n is delayed by one period by the FF 30 . That is, the FF 30 outputs a signal ds _{n-1 , which} is a signal preceding one cycle of the signal ds _n . The multiplier 40 multiplies the signal ds _n−1 by the tap coefficient C ₁ and outputs a signal d _F obtained by multiplying the signal ds n−1 by the tap coefficient C 1 . Signal d _F is negatively fed back to remove the postcursor of signal x _n .

In the 1-tap decision feedback equalizer, in order to obtain optimal performance, the sampling edge of the clock must occur at the point where the output of the adder 10 has the largest value, and the tap coefficient ( C ₁ ) must be determined.

4A is a diagram illustrating a signal d _n from which a post-cursor is partially removed. Referring to FIG. 4A , the post cursor of t=T _b is removed (that is, d _n =x _n -C ₁ x ds _n-1 ), but the post cursor of t=2T _b is not removed.

A 2-tap decision feedback equalizer is proposed to remove the postcursor of t= _2Tb .

3 is a block diagram showing a 2-tap decision feedback equalizer according to the prior art.

Referring to FIG. 3, the 2-tap decision feedback equalizer includes an adder 10, a slicer 20, flip-flops (FF) 30a and 30b, and multipliers 40a and 40b. Compared with the 1-tap decision feedback equalizer shown in Fig. 2, the 2-tap decision feedback equalizer further includes an FF 30b and a multiplier 40b.

The operation of the 2-tap decision feedback equalizer of FIG. 3 is substantially the same as that of the 1-tap decision feedback equalizer of FIG. Specifically, assuming that the rising edge of the clock occurs at a time that is a multiple of T _b , such as t = 0, T _b , 2T _b , and the sum of the delay of FF and the delay of the feedback loop is approximately T _b /2, t From =T _b /2 to t=3T _b /2, ds _n-1 =1, and from t=3T _b /2 to t=5T _b /2, ds _n-2 =1. Therefore, x _n -C ₁ ㅧds _n-1 between t=T _b /2 and t=3T _b /2, and x _n -C ₂ ㅧ between t=3T _b /2 and t=5T _b /2 ds _n-2 . As a result, a signal d _n from which the post cursor of t=T _b and the post cursor of t=2T _b shown in FIG. 4B are removed can be obtained.

As the signal transmission rate increases, the clock rate of the decision feedback equalizer must also increase. That is, a high-speed clock signal is required to receive high-speed data.

In order to obtain a high-speed clock signal, a voltage controlled oscillator (VCO) capable of generating a high-speed clock signal is required. In addition, there is a problem in that the circuit itself must also be designed to operate on a high-speed clock signal.

To solve this problem, a half-rate decision feedback equalizer that reduces the clock signal by half has been proposed.

Since the half-rate decision feedback equalizer operates according to the clock signal and the inverted clock signal, the clock speed is 1/2 compared to the full-rate decision feedback equalizer using only the clock signal.

5 is a block diagram illustrating a half-rate decision feedback equalizer according to the prior art.

Referring to FIG. 5, two flip-flops (FF) of the prior art half-rate decision feedback equalizer operate according to a clock signal (CLK) and an inverted clock signal (CLKB), respectively.

The prior art half-rate decision feedback equalizer of FIG. 5 is the same as the 2-tap full-rate decision feedback equalizer shown in FIG. 3 in that postcursor C ₁ and postcursor C ₂ are removed. The frequency of the clock signal CLK and the inverted clock signal CLKB is 1/2 of that of the clock signal CLK of the 2-tap decision feedback equalizer shown in FIG.

The decision feedback equalizer of FIG. 3 and the decision feedback equalizer of FIG. 5 will be compared and described with reference to FIGS. 6A and 6B.

6A and 6B are full-rate and half-rate timing diagrams, respectively.

Referring to FIG. 6A, the full-rate decision feedback equalizer samples the signal X _n received at each rising edge of the clock signal CLK. Therefore, Ds _n-2 =A, B, C, D, . . . is output.

On the other hand, referring to FIG. 6B , the half-rate decision feedback equalizer samples the signal X _n received at the rising edge of the clock signal CLK and the rising edge of the inverted clock signal CLKB. Here, the frequency of the clock signal CLK and the inverted clock signal CLKB of the half-rate decision feedback equalizer is 1/2 of that of the clock signal CLK of the full-rate decision feedback equalizer.

Typically, the data sampled at the rising edge of the clock signal (CLK) of the half-rate decision feedback equalizer is called even data, and the data sampled at the rising edge of the inverted clock signal (CLKB) is called odd-numbered data. It is called odd data. For example, "e" in Dse _n-2 means even-numbered data, and "o" in Dso _n-2 means odd-numbered data. Hereinafter, "e" is included in the signal name when referring to even-numbered data, and "o" is included in the signal name when referring to odd-numbered data.

Referring continuously to FIG. 6B, even data and odd data are alternately output to the output of the prior art half-rate decision feedback equalizer. Specifically, X _n =A, B, C, D, E, F, . . . If Dse _n-2 =A, C, E, . . . , Dso _n-2 =B, D, F, ... is output. That is, data before one De _n is Dso _n-2 . For example, since the data before one C is B, if De _n =C, then Dso _n-2 =B. Similarly, if Don _n =D, then Dse _n-2 =C.

If this is applied to the half-rate decision feedback equalizer of FIG. 5, it is as follows.

For example, even data sampled at the rising edge T ₁ of the clock signal CLK of FIG. 6B is C, and data required for feedback at this time are A and B. Therefore, data A and B should be prepared in a section before the rising edge T ₁ (indicated by a dotted arrow in FIG. 6B). However, referring to FIG. 6B , it can be seen that Dse _n-2 =A and Dso _n-2 =B in the section before the rising edge (T ₁ ).

Similarly, odd data sampled at the rising edge T ₂ of the inverted clock signal CLKB of FIG. 6B is D, and data required for feedback at this time are C and B. Therefore, data C and B must be prepared before the rising edge (T ₂ ). However, referring to FIG. 6B , it can be seen that Dse _n-2 =C and Dso _n-2 =B in the section before the rising edge T ₂ .

In this way, in the half-rate decision feedback equalizer according to the related art, in order for FF to sample De _n , Dse _n-2 , which is 2-bit previous data, is required. Since the post cursor (C ₂ ) is related to data 2 bits earlier, in order to remove the post cursor (C ₂ ) of even data, Dse _n-2 is multiplied by the gain C ₂ to give negative feedback to the even data side. Similarly, in order to remove the post cursor (C ₂ ) of odd data, Dso _n-2 is multiplied by gain C ₂ and returns negative to the odd data side. This is because data 2 bits prior to any even data is output from the even data side, and data 2 bits prior to any odd data is output from the odd data side.

On the other hand, since the postcursor (C ₁ ) is related to the data 1 bit earlier, in order to remove the post cursor (C ₁ ) of even data, Dso _n-2 is multiplied by the gain C ₁ and returns negative feedback to the even data side. Similarly, to remove the odd data post cursor (C ₁ ), Dse _n-2 is multiplied by the gain C ₁ and returns negative to the odd data side. This is because data 1 bit prior to any even data is output from the odd data side, and data 1 bit prior to any odd data is output from the even data side.

If the above contents are expressed as equations, they are equivalent to equations 1 and 2, respectively.

In order for the decision feedback equalizer to operate normally, data processing must be completed within one cycle (1 UI) from the rising edge of the clock signal to the next rising edge. That is, there is a time constraint that the sum of time taken to process data including feedback must be less than 1 UI. This is called timing constraint.

Factors affecting the timing constraint of the decision feedback equalizer include CK2Q delay, setup time, and feedback delay. Here, the CK2Q delay is a delay occurring in the FF, and is the time taken for data to reach the output terminal of the FF from the rising edge of the clock signal in a state in which data has arrived at the input terminal of the FF. In addition, input data must arrive before the rising edge of the clock signal on which sampling is performed, and this time margin is referred to as setup time. In other words, it is the minimum time from when the input data is stable to the rising edge of the clock signal. The feedback delay is the time it takes for the output of FF to be fed back.

First, in the full-rate decision feedback equalizer according to the prior art shown in FIG. 3, in order for the FF to sample d _n , ds _n- 1, which is one bit previous data, is required. Therefore, in the full-rate decision feedback equalizer according to the prior art, the CK2Q delay (t _CK2Q ) is the time taken from the rising edge of the clock signal to the output of ds _n-1 when ds _n reaches the input terminal of FF. , the feedback delay (t _FB ) is the time it takes for the output ds _n-1 of the FF to be fed back and reach ds _n . Since the setup time (t _SETUP.FF ) is constant, the timing constraint for the normal operation of the decision feedback equalizer is as follows.

Here, 1 UI is the time from the rising edge of the clock signal CLK to the next rising edge, that is, 1 clock signal.

In the half-rate decision feedback equalizer shown in FIG. 5, the CK2Q delay (t _CK2Q ) is the time taken from the rising edge of the clock signal to the output of Dse _n-2 when De _n reaches the input terminal of FF, The feedback delay (t _FB ) is the time it takes for the feedback output Dse _n-2 of FF to reach Don _n through the multiplier and adder. Since the setup time (t _SETUP.FF ) is constant, the timing constraint for the normal operation of the half-rate decision feedback equalizer is as follows.

Here, 1 UI is the time from the rising edge to the falling edge of the clock signal CLK or the inverted clock signal CLKB, or the time from the falling edge to the rising edge, that is, 1/2 of 1 clock signal.

According to Equations 3 and 4, the timing constraints of the full-rate decision feedback equalizer and the half-rate decision feedback equalizer are the same. That is, there is a problem that the timing constraint is not relieved even if the half-rate decision feedback equalizer is used. In order to ensure normal operation of the decision feedback equalizer while maintaining the clock speed, it is necessary to relax the timing constraint.

Patent Document: US Patent Publication No. 2008-0310495

Paper: Low-Power CMOS Equalizer Design for 20-Gb/s Systems, IEEE Journal of Solid-State Circuits (Volume: 46, Issue: 6, June 2011) by Sameh Ibrahim, et al. Paper: Design Techniques for a 66 Gb/s 46 mW 3-Tap Decision Feedback Equalizer in 65 nm CMOS, IEEE Journal of Solid-State Circuits ( Volume: 48, Issue: 12, Dec. 2013) by Yue Lu, et al.

An object of the present invention is to provide a decision feedback equalizer capable of relieving timing constraints by using a plurality of latches connected in a cascade form.

으로 표시되는 신호 De_n을 상기 제1 래치(LE₁)의 입력단에 인가하는 제1 가산기;

으로 표시되는 신호 Do_n을 상기 제1 래치(LO₁)의 입력단에 인가하는 제2 가산기; 및 상기 제1 래치(LE₁) 내지 제N 래치(LE_N) 중 짝수번째 래치(LE₂, LE₄, …)와 상기 제1 래치(LO₁) 내지 제N 래치(LO_N) 중 홀수번째 래치(LO₁, LO₃, …)의 클럭 입력단(EN)에 각각 클럭 신호(CLK)를 인가하고, 상기 제1 래치(LE₁) 내지 제N 래치(LE_N) 중 홀수번째 래치(LE₁, LE₃, …)와 상기 제1 래치(LO₁) 내지 제N 래치(LO_N) 중 짝수번째 래치(LO₂, LO₄, …)의 클럭 입력단(EN)에 각각 반전 클럭 신호(CLKB)를 인가하는 클럭 신호 생성기(CLK_GEN)를 포함하는 것을 특징으로 한다(단, X_n은 수신된 신호이며, N은 1 이상의 자연수).The decision feedback equalizer according to the present invention includes first latches (LE ₁ ) to N-th latches (LE _N ) connected in a cascade form; First multipliers ME 1 to Nth multipliers (ME ₁ ) to generate output signals (ME _{1_OUT} ) to output signals (ME _{N_OUT} ) by amplifying the output signals of the first latch (LE 1 ) to the Nth latch (LE _N ) _, respectively. multiplier (ME _N ); a first latch (LO ₁ ) to an N-th latch (LO _N ) connected in a cascade form; First multipliers (MO ₁ ) to N-th multipliers (MO 1 ) to generate output signals (MO _{1_OUT} ) to (MO _{N_OUT} ) by amplifying the output signals of the first to N-th latches (LO ₁ ) to (LO _N ), respectively. multiplier (MO _N );

a first adder for applying a signal De _n represented by ? to an input terminal of the first latch LE ₁ ;

a second adder for applying the signal Don _n represented by ? to an input terminal of the first latch LO ₁ ; and even-numbered latches LE ₂ , LE ₄ , ... among the first to N-th latches LE ₁ to LE _N , and odd-numbered latches among the first to N-th latches LO ₁ to LO _N . The clock signal CLK is applied to clock input terminals EN of the latches LO ₁ , LO ₃ , ..., respectively, and the odd-numbered latches LE ₁ among the first to N-th latches LE ₁ to LE _N . , LE ₃ , ...) and the clock input terminal EN of the even-numbered latches LO ₂ , LO ₄ , ... among the first latches LO ₁ to N-th latches LO _N , respectively, an inverted clock signal CLKB is provided. It is characterized in that it includes a clock signal generator (CLK_GEN) for applying (provided that X _n is a received signal and N is a natural number greater than or equal to 1).

The first latch (LE ₁ ) to the Nth latch (LE _N ) and the first latch (LO ₁ ) to the Nth latch (LO _N ) each have an input terminal (D), a clock input terminal (EN), and an output terminal (Q). It is preferable to include a D-latch that includes.

The output terminal (Q) of the Kth latch (LE _K ), which is any one of the first to Nth latches (LE _N ) connected in a cascade form, is the ( _Kth ) adjacent to the Kth latch (LE _K ). +1) It is electrically connected to the input terminal (D) of the latch (LE _(K+1) ), and the clocks of the Kth latch (LE _K ) and the (K+1)th latch (LE _(K+1) ) Preferably, the clock signal CLK and the inverted clock signal CLKB are respectively applied to the input terminal EN (provided that N is a natural number equal to or greater than 3 and K satisfies 1≤K≤(N-1)). Even).

The output terminal ( _Q ) of the Kth latch (LO K ), which is any one of the first to Nth latches (LO _N ) connected in a cascade form, is the ( _Kth ) adjacent to the Kth latch (LO _K ). +1) It is electrically connected to the input terminal (D) of the latch (LO _(K+1) ), and the clocks of the Kth latch (LO _K ) and the (K+1)th latch (LO _(K+1) ) Preferably, the inverted clock signal CLKB and the clock signal CLK are respectively applied to the input terminal EN.

The output terminal (Q) of the Kth latch (LE _K ), which is any one of the first to Nth latches (LE _N ) connected in a cascade form, is the ( _Kth ) adjacent to the Kth latch (LE _K ). +1) It is electrically connected to the input terminal (D) of the latch (LE _(K+1) ), and the clocks of the Kth latch (LE _K ) and the (K+1)th latch (LE _(K+1) ) Preferably, the inverted clock signal CLKB and the clock signal CLK are respectively applied to the input terminal EN (N is a natural number equal to or greater than 2, and K satisfies 1≤K≤(N-1). odd number).

The output terminal ( _Q ) of the Kth latch (LO K ), which is any one of the first to Nth latches (LO _N ) connected in a cascade form, is the ( _Kth ) adjacent to the Kth latch (LO _K ). +1) It is electrically connected to the input terminal (D) of the latch (LO _(K+1) ), and the clocks of the Kth latch (LO _K ) and the (K+1)th latch (LO _(K+1) ) Preferably, the clock signal CLK and the inverted clock signal CLKB are respectively applied to the input terminal EN.

으로 표시되는 신호(De_n)를 상기 제1 래치(LE₁)의 입력단(D)에 인가하는 제1 가산기;

으로 표시되는 신호(Do_n)를 상기 제1 래치(LO₁)의 입력단(D)에 인가하는 제2 가산기; 및 상기 제1 래치(LO₁)의 클럭 입력단(EN)에 클럭 신호(CLK)를 인가하고, 상기 제1 래치(LE₁)의 클럭 입력단(EN)에 반전 클럭 신호(CLKB)를 인가하는 클럭 신호 생성기(CLK_GEN)를 포함할 수 있다.N=1, and the decision feedback equalizer according to the present invention includes a first latch (LE ₁ ) and a first latch (LO ₁ ); A first multiplier configured to generate output signals ME _{1_OUT} and MO _{1_OUT} by amplifying the output signals Dse _n-1 and Dso _n-1 of the first latch LE ₁ and the first latch LO ₁ , respectively. (ME ₁ ) and a first multiplier (MO ₁ );

a first adder applying a signal (De _n ) represented by ? to an input terminal (D) of the first latch (LE ₁ );

a second adder for applying the signal _Don represented by ? to the input terminal D of the first latch LO ₁ ; and a clock which applies a clock signal CLK to the clock input terminal EN of the first latch LO ₁ and applies an inverted clock signal CLKB to the clock input terminal EN of the first latch LE ₁ . A signal generator (CLK_GEN) may be included.

으로 표시되는 신호(De_n)를 상기 제1 래치(LE₁)의 입력단(D)에 인가하는 제1 가산기;

으로 표시되는 신호(Do_n)를 상기 제1 래치(LO₁)의 입력단(D)에 인가하는 제2 가산기; 및 상기 제2 래치(LE₂)와 상기 제1 래치(LO₁)의 클럭 입력단(EN)에 각각 클럭 신호(CLK)를 인가하고, 상기 제1 래치(LE₁)와 제2 래치(LO₂)의 클럭 입력단(EN)에 각각 반전 클럭 신호(CLKB)를 인가하는 클럭 신호 생성기(CLK_GEN)를 포함할 수 있다.N=2, and the decision feedback equalizer according to the present invention includes a first latch (LE ₁ ) and a first latch (LO ₁ ); The second latch LE ₂ and the second latch LE ₂ to which the output signals Dse _n-1 and Dso _n-1 of the first latch LE 1 and the first latch LO ₁ are respectively applied to their input terminals D. latch (LO ₂ ); A first step configured to generate output signals ME 1_OUT and ME _{2_OUT} by amplifying output signals _{Dse n-1} and Dse _n-2 of the first latch LE ₁ and the second latch LE ₂ , respectively. a multiplier (ME ₁ ) and a second multiplier (ME ₂ ); A first step generating output signals MO _{1_OUT} and MO _{2_OUT} by amplifying output signals Dso _n-1 and Dso _{n-2 of} the first latch LO 1 and the second latch LO ₂ , respectively. a multiplier (MO ₁ ) and a second multiplier (MO ₂ );

a first adder applying a signal (De _n ) represented by ? to an input terminal (D) of the first latch (LE ₁ );

a second adder for applying the signal _Don represented by ? to the input terminal D of the first latch LO ₁ ; and applying a clock signal CLK to clock input terminals EN of the second latch LE ₂ and the first latch LO ₁ , respectively, and applying the clock signal CLK to the first latch LE ₁ and the second latch LO _{2 .} ) may include a clock signal generator (CLK_GEN) for applying an inverted clock signal (CLKB) to the clock input terminal (EN).

으로 표시되는 신호(De_n)를 상기 제1 래치(LE₁)의 입력단(D)에 인가하는 제1 가산기;

으로 표시되는 신호(Do_n)를 상기 제1 래치(LO₁)의 입력단(D)에 인가하는 제2 가산기; 및 상기 제2 래치(LE₂), 상기 제1 래치(LO₁) 및 상기 제3 래치(LO₃)의 클럭 입력단(EN)에 각각 클럭 신호(CLK)를 인가하고, 상기 제1 래치(LE₁), 상기 제3 래치(LE₃) 및 제2 래치(LO₂)의 클럭 입력단(EN)에 각각 반전 클럭 신호(CLKB)를 인가하는 클럭 신호 생성기(CLK_GEN)를 포함할 수 있다.N=3, and the decision feedback equalizer according to the present invention includes a first latch (LE ₁ ) and a first latch (LO ₁ ); The second latch LE ₂ and the second latch LE ₂ to which the output signals Dse _n-1 and Dso _n-1 of the first latch LE 1 and the first latch LO ₁ are respectively applied to their input terminals D. latch (LO ₂ ); The third latch LE ₃ and the third latch LE ₃ to which the output signals Dse _n-2 and Dso _n-2 of the second latch LE 2 and the second latch LO ₂ are respectively applied to their input terminals D. latch (LO ₃ ); The output signals Dse n- ₁ , Dse _{n-2 ,} and Dse n-3 of the first latch LE 1 , the second latch LE ₂ , and the _third latch _{LE 3} are amplified and output. a first multiplier (ME _{1 )} , a second multiplier (ME ₂ ), and a third multiplier (ME ₃ ) generating signals (ME _{1_OUT} , ME _{2_OUT} , and ME _{3_OUT} ), respectively; The output signals Dso n- ₁ , Dso _{n- 2} , and Dso n- ₃ of the first latch LO 1 , the second latch LO ₂ , and the third latch _{LO 3} are amplified and output, respectively. a first multiplier (MO _{1 )} , a second multiplier (MO ₂ ), and a third multiplier (MO ₃ ) generating signals (MO _{1_OUT} , MO _{2_OUT} , and MO _{3_OUT} ), respectively;

a first adder applying a signal (De _n ) represented by ? to an input terminal (D) of the first latch (LE ₁ );

a second adder for applying the signal _Don represented by ? to the input terminal D of the first latch LO ₁ ; and applying a clock signal CLK to clock input terminals EN of the second latch LE ₂ , the first latch LO ₁ , and the third latch LO ₃ , respectively, and applying the clock signal CLK to the first latch LE. ₁ ), and a clock signal generator CLK_GEN for applying an inverted clock signal CLKB to clock input terminals EN of the third latch LE ₃ and the second latch LO ₂ .

으로 표시되는 신호(De_n)를 상기 제1 래치(LE₁)의 입력단(D)에 인가하는 제1 가산기;

으로 표시되는 신호(Do_n)를 상기 제1 래치(LO₁)의 입력단(D)에 인가하는 제2 가산기; 및 상기 제2 래치(LE₂), 상기 제4 래치(LE₄), 상기 제1 래치(LO₁) 및 상기 제3 래치(LO₃)의 클럭 입력단(EN)에 각각 클럭 신호(CLK)를 인가하고, 상기 제1 래치(LE₁), 상기 제3 래치(LE₃), 제2 래치(LO₂) 및 제4 래치(LO₄)의 클럭 입력단(EN)에 각각 반전 클럭 신호(CLKB)를 인가하는 클럭 신호 생성기(CLK_GEN)를 포함할 수 있다.N=4, and the decision feedback equalizer according to the present invention includes a first latch (LE ₁ ) and a first latch (LO ₁ ); The second latch LE ₂ and the second latch LE ₂ to which the output signals Dse _n-1 and Dso _n-1 of the first latch LE 1 and the first latch LO ₁ are respectively applied to their input terminals D. latch (LO ₂ ); The third latch LE ₃ and the third latch LE ₃ to which the output signals Dse _n-2 and Dso _n-2 of the second latch LE 2 and the second latch LO ₂ are respectively applied to their input terminals D. latch (LO ₃ ); The fourth latch LE ₄ and the fourth latch LE ₄ to which the output signals Dse _n-3 and Dso _n-3 of the third latch LE 3 and LO ₃ are respectively applied to their input terminals D. latch (LO ₄ ); Output signals Dse n− ₁ , Dse _n− 2 _{, and} Dse of the first latch LE 1 , the second latch LE ₂ , the third latch LE ₃ , and the fourth latch LE ₄ A first multiplier (ME ₁ ), a second multiplier (ME 2 ), and a third multiplier (ME ₁ ) generate output signals (ME _{1_OUT} , ME _{2_OUT} , ME _{3_OUT} , ME _{4_OUT} ) by respectively amplifying n- ₃ and Dse _n-4 ). a multiplier (ME ₃ ) and a fourth multiplier (ME ₄ ); Output signals Dso n- ₁ , Dso _n- 2 _{, and} Dso of the first latch LO 1 , the second latch LO ₂ , the third latch LO ₃ , and the fourth latch LO ₄ . _n-3 , Dso _n-4 ) to generate output signals MO _{1_OUT} , MO _{2_OUT} , MO _{3_OUT} MO _{4_OUT} ), respectively, a first multiplier (MO ₁ ), a second multiplier (MO ₂ ), and a third multiplier ( MO ₃ ) and a fourth multiplier (MO ₄ );

a first adder applying a signal (De _n ) represented by ? to an input terminal (D) of the first latch (LE ₁ );

a second adder for applying the signal _Don represented by ? to the input terminal D of the first latch LO ₁ ; and applying a clock signal CLK to clock input terminals EN of the second latch LE ₂ , the fourth latch LE ₄ , the first latch LO ₁ , and the third latch LO ₃ , respectively. and an inverted clock signal (CLKB) to clock input terminals (EN) of the first latch (LE ₁ ), the third latch (LE ₃ ), the second latch (LO ₂ ) and the fourth latch (LO ₄ ), respectively. It may include a clock signal generator (CLK_GEN) for applying.

The decision feedback equalizer according to the present invention has the following advantages.

(1) The decision feedback equalizer according to the present invention can process high-speed signals precisely because timing constraints are alleviated compared to the prior art half-rate decision feedback equalizer.

(2) The decision feedback equalizer according to the present invention can freely configure an N-tap decision feedback equalizer using a latch.

1 is a schematic diagram showing distortion of a waveform;
2 is a block diagram illustrating a full rate 1-tap decision feedback equalizer according to the prior art;
3 is a block diagram illustrating a full rate 2-tap decision feedback equalizer according to the prior art;
4A and 4B are diagrams illustrating a signal d _n from which a post-cursor has been removed, respectively.
5 is a block diagram illustrating a prior art half-rate decision feedback equalizer;
6A and 6B are full-rate and half-rate timing diagrams, respectively.
7A and 7B are block diagrams illustrating latches included in the decision feedback equalizer according to the present invention.
8A and 8B are block diagrams illustrating a decision feedback equalizer in accordance with the present invention.
9 is a block diagram illustrating a decision feedback equalizer according to the present invention when N=1;
Fig. 10 is a waveform diagram of the decision feedback equalizer according to the present invention shown in Fig. 9;
11 is a block diagram illustrating a decision feedback equalizer according to the present invention when N=2;
Fig. 12 is a waveform diagram of the decision feedback equalizer according to the present invention shown in Fig. 11;
13A and 13B are waveform diagrams showing timing constraints of the half-rate decision feedback equalizer according to the prior art shown in FIG. 5 and the decision feedback equalizer according to the present invention shown in FIG. 11, respectively.
14 is a block diagram illustrating a decision feedback equalizer according to the present invention when N=3;
Fig. 15 is a waveform diagram of the decision feedback equalizer according to the present invention shown in Fig. 14;
16 is a block diagram illustrating a decision feedback equalizer according to the present invention when N=4;
Fig. 17 is a waveform diagram of the decision feedback equalizer according to the present invention shown in Fig. 16;

Hereinafter, an adaptive tap coefficient adjusting device for a decision feedback equalizer according to the present invention will be described in detail with reference to the accompanying drawings.

7A and 7B are diagrams illustrating latches included in the decision feedback equalizer according to the present invention, and are block diagrams showing a data latch (or D-latch).

The latch shown in Figure 7a includes one inverter, two AND gates and two NOR gates. Referring to FIG. 7A , the latch includes a data input terminal (D), a clock input terminal (EN), and a data output terminal (Q).

The latch shown in Figure 7b includes one inverter and four NAND gates. Referring to FIG. 7B , the latch includes a data input terminal (D), a clock input terminal (EN), and a data output terminal (Q).

The latch shown in FIGS. 7A and 7B conforms to the truth table of Table 1 below.

D EN Q 0 One 0 One One One 0 0 stored value One 0 stored value

According to the truth table of Table 1, the latch outputs the input value as it is (pass-through) when the clock signal is High, and outputs the stored value when the clock signal is Low.

The latch shown in FIGS. 7A and 7B is an example of a latch constituting the decision feedback equalizer according to the present invention described below. The latch constituting the decision feedback equalizer according to the present invention has the configuration shown in FIGS. 7A and 7B not limited to That is, a latch that includes a data input terminal (D), a clock input terminal (EN) and a data output terminal (Q) and follows the truth table of Table 1 can be used as a latch constituting the decision feedback equalizer according to the present invention.

Hereinafter, “latch” refers to a latch illustrated in FIGS. 7A and 7B or a latch conforming to the truth table of Table 1.

8A and 8B are block diagrams illustrating a decision feedback equalizer according to the present invention, respectively showing a first embodiment in which N is an odd natural number and a second embodiment in which N is an even natural number.

Hereinafter, the decision feedback equalizer according to the first embodiment of the present invention will be described in detail.

Referring to FIG. 8A , the decision feedback equalizer 1000O according to the first embodiment of the present invention includes first latches LE ₁ to N th latches LE _N ; a first latch (LO ₁ ) to an Nth latch (LO _N ); clock signal generator (CLK_GEN); a first multiplier (ME ₁ ) to an Nth multiplier (ME _N ); a first multiplier (MO ₁ ) to an Nth multiplier (MO _N ); a first adder (SUM ₁ ); and a second adder (SUM ₂ ). Here, N is an odd natural number greater than or equal to 1.

The first latch LE ₁ to the Nth latch LE _N are connected in a cascade form. Here, the "cascade form" means that the output terminal (Q) of the first latch (LE ₁ ) is electrically connected to the input terminal (D) of the second latch (LE ₂ ), and the output terminal (Q) of the second latch (LE ₃ ) This means that it is connected to the input terminal (D) of the third latch (LE ₃ ). That is, any latch among the first to Nth latches (LE ₁ ) to the Nth latch (LE _N ) is referred to as the Kth latch (LE _K ), and a latch at the next stage adjacent to the Kth latch (LE _K ) is the first (K+ 1) If it is a latch (LE _(K+1) ), the "cascade form" is that the output terminal (Q) of the Kth latch (LE _{K )} is the input terminal ( D) (however, K is a natural number that satisfies 1≤K≤(N-1)).

Similarly, the first latch LO ₁ to the Nth latch LO _N are connected in a cascade form. Here, the "cascade form" means that the output terminal (Q) of the first latch (LO ₁ ) is electrically connected to the input terminal (D) of the second latch (LO ₂ ), and the output terminal (Q) of the second latch (LO ₃ ) This means that it is connected to the input terminal (D) of the third latch (LO ₃ ). That is, any latch among the first to Nth latches LO ₁ to LO _N is referred to as the K-th latch LO _K , and a latch next to the K-th latch LO _K is referred to as the first (K+ 1) If it is a latch (LO _(K+1) ), the "cascade form" is that the output terminal (Q) of the Kth latch (LO _K ) is the input terminal of the (K+1)th latch (LO _{(K+1) )} D) (however, K is a natural number that satisfies 1≤K≤(N-1)).

The clock signal generator CLK_GEN outputs a clock signal CLK to clock input terminals EN of the first latch LE ₁ to the Nth latch _LEN and the first latch LO ₁ to the Nth latch LO _N . Alternatively, the inverted clock signal CLKB is applied.

Specifically, the clock signal generator CLK_GEN includes the even-numbered latches LE ₂ , LE ₄ , ..., LE _N-1 and the first latch _LO among the first latches LE ₁ to the N-th latches LE N . The clock signal CLK is applied to the clock _input terminals EN of the odd-numbered latches LO ₁ , LO ₃ , ..., LO _N among the 1) to N-th latches LO _N , respectively, and the first latch LE ₁ Odd-numbered latches (LE ₁ , LE ₃ , ..., LE _N ) among the to N-th latches (LE _N ) and even-numbered latches (LO ₂ , _{LO 4 )} among the first latches (LO 1 ) to the N-th latches (LO _N ) , ..., the inverted clock signal (CLKB) is applied to the clock input terminal (EN) of LO _N-1, respectively. Therefore, even-numbered latches LE ₂ , LE ₄ , ..., LE _{N−1 among} the first latches LE 1 to N th latches LE _N and the first latches LO ₁ to N th latches LO _N ), the odd-numbered latches LO ₁ , LO ₃ , ..., LO _N operate when the clock signal CLK is high, and the odd-numbered latches among the first to Nth latches LE ₁ to LE _N operate. The even-numbered latches (LO ₂ , LO ₄ , ..., LO _{N −1} ) among the th latch (LE 1 , LE _{3 ,} …, LE _N ) and the first latch (LO 1 ) to the N th latch (LO _N ) are inverted. It operates when the clock signal CLKB is high (or when the clock signal CLK is low).

The first multiplier ME ₁ to the Nth multiplier ME _N are output signals Dse _n-1 , Dse _n-2 , ..., Dse _n- of the first latch LE ₁ to the Nth latch LE _N . _(N-1) , Dse _nN ) are amplified to generate output signals (ME _{1_OUT} , ME _{2_OUT} , …, ME _{(N-1)_OUT} , ME _{N_OUT} ), respectively.

Specifically, the first multiplier ME ₁ to the Nth multiplier ME _N are output signals Dse _{n-1 ,} Dse _{n -2} , . , Dse _n-(N-1) , Dse _nN ) is amplified according to the gain (C ₁ , C ₂ , …, C _N ), and output signals (ME _{1_OUT} , ME _{2_OUT} , …, ME _{(N-1)_OUT} , ME _{N_OUT} ) respectively. That is, ME _{1_OUT} =C ₁ ㅧDse _n-1 , ME _{2_OUT} =C ₂ ㅧDse _n-2 , . , ME _{(N-1)_OUT} =C _N-1 ㅧDse _n-(N-1) , ME _{N_OUT} =C _N ㅧDse _nN .

The output signals (ME _{1_OUT} , ME _{2_OUT} , ..., ME _{(N-1)_OUT} , ME _{N_OUT} ) are negatively fed back to the first adder (SUM ₁ ) or the second adder (SUM ₂ ).

8A, the K-th latch (LE _K ) as the K-th latch, the K-th multiplier (ME _K ) as the K-th latch, and the (K+1)-th latch (LE (K+1 _{)) as the (K+1)-th} latch , the (K+1)th multiplier ME _{(K+1) , which is the (K+1)th} multiplier, is shown. Here, K is any even number that satisfies 1≤K≤(N-1). That is, the K-th latch (LE _K ) is an arbitrary even-numbered latch among the first latch (LE ₁ ) to the N-th latch (LE _N ). Since K is an even number, the K th multiplier (ME _K ) amplifies the output signal (Dse _nK ) of the K th latch (LE _K ) by the gain (C _K ), and converts the output signal (ME _{K_OUT} ) to the first adder (SUM ₁ ), and the (K+1)th multiplier ME _(K+1) is the output signal Dse _n- (K+1) of the ( _{K+1)th latch LE (K+1)} ) The output signal (ME ( _{K+1 )_OUT ) obtained by amplifying by the gain (C K+1 )} is negatively fed back to the second adder (SUM ₂ ). Since K is an even number, the clock signal CLK is applied to the Kth latch LE _K , and the inverted clock signal CLKB is applied to the (K+1)th latch LE _(K+1 ) . 8A illustrates a case where K and N are even and odd numbers, respectively, but is not limited thereto. For example, K and N may both be odd numbers.

The first multiplier MO ₁ to the Nth multiplier MO _N are output signals Dso _n-1 , Dso _n-2 , ..., Dso _n- of the first latch LO ₁ to the Nth latch LO _N . _(N-1) , Dso _nN ) are amplified, respectively, to generate output signals (MO _{1_OUT} , MO _{2_OUT} , ..., MO _{(N-1)_OUT} , MO _{N_OUT} ), respectively.

Specifically, the first multiplier MO ₁ to the Nth multiplier MO _N are output signals Dso _n-1 , Dso _n-2 , . . . of the first latch LO ₁ to the Nth latch LO _N . , Dso _n-(N-1) , Dso _nN ) are amplified according to the gains (C ₁ , C ₂ , …, C _N-1 , C _N ), and output signals (MO _{1_OUT} , MO _{2_OUT} , …, MO _{(N -1)_OUT} , MO _{N_OUT} ) are created respectively. That is, MO _{1_OUT} =C ₁ ㅧDso _n-1 , MO _{2_OUT} =C ₂ ㅧDso _n-2 , . , MO _{(N-1)_OUT} =C _N-1 ㅧDso _n-(N-1) , MO _{N_OUT} =C _N ㅧDso _nN .

The output signals (MO _{1_OUT} , MO _{2_OUT} , ..., MO _{(N-1)_OUT} , MO _{N_OUT} ) are negatively fed back to the first adder (SUM ₁ ) or the second adder (SUM ₂ ).

8A, the K-th latch (LO _K ), the K-th latch (MO _K ), the (K+1)-th latch (K+1) latch (LO _(K+1) ) , the (K+1)th multiplier MO (K+1) , which is the _(K+1)th multiplier, is shown. As described above, K is any even number that satisfies 1≤K≤(N-1). That is, the K-th latch LO _K is an arbitrary even-numbered latch among the first to N-th latches LO ₁ to LO _N . Therefore, the Kth multiplier MO _K amplifies the output signal Dso _nK of the Kth latch LO _K by the gain C _K and adds the output signal MO _{K_OUT} obtained by the second adder SUM ₂ feedback, and the (K+1)th multiplier MO _(K+1 ) converts the output signal Dso _n-( K+1) of the ( _{K+1)th latch LO (} K+1) to a gain ( The output signal (MO _{(K+1)_OUT} ) obtained by amplifying by C _K+1 ) is negatively fed back to the first adder (SUM ₁ ). Since K is an even number, the inverted clock signal CLKB is applied to the Kth latch LO _K , and the clock signal CLK is applied to the (K+1)th latch LO _(K+1) . 8A illustrates a case where K and N are even and odd numbers, respectively, but is not limited thereto. For example, K and N may both be odd numbers.

The first adder SUM ₁ applies a signal De _n , which is a difference between the received signal X _n and the feedback output signal of the multiplier, to the input terminal D of the first latch LE ₁ .

Specifically, as shown in FIG. 8A, the output of even-numbered multipliers (ME ₂ , ME ₄ , ME ₆ , _... , ME _N-1 ) among the first multipliers ME 1 to N th multipliers ME _N . Among the signals ME _{2_OUT} , ME _{4_OUT} , ME _{6_OUT} ,..., ME _{(N-1)_OUT} ) and the first multiplier MO ₁ to the Nth multiplier MO _N , the odd-numbered multipliers MO ₁ , MO ₃ , MO ₅ , …, MO _N ) output signals (MO _{1_OUT} , MO _{3_OUT} , MO _{5_OUT} , …, MO _{N_OUT} ) are negatively fed back to the first adder (SUM ₁ ).

That is, as shown in FIG. 8A , the first adder SUM ₁ applies the signal De _n according to Equation 5 below to the input terminal of the first latch LE ₁ .

The second adder SUM ₂ applies a signal Don _n , which is a difference between the received signal X _n and the feedback output signal of the multiplier, to the input terminal D of the first latch LO ₁ .

Specifically, as shown in FIG. 8A, the output signals of odd-numbered multipliers ( _{ME 1 ,} ME ₃ , ME ₅ , ..., ME _N ) among the first multipliers ME 1 to N th multipliers ME _N ( ME _{1_OUT} , ME _{3_OUT} , ME _{4_OUT} ,…, ME _{N_OUT} ) and the even-numbered multipliers (MO ₂ , MO ₄ , MO ₆ , …, MO _N - ₁ ) among the first multipliers (MO ₁ ) to the N-th multipliers (MO N ) ) output signals (MO _{2_OUT} , MO _{4_OUT} , MO _{6_OUT} ,..., MO _{(N-1)_OUT} ) are negatively fed back to the second adder (SUM ₂ ).

That is, as shown in FIG. 8A , the second adder SUM ₂ applies the signal _Don according to Equation 6 below to the input terminal of the first latch LO ₁ .

Since FIG. 8A shows a decision feedback equalizer when N is an odd number, the signal (De _n ) of Equation 5 and the signal (Don _n ) of Equation 6 are expressed as Equations 7 and 8, respectively. .

Hereinafter, a decision feedback equalizer according to a second embodiment of the present invention will be described in detail.

Referring to FIG. 8B , the decision feedback equalizer 1000E according to the second embodiment of the present invention includes first latches LE ₁ to N th latches LE _N ; a first latch (LO ₁ ) to an Nth latch (LO _N ); clock signal generator (CLK_GEN); a first multiplier (ME ₁ ) to an Nth multiplier (ME _N ); a first multiplier (MO ₁ ) to an Nth multiplier (MO _N ); a first adder; and a second adder. Here, N is an even natural number equal to or greater than 1.

The first latch LE ₁ to the Nth latch LE _N are connected in a cascade form.

Similarly, the first latch LO ₁ to the Nth latch LO _N are connected in a cascade form. The first latch (LE ₁ ) to the N-th latch (LE _N ) and the first latch (LO ₁ ) to the N-th latch (LO _N ) of the decision feedback equalizer 1000E according to the second embodiment of the present invention are Since it is the same as that of Example 1, detailed description is omitted.

The clock signal generator CLK_GEN outputs a clock signal CLK to clock input terminals EN of the first latch LE ₁ to the Nth latch _LEN and the first latch LO ₁ to the Nth latch LO _N . Alternatively, the inverted clock signal CLKB is applied.

Specifically, the clock signal generator CLK_GEN includes the even-numbered latches LE ₂ , LE ₄ , ..., _{LE N and} the first latch LO ₁ among the first latches _LE 1 to the N-th latches LE N . The clock signal CLK is applied to the clock input terminals EN of the odd-numbered latches LO ₁ , LO ₃ , ..., LO _N−1 among the _through Nth latches LO N , respectively, and the first latch LE ₁ Odd-numbered latches LE ₁ , LE ₃ , ..., LE _N−1 among _the to Nth latches LE N and even-numbered latches LO ₂ , among the first latches LO ₁ to the N-th latches LO _N The inverted clock signal CLKB is applied to clock input terminals EN of LO ₄ , ..., LO _N , respectively. Therefore, even-numbered latches LE ₂ , LE ₄ , ..., LE _N among the first latches LE ₁ to N th latches _{LE N} and among the first latches LO ₁ to N th latches LO _N The odd-numbered latches LO ₁ , LO ₃ , ..., LO _N-1 operate when the clock signal CLK is high, and the odd number among the first to N-th latches LE ₁ to LE _N . The even-numbered latches (LO ₂ , LO 4 , ..., LO _N ) among the th latch ₍ LE 1 , LE ₃ , ..., LE _N-1 ) and the first latch (LO ₁ ) to the N-th latch ₍ LO _N ) are inverted. It operates when the clock signal CLKB is high (or when the clock signal CLK is low).

The first multiplier ME ₁ to the Nth multiplier ME _N are output signals Dse _n-1 , Dse _n-2 , ..., Dse _n- of the first latch LE ₁ to the Nth latch LE _N . _(N-1) , Dse _nN ) are amplified to generate output signals (ME _{1_OUT} , ME _{2_OUT} , …, ME _{(N-1)_OUT} , ME _{N_OUT} ), respectively.

Specifically, the first multiplier ME ₁ to the Nth multiplier ME _N are output signals Dse _{n-1 ,} Dse _{n -2} , . , Dse _n-(N-1) , Dse _nN ) is amplified according to the gain (C ₁ , C ₂ , …, C _N ), and output signals (ME _{1_OUT} , ME _{2_OUT} , …, ME _{(N-1)_OUT} , ME _{N_OUT} ) respectively. That is, ME _{1_OUT} =C ₁ ㅧDse _n-1 , ME _{2_OUT} =C ₂ ㅧDse _n-2 , . , ME _{(N-1)_OUT} =C _N-1 ㅧDse _n-(N-1) , ME _{N_OUT} =C _N ㅧDse _nN .

The output signals (ME _{1_OUT} , ME _{2_OUT} , ..., ME _{(N-1)_OUT} , ME _{N_OUT} ) are negatively fed back to the first adder (SUM ₁ ) or the second adder (SUM ₂ ).

8B, the K-th latch (LE _K ) as the K-th latch, the K-th multiplier (ME _K ) as the K-th multiplier, and the (K+1)-th latch (LE (K+1) _{) as the (K+1)-th} latch , the (K+1)th multiplier ME _{(K+1) , which is the (K+1)th} multiplier, is shown. Here, K is any odd number that satisfies 1≤K≤(N-1). That is, the K-th latch (LE _K ) is an arbitrary odd-numbered latch among the first to N-th latches (LE ₁ ) to (LE _N ). Since K is an odd number, the K th multiplier (ME _K ) amplifies the output signal (Dse _nK ) of the K th latch (LE _K ) by the gain (C _K ), and converts the output signal (ME _{K_OUT} ) to the second adder (SUM ₂ ), and the (K+1)th multiplier ME _(K+1) is the output signal Dse _n- (K+1) of the ( _{K+1)th latch LE (K+1)} ) The output signal (ME ( _{K+1 )_OUT ) obtained by amplifying by the gain (C K+1 )} is negatively fed back to the first adder (SUM ₁ ). Since K is an odd number, the inverted clock signal CLKB is applied to the Kth latch LE _K , and the clock signal CLK is applied to the (K+1)th latch LE _(K+1) . 8B illustrates a case where K and N are odd and even numbers, respectively, but is not limited thereto. For example, both K and N may be even numbers.

The first multiplier MO ₁ to the Nth multiplier MO _N are output signals Dso _n-1 , Dso _n-2 , ..., Dso _n- of the first latch LO ₁ to the Nth latch LO _N . _(N-1) , Dso _nN ) are amplified, respectively, to generate output signals (MO _{1_OUT} , MO _{2_OUT} , ..., MO _{(N-1)_OUT} , MO _{N_OUT} ), respectively.

Specifically, the first multiplier MO ₁ to the Nth multiplier MO _N are output signals Dso _n-1 , Dso _n-2 , . . . of the first latch LO ₁ to the Nth latch LO _N . , Dso _n-(N-1) , Dso _nN ) are amplified according to the gains (C ₁ , C ₂ , …, C _N-1 , C _N ), and output signals (MO _{1_OUT} , MO _{2_OUT} , …, MO _{(N -1)_OUT} , MO _{N_OUT} ) are created respectively. That is, MO _{1_OUT} =C ₁ ㅧDso _n-1 , MO _{2_OUT} =C ₂ ㅧDso _n-2 , . , MO _{(N-1)_OUT} =C _N-1 ㅧDso _n-(N-1) , MO _{N_OUT} =C _N ㅧDso _nN .

The output signals (MO _{1_OUT} , MO _{2_OUT} , ..., MO _{(N-1)_OUT} , MO _{N_OUT} ) are negatively fed back to the first adder (SUM ₁ ) or the second adder (SUM ₂ ).

8B , the K-th latch (LO _K ), the K-th latch (MO _K ), and the (K+1)-th latch (K+1) latch (LO _(K+1) ) , the (K+1)th multiplier MO (K+1) , which is the _(K+1)th multiplier, is shown. As described above, K is an arbitrary odd number that satisfies 1≤K≤(N-1). That is, the K-th latch LO _K is an arbitrary odd-numbered latch among the first to N-th latches LO ₁ to LO _N . Therefore, the Kth multiplier MO _K amplifies the output signal Dso _nK of the Kth latch LO _K by the gain C _K and adds the output signal MO _{K_OUT} obtained by the first adder SUM ₁ feedback, and the (K+1)th multiplier MO _(K+1 ) converts the output signal Dso _n-( K+1) of the ( _{K+1)th latch LO (} K+1) to a gain ( The output signal (MO _{(K+1)_OUT} ) obtained by amplifying by C _K+ 1 ) is negatively fed back to the second adder (SUM ₂ ). Since K is an odd number, the clock signal CLK is applied to the Kth latch LO _K , and the inverted clock signal CLKB is applied to the (K+1)th latch LO _(K+1 ) . 8B illustrates a case where K and N are odd and even numbers, respectively, but is not limited thereto. For example, both K and N may be even numbers.

The first adder SUM ₁ applies a signal De _n , which is a difference between the received signal X _n and the feedback output signal of the multiplier, to the input terminal D of the first latch LE ₁ .

Specifically, as shown in FIG. 8B , the output signals of the even-numbered multipliers (ME ₂ , ME ₄ , ME ₆ , _... , ME _N ) among the first multipliers ME 1 to N th multipliers ME _N ( ME _{2_OUT} , ME _{4_OUT} , ME _{6_OUT} ,…, ME _{N_OUT} ) and odd-numbered multipliers (MO ₁ , MO ₃ , MO ₅ , …, MO _{N- 1} ) among the first multipliers (MO ₁ ) to the N-th multipliers (MO N ) ) output signals (MO _{1_OUT} , MO _{3_OUT} , MO _{5_OUT} ,..., MO _{(N-1)_OUT} ) are negatively fed back to the first adder (SUM ₁ ).

That is, as shown in FIG. 8B , the first adder SUM ₁ applies the signal De _n according to Equation 5 to the input terminal of the first latch LE ₁ .

The second adder SUM ₂ applies a signal Don _n , which is a difference between the received signal X _n and the feedback output signal of the multiplier, to the input terminal D of the first latch LO ₁ .

Specifically, as shown in FIG. 8B , the output of odd-numbered multipliers ( _{ME 1 ,} ME ₃ , ME ₅ , ..., ME _N-1 ) among the first multipliers ME 1 to N th multipliers ME _N . Among the signals (ME _{1_OUT} , ME _{3_OUT} , ME _{4_OUT} ,..., ME _{(N-1)_OUT} ) and the first multiplier (MO ₁ ) to the N-th multiplier (MO _N ), the even-numbered multipliers (MO ₂ , MO ₄ , MO _{6 )} , ..., MO _N output signals (MO _{2_OUT} , MO _{4_OUT} , MO _{6_OUT} , ..., MO _{N_OUT} ) are negatively fed back to the second adder (SUM ₂ ).

That is, as shown in FIG. 8B , the second adder SUM ₂ applies the signal _Don according to Equation 6 to the input terminal of the first latch LO ₁ .

Since FIG. 8B shows a decision feedback equalizer when N is an even number, the signal (De _n ) of Equation 5 and the signal (Don _n ) of Equation 6 are represented by Equations 9 and 10, respectively. .

According to the first and second embodiments shown in FIGS. 8A and 8B, respectively, the first latch (LE ₁ ) to the Nth latch (LE _N ) (or the first latch (LO ₁ ) to the Nth latch ( Regardless of whether LO _N ) is an odd number or an even number, the output signals _of the even-numbered latches LE ₂ , LE ₄ , ... and the first latch (LE ₁ ) to the N-th latch (LE N ) The output signal of the odd-numbered latch (LO ₁ , LO _{3 ,} ...) among the LO 1 ) to the N-th latch (LO _N ) is negatively fed back to the first adder (SUM ₁ ) through each multiplier, and the first latch (LE _{1 )} ) to Nth latches (LE _N ) to odd-numbered latches (LE ₁ , LE ₃ , ...) and first latches (LO ₁ ) to even-numbered latches (LO ₂ , LO ₄ , ...) to N-th latches (LO _N ). The output signal of ) is negatively fed back to the second adder (SUM ₂ ) through each multiplier.

Hereinafter, the configuration and operation of the decision feedback equalizer according to the present invention described with reference to FIGS. 9 to 17 will be described in detail. The configuration and operation of the decision feedback equalizer according to the present invention will be described based on an embodiment in which N=1, 2, 3, and 4, respectively.

9 is a block diagram illustrating a decision feedback equalizer according to the present invention when N=1.

Specifically, the decision feedback equalizer shown in FIG. 9 includes a first latch LE ₁ and a first latch LO ₁ since N=1 in the decision feedback equalizer shown in FIG. 8A .

Specifically, the output signal Dse _n−1 of the first latch LE ₁ is negatively fed back to the second adder SUM ₂ via the first multiplier ME ₁ , and the output signal of the first latch LO ₁ The output signal Dso _n−1 is negatively fed back to the first adder SUM ₁ via the first multiplier MO ₁ .

The first multiplier ME ₁ and the first multiplier MO ₁ amplify and output the output signals Dse _n-1 and Dso _n-1 of the first latch LE ₁ and the first latch LO ₁ , respectively. Signals (ME _{1_OUT} , MO _{1_OUT} ) are output respectively. The output signal (ME _{1_OUT} ) is negatively fed back to the second adder (SUM ₂ ) and applied to the input terminal (D) of the first latch (LO ₁ ), and the output signal (MO _{1_OUT} ) is added to the first adder (SUM ₁ ). Feedback is applied to the input terminal (D) of the first latch (LE ₁ ).

으로 표시되는 신호(De_n)를 제1 래치(LE₁)의 입력단(D)에 인가한다.The first adder SUM ₁ applies a signal De _n , which is a difference between the received signal X _n and the feedback output signal of the multiplier, to the input terminal D of the first latch LE ₁ . That is, the first adder (SUM ₁ )

A signal (De _n ) represented by is applied to the input terminal (D) of the first latch (LE ₁ ).

으로 표시되는 신호(Do_n)를 제1 래치(LO₁)의 입력단(D)에 인가한다.The second adder (SUM ₂ ) applies the difference (Don _n ) between the received signal (X _n ) and the feedback output signal of the multiplier to the input terminal (D) of the first latch (LO ₁ ). That is, the second adder (SUM ₂ ) is

The signal _Don represented by is applied to the input terminal D of the first latch LO ₁ .

The clock signal generator CLK_GEN applies the clock signal CLK to the clock input terminal EN of the first latch LO ₁ and generates an inverted clock signal CLKB to the clock input terminal EN of the first latch LE ₁ . authorize

The operation of the decision feedback equalizer according to the present invention shown in FIG. 9 will be described in detail with reference to FIG. 10 .

FIG. 10 is a waveform diagram of the decision feedback equalizer according to the present invention shown in FIG. 9 .

9 and 10, the latch LE ₁ outputs the input value as it is in a section where the inverted clock signal CLKB is maintained at High, and in a section where the inverted clock signal CLKB is maintained at Low, the latch LE 1 outputs the previous value. Outputs the value of (stored value). Accordingly, data “D” and “E” are sequentially output in a high section between the rising edge T1 _CLKB and the rising edge T2 _CLKB of the inverted clock signal CLKB. That is, since X _n =D→E from the rising edge (T1 _CLKB ) of the inverted clock signal CLKB to just before the Low period, Dse _n-1 =D→E is output. When the inverted clock signal (CLKB) turns low, the stored value Dse _n-1 =E is output. Similarly, data “F” and “G” are sequentially output in the High period between the rising edge T2 _CLKB and the rising edge T3 _CLKB of the inverted clock signal CLKB. That is, since X _n =F→G from the rising edge (T2 _CLKB ) of the inverted clock signal CLKB to just before the Low section, Dse _n−1 =F→G is output. When the inverted clock signal (CLKB) turns low, the stored value Dse _n-2 =G is output. This process is repeated so that the latch LE ₁ outputs a waveform such as Dse _n-1 of FIG. 10 .

The latch LO ₁ sequentially outputs data "C" and "D" during a high period between the rising edge T1 _CLK and the rising edge T2 _CLK of the clock signal CLK. That is, since X _n =C→D from the rising edge (T1 _CLK ) of the clock signal CLK to just before the Low period, Dso _n-1 =C→D is output. When the clock signal (CLK) turns low, the stored value Dso _n-1 =D is output. Similarly, data “E” and “F” are sequentially output in the High period between the rising edge T2 _CLK and the rising edge T3 _CLK of the clock signal CLK. That is, since X _n =E→F from the rising edge (T2 _CLK ) of the clock signal CLK to just before the Low section, Dso _n-1 =E→F is output. When the clock signal (CLK) turns low, the stored value Dso _n-1 =F is output. This process is repeated so that the latch LO ₁ outputs a waveform such as Dso _n-1 of FIG. 10 .

Hereinafter, the feedback of the decision feedback equalizer according to the present invention shown in FIG. 9 for post-cursor removal will be described in detail.

Referring to FIG. 10 , at the rising edge T1 _CLK of the clock signal CLK, since X _n =C, data required for feedback is “B”. That is, in the 1-tap decision feedback equalizer shown in FIG. 9, since the previous one bit is required to remove the postcursor (C ₁ ), when X _n =C, data “B” for feedback is need. At the rising edge (T1 _CLK ), since Dso _n−1 =B, Dso _n−1 is fed back to De _n as shown in FIG. 9 . With this configuration, the post cursor (C ₁ ) of even data can be removed.

Similarly, at the rising edge T1 _CLKB of the inverted clock signal CLKB, since X _n =D, data required for feedback is “C”. That is, in the 1-tap decision feedback equalizer shown in FIG. 9, since one previous bit is required to remove the postcursor (C ₁ ), when X _n =D, data “C” for feedback is need. At the rising edge (T1 _CLKB ), since Dse _n−1 =C, Dse _n−1 is fed back to Don _n as shown in FIG. 9 . With this configuration, the odd data post cursor (C ₁ ) can be removed.

Looking at the configuration of the decision feedback equalizer according to the present invention shown in FIG. 9, the output signal of the odd-numbered latch (LO ₁ ) is negatively fed back to the first adder (SUM ₁ ) via the multiplier (MO ₁ ), and The output signal of the latch (LE ₁ ) is negatively fed back to the second adder (SUM ₂ ) via the multiplier (ME ₁ ). In addition, the clock signal CLK is applied to the odd-numbered latch LO ₁ , and the inverted clock signal CLKB is applied to the odd-numbered latch LE ₁ .

11 is a block diagram illustrating a decision feedback equalizer according to the present invention when N=2.

Specifically, since the decision feedback equalizer shown in FIG. 11 is N=2 in the decision feedback equalizer shown in FIG. 8B, the first latch LE ₁ and the second latch LE ₂ connected in a cascade form and a first latch LO ₁ and a second latch LO ₂ connected in a cascade form.

Specifically, the output signal Dse _n−1 of the first latch LE ₁ is applied to the input terminal D of the second latch LE ₂ , and the output signal Dso _n of the first latch LO _{1 -1} ) is applied to the input terminal (D) of the second latch (LO ₂ ).

The first multiplier ME ₁ and the second multiplier ME ₂ amplify and output the output signals Dse _n-1 and Dse _{n-2 of} the first latch LE ₁ and the second latch LE 2 , respectively. It outputs signals (ME _{1_OUT} and ME _{2_OUT} ) respectively. The output signal ME _{1_OUT} is negatively fed back to the second adder SUM ₂ , and the output signal ME _{2_OUT} is negatively fed back to the first adder SUM ₁ .

The first multiplier MO ₁ and the second multiplier MO ₂ amplify and output the output signals Dso _{n- 1} and Dso _{n-2 of} the first latch LO 1 and the second latch LO 2 , respectively. Signals MO _{1_OUT} and MO _{2_OUT} are output respectively. The output signal MO _{1_OUT} is negatively fed back to the first adder SUM ₁ , and the output signal MO _{2_OUT} is negatively fed back to the second adder SUM ₂ .

으로 표시되는 신호(De_n)를 제1 래치(LE₁)의 입력단(D)에 인가한다.The first adder SUM ₁ applies a signal De _n , which is a difference between the received signal X _n and the feedback output signal of the multiplier, to the input terminal D of the first latch LE ₁ . That is, the first adder (SUM ₁ )

A signal (De _n ) represented by is applied to the input terminal (D) of the first latch (LE ₁ ).

으로 표시되는 신호(Do_n)를 제1 래치(LO₁)의 입력단(D)에 인가한다.The second adder (SUM ₂ ) applies the difference (Don _n ) between the received signal (X _n ) and the feedback output signal of the multiplier to the input terminal (D) of the first latch (LO ₁ ). That is, the second adder (SUM ₂ ) is

The signal _Don represented by is applied to the input terminal D of the first latch LO ₁ .

The clock signal generator CLK_GEN applies the clock signal CLK to clock input terminals EN of the second latch LE ₂ and the first latch LO ₁ , respectively, and applies the clock signal CLK to the first latch LE ₁ and the second latch LE 1 . The inverted clock signal CLKB is applied to the clock input terminal EN of (LO ₂ ), respectively.

The operation of the decision feedback equalizer according to the present invention shown in FIG. 11 will be described in detail with reference to FIGS. 12, 13A and 13B.

FIG. 12 is a waveform diagram of the decision feedback equalizer according to the present invention shown in FIG. 11;

Referring to FIGS. 11 and 12, the latch LE ₁ outputs the input value as it is in the section where the inverted clock signal CLKB is maintained at High, and in the section where the inverted clock signal CLKB is maintained at Low, the latch LE 1 outputs the previous value as it is. Outputs the value of (stored value). Accordingly, data “D” and “E” are sequentially output in a high section between the rising edge T1 _CLKB and the rising edge T2 _CLKB of the inverted clock signal CLKB. That is, since X _n =D→E from the rising edge (T1 _CLKB ) of the inverted clock signal CLKB to just before the Low period, Dse _n-1 =D→E is output. When the inverted clock signal (CLKB) turns low, the stored value Dse _n-1 =E is output. Similarly, data “F” and “G” are sequentially output in a high period between the rising edge T2 _CLKB and the rising edge T3 _CLKB of the inverted clock signal CLKB. That is, since X _n =F→G from the rising edge (T2 _CLKB ) of the inverted clock signal CLKB to just before the Low section, Dse _n−1 =F→G is output. When the inverted clock signal (CLKB) turns low, the stored value Dse _n-2 =G is output. This process is repeated so that the latch LE ₁ outputs a waveform such as Dse _n-1 of FIG. 12 .

The latch LE ₂ outputs Dse _n-1 as it is during the High section between the rising edge T1 _CLK and the rising edge T2 _CLK of the clock signal CLK. That is, the latch LE ₂ outputs data “C”. In other words, since Dse _n−1 =C from the rising edge T1 _CLK of the clock signal CLK to just before the Low period, Dse _n−2 =C is output. When the clock signal (CLK) turns low, the stored value Dse _n-2 =C is output. Similarly, the latch LE ₂ outputs data “E” during a high period between the rising edge T2 _CLK and the rising edge T3 _CLK of the clock signal CLK. That is, since Dse _n−1 =E from the rising edge (T2 _CLK ) of the clock signal CLK to just before the Low period, Dse _n−2 =E is output. When the clock signal (CLK) turns low, the stored value Dse _n-2 =E is output. This process is repeated so that the latch LE ₂ outputs a waveform such as Dse _n-2 of FIG. 12 .

The latch LO ₁ sequentially outputs data "C" and "D" during a high period between the rising edge T1 _CLK and the rising edge T2 _CLK of the clock signal CLK. That is, since X _n =C→D from the rising edge (T1 _CLK ) of the clock signal CLK to just before the Low period, Dso _n-1 =C→D is output. When the clock signal (CLK) turns low, the stored value Dso _n-1 =D is output. Similarly, data “E” and “F” are sequentially output in the High period between the rising edge T2 _CLK and the rising edge T3 _CLK of the clock signal CLK. That is, since X _n =E→F from the rising edge (T2 _CLK ) of the clock signal CLK to just before the Low section, Dso _n-1 =E→F is output. When the clock signal (CLK) turns low, the stored value Dso _n-1 =F is output. This process is repeated so that the latch LO ₁ outputs a waveform such as Dso _n-1 of FIG. 12 .

The latch LO ₂ outputs Dso _n-1 as it is during the High period between the rising edge T1 _CLKB and the rising edge T2 _CLKB of the inverted clock signal CLKB. That is, the latch LO ₂ outputs data “D”. In other words, since Dso _n-1 =D from the rising edge (T1 _CLKB ) of the inverted clock signal CLKB to just before the Low period, Dso _n-2 =D is output. When the inverted clock signal (CLKB) turns low, the stored value Dso _n-2 =D is output. Similarly, in the high section between the rising edge T2 _CLKB and the rising edge T3 _CLKB of the inverted clock signal CLKB, the latch LO ₂ outputs data “F”. That is, since Dso _n−1 =F from the rising edge (T2 _CLKB ) of the inverted clock signal CLKB to just before the Low period, Dso _n−2 =F is output. When the inverted clock signal (CLKB) turns low, the stored value Dso _n-2 =F is output. This process is repeated so that the latch LO ₂ outputs a waveform as shown in Dso _n-2 of FIG. 12 .

Hereinafter, the feedback of the decision feedback equalizer according to the present invention shown in FIG. 11 for post-cursor removal will be described in detail.

Referring to FIG. 12 , at the rising edge T1 _CLK of the clock signal CLK, since X _n =C, data necessary for feedback are “A” and “B”. That is, in the 2-tap decision feedback equalizer shown in FIG. 11, since the previous two bits are required to remove the postcursor (C ₁ ) and the postcursor (C ₂ ), feedback when X _n =C requires data "B" and "A", respectively. At the rising edge (T1 _CLK ), since Dso _n−1 =B, Dso _n−1 is fed back to De _n as shown in FIG. 11 . Also, at the rising edge T1 _CLK , since Dse _n−2 =A, Dse _n−2 is fed back to De _n as shown in FIG. 11 . With this configuration, postcursor C ₁ and postcursor C ₂ of even data can be removed.

Similarly, at the rising edge T1 _CLKB of the inverted clock signal CLKB, since X _n =D, data required for feedback are "B" and "C". That is, in the 2-tap decision feedback equalizer shown in FIG. 11, since the previous two bits are required to remove the postcursor C ₁ and the postcursor C ₂ , when X _n =D, feedback requires data "C" and "B", respectively. At the rising edge (T1 _CLKB ), since Dse _n−1 =C, Dse _n−1 is fed back to Don _n as shown in FIG. 11 . Also, at the rising edge T1 _CLKB , since Dso _n−2 =B, Dso _n−2 is fed back to Don _n as shown in FIG. 11 . With this configuration, odd data postcursors (C ₁ ) and postcursors (C ₂ ) can be removed.

Looking at the configuration of the decision feedback equalizer according to the present invention shown in FIG. 11, the output signal of the even-numbered latch (LE ₂ ) and the output signal of the odd-numbered latch (LO ₁ ) are multipliers (ME ₂ ) and multipliers (MO), respectively. ₁ ) through the first adder (SUM ₁ ), and the output signals of the odd-numbered latch (LE ₁ ) and the even-numbered latch (LO ₂ ) are divided through the multiplier (ME ₁ ) and the multiplier (MO ₂ ), respectively. It is negatively fed back to the 2 adder (SUM ₂ ). In addition, the clock signal CLK is applied to the even-numbered latch (LE ₂ ) and the odd-numbered latch (LO ₁ ), and the inverted clock signal (CLKB) is applied to the odd-numbered latch (LE ₁ ) and the even-numbered latch (LO ₂ ). is authorized

Hereinafter, with reference to FIGS. 13A and 13B , the timing constraints of the decision feedback equalizer according to the prior art shown in FIG. 5 and the decision feedback equalizer according to the present invention shown in FIG. 11 are compared.

13A and 13B are waveform diagrams showing timing constraints of the half-rate decision feedback equalizer according to the prior art shown in FIG. 5 and the decision feedback equalizer according to the present invention shown in FIG. 11, respectively.

As described above, factors affecting timing constraints of the prior art half-rate decision feedback equalizer shown in FIG. 5 include CK2Q delay, setup time, feedback delay, and the like.

FIG. 13A shows conditions for the normal operation of the half-rate decision feedback equalizer according to the prior art shown in FIG. 5 .

Referring to FIG. 13A, in order for the prior art half-rate decision feedback equalizer to operate normally, before the rising edge of the inverted clock signal CLKB (or the falling edge of the clock signal CLK) for which _Don is sampled, Do _n't be prepared for this. That is, before the rising edge of the inverted clock signal CLKB, De _n is input to FF at the rising edge of the clock signal CLKB, and Dse _n-2 is output, and Dse _n-2 is fed back through the multiplier to obtain _Don should reach up to

을 만족해야 한다.The time taken from the rising edge of the clock signal (CLK) to the output of Dse _n-2 in the state where De _n is input to FF is CK2Q delay (t _CK2Q ), and the time taken for feedback is t _FB . If the setup time, which is the minimum time margin required for sampling in FF, is t _SETUP.FF , t _TC.FF , the timing constraint of the prior art half-rate decision feedback equalizer shown in FIG. Equation 4 must be satisfied. in other words,

should satisfy

Hereinafter, it is examined whether the timing constraint of the half-rate decision feedback equalizer according to the present invention is more relaxed than the timing constraint of the half-rate decision feedback equalizer according to the prior art.

First, in the latch, input data is output as it is when the clock signal is high, and the previous value is maintained when the clock signal is low. As shown in FIG. 13B, when De _n changes from "1" to "0" in the period where the inverted clock signal CLKB is high, the time taken for the latch to output Dse _n-1 =0, that is, the delay Time is t _DQ.LAT . The time required for Dse _n-1 to reach Don _n through feedback is t _FB . Setup time, which is the minimum time margin required for sampling in the latch, is t _SETUP.LAT . By the way, since the setup time is the minimum time margin required right before the rising edge or falling edge of the inverted clock signal CLKB (right before the falling edge or rising edge in the case of the clock signal CLK), as shown in FIG. Likewise, the setup time (t _SETUP.LAT ) required right before the falling edge of the inverted clock signal (CLKB) is included in the delay time (t _DQ.LAT ). Therefore, t _TC.LAT , a timing constraint of the half-rate decision feedback equalizer according to the present invention shown in FIG. 11, must satisfy Equation 11 below.

According to the experimental results of the inventors of the present invention, t _TC.LAT ? 0.5 x t _TC.FF. That is, since t _TC.LAT is smaller than t _TC.FF , 1 UI can be reduced, and thus the clock speed can be increased, enabling high-speed transmission.

14 is a block diagram illustrating a decision feedback equalizer according to the present invention when N=3, and FIG. 15 is a waveform diagram of the decision feedback equalizer according to the present invention shown in FIG.

Specifically, since the decision feedback equalizer shown in FIG. 14 is N=3 in the decision feedback equalizer shown in FIG. 8A, the first latch LE ₁ and the second latch LE ₂ connected in a cascade form and a third latch LE ₃ , and a first latch LO ₁ , a second latch LO ₂ , and a third latch LO ₃ connected in a cascade form.

Specifically, the output signal Dse _n−1 of the first latch LE ₁ is applied to the input terminal D of the second latch LE ₂ , and the output signal Dse _n of the second latch LE _{2 -2} ) is applied to the input terminal (D) of the third latch (LE ₃ ). In addition, the output signal Dso _n-1 of the first latch LO ₁ is applied to the input terminal D of the second latch LO ₂ , and the output signal Dso _{n- 2} of the second latch LO 2 ) is applied to the input terminal D of the third latch LO ₃ .

The first multiplier ME ₁ , the second multiplier ME ₂ , and the third multiplier ME ₃ output signals of the first latch LE ₁ , the second latch LE ₂ , and the third latch LE ₃ . (Dse _n-1 , Dse _n-2 , Dse _n-3 ) are amplified and output signals (ME _{1_OUT} , ME _{2_OUT} , ME _{3_OUT} ) are respectively output. The output signals ME _{1_OUT} and ME _{3_OUT} are negatively fed back to the second adder SUM ₂ , and the output signal ME _{2_OUT} is negatively fed back to the first adder SUM ₁ .

The first multiplier MO ₁ , the second multiplier MO ₂ , and the third multiplier MO ₃ output signals of the first latch LO ₁ , the second latch LO ₂ , and the third latch LO ₃ . (Dso _n-1 , Dso _n-2 , Dso _n-3 ) are amplified and output signals (MO _{1_OUT} , MO _{2_OUT} , MO _{3_OUT} ) are respectively output. The output signals MO _{1_OUT} and MO _{3_OUT} are negatively fed back to the first adder SUM ₁ , and the output signal MO _{2_OUT} is negatively fed back to the second adder SUM ₂ .

으로 표시되는 신호(De_n)를 제1 래치(LE₁)의 입력단(D)에 인가한다.The first adder SUM ₁ applies a signal De _n , which is a difference between the received signal X _n and the feedback output signal of the multiplier, to the input terminal D of the first latch LE ₁ . That is, the first adder (SUM ₁ )

A signal (De _n ) represented by is applied to the input terminal (D) of the first latch (LE ₁ ).

으로 표시되는 신호(Do_n)를 제1 래치(LO₁)의 입력단(D)에 인가한다.The second adder (SUM ₂ ) applies the difference (Don _n ) between the received signal (X _n ) and the feedback output signal of the multiplier to the input terminal (D) of the first latch (LO ₁ ). That is, the second adder (SUM ₂ ) is

The signal _Don represented by is applied to the input terminal D of the first latch LO ₁ .

The clock signal generator CLK_GEN applies the clock signal CLK to clock input terminals EN of the second latch LE ₂ , the first latch LO ₁ , and the third latch LO ₃ , respectively, and The inverted clock signal CLKB is applied to clock input terminals EN of (LE ₁ ), the third latch (LE ₃ ), and the second latch (LO ₂ ), respectively.

The operation of the decision feedback equalizer according to the present invention shown in FIG. 14 will be described in detail with reference to FIG. 15 .

15 is a waveform diagram of the decision feedback equalizer according to the present invention shown in FIG. 14;

Referring to FIGS. 14 and 15 , Dse _n−1 output of the latch LE ₁ , Dse _n−2 output of the latch LE ₂ , Dso n ₋₁ output of the latch LO ₁ , and the latch ( Dso _{n-2 ,} which is the output of LO _{2 ,} is Dse _{n-1 ,} which is the output of the latch LE ₁ shown in FIG. Dso _n-1 is the same as Dso _n-2 , which is the output of the latch (LO ₂ ). Therefore, Dse _n-1 is the output of the latch (LE ₁ ), Dse _n-2 is the output of the latch (LE ₂ ), Dso _n-1 is the output of the latch (LO ₁ ), and Dso is the output of the latch (LO ₂ ). A detailed description of _n-2 is omitted.

The latch LE ₃ outputs Dse _n-2 as it is during the High section between the rising edge T1 _CLKB and the rising edge T2 _CLKB of the inverted clock signal CLKB. That is, the latch LE ₃ outputs data “C”. In other words, since Dse _n-2 =C from the rising edge (T2 _CLKB ) of the inverted clock signal CLKB to just before the Low period, Dse _n-3 =C is output. When the inverted clock signal (CLKB) turns low, the stored value Dse _n-3 =C is output. Similarly, in the high section between the rising edge T2 _CLKB and the rising edge T3 _CLKB of the inverted clock signal CLKB, the latch LE ₃ outputs data “E”. That is, since Dse _n-2 =E from the rising edge (T2 _CLKB ) of the inverted clock signal CLKB to just before the Low period, Dse _n-3 =E is output. When the inverted clock signal (CLKB) turns low, the stored value Dse _n-3 =E is output. This process is repeated so that the latch LE ₃ outputs a waveform such as Dse _n-3 of FIG. 15 .

The latch LO ₃ outputs Dso _n-2 as it is during the High period between the rising edge T1 _CLK and the rising edge T2 _CLK of the clock signal CLK. That is, the latch LO ₃ outputs data “B”. In other words, since Dso _n-2 =B from the rising edge T1 _CLK of the clock signal CLK to just before the Low period, Dso _n-3 =B is output. When the clock signal (CLK) turns low, the stored value Dso _n-3 =B is output. Similarly, the latch LO ₃ outputs data “D” during a high period between the rising edge T2 _CLK and the rising edge T3 _CLK of the clock signal CLK. That is, since Dso _n-2 =D from the rising edge T2 _CLK of the clock signal CLK to just before the Low period, Dso _n-3 =D is output. When the clock signal (CLK) turns low, the stored value Dso _n-3 =D is output. This process is repeated so that the latch LO ₃ outputs a waveform as shown in Dso _n-3 of FIG. 15 .

Hereinafter, the feedback of the decision feedback equalizer according to the present invention shown in FIG. 14 for post-cursor removal will be described in detail.

Referring to FIG. 15 , at the rising edge T2 _CLK of the clock signal CLK, since X _n =E, data necessary for feedback are “D”, “C”, and “B”. That is, in the 3-tap decision feedback equalizer shown in FIG. 14, since the previous three bits are required to remove postcursor C ₁ , postcursor C ₂ , and postcursor C ₃ , When X _n =E, data "D", "C" and "B" are required for feedback, respectively. At the rising edge (T2 _CLK ), since Dso _n−1 =D, Dso _n−1 is fed back to De _n as shown in FIG. 14 . Also, at the rising edge T2 _CLK , since Dse _n−2 =C, Dse _n−2 is fed back to De _n as shown in FIG. 14 . Also, at the rising edge T2 _CLK , since Dso _n−3 =B, Dso _n−3 is fed back to De _n as shown in FIG. 14 . With this configuration, even data postcursor (C ₁ ), postcursor (C ₂ ), and postcursor (C ₃ ) can be removed.

Similarly, at the rising edge T1 _CLKB of the inverted clock signal CLKB, since X _n =D, data required for feedback are "C", "B", and "A". That is, in the 3-tap decision feedback equalizer shown in FIG. 14, since the previous three bits are required to remove postcursor C ₁ , postcursor C ₂ , and postcursor C ₃ , When X _n =D, data "C", "B" and "A" are required for feedback, respectively. At the rising edge (T1 _CLKB ), since Dse _n−1 =C, Dse _n−1 is fed back to Don _n as shown in FIG. 14 . Also, at the rising edge T1 _CLKB , since Dso _n−2 =B, Dso _n−2 is fed back to Don _n as shown in FIG. 14 . Also, at the rising edge T1 _CLKB , since Dse _n−3 =A, Dse _n−3 is fed back to Don _n as shown in FIG. 14 . With this configuration, odd data post cursors (C ₁ ), post cursors (C ₂ ), and post cursors (C ₃ ) can be removed.

Looking at the configuration of the decision feedback equalizer according to the present invention shown in FIG. 14, the output signals of the even-numbered latches LE ₂ and odd-numbered latches LO ₁ and LO ₃ are multipliers ME ₂ and multipliers MO, respectively. ₁ , MO ₃ ) and negative feedback to the first adder (SUM ₁ ), and the output signals of odd-numbered latches (LE ₁ , LE ₃ ) and even-numbered latches (LO ₂ ) are multipliers (ME ₁ , ME ₃ ), respectively. And it is negatively fed back to the second adder (SUM ₂ ) through the multiplier (MO ₂ ). In addition, the clock signal CLK is applied to the even-numbered latches (LE ₂ ) and the odd-numbered latches (LO ₁ and LO ₃ ), and the reverse signal is applied to the odd-numbered latches (LE ₁ and LE ₃ ) and the even-numbered latches (LO ₂ ). A clock signal CLKB is applied.

16 is a block diagram illustrating a decision feedback equalizer according to the present invention when N=4, and FIG. 17 is a waveform diagram of the decision feedback equalizer according to the present invention shown in FIG.

Specifically, since the decision feedback equalizer shown in FIG. 16 is N=4 in the decision feedback equalizer shown in FIG. 8B, the first latch LE ₁ and the second latch LE ₂ connected in a cascade form , the third latch (LE ₃ ) and the fourth latch (LE ₄ ), and the first latch (LO ₁ ), the second latch (LO ₂ ), the third latch (LO ₃ ) and the fourth latch connected in a cascade form. (LO ₄ ).

Specifically, the output signal Dse _n−1 of the first latch LE ₁ is applied to the input terminal D of the second latch LE ₂ , and the output signal Dse _n of the second latch LE _{2 -2} ) is applied to the input terminal (D) of the third latch (LE ₃ ), and the output signal (Dse _n-3 ) of the third latch (LE ₃ ) is applied to the input terminal (D) of the fourth latch (LE ₄ ). is authorized In addition, the output signal Dso _n-1 of the first latch LO ₁ is applied to the input terminal D of the second latch LO ₂ , and the output signal Dso _{n- 2} of the second latch LO 2 ) is applied to the input terminal (D) of the third latch (LO ₃ ), and the output signal (Dso _n-3 ) of the third latch (LO ₃ ) is applied to the input terminal (D) of the fourth latch (LO ₄ ). .

The first multiplier ME ₁ , the second multiplier ME ₂ , the third multiplier ME ₃ , and the fourth multiplier ME ₄ include the first latch LE ₁ , the second latch LE ₂ , and the third The output signals (Dse _n-1 , Dse _n-2 , Dse _n-3 , and Dse _n-4 ) of the latch (LE ₃ ) and the fourth latch (LE ₄ ) are amplified, respectively, and the output signals (ME _{1_OUT} , ME _{2_OUT} , ME _{3_OUT} , ME _{4_OUT} ) are output respectively. The output signals ME _{1_OUT} and ME _{3_OUT} are negatively fed back to the second adder SUM ₂ , and the output signals ME _{2_OUT} and ME _{4_OUT} are negatively fed back to the first adder SUM ₁ .

The first multiplier MO ₁ , the second multiplier MO ₂ , the third multiplier MO ₃ , and the fourth multiplier MO ₄ include the first latch LO ₁ , the second latch LO ₂ , and the third multiplier MO 4 . The output signals (Dso _n-1 , Dso _n-2 , Dso _n-3 , and Dso _n-4 ) of the latch (LO ₃ ) and the fourth latch (LO ₄ ) are amplified, respectively, and the output signals (MO _{1_OUT} , MO _{2_OUT} , MO _{3_OUT} MO _{4_OUT} ) are output respectively. The output signals MO _{1_OUT} and MO _{3_OUT} are negatively fed back to the first adder SUM ₁ , and the output signals MO _{2_OUT} and MO _{4_OUT} are negatively fed back to the second adder SUM ₂ .

으로 표시되는 신호(De_n)를 제1 래치(LE₁)의 입력단(D)에 인가한다.The first adder SUM ₁ applies a signal De _n , which is a difference between the received signal X _n and the feedback output signal of the multiplier, to the input terminal D of the first latch LE ₁ . That is, the first adder (SUM ₁ )

A signal (De _n ) represented by is applied to the input terminal (D) of the first latch (LE ₁ ).

으로 표시되는 신호(Do_n)를 제1 래치(LO₁)의 입력단(D)에 인가한다.The second adder (SUM ₂ ) applies the difference (Don _n ) between the received signal (X _n ) and the feedback output signal of the multiplier to the input terminal (D) of the first latch (LO ₁ ). That is, the second adder (SUM ₂ ) is

The signal _Don represented by is applied to the input terminal D of the first latch LO ₁ .

The clock signal generator CLK_GEN outputs a clock signal CLK to clock input terminals EN of the second latch LE ₂ , the fourth latch LE ₄ , the first latch LO ₁ , and the third latch LO ₃ , respectively. ) is applied, and an inverted clock signal (CLKB) is applied to clock input terminals (EN) of the first latch (LE ₁ ), the third latch (LE ₃ ), the second latch (LO ₂ ), and the fourth latch (LO ₄ ), respectively. authorize

The operation of the decision feedback equalizer according to the present invention shown in FIG. 16 will be described in detail with reference to FIG. 17 .

17 is a waveform diagram of the decision feedback equalizer according to the present invention shown in FIG. 16;

Referring to FIGS. 16 and 17 , Dse _n−1 output of the latch LE ₁ , Dse _n−2 output of the latch LE ₂ , Dse n ₋ 3 output of the latch LE ₃ , and the latch ( Dso _n-1 , output of LO ₁ ), Dso _n-2 , output of latch LO ₂ , and Dso _n-3 output of latch LO ₃ are outputs of latch LE ₁ shown in FIG. 15 . Dse _n-1 , output of latch (LE ₂ ) Dse _n-2 , output of latch (LE ₃ ) Dse _n-3 , output of latch (LO ₁ ) Dso _n-1 , output of latch (LO ₂ ) It is the same as Dso _n-2 , the output, and Dso _n-3 , the output of the latch (LO ₃ ), respectively. Therefore, Dse _n-1 is the output of the latch (LE ₁ ), Dse _n-2 is the output of the latch (LE ₂ ), Dse _{n-3 is} the output of the latch (LE 3 ), and Dso is the output of the latch (LO ₁ ). Detailed descriptions of _n-1 , Dso _{n-2 output} of the latch LO 2 , and Dso _{n-3 output} of the latch LO 3 are omitted.

The latch LE ₄ outputs Dse _n-3 as it is during the high period between the rising edge T1 _CLK and the rising edge T2 _CLK of the clock signal CLK. That is, the latch LE ₄ outputs data “A”. In other words, since Dse _n-3 =A from the rising edge (T1 _CLK ) of the clock signal CLK to just before the Low period, Dse _n-4 =A is output. When the clock signal (CLK) turns low, the stored value Dse _n-4 =A is output. Similarly, the latch LE ₄ outputs data “C” during a high period between the rising edge T2 _CLK and the rising edge T3 _CLK of the clock signal CLK. That is, since Dse _n-3 =C from the rising edge (T2 _CLK ) of the clock signal CLK to just before the Low period, Dse _n-4 =C is output. When the clock signal (CLK) turns low, the stored value Dse _n-4 =C is output. This process is repeated so that the latch LE ₄ outputs a waveform such as Dse _n-4 of FIG. 17 .

The latch LO ₄ outputs Dso _n-3 as it is during the High period between the rising edge T1 _CLKB and the rising edge T2 _CLKB of the inverted clock signal CLKB. That is, the latch LO ₄ outputs data “B”. In other words, since Dso _n-3 =B from the rising edge (T1 _CLKB ) of the inverted clock signal CLKB to just before the Low period, Dso _n-4 =B is output. When the inverted clock signal (CLKB) turns low, the stored value Dso _n-4 =B is output. Similarly, in the high period between the rising edge T2 _CLKB and the rising edge T3 _CLKB of the inverted clock signal CLKB, the latch LO ₄ outputs data “D”. That is, since Dso _n-3 =D from the rising edge (T2 _CLKB ) of the inverted clock signal CLKB to just before the Low period, Dso _n-4 =D is output. When the inverted clock signal (CLKB) turns low, the stored value Dso _n-4 =D is output. This process is repeated so that the latch LO ₄ outputs a waveform as shown in Dso _n-4 of FIG. 17 .

Hereinafter, the feedback of the decision feedback equalizer according to the present invention shown in FIG. 16 for post-cursor removal will be described in detail.

Referring to FIG. 17 , at the rising edge T2 _CLK of the clock signal CLK, since X _n =E, data required for feedback are “D”, “C”, “B”, and “A”. That is, in the 4-tap decision feedback equalizer shown in FIG. 16, to remove postcursor (C ₁ ), postcursor (C ₂ ), postcursor (C ₃ ) and postcursor (C ₄ ), the previous four bits (bit) is required, so when X _n =E, data “D”, “C”, “B” and “A” are required for feedback, respectively. At the rising edge (T2 _CLK ), since Dso _n−1 =D, Dso _n−1 is fed back to De _n as shown in FIG. 16 . Also, at the rising edge T2 _CLK , since Dse _n−2 =C, Dse _n−2 is fed back to De _n as shown in FIG. 16 . Also, at the rising edge T2 _CLK , since Dso _n−3 =B, Dso _n−3 is fed back to De _n as shown in FIG. 16 . Also, at the rising edge T2 _CLK , since Dse _n−4 =A, Dse _n−4 is fed back to De _n as shown in FIG. 16 .

With this configuration, even data postcursor (C ₁ ), postcursor (C ₂ ), postcursor (C ₃ ) and postcursor (C ₄ ) can be removed.

Similarly, at the rising edge T2 _CLKB of the inverted clock signal CLKB, since X _n =F, data required for feedback are "E", "D", "C", and "B". That is, in the 4-tap decision feedback equalizer shown in FIG. 16, to remove postcursor (C ₁ ), postcursor (C ₂ ), postcursor (C ₃ ) and postcursor (C ₄ ), the previous four bits (bit) is required, so when X _n =F, data “E”, “D”, “C”, and “B” are required for feedback, respectively. At the rising edge (T2 _CLKB ), since Dse _n−1 =E, Dse _n−1 is fed back to Don _n as shown in FIG. 16 . Also, at the rising edge T2 _CLKB , since Dso _n−2 =D, Dso _n−2 is fed back to Don _n as shown in FIG. 16 . Also, at the rising edge T2 _CLKB , since Dse _n−3 =C, Dse _n−3 is fed back to Don _n as shown in FIG. 16 . Also, at the rising edge T2 _CLKB , since Dso _n−4 =B, Dso _n−4 is fed back to Don _n as shown in FIG. 16 .

With this configuration, odd data post cursors (C ₁ ), post cursors (C ₂ ), post cursors (C ₃ ), and post cursors (C ₄ ) can be removed.

Looking at the configuration of the decision feedback equalizer according to the present invention shown in FIG. 16, the output signals of the even-numbered latches LE ₂ and LE ₄ and the odd-numbered latches LO ₁ and LO ₃ are multipliers ME ₂ and ME, respectively. ₄ ) and multipliers (MO ₁ , MO ₃ ) and negative feedback to the first adder (SUM ₁ ), and the output signals of odd-numbered latches (LE ₁ , LE ₃ ) and even-numbered latches (LO ₂ , LO ₄ ) are It passes through the multipliers ME ₁ and ME ₃ and the multipliers MO ₂ and MO ₄ , respectively, and is negatively fed back to the second adder SUM ₂ . In addition, the clock signal CLK is applied to the even-numbered latches LE ₂ and LE ₄ and the odd-numbered latches LO ₁ and LO ₃ , and the odd-numbered latches LE ₁ and LE ₃ and the even-numbered latches LO ₂ , LO ₄ ) is applied with an inverted clock signal CLKB.

The configuration and operation of the decision feedback equalizer according to the present invention when N=1, 2, 3, and 4 have been described in detail above. Even when N is 5 or more, the above-described operation and configuration are equally applied. That is, when N is a natural number greater than or equal to 1 as shown in FIGS. 8A and 8B , the above-described operation and configuration are equally applied.

Claims (10)

a first latch (LE ₁ ) to an N-th latch (LE _N ) connected in a cascade form;
First multipliers ME 1 to Nth multipliers (ME ₁ ) to generate output signals (ME _{1_OUT} ) to output signals (ME _{N_OUT} ) by amplifying the output signals of the first latch (LE 1 ) to the Nth latch (LE _N ) _, respectively. multiplier (ME _N );
a first latch (LO ₁ ) to an N-th latch (LO _N ) connected in a cascade form;
First multipliers (MO ₁ ) to N-th multipliers (MO 1 ) to generate output signals (MO _{1_OUT} ) to (MO _{N_OUT} ) by amplifying the output signals of the first to N-th latches (LO ₁ ) to (LO _N ), respectively. multiplier (MO _N );

a first adder for applying a signal De _n represented by ? to an input terminal of the first latch LE ₁ ;

a second adder for applying the signal Don _n represented by ? to an input terminal of the first latch LO ₁ ; and
Even-numbered latches (LE ₂ , LE ₄ , ...) among the first latches (LE ₁ ) to N-th latches (LE _N ) and odd-numbered latches among the first latches (LO ₁ ) to N-th latches (LO _N ) A clock signal CLK is applied to clock input terminals EN of (LO ₁ , LO ₃ , ...), respectively, and odd-numbered latches LE ₁ , among the first to N- _th latches LE ₁ , An inverted clock signal CLKB is applied to clock input terminals EN of the even-numbered latches LO ₂ , LO ₄ , … among the first latch LO ₁ to the N-th latch LO _N , _respectively . Clock signal generator to apply (CLK_GEN)
A decision feedback equalizer characterized in that it comprises (provided that X _n is a received signal, and N is a natural number greater than or equal to 1). According to claim 1,
The first latch (LE ₁ ) to the Nth latch (LE _N ) and the first latch (LO ₁ ) to the Nth latch (LO _N ) each have an input terminal (D), a clock input terminal (EN), and an output terminal (Q). A decision feedback equalizer comprising a D-latch comprising: According to claim 2,
The output terminal (Q) of the Kth latch (LE _K ), which is any one of the first to Nth latches (LE _N ) connected in a cascade form, is the ( _Kth ) adjacent to the Kth latch (LE _K ). +1) It is electrically connected to the input terminal (D) of the latch (LE _(K+1) ), and the clocks of the Kth latch (LE _K ) and the (K+1)th latch (LE _(K+1) ) Decision feedback equalizer characterized in that the clock signal (CLK) and the inverted clock signal (CLKB) are respectively applied to the input terminal (EN) (where N is a natural number equal to or greater than 3, and K is 1≤K≤(N- an even number that satisfies 1)). According to claim 3,
The output terminal ( _Q ) of the Kth latch (LO K ), which is any one of the first to Nth latches (LO _N ) connected in a cascade form, is the ( _Kth ) adjacent to the Kth latch (LO _K ). +1) It is electrically connected to the input terminal (D) of the latch (LO _(K+1) ), and the clocks of the Kth latch (LO _K ) and the (K+1)th latch (LO _(K+1) ) The decision feedback equalizer, characterized in that the inverted clock signal (CLKB) and the clock signal (CLK) are respectively applied to the input terminal (EN). According to claim 2,
The output terminal (Q) of the Kth latch (LE _K ), which is any one of the first to Nth latches (LE _N ) connected in a cascade form, is the ( _Kth ) adjacent to the Kth latch (LE _K ). +1) It is electrically connected to the input terminal (D) of the latch (LE _(K+1) ), and the clocks of the Kth latch (LE _K ) and the (K+1)th latch (LE _(K+1) ) The decision feedback equalizer characterized in that the inverted clock signal (CLKB) and the clock signal (CLK) are respectively applied to the input terminal (EN) (N is a natural number equal to or greater than 2, and K is 1≤K≤(N- an odd number that satisfies 1). According to claim 5,
The output terminal ( _Q ) of the Kth latch (LO K ), which is any one of the first to Nth latches (LO _N ) connected in a cascade form, is the ( _Kth ) adjacent to the Kth latch (LO _K ). +1) It is electrically connected to the input terminal (D) of the latch (LO _(K+1) ), and the clocks of the Kth latch (LO _K ) and the (K+1)th latch (LO _(K+1) ) The decision feedback equalizer, characterized in that the clock signal (CLK) and the inverted clock signal (CLKB) are respectively applied to the input terminal (EN). According to claim 2,
N=1, and
a first latch (LE ₁ ) and a first latch (LO ₁ );
A first multiplier configured to generate output signals ME _{1_OUT} and MO _{1_OUT} by amplifying the output signals Dse _n-1 and Dso _n-1 of the first latch LE ₁ and the first latch LO ₁ , respectively. (ME ₁ ) and a first multiplier (MO ₁ );

a first adder applying a signal (De _n ) represented by ? to an input terminal (D) of the first latch (LE ₁ );

a second adder for applying the signal _Don represented by ? to the input terminal D of the first latch LO ₁ ; and
A clock signal for applying a clock signal CLK to the clock input terminal EN of the first latch LO ₁ and applying an inverted clock signal CLKB to the clock input terminal EN of the first latch LE ₁ . Generator (CLK_GEN)
A decision feedback equalizer comprising: According to claim 2,
N=2, and
a first latch (LE ₁ ) and a first latch (LO ₁ );
The second latch LE ₂ and the second latch LE ₂ to which the output signals Dse _n-1 and Dso _n-1 of the first latch LE 1 and the first latch LO ₁ are respectively applied to their input terminals D. latch (LO ₂ );
A first step configured to generate output signals ME 1_OUT and ME _{2_OUT} by amplifying output signals _{Dse n-1} and Dse _n-2 of the first latch LE ₁ and the second latch LE ₂ , respectively. a multiplier (ME ₁ ) and a second multiplier (ME ₂ );
A first step generating output signals MO _{1_OUT} and MO _{2_OUT} by amplifying output signals Dso _n-1 and Dso _{n-2 of} the first latch LO 1 and the second latch LO ₂ , respectively. a multiplier (MO ₁ ) and a second multiplier (MO ₂ );

a first adder for applying a signal (De _n ) represented by , to an input terminal (D) of the first latch (LE ₁ );

a second adder for applying the signal _Don represented by ? to the input terminal D of the first latch LO ₁ ; and
A clock signal CLK is applied to the clock input terminal EN of the second latch LE ₂ and the first latch LO _{1 ,} respectively, and the first latch LE ₁ and the second latch LO ₂ A clock signal generator (CLK_GEN) that applies an inverted clock signal (CLKB) to the clock input terminal (EN) of
A decision feedback equalizer comprising: According to claim 2,
N=3, and
a first latch (LE ₁ ) and a first latch (LO ₁ );
The second latch LE ₂ and the second latch LE ₂ to which the output signals Dse _n-1 and Dso _n-1 of the first latch LE 1 and the first latch LO ₁ are respectively applied to their input terminals D. latch (LO ₂ );
The third latch LE ₃ and the third latch LE ₃ to which the output signals Dse _n-2 and Dso _n-2 of the second latch LE 2 and the second latch LO ₂ are respectively applied to their input terminals D. latch (LO ₃ );
The output signals Dse n- ₁ , Dse _{n-2 ,} and Dse n-3 of the first latch LE 1 , the second latch LE ₂ , and the _third latch _{LE 3} are amplified and output. a first multiplier (ME _{1 )} , a second multiplier (ME ₂ ), and a third multiplier (ME ₃ ) generating signals (ME _{1_OUT} , ME _{2_OUT} , and ME _{3_OUT} ), respectively;
The output signals Dso n- ₁ , Dso _{n- 2} , and Dso n- ₃ of the first latch LO 1 , the second latch LO ₂ , and the third latch _{LO 3} are amplified and output, respectively. a first multiplier (MO _{1 )} , a second multiplier (MO ₂ ), and a third multiplier (MO ₃ ) generating signals (MO _{1_OUT} , MO _{2_OUT} , and MO _{3_OUT} ), respectively;

a first adder applying a signal (De _n ) represented by ? to an input terminal (D) of the first latch (LE ₁ );

a second adder for applying the signal _Don represented by ? to the input terminal D of the first latch LO ₁ ; and
A clock signal CLK is applied to clock input terminals EN of the second latch LE ₂ , the first latch LO ₁ , and the third latch LO ₃ , respectively, and the first latch LE ₁ ), a clock signal generator (CLK_GEN) for applying an inverted clock signal (CLKB) to clock input terminals (EN) of the third latch (LE ₃ ) and the second latch (LO ₂ ), respectively.
A decision feedback equalizer comprising: According to claim 2,
N=4, and
a first latch (LE ₁ ) and a first latch (LO ₁ );
The second latch LE ₂ and the second latch LE ₂ to which the output signals Dse _n-1 and Dso _n-1 of the first latch LE 1 and the first latch LO ₁ are respectively applied to their input terminals D. latch (LO ₂ );
The third latch LE ₃ and the third latch LE ₃ to which the output signals Dse _n-2 and Dso _n-2 of the second latch LE 2 and the second latch LO ₂ are respectively applied to their input terminals D. latch (LO ₃ );
The fourth latch LE ₄ and the fourth latch LE ₄ to which the output signals Dse _n-3 and Dso _n-3 of the third latch LE 3 and LO ₃ are respectively applied to their input terminals D. latch (LO ₄ );
Output signals Dse n− ₁ , Dse _n− 2 _{, and} Dse of the first latch LE 1 , the second latch LE ₂ , the third latch LE ₃ , and the fourth latch LE ₄ A first multiplier (ME ₁ ), a second multiplier (ME 2 ), and a third multiplier (ME ₁ ) generate output signals (ME _{1_OUT} , ME _{2_OUT} , ME _{3_OUT} , ME _{4_OUT} ) by respectively amplifying n- ₃ and Dse _n-4 ). a multiplier (ME ₃ ) and a fourth multiplier (ME ₄ );
Output signals Dso n- ₁ , Dso _n- 2 _{, and} Dso of the first latch LO 1 , the second latch LO ₂ , the third latch LO ₃ , and the fourth latch LO ₄ . _n-3 , Dso _n-4 ) to generate output signals MO _{1_OUT} , MO _{2_OUT} , MO _{3_OUT} MO _{4_OUT} ), respectively, a first multiplier (MO ₁ ), a second multiplier (MO ₂ ), and a third multiplier ( MO ₃ ) and a fourth multiplier (MO ₄ );

a first adder for applying a signal (De _n ) represented by , to an input terminal (D) of the first latch (LE ₁ );

a second adder for applying the signal _Don represented by ? to the input terminal D of the first latch LO ₁ ; and
A clock signal CLK is applied to clock input terminals EN of the second latch LE ₂ , the fourth latch LE ₄ , the first latch LO ₁ , and the third latch LO ₃ , respectively. and applies an inverted clock signal CLKB to clock input terminals EN of the first latch LE ₁ , the third latch LE ₃ , the second latch LO ₂ , and the fourth latch LO ₄ , respectively. Clock signal generator to apply (CLK_GEN)
A decision feedback equalizer comprising:

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