KR20230061598A - Electronic apparatus - Google Patents

Abstract

An electronic device according to an embodiment of the present invention includes a first substrate including a plurality of light emitting elements and driving elements connected to the light emitting elements, a second substrate including a light control member and disposed facing the first substrate, a first substrate, and a light control member. A filling member disposed between the second substrate and covering a plurality of light emitting elements, a sealing member disposed between the first substrate and the second substrate and coupling the first substrate and the second substrate, and between the first substrate and the second substrate. and a spacer disposed on and overlapping with the sealing member on a plane, and the sealing member may be spaced apart from the light emitting elements on a plane.

Description

Electronic device {ELECTRONIC APPARATUS}

The present invention relates to an electronic device, and more particularly, to an electronic device with improved reliability.

Multimedia electronic devices such as televisions, mobile phones, tablets, computers, navigation devices, game machines, and the like may include display panels for displaying images. The display panel may include a plurality of pixels for displaying an image, and each of the pixels may include a light emitting element generating light and a driving element connected to the light emitting element.

Recently, a display device including a light conversion layer is being developed in order to improve visibility and color purity of the display device. Accordingly, the electronic device may be manufactured by bonding the substrate on which the light emitting element is formed and the substrate on which the light conversion layer is formed. However, defects may be caused in the process of bonding the substrates of the electronic device, and research is needed to solve this problem.

SUMMARY OF THE INVENTION An object of the present invention is to provide an electronic device that displays an image with uniform luminance and reduces a deviation of a gap between substrates in a display area in a process of bonding substrates constituting the electronic device.

SUMMARY OF THE INVENTION An object of the present invention is to improve reliability of an electronic device by preventing a difference in degree of deterioration between pixels caused by compensating for luminance non-uniformity by reducing a deviation of a gap between substrates in a display area.

An embodiment includes a first substrate including a plurality of light emitting elements and driving elements connected to the light emitting elements, a second substrate including a light control member and disposed facing the first substrate, the first substrate and the first substrate. A filling member disposed between a second substrate and covering the plurality of light emitting elements, a sealing member disposed between the first substrate and the second substrate and coupling the first substrate and the second substrate, and the first substrate. and a spacer disposed between a substrate and the second substrate and overlapping the sealing member on a plane, wherein the sealing member is spaced apart from the light emitting elements on a plane.

The spacer may include at least one organic layer.

The spacer may be disposed between the first substrate and the sealing member in a thickness direction.

The spacer may be disposed between the second substrate and the sealing member in a thickness direction.

The spacer may include a first spacer disposed between the first substrate and the sealing member in a thickness direction and a second spacer disposed between the second substrate and the sealing member.

The spacer may be entirely covered by the sealing member.

A side surface of the spacer may be spaced apart from the sealing member.

The first substrate may further include a plurality of insulating layers disposed between the light emitting elements and the driving elements, and the spacer may include the same material as at least one of the plurality of insulating layers.

The first substrate may further include a pixel defining layer defining light emitting regions of the light emitting elements, and the spacer may include the same material as the pixel defining layer.

The first substrate further includes an encapsulation layer disposed between the filling member and the light emitting elements, and a dam disposed outside the encapsulation layer and in contact with the encapsulation layer, and the spacer and the sealing member are the dam and spaced apart on a plane, and the spacer may include the same material as the dam.

The light control member may include a bank portion disposed on the filling member and defining a plurality of openings each overlapping the light emitting elements, and a plurality of light conversion units each disposed at the plurality of openings. there is.

The spacer may include the same material as the bank part.

Each of the light emitting elements may provide source light, and the light conversion units may include quantum dots that convert a wavelength of the source light.

The light control member may include a plurality of color filters disposed on the filling member and overlapping the light emitting elements.

An embodiment includes a first base substrate including an upper surface, a second base substrate including a rear surface facing the upper surface, a pixel defining layer disposed on the upper surface and including a light emitting opening, and a light emitting element disposed on the light emitting opening. , a driving element disposed between the first base substrate and the light emitting element and connected to the light emitting element, at least one insulating layer disposed between the driving element and the light emitting element, disposed on the rear surface and corresponding to the light emitting element A bank unit including an opening, a light conversion unit disposed in the opening, a charging member disposed between the light conversion unit and the light emitting element, and disposed between the first base substrate and the second base substrate and the light emitting element and a sealing member spaced apart from the bank unit and a first spacer disposed on the same layer as the bank unit, wherein the first spacer overlaps the sealing member on a plane.

A side surface of the first spacer may be covered by the sealing member.

A side surface of the first spacer may be spaced apart from the sealing member.

The electronic device further includes a dam disposed between the sealing member and the light emitting element on a plane and spaced apart from the sealing member, and a second spacer disposed on the same layer as the dam, wherein the dam comprises the insulating layer and the The second spacer may include the same material as at least one of the pixel defining layers, and the second spacer may include the same material as the dam.

A side surface of the second spacer may be covered by the sealing member.

A side surface of the second spacer may be spaced apart from the sealing member.

The spacer according to an embodiment of the present invention may be formed in the process of manufacturing the first substrate and the second substrate, and the spacer supports the sealing member in the process of bonding the first substrate and the second substrate, so that the substrates according to the area It is possible to reduce the gap deviation between the substrates and prevent the bending problem of the substrates.

The spacer according to an embodiment of the present invention supports a sealing member so that a gap between the first substrate and the second substrate at the boundary of the display area adjacent to the sealing member and a gap between the first substrate and the second substrate at the center of the display area are reduced. Therefore, the electronic device of the present invention can output an image with uniform luminance in the entire display area.

The spacer according to an embodiment of the present invention reduces a gap deviation between substrates, thereby reducing a current difference and a degradation rate difference between pixels for compensating for luminance non-uniformity in a display area, and display by the degradation rate difference It is possible to prevent a problem in which a stain within a region is visually recognized.

1 is a perspective view of an electronic device according to an embodiment of the present invention.
2 is an exploded perspective view of an electronic device according to an embodiment of the present invention.
3 is a cross-sectional view of a display module according to an embodiment of the present invention.
4 is a plan view of a display panel according to an exemplary embodiment of the present invention.
5A and 5B are enlarged plan views of a display panel according to an exemplary embodiment of the present invention.
6 is a cross-sectional view of a display panel according to an exemplary embodiment of the present invention.
7 is a cross-sectional view of a display module according to an embodiment of the present invention.
8A and 8B are cross-sectional views of a display module according to an exemplary embodiment.
9A is a cross-sectional view of a display module of a comparative example of the present invention.
9B is a cross-sectional view of a display module according to an embodiment of the present invention.
10 is a graph illustrating a cell gap according to a position of a display area of an embodiment of the present invention and a comparative example.
11A to 11C are cross-sectional views of a display module according to an exemplary embodiment.

Since the present invention may have various changes and various forms, specific embodiments are illustrated in the drawings and described in detail in the text. However, it should be understood that this is not intended to limit the present invention to the specific disclosed form, and includes all modifications, equivalents, and substitutes included in the spirit and scope of the present invention.

In this specification, when an element (or region, layer, section, etc.) is referred to as being “on,” “connected to,” or “coupled to” another element, it is directly placed/placed on the other element. It means that they can be connected/combined or a third component may be placed between them.

Like reference numerals designate like components. Also, in the drawings, the thickness, ratio, and dimensions of components are exaggerated for effective description of technical content. “And/or” includes any combination of one or more that the associated elements may define.

Terms such as first and second may be used to describe various components, but the components should not be limited by the terms. These terms are only used for the purpose of distinguishing one component from another. For example, a first element may be termed a second element, and similarly, a second element may be termed a first element, without departing from the scope of the present invention. Singular expressions include plural expressions unless the context clearly dictates otherwise.

In addition, terms such as "below", "lower side", "above", and "upper side" are used to describe the relationship between components shown in the drawings. The above terms are relative concepts and will be described based on the directions shown in the drawings.

Terms such as "include" or "have" are intended to indicate that a feature, number, step, operation, component, part, or combination thereof described in the specification exists, but that one or more other features, numbers, or steps are present. However, it should be understood that it does not preclude the possibility of existence or addition of operations, components, parts, or combinations thereof.

Unless defined otherwise, all terms (including technical terms and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. In addition, terms such as terms defined in commonly used dictionaries should be interpreted as having a meaning consistent with the meaning in the context of the related art, and unless explicitly defined herein, interpreted as too idealistic or too formal. It shouldn't be.

Hereinafter, an electronic device according to an embodiment of the present invention will be described with reference to the drawings.

1 is a perspective view of an electronic device according to an exemplary embodiment. FIG. 2 is an exploded perspective view of an electronic device according to an exemplary embodiment shown in FIG. 1 .

The electronic device DD may be a device that is activated according to an electrical signal and displays an image. The electronic device DD may include various embodiments that provide images to the user. For example, the electronic device DD includes large devices such as televisions and billboards, monitors, mobile phones, tablet computers, and the like. It may include small and medium-sized devices such as a navigation device and a game machine. Meanwhile, the embodiments of the electronic device DD are exemplary, and are not limited to any one unless departing from the concept of the present invention.

Referring to FIG. 1 , the electronic device DD may have a rectangular shape having long sides extending in the first direction DR1 and short sides extending in the second direction DR2 on a plane. However, it is not limited thereto, and the electronic device DD may have various shapes such as a circular shape and a polygonal shape.

The electronic device DD may display the image IM in the third direction DR3 through the display surface IS parallel to the plane defined by the first and second directions DR1 and DR2. The third direction DR3 may be substantially parallel to the normal direction of the display surface IS. The display surface IS on which the image IM is displayed may correspond to the front surface of the electronic device DD. The image IM may include a still image as well as a dynamic image. 1 illustrates icon images as an example of an image IM.

In this embodiment, the front (or upper surface) and rear surface (or lower surface) of each member or unit may be defined based on the direction in which the image IM is displayed. The front surface and the rear surface may oppose each other in the third direction DR3, and a normal direction of each of the front surface and the rear surface may be parallel to the third direction DR3. The separation distance between the front surface and the rear surface defined along the third direction DR3 may correspond to the thickness of the member (or unit). In this specification, "on a plane" may be defined as a state viewed from the third direction DR3. In this specification, "on a cross section" may be defined as a state viewed from the first direction DR1 or the second direction DR2. Meanwhile, directions indicated by the first to third directions DR1 , DR2 , and DR3 may be converted into other directions as a relative concept.

1 illustrates an electronic device DD having a planar display surface IS as an example. However, the shape of the display surface IS of the electronic device DD is not limited thereto and may be a curved shape or a three-dimensional shape.

The electronic device DD may be flexible. “Flexible” means a property that can be bent, and may include everything from a completely foldable structure to a structure that can be bent at the level of several nanometers. For example, the flexible electronic device DD may be a curved device or a foldable device. It is not limited thereto, and the electronic device DD may be rigid.

The display surface IS of the electronic device DD may include a display area D-DA and a non-display area D-NDA. The display unit D-DA may be a portion on the front of the electronic device DD where the image IM is displayed, and a user may view the image IM through the display unit D-DA. Although the present embodiment shows the display unit D-DA having a rectangular shape as an example, the display unit D-DA may have various shapes according to designs.

The non-display area D-NDA may be a portion on the front side of the electronic device DD on which the image IM is not displayed. The non-display portion D-NDA may be a portion having a predetermined color and blocking light. The non-display area D-NDA may be adjacent to the display area D-DA. For example, the non-display portion D-NDA may be disposed outside the display portion D-DA to surround the display portion D-DA. However, this is illustrated as an example, and the non-display unit D-NDA may be adjacent to only one side of the display unit D-DA or disposed on a side surface of the electronic device DD other than the front, but is not limited thereto. and the non-display unit D-NDA may be omitted.

The electronic device DD according to an embodiment may detect an external input applied from the outside. The external input may have various forms such as externally provided pressure, temperature, light, and the like. The external input may include not only an input contacting the electronic device DD (eg, contact by a user's hand or a pen) but also an input applied close to the electronic device DD (eg, hovering). can

Referring to FIG. 2 , the electronic device DD may include a window WM, a display module DM, and an external case HAU. The display module DM may include a display panel DP and a light control member LCM disposed on the display panel DP.

The window WM and the outer case HAU may be combined to configure the exterior of the electronic device DD, and provide an internal space capable of accommodating components of the electronic device DD such as the display module DM. can

The window WM may be disposed on the display module DM. The window WM may protect the display module DM from external impact. The front surface of the window WM may correspond to the aforementioned display surface IS of the electronic device DD. The front surface of the window WM may include a transmissive area TA and a bezel area BA.

The transmission area TA of the window WM may be an optically transparent area. The window WM can transmit an image provided by the display module DM through the transmission area TA, and the user can view the corresponding image. The transmission area TA may correspond to the display units D-DA of the electronic device DD.

The window WM may include an optically transparent insulating material. For example, the window WM may include glass, sapphire, or plastic. The window WM may have a single-layer or multi-layer structure. The window WM may further include functional layers such as an anti-fingerprint layer, a phase control layer, and a hard coating layer disposed on an optically transparent substrate.

The bezel area BA of the window WM may correspond to an area provided by depositing, coating, or printing a material having a predetermined color on a transparent substrate. The bezel area BA of the window WM may prevent one component of the display module DM disposed overlapping the bezel area BA from being viewed to the outside. The bezel area BA may correspond to the non-display area D-NDA of the electronic device DD.

The display module DM may be disposed between the window WM and the outer case HAU. The display module DM may display an image according to an electrical signal. The display module DM may include a display area DA and a peripheral area NDA adjacent to the display area DA.

The display area DA may be an area activated according to an electrical signal. The display area DA may be an area for outputting an image provided from the display module DM. The display area DA of the display module DM may correspond to the above-described transmission area TA. An image generated in the display area DA can be viewed from the outside through the transmission area TA. Meanwhile, in the present specification, “regions/parts and regions/parts correspond” means “overlap each other” and are not limited to having the same area and/or the same shape.

The peripheral area NDA may be adjacent to the display area DA. For example, the peripheral area NDA may surround the display area DA. However, it is not limited thereto, and the peripheral area NDA may be defined in various shapes. The peripheral area NDA may be an area where driving circuits or driving wires for driving elements disposed in the display area DA, various signal lines providing electrical signals, and pads are disposed. The peripheral area NDA of the display module DM may correspond to the bezel area BA of the window WM, and elements of the display module DM disposed in the peripheral area NDA are in the bezel area BA. It can be prevented from being visible to the outside by

The display panel DP according to an exemplary embodiment may be a light emitting display panel, and is not particularly limited thereto. For example, the display panel DP may be an organic light emitting display panel, an inorganic light emitting display panel, or a quantum dot light emitting display panel. The light emitting layer of the organic light emitting display panel may include an organic light emitting material, and the light emitting layer of the inorganic light emitting display panel may include an inorganic light emitting material. The light emitting layer of the quantum dot light emitting display panel may include quantum dots and quantum rods. Hereinafter, the display panel DP will be described as an organic light emitting display panel.

The light control member LCM may be disposed on the display panel DP. After the light control member LCM is provided on the display panel DP, it may be combined with the display panel DP through a bonding process. In this specification, the display panel DP formed below the display module DM may be defined as a first substrate, and the light control member LCM bonded to the first substrate may be defined as a second substrate. .

The light control member LCM may convert a wavelength of light provided by the display panel DP or selectively transmit light provided by the display panel DP. Also, the light control member LCM may prevent reflection of external light incident from the outside of the electronic device DD.

The outer case HAU may be disposed under the display module DM to accommodate the display module DM. The outer case HAU may protect the display module DM by absorbing shock applied to the display module DM from the outside and preventing foreign substances/moisture from penetrating into the display module DM. The outer case HAU according to an embodiment may be provided in a form in which a plurality of accommodating members are combined.

Meanwhile, the electronic device DD may further include an input detection module, and the input detection module may acquire coordinate information of an external input applied from the outside of the electronic device DD. The input sensing module of the electronic device DD may be driven in various ways such as a capacitive type, a resistive type, an infrared type, or a pressure type, and is not limited to any one.

In one embodiment, the input detection module may be disposed on the display module DM. The input sensing module may be directly disposed on the display module DM through a continuous process, or may be manufactured separately from the display module DM and attached to the display module DM by an adhesive layer. Without being limited thereto, in one embodiment, the input detection module may be disposed between components of the display module DM. For example, the input detection module may be disposed between the display panel DP and the light control member LCM.

The electronic device DD includes an electronic module including various functional modules for operating the display module DM, a power supply module supplying power necessary for the electronic device DD, the display module DM, and/or an external case ( HAU) and may further include a bracket dividing the internal space of the electronic device (DD).

3 is a cross-sectional view of a display module according to an exemplary embodiment. Referring to FIG. 3 , the display module DM may include a display panel (DP, or first substrate) and a light control member (LCM, or second substrate). The above description may be equally applied to the display panel DP and the light control member LCM.

The display panel DP may include a first base substrate SUB1 or a lower substrate, a circuit layer DP-CL, a light emitting device layer DP-OL, and an encapsulation layer TFE.

The first base substrate SUB1 may include a glass substrate, a polymer substrate, or an organic/inorganic composite material substrate. The first base substrate SUB1 may include upper and lower surfaces parallel to each of the first and second directions DR1 and DR2 . The circuit layer DP-CL, the light emitting element layer DP-OL, and the encapsulation layer TFE may be sequentially stacked and formed on the upper surface of the first base substrate SUB1, which will be defined as the first substrate. can

The light emitting element layer DP-OL may include light emitting elements disposed to overlap the display area DA. The circuit layer DP-CL may be disposed between the light emitting device layer DP-OL and the first base substrate SUB1 and may include driving devices, signal lines, and signal pads connected to the light emitting devices. The light emitting elements of the light emitting element layer DP-OL may provide source light (or first light) toward the light control member LCM within the display area DA.

The encapsulation layer TFE is disposed on the light emitting element layer DP-OL to seal the light emitting elements. The encapsulation layer TFE may include a plurality of thin films. Thin films of the encapsulation layer TFE may be disposed to improve optical efficiency of light emitting elements or to protect light emitting elements.

The light control member LCM may include a second base substrate SUB2 or an upper substrate, a color filter layer CFL, and a light conversion layer LCL.

The second base substrate SUB2 may include a glass substrate, a polymer substrate, or an organic/inorganic composite material substrate. The second base substrate SUB2 may include a front surface and a rear surface parallel to each of the first and second directions DR1 and DR2 . The rear surface of the second base substrate SUB2 may face the top surface of the first base substrate SUB1. The color filter layer CFL and the light conversion layer LCL may be sequentially stacked and formed on the rear surface of the second base substrate SUB2, which may be defined as the second substrate.

The light conversion layer LCL is disposed to overlap the display area DA, and may include light conversion units that convert optical properties of source light provided by the light emitting device. The light conversion layer LCL may selectively convert or transmit the color of source light. A portion of the light conversion layer LCL may overlap the peripheral area NDA.

The color filter layer CFL may be disposed to overlap the display area DA, and transmit light selectively converted or transmitted by the light conversion layer LCL. The color filter layer CFL absorbs light passing through without being converted by the light conversion layer LCL, thereby preventing color purity of the electronic device DD (refer to FIG. 1 ) from deteriorating. The color filter layer CFL may include color filters displaying the same color as the pixel. Through this, the color filter layer CFL can filter external light into the same colors as the pixels and reduce external light reflectance.

A portion of the color filter layer CFL may be disposed to overlap the peripheral area NDA. The color filter layer CFL may include color filters sequentially stacked in the peripheral area NDA, and may absorb light emitted or reflected through the peripheral area NDA.

The sealing member SAL may be disposed between the display panel DP and the light control member LCM to couple the display panel DP and the light control member LCM. The sealing member SAL may be disposed to overlap the peripheral area NDA. The display panel DP and the light control member LCM may be manufactured through separate processes. For example, elements of the display panel DP may be formed on the first base substrate SUB1 and elements of the light control member LCM may be formed on the second base substrate SUB2 through a separate process. there is. After that, the display panel DP and the light control member LCM may be adhered to each other by the sealing member SAL and provided to the display module DM. The sealing member SAL may include an ultraviolet curing material.

The filling member FL is disposed between the display panel DP and the light control member LCM to fill an empty space between the display panel DP and the light control member LCM overlapping the display area DA. can In one embodiment, the filling member FL may be disposed between the encapsulation layer TFE of the display panel DP and the light conversion layer LCL of the light control member LCM. The filling member FL may include a silicone, epoxy, or acrylic-based thermosetting material. However, the material of the filling member FL is not limited to the above example.

A distance between the first substrate and the second substrate in the display area, that is, a gap may affect luminance of an image. Depending on the arrangement of the stacked structures, the thicknesses of the first and second substrates corresponding to the peripheral area may be smaller than the thicknesses of the first and second substrates corresponding to the display area. In this case, in the process of bonding the first substrate and the second substrate, portions of peripheral regions of the first substrate and the second substrate bonded by the sealing member may bend toward each other. As a result, a deviation may occur between a gap between the first and second substrates at the boundary of the display area adjacent to the peripheral area and a gap between the first and second substrates at the center of the display area. According to the present invention, a gap deviation according to regions of a first substrate and a second substrate can be compensated for by disposing a spacer supporting a sealing member in the process of forming a first substrate or a second substrate, and image reliability of an electronic device can be improved. can be improved A detailed description of this will be described later.

4 is a plan view of a display panel according to an exemplary embodiment. Referring to FIG. 4 , the first base substrate SUB1 of the display panel DP may include a display area DA and a peripheral area NDA. The display panel DP may include pixels PX11 to PXnm disposed in the display area DA and signal lines GL1 to GLn and DL1 to DLm electrically connected to the pixels PX11 to PXnm. . The display panel DP may include a driving circuit GDC and pads PD disposed in the peripheral area NDA.

Each of the pixels PX11 to PXnm may include a pixel driving circuit including a light emitting element to be described later and a plurality of transistors (eg, a switching transistor, a driving transistor, etc.) connected to the light emitting element. The pixels PX11 to PXnm may emit light in response to electrical signals applied to the pixels PX11 to PXnm. Although FIG. 4 illustratively illustrates the pixels PX11 to PXnm arranged in a matrix form, the arrangement of the pixels PX11 to PXnm is not limited thereto.

The signal lines GL1 to GLn and DL1 to DLm may include gate lines GL1 to GLn and data lines DL1 to DLm. Each of the pixels PX11 to PXnm may be connected to a corresponding gate line among the gate lines GL1 to GLn and a corresponding data line among the data lines DL1 to DLm. Depending on the configuration of the pixel driving circuit of the pixels PX11 to PXnm, more types of signal lines may be provided in the display panel DP.

The driving circuit GDC may include a gate driving circuit. The gate driving circuit may generate gate signals and sequentially output the gate signals to the gate lines GL1 to GLn. The gate driving circuit may further output another control signal to the pixel driving circuits of the pixels PX11 to PXnm.

The pads PD may be arranged along one direction on the peripheral area NDA. The pads PD may be parts connected to the circuit board. Each of the pads PD may be connected to a corresponding signal line among the plurality of signal lines GL1 to GLn and DL1 to DLm, and may be connected to a corresponding pixel through the signal line. The pads PD may have an integral shape with the signal lines GL1 to GLn and DL1 to DLm. However, it is not limited thereto, and the pads PD may be disposed on a different layer from the signal lines GL1 to GLn and DL1 to DLm and connected through contact holes.

FIG. 4 exemplarily illustrates a sealing member arrangement area SAL-a corresponding to an area in which the sealing member SAL (see FIG. 3 ) is disposed on a plane. The sealing member arrangement area SAL-a overlaps the peripheral area NDA and may correspond to a portion of the peripheral area NDA. The sealing member disposing area SAL-a is adjacent to the edge of the display panel DP and may extend along an extending direction of the edge of the display panel DP. The sealing member arrangement area SAL-a may surround the display area DA on a plane. In one embodiment, the sealing member arrangement area SAL-a may be defined outside the driving circuit GDC.

5A and 5B are enlarged plan views of a display panel according to an exemplary embodiment.

5A and 5B , the display area DA includes light emitting areas PXA1 , PXA2 , and PXA3 corresponding to light emitting elements and a non-light emitting area NPXA surrounding the light emitting areas PXA1 , PXA2 , and PXA3 . ) may be included. 5A and 5B illustrate shapes of the light emitting regions PXA1 , PXA2 , and PXA3 .

The light emitting areas PXA1 , PXA2 , and PXA3 may correspond to areas from which light provided from the light emitting device is emitted. The light emitting areas PXA1 , PXA2 , and PXA3 may include a first light emitting area PXA1 , a second light emitting area PXA2 , and a third light emitting area PXA3 . The first to third light emitting regions PXA1 , PXA2 , and PXA3 may be classified according to the color of light emitted toward the outside of the electronic device DD. The non-emission area NPXA sets boundaries between the first to third light-emitting areas PXA1 , PXA2 , and PXA3 and prevents color mixing between the first to third light-emitting areas PXA1 , PXA2 , and PXA3 . there is.

one of the first to third light emitting regions PXA1 , PXA2 , and PXA3 provides a first color light corresponding to the source light provided by the light emitting device, and the other provides a second color light different from the first color light; The other one may provide a third color light different from the first color light and the second color light. For example, the first color light may be blue light, the second color light may be red light, and the third color light may be green light. However, examples of color light are not necessarily limited to the above examples.

The first to third light emitting areas PXA1 , PXA2 , and PXA3 may be repeatedly arranged in a predetermined arrangement in the display area DA. Some of the first to third light emitting regions PXA1 , PXA2 , and PXA3 may be arranged in rows along the first direction DR1 , and a plurality of rows may be arranged in the second direction DR2 . .

The first to third light emitting regions PXA1 , PXA2 , and PXA3 may have various shapes on a plane. For example, the first to third light emitting regions PXA1 , PXA2 , and PXA3 may have a polygonal shape such as a quadrangle, a circular shape, or an elliptical shape. The first to third light emitting regions PXA1 , PXA2 , and PXA3 may have the same shape as each other on a plane. However, the present invention is not limited thereto, and the first to third light emitting regions PXA1 , PXA2 , and PXA3 may include two or more light emitting regions having different shapes.

The first to third light emitting regions PXA1 , PXA2 , and PXA3 may have the same area on a plane. However, it is not limited thereto, and at least two or more light emitting areas among the first to third light emitting areas PXA1 , PXA2 , and PXA3 may have different areas.

Areas of the first to third light emitting regions PXA1 , PXA2 , and PXA3 may be set according to the emission color. For example, among the main colors, the area of the light emitting region emitting green light may be the largest and the area of the light emitting region emitting blue light may be the smallest. However, the embodiment is not necessarily limited thereto, and may vary depending on the structure of the display panel DP. Next, referring to FIGS. 5A and 5B , an arrangement of the first to third light emitting regions PXA1 , PXA2 , and PXA3 according to an exemplary embodiment will be described.

In an embodiment, each of the first to third light emitting regions PXA1 , PXA2 , and PXA3 may have the same shape on a plane and different plane areas. Referring to FIG. 5A , the first to third light emitting regions PXA1 , PXA2 , and PXA3 may have a rectangular shape with planar areas different from each other. 5A illustrates the first to third light emitting regions PXA1 , PXA2 , and PXA3 having a rectangular shape with right angle corners, but is not limited thereto, and the first to third light emitting regions PXA1 , PXA2 , and PXA3 may have a substantially rectangular shape with rounded corners.

The first light emitting areas PXA1 arranged along the first direction DR1 may be defined as a first row, and the second light emitting areas PXA2 and the third light emitting areas PXA2 arranged along the first direction DR1 Areas PXA3 may be defined as a second row. In the second row, the second light emitting regions PXA2 and the third light emitting regions PXA3 may be alternately arranged along the first direction DR1 .

The first row including the first light emitting regions PXA1 may be provided in plurality and arranged along the second direction DR2, and similarly, the second light emitting regions PXA2 and the third light emitting regions ( A plurality of second rows including PXA3) may be provided and arranged along the second direction DR2. As shown in FIG. 5A , first rows and second rows may be alternately arranged along the second direction DR2 .

Referring to FIG. 5B , in one embodiment, the first and second light emitting regions PXA1 and PXA2 may have the same polygonal shape on a plane. The first light emitting area PXA1 may have a shape symmetrical to that of the second light emitting area PXA2 with respect to an imaginary axis extending along the second direction DR2 . The third light emitting area PXA3 may have a polygonal shape different from those of the first and second light emitting areas PXA1 and PXA2 .

The first light emitting areas PXA1 and the second light emitting areas PXA2 having symmetrical shapes may be alternately arranged in a row along the first direction DR1 . A plurality of rows including the first light emitting regions PXA1 and the second light emitting regions PXA2 may be provided and arranged along the second direction DR2 .

Each of the third light emitting regions PXA3 may be disposed between the first light emitting regions PXA1 and the second light emitting regions PXA2 along the first and second directions DR1 and DR2 . The third light emitting regions PXA3 may overlap portions of the first light emitting regions PXA1 and portions of the second light emitting regions PXA2 in the first and second directions DR1 and DR2 . there is.

Meanwhile, the arrangement of the first to third light-emitting regions PXA1, PXA2, and PXA3 shown in FIGS. 5A and 5B is exemplary, and the arrangement of the light-emitting regions may vary according to the design of the electronic device DD. can Meanwhile, the shape, area, and arrangement of the light emitting regions may be designed in various ways according to light emission efficiency according to color, and are not limited to the embodiments shown in FIGS. 5A and 5B.

6 is a cross-sectional view of a display panel according to an exemplary embodiment. Referring to FIG. 6 , the display panel DP may include a first base substrate SUB1, a circuit layer DP-CL, a light emitting element layer DP-OL, and an encapsulation layer TFE, and each component The above description may be equally applied to the description.

The display panel DP may include insulating layers, semiconductor patterns, conductive patterns, and signal lines. In the manufacturing step of the display panel DP, an insulating layer, a semiconductor layer, and a conductive layer may be formed on the first base substrate SUB1 by coating, deposition, or the like. Thereafter, the insulating layer, the semiconductor layer, and the conductive layer may be selectively patterned by photolithography. Through this process, semiconductor patterns, conductive patterns, signal lines, etc. included in the display panel DP may be formed.

Each of the pixels may have an equivalent circuit including transistors, at least one capacitor, and a light emitting device, and the equivalent circuit of the pixel may be modified in various forms. The semiconductor patterns may be arranged in a predetermined rule across the pixels according to an equivalent circuit. FIG. 6 exemplarily illustrates one transistor TR and a light emitting element OL included in a pixel.

Referring to FIG. 6 , the first base substrate SUB1 may provide a base surface on which the circuit layer DP-CL is formed. The first base substrate SUB1 may have a single-layer or multi-layer structure. For example, the multi-layered first base substrate SUB1 includes synthetic resin layers and at least one inorganic layer disposed between the synthetic resin layers, or includes a glass substrate and a synthetic resin layer disposed on the glass substrate. can include

The synthetic resin layer included in the first base substrate SUB1 includes acrylic resin, methacrylic resin, polyisoprene, vinyl resin, epoxy resin, urethane resin, cellulose resin, siloxane resin, polyamide resin, and ferryl resin. It may include at least one of a rene-based resin and a polyimide-based resin. However, the material of the first base substrate SUB1 is not limited to the above example.

The circuit layer DP-CL may be disposed on the first base substrate SUB1. The circuit layer DP-CL may include at least one insulating layer, a conductive pattern, and a semiconductor pattern. Meanwhile, the stacked structure of the circuit layer DP-CL may be variously modified according to the process step of manufacturing the circuit layer DP-CL or the configuration of elements included in the pixel, and FIG. 6 shows an example of the circuit layer ( It shows the stacked form of DP-CL). However, this is merely exemplary, and the circuit layer DP-CL of the present invention is not limited to one embodiment as long as it includes driving elements for driving pixels.

Referring to FIG. 6 , the circuit layer DP-CL includes a light blocking pattern BML, a transistor TR, connection electrodes CNE1 and CNE2, an insulating pattern GI, and a plurality of insulating layers INS10, INS11, INS12) may be included.

The light blocking pattern BML may be disposed on the first base substrate SUB1. The light blocking pattern BML may overlap the transistor TR. The light blocking pattern BML may prevent the conductive patterns included in the circuit layers DP-CL from being recognized by external light or prevent the semiconductor layer included in the transistor TR from being damaged by external light. .

The buffer layer BFL may be disposed on the first base substrate SUB1 to cover a portion of the light blocking pattern BML. A contact hole exposing a portion of the light blocking pattern BML may be defined in the buffer layer BFL. The buffer layer BFL may improve bonding force between the first base substrate SUB1 and the semiconductor pattern.

The buffer layer BFL may include an inorganic material. For example, the buffer layer BFL may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. However, the material of the buffer layer BFL is not limited to the above example.

A semiconductor pattern of the transistor TR may be disposed on the buffer layer BFL. The semiconductor pattern may include polysilicon. However, it is not limited thereto, and the semiconductor pattern may include amorphous silicon, crystalline oxide, or amorphous oxide.

The source region Sa, the drain region Da, and the channel region Aa of the transistor TR may be formed from a semiconductor pattern. The semiconductor pattern may be divided into a plurality of regions according to conductivity. For example, the semiconductor pattern may have different electrical properties depending on whether it is doped or reduced by metal oxide. A highly conductive region of the semiconductor pattern may serve as an electrode or a signal line, and may correspond to the source region Sa and the drain region Da of the transistor TR. The non-doped or non-reduced region having relatively low conductivity may correspond to the channel region (or active region) of the transistor TR.

An insulating layer may be formed on the semiconductor pattern of the transistor TR and then patterned to form the insulating pattern GI. A gate electrode Ga may be disposed on the insulating pattern GI. The gate electrode Ga may be used as a mask in a process of forming the insulating pattern GI. The gate electrode Ga may overlap the channel region Aa and may be spaced apart from the semiconductor pattern of the transistor TR with the insulating pattern GI therebetween in a thickness direction.

A plurality of insulating layers INS10 , INS11 , and INS12 may be disposed on the buffer layer BFL. Each of the plurality of insulating layers INS10 , INS11 , and INS12 may include at least one inorganic layer or organic layer. For example, the inorganic films of the insulating layers INS10, INS11, and INS12 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide, It is not limited to the above materials. The organic film of the insulating layers (INS10, INS11, INS12) is a phenolic polymer, an acrylic polymer, an imide polymer, an arylether polymer, an amide polymer, a fluorine polymer, a p-xylene polymer, a vinyl alcohol polymer, or a combination thereof. It may include one polymer, but is not limited to the above materials.

The first insulating layer INS10 is disposed on the buffer layer BFL and may cover the gate electrode Ga. A contact hole exposing a portion of the semiconductor pattern of the transistor TR may be defined in the first insulating layer INS10 .

The connection electrodes CNE1 and CNE2 may include a first connection electrode CNE1 and a second connection electrode CNE2 disposed on the first insulating layer INS10. The first connection electrode CNE1 may be connected to the source region Sa of the transistor TR through a contact hole penetrating the first insulating layer INS10. In one embodiment, the first connection electrode CNE1 may be connected to the light blocking pattern BML through a contact hole penetrating the first insulating layer INS10 and the buffer layer BFL. The second connection electrode CNE2 may be connected to the drain region Da of the transistor TR through a contact hole penetrating the first insulating layer INS10. The second connection electrode CNE2 may extend on a plane and be connected to another transistor or wiring.

The second insulating layer INS11 and the third insulating layer INS12 may be disposed on the first insulating layer INS10 to cover the connection electrodes CNE1 and CNE2 . The second insulating layer INS11 and the third insulating layer INS12 may define a through hole exposing a portion of the first connection electrode CNE1 , and the first connection electrode CNE1 may have a third insulating layer ( It may be connected to the first electrode AE of the light emitting element OL disposed on the INS12). In one embodiment, the third insulating layer INS12 may include an organic layer and may provide a flat upper surface. However, the embodiments are not necessarily limited thereto.

The light emitting element layer DP-OL may be disposed on the circuit layer DP-CL. The light emitting element layer DP-OL may include a plurality of light emitting elements OL and a pixel defining layer PDL, and FIG. 6 illustrates one light emitting element OL among the plurality of light emitting elements OL. Corresponding cross sections are shown.

The display area DA may include a light emitting area PXA corresponding to the light emitting element OL and a non-emitting area NPXA surrounding the light emitting area PXA. The light emitting element OL may include a first electrode AE, a hole control layer HCL, an emission layer EML, an electron control layer ECL, and a second electrode CE.

The pixel defining layer PDL may be disposed on the third insulating layer INS12. A light emitting opening PX-OP exposing a portion of the first electrode AE may be defined in the pixel defining layer PDL. The pixel defining layer PDL may cover a portion of the upper surface of the first electrode AE. In this embodiment, a portion of the first electrode AE exposed by the light emitting opening PX-OP may correspond to the light emitting area PXA. An area where the pixel defining layer PDL is disposed may correspond to a non-emission area NPXA surrounding the emission area PXA.

The pixel defining layer (PDL) may include a polymer resin. For example, the pixel defining layer PDL may include a polyacrylate-based resin or a polyimide-based resin. The pixel defining layer (PDL) may be formed by further including an inorganic material in addition to the polymer resin. It is not limited thereto, and the pixel defining layer PDL may include an inorganic material. For example, the pixel defining layer PDL may include silicon nitride (SiN _x ), silicon oxide (SiO _x ), silicon nitride oxide (SiO _x N _y ), or the like.

Meanwhile, in one embodiment, the pixel defining layer (PDL) may include a light absorbing material. The pixel defining layer PDL may include a black coloring agent. The black component may include black dye and black pigment. The black component may include carbon black, metals such as chromium, or oxides thereof. However, the embodiment of the pixel defining layer PDL is not limited to the above example.

The hole control layer HCL may be disposed on the first electrode AE and the pixel defining layer PDL. The hole control layer HCL may be commonly disposed in a plurality of pixels. The hole control layer HCL may overlap the emission area PXA and the non-emission area NPXA. The hole control layer (HCL) may include at least one of a hole transport layer and a hole injection layer.

The light emitting layer EML may be disposed on the hole control layer HCL. The light emitting layer EML may be disposed in an area corresponding to the light emitting opening PX-OP of the pixel defining layer PDL. The light emitting layer EML may include organic light emitting materials, inorganic light emitting materials, quantum dots, quantum rods, and the like. The light emitting layer EML may be separated from each of the pixels and formed in the form of a light emitting pattern. However, it is not limited thereto, and the light emitting layer EML may be formed of a common layer commonly provided to the pixels. The light emitting layer EML may generate first light that is a source light. For example, the first light may be blue light, but the embodiment is not necessarily limited thereto.

Meanwhile, in one embodiment, the light emitting device OL may be a light emitting device having a tandem structure including a plurality of light emitting layers. A plurality of light emitting layers may be stacked along the thickness direction on the first electrode AE. Some of the plurality of light emitting layers may generate light of substantially the same color, and some of the light emitting layers may generate light of different colors. For example, the light emitting element OL of one embodiment may include four light emitting layers, three light emitting layers of the four light emitting layers may generate blue light, and one light emitting layer may generate green light. . However, this is just one example and the structure of the light emitting layer EML is not necessarily limited thereto. The light emitting device of the tandem structure may further include functional layers such as a hole control layer, an electron control layer, and a charge generation layer disposed between the plurality of light emitting layers.

The electronic control layer ECL may be disposed on the light emitting layer EML. The electronic control layer ECL may be commonly disposed in a plurality of pixels. The electronic control layer ECL may overlap the emission area PXA and the non-emission area NPXA. The electron control layer (ECL) may include at least one of an electron transport layer and an electron injection layer.

The second electrode CE may be disposed on the electronic control layer ECL. The second electrode CE may be disposed in common with a plurality of pixels. The second electrode CE may overlap the emission area PXA and the non-emission area NPXA. A common voltage may be provided to the second electrode CE, and the second electrode CE may be referred to as a common electrode.

A first voltage may be applied to the first electrode AE through the transistor TR, and a common voltage may be applied to the second electrode CE. Holes injected into the light emitting layer EML are combined with electrons to form excitons, and the light emitting element OL may emit light while the excitons transition to a ground state.

The encapsulation layer TFE may be disposed on the light emitting device layer DP-OL to seal the light emitting device layer DP-OL. The encapsulation layer TFE may include first to third encapsulation films EN1 , EN2 , and EN3 . The first encapsulation film EN1 may be disposed on the second electrode CE, and the second encapsulation film EN2 and the third encapsulation film EN3 may be sequentially disposed on the first encapsulation film EN1. can

In an embodiment, the first and third encapsulation layers EN1 and EN3 may include an inorganic layer, and the inorganic layer may protect the light emitting element layer DP-OL from moisture and/or oxygen. For example, the inorganic layer may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide, but is not limited to the above example.

In an embodiment, the second encapsulation layer EN2 may include an organic layer, and the organic layer may protect the light emitting device layer DP-OL from foreign substances such as dust particles. For example, the organic layer may include an acryl-based resin, but is not limited to the above example.

7 is a cross-sectional view of a display module according to an exemplary embodiment. FIG. 7 illustrates a partial cross section of the display module DM corresponding to the first to third light emitting areas PXA1 , PXA2 , and PXA3 disposed in the center of the display area DA. The description of each component of the display module DM shown in FIG. 7 may be equally applied to the above description.

Referring to FIG. 7 , the light emitting device layer DP-OL may include a plurality of light emitting devices OL1, OL2, and OL3. Each of the plurality of light emitting devices OL1 , OL2 , and OL3 may include the above-described first electrode AE, the light emitting layer EML, and the second electrode CE. Although not shown in FIG. 7, each of the plurality of light emitting elements OL1, OL2, and OL3 may further include the aforementioned hole control layer (HCL, see FIG. 6) and electron control layer (ECL, see FIG. 6). there is.

Each of the first electrodes AE of the plurality of light emitting devices OL1 , OL2 , and OL3 may be disposed spaced apart from each other on the circuit layer DP-CL. A plurality of light emitting openings PX-OP exposing portions of the first electrodes AE may be defined in the pixel defining layer PDL. The first electrodes AE of the first to third light emitting devices OL1 , OL2 , and OL3 exposed by the plurality of light emitting openings PX-OP are respectively the first to third light emitting regions PXA1 , PXA2 and PXA3).

The light emitting layers EML of the plurality of light emitting devices OL1 , OL2 , and OL3 may be provided in a pattern form disposed to correspond to the light emitting openings PX-OP, respectively. However, the present invention is not limited thereto, and the light emitting layers EML of the plurality of light emitting elements OL1 , OL2 , and OL3 may be provided to have an integral shape.

The second electrodes CE of the plurality of light emitting elements OL1 , OL2 , and OL3 may be connected to each other and provided in an integral shape. The integrally shaped second electrode CE may overlap the first to third light emitting areas PXA1 , PXA2 , and PXA3 and the non-light emitting area NPXA.

The light control member LCM may be disposed on the display panel DP. The light control member LCM may include a second base substrate SUB2, a color filter layer CFL, a low refractive index layer LR, and a light conversion layer LCL. The light control member LCM includes a first capping layer CP1 disposed between the low refractive index layer LR and the light conversion layer LCL and a second capping layer CP2 disposed on the rear surface of the light conversion layer LCL. ) may be further included. Each of the low refractive index layer LR, the first capping layer CP1 and the second capping layer CP2 may be defined as an insulating layer.

The rear surface of the second base substrate SUB2 may face the top surface of the first base substrate SUB1. Referring to FIG. 7 , the color filter layer CFL, the low refractive index layer LR, the first capping layer CP1, the light conversion layer LCL, and the second capping layer CP2 are formed on the second base substrate SUB2. It can be arranged sequentially on the rear surface. That is, in the manufacturing process of the light control member LCM, the rear surface of the second base substrate SUB2 may serve as a base surface on which the color filter layer CFL and the light conversion layer LCL are formed.

The color filter layer CFL may include a first color filter CF1 , a second color filter CF2 , and a third color filter CF3 . The first to third color filters CF1 , CF2 , and CF3 are patterned to overlap corresponding regions among the first to third light emitting regions PXA1 , PXA2 , and PXA3 on the rear surface of the second base substrate SUB2 . can be provided in the form That is, the first to third color filters CF1 , CF2 , and CF3 may be disposed to correspond to the first to third light emitting regions PXA1 , PXA2 , and PXA3 on a plane, respectively.

Specifically, the first color filter CF1 may be disposed to overlap the first light emitting area PXA1, and the second color filter CF2 may be disposed to overlap the second light emitting area PXA2. The 3 color filter CF3 may be disposed to overlap the third light emitting area PXA3. Descriptions of the first to third color filters CF1 , CF2 , and CF3 will be described later in detail.

The low refractive index layer LR may be disposed on the rear surface of the second base substrate SUB2 to cover the lower surface (or rear surface) of the color filter layer CFL. The low refractive index layer LR may have a refractive index smaller than that of each of the first light conversion part WCP1, the second light conversion part WCP2, and the transmission part WCP3, which will be described later. For example, the refractive index of the low refractive index layer LR may be greater than or equal to 1.1 and less than or equal to 1.3. However, the refractive index of the low refractive index layer LR is not limited to the numerical example.

The low refractive index layer LR may include an organic material. The low refractive index layer LR may further include scattering particles dispersed in a resin containing an organic material. The low refractive index layer LR can improve light efficiency of the electronic device (DD, see FIG. 2 ) through recirculation of light using a refractive index. Meanwhile, in one embodiment, the low refractive index layer LR may be omitted.

The first capping layer CP1 may be disposed on the lower surface of the low refractive index layer LR. In one embodiment, the first capping layer CP1 may be provided on a base surface on which the light conversion layer LCL is formed, and may protect the light conversion layer LCL and the color filter layer CFL. The first capping layer CP1 of one embodiment may include an inorganic material.

Meanwhile, the stacking order of components of the light control member LCM is not limited to that shown in FIG. 7 . For example, the light control member LCM according to an embodiment includes a color filter layer CFL, a light conversion layer LCL, and a low refractive index layer LR sequentially disposed on the rear surface of the second base substrate SUB2. can do. The light control member (LCM) of another embodiment includes a plurality of low refractive index layers, and one low refractive index layer among the plurality of low refractive index layers is disposed between the color filter layer (CFL) and the light conversion layer (LCL). and another low refractive index layer may be disposed on the rear surface of the light conversion layer LCL. The stacking order of the color filter layer (CFL), the low refractive index layer (LR), and the light conversion layer (LCL) constituting the light control member (LCM) may be variously modified according to embodiments.

The light conversion layer LCL may include a first light conversion part WCP1 , a second light conversion part WCP2 , a transmission part WCP3 , and a bank part BK. 7 illustrates a cross section in which first and second light conversion units WCP1 and WCP2 and a transmission unit WCP3 are provided as one, respectively, but the first and second light conversion units WCP1 and WCP2 and the transmission unit WCP3 are provided. ) may be provided in plurality within the display area DA, and the bank unit BK includes a plurality of first light conversion units WCP1, a plurality of second light conversion units WCP2, and a plurality of transmission units WCP3. ) can be surrounded.

The first light conversion part WCP1 , the second light conversion part WCP2 , and the transmission part WCP3 may be disposed on a plane to correspond to the first to third light emitting regions PXA1 , PXA2 , and PXA3 . Specifically, the first light conversion unit WCP1 may be disposed to overlap the first light emitting area PXA1, and the second light conversion unit WCP2 may be disposed to overlap the second light emitting area PXA2. The transmission part WCP3 may be disposed to overlap the third light emitting area PXA3.

The second capping layer CP2 may be disposed on the lower surface (or rear surface) of the light conversion layer LCL to cover the light conversion layer LCL. The second capping layer CP2 may prevent moisture or foreign matter from penetrating the light conversion layer LCL. The second capping layer CP2 of one embodiment may include an inorganic material.

Each of the first light conversion unit WCP1 and the second light conversion unit WCP2 may include a base resin and quantum dots dispersed in the base resin. The quantum dots may convert a wavelength range of source light provided from the light emitting devices OL1 , OL2 , and OL3 . For example, the first light conversion unit WCP1 may include first quantum dots that convert the first light provided by the first light emitting element OL1 into second light having a wavelength range different from that of the first light. can The second light conversion unit WCP2 may include second quantum dots that convert the first light provided by the second light emitting element OL2 into third light having a wavelength range different from that of the first light. Here, the wavelength range of the second light and the wavelength range of the third light may be different.

The light emitting elements OL1 , OL2 , and OL3 may provide source light (or first light). In one embodiment, the source light may be blue light, but is not limited thereto. For example, the source light may correspond to light provided by stacking light emitting layers emitting blue light and at least one light emitting layer emitting green light. The first quantum dots of the first light conversion unit WCP1 may convert source light incident from the first light emitting element OL1 to the first light conversion unit WCP1 into green light. The second quantum dots of the second light conversion unit WCP2 may convert source light incident from the second light emitting device OL2 to the second light conversion unit WCP2 into red light.

The transmission part WCP3 may include a base resin. The transmission part WCP3 may transmit source light provided from the third light emitting element OL3. For example, the third light emitting element OL3 may provide blue light, and the blue light may pass through the transmission part WCP3 and be emitted toward the front surface of the display module DM. The transmission part WCP3 according to an embodiment may further include scattering particles dispersed in the base resin. The scattering particles of the transmission part WCP3 may scatter the light incident toward the transmission part WCP3 in various directions.

Accordingly, the display module DM can emit green light through the first light emitting area PXA1, emit red light through the second light emitting area PXA2, and emit light through the third light emitting area PXA3. Through this, blue light can be emitted. The display module DM may display a predetermined image in the display area DA through the first to third light emitting areas PXA1 , PXA2 , and PXA3 respectively displaying green, red, and blue. However, the color of light emitted through the regions is not necessarily limited thereto.

Meanwhile, at least one of the first light conversion unit WCP1 and the second light conversion unit WCP2 may further include scattering particles. The scattering particles scatter the first light incident from the light emitting devices OL1 , OL2 , and OL3 toward the light conversion unit to improve light conversion efficiency by the quantum dots in the light conversion unit.

The cores of the quantum dots included in the first light conversion unit WCP1 and the second light conversion unit WCP2 include a group II-VI compound, a group III-VI compound, a group I-III-VI compound, a group III-V compound, It may be selected from Group IV-VI compounds, Group IV elements, Group IV compounds, and combinations thereof.

Group II-VI compounds are CdSe, CdTe, CdS, ZnS, ZnSe, ZnTe, ZnO, HgS, HgSe, HgTe, MgSe, MgS and a binary element compound selected from the group consisting of mixtures thereof, CdSeS, CdSeTe, CdSTe, ZnSeS , ZnSeTe, ZnSTe, HgSeS, HgSeTe, HgSTe, CdZnS, CdZnSe, CdZnTe, CdHgS, CdHgSe, CdHgTe, HgZnS, HgZnSe, HgZnTe, MgZnSe, MgZnS, and a ternary compound selected from the group consisting of mixtures thereof, and HgZnTeS, C dZnSeS , CdZnSeTe, CdZnSTe, CdHgSeS, CdHgSeTe, CdHgSTe, HgZnSeS, HgZnSeTe, HgZnSTe, and a quaternary compound selected from the group consisting of mixtures thereof.

The group III-VI compound may include a binary compound such as In2S3, In2Se3, or the like, a ternary compound such as InGaS3, InGaSe3, or the like, or any combination thereof.

Group I-III-VI compounds may be selected from ternary compounds selected from the group consisting of AgInS, AgInS2, CuInS, CuInS2, AgGaS2, CuGaS2 CuGaO2, AgGaO2, AgAlO2 and mixtures thereof, or quaternary compounds such as AgInGaS2 and CuInGaS2. can

Group III-V compounds are GaN, GaP, GaAs, GaSb, AlN, AlP, AlAs, AlSb, InN, InP, InAs, InSb, and binary element compounds selected from the group consisting of mixtures thereof, GaNP, GaNAs, GaNSb, and GaPAs. ternary compounds selected from the group consisting of GaPSb, AlNP, AlNAs, AlNSb, AlPAs, AlPSb, InGaP, InAlP, InNP, InNAs, InNSb, InPAs, InPSb and mixtures thereof, and GaAlNP, GaAlNAs, GaAlNSb, GaAlPAs, GaAlPSb , GaInNP, GaInNAs, GaInNSb, GaInPAs, GaInPSb, InAlNP, InAlNAs, InAlNSb, InAlPAs, InAlPSb, and quaternary compounds selected from the group consisting of mixtures thereof. Meanwhile, the group III-V compound may further include a group II metal. For example, InZnP and the like may be selected as the III-II-V compound.

Group IV-VI compounds are SnS, SnSe, SnTe, PbS, PbSe, PbTe, and binary element compounds selected from the group consisting of and mixtures thereof, SnSeS, SnSeTe, SnSTe, PbSeS, PbSeTe, PbSTe, SnPbS, SnPbSe, SnPbTe, and these It may be selected from the group consisting of a three-element compound selected from the group consisting of a mixture of, and a quaternary compound selected from the group consisting of SnPbSSe, SnPbSeTe, SnPbSTe, and mixtures thereof. Group IV elements may be selected from the group consisting of Si, Ge, and mixtures thereof. The group IV compound may be a binary element compound selected from the group consisting of SiC, SiGe, and mixtures thereof.

In this case, the two-element compound, the three-element compound, or the quaternary element compound may be present in the particle at a uniform concentration or may be present in the same particle in a state in which the concentration distribution is partially different.

Quantum dots may have a core-shell structure including a core and a shell surrounding the core. Also, in one embodiment, one quantum dot may have a core/shell structure surrounding another quantum dot. The interface between the core and the shell may have a concentration gradient in which the concentration of elements present in the shell decreases toward the center.

In one embodiment, the quantum dot may have a core-shell structure including the aforementioned nanocrystal. The shell of the quantum dots may serve as a protective layer for maintaining semiconductor properties by preventing chemical denaturation of the core and/or as a charging layer for imparting electrophoretic properties to the quantum dots. The shell may be monolayer or multilayer. The interface between the core and the shell may have a concentration gradient in which the concentration of elements present in the shell decreases toward the center. Examples of the quantum dot shell include metal oxides, oxides of non-metals, semiconductor compounds, or combinations thereof.

For example, metal oxides and non-metal oxides are SiO ₂ , Al ₂ O ₃ , TiO2, ZnO, MnO, Mn ₂ O ₃ , Mn ₃ O ₄ , CuO, FeO, Fe ₂ O ₃ , Fe ₃ O ₄ , CoO , Co ₃ O ₄ , binary element compounds such as NiO, or MgAl ₂ O ₄ , CoFe ₂ O ₄ , NiFe ₂ O ₄ , CoMn ₂ O ₄ may include a ternary element compound such as, but the material is limited to the above example. It is not.

In addition, the semiconductor compound may include CdS, CdSe, CdTe, ZnS, ZnSe, ZnTe, ZnSeS, ZnTeS, GaAs, GaP, GaSb, HgS, HgSe, HgTe, InAs, InP, InGaP, InSb, AlAs, AlP, AlSb, and the like. However, the material is not limited to the above examples.

The quantum dots may have a full width of half maximum (FWHM) of the emission wavelength spectrum of about 45 nm or less, preferably about 40 nm or less, and more preferably about 30 nm or less, and improve color purity or color reproducibility within the above range can make it In addition, since light emitted through the quantum dots is emitted in all directions, a wide viewing angle may be improved.

The shape of the quantum dots is not particularly limited to those commonly used in the field, but examples include spherical, pyramidal, multi-arm, or cubic nanoparticles, nanotubes, nanowires, Forms such as nanofibers and nanoplate-like particles can be used.

Quantum dots can control the color of light emitted according to the particle size, and thus, quantum dots can have various luminous colors such as blue, red, and green. Meanwhile, when the light emitting layer EML includes the quantum dot material, the above description of the quantum dot may be equally applied to the quantum dot material included in the light emitting layer EML.

The bank part BK may overlap the non-emission area NPXA on a plane. In the bank part BK, a plurality of openings BK-OP corresponding to the first to third light emitting regions PXA1 , PXA2 , and PXA3 may be defined. The first light conversion unit WCP1 , the second light conversion unit WCP2 , and the transmission unit WCP3 may be disposed to correspond to the plurality of openings BK-OP defined in the bank unit BK, respectively.

The bank part BK may include a material having a predetermined color. For example, the bank portion BK may include black dye or black pigment. The bank unit BK may prevent color mixing by setting a boundary between the first light conversion unit WCP1 , the second light conversion unit WCP2 , and the transmission unit WCP3 .

Each of the first to third color filters CF1 , CF2 , and CF3 may include a base resin and a pigment or dye dispersed in the base resin. Each of the first to third color filters CF1 , CF2 , and CF3 may transmit light having a predetermined wavelength range and absorb most of light having a wavelength range outside the predetermined wavelength range. For example, one of the first to third color filters CF1 , CF2 , and CF3 may include a red color filter, the other may include a green color filter, and the other may include a blue color filter. can include

The red color filter can transmit red light and absorb most of green light and blue light. The green color filter can transmit green light and absorb most of red light and blue light. The blue color filter can transmit blue light and absorb most of red light and green light.

The first color filter CF1 may be disposed on the first light conversion unit WCP1. The first color filter may transmit second light provided from the first light conversion unit WCP1. For example, the first light conversion unit WCP1 may convert blue light provided from the first light emitting element OL1 into green light, and the first color filter CF1 may convert the first light conversion unit WCP1 to green light. It can transmit green light provided from. The first color filter CF1 may absorb first and third light incident toward the first color filter CF1. Therefore, it is possible to prevent color purity from deteriorating in the first light emitting area PXA1 by absorbing the first light incident toward the first color filter CF1 without being changed by the first light conversion unit WCP1. there is.

The second color filter CF2 is disposed on the second light conversion unit WCP2 to transmit third light provided from the second light conversion unit WCP2. For example, the second light conversion unit WCP2 may convert blue light provided from the second light emitting element OL2 into red light, and the second color filter CF2 may convert the second light conversion unit WCP2 to red light. It can transmit red light provided from. The second color filter CF2 may absorb the first light and the second light incident toward the second color filter CF2. Therefore, it is possible to prevent color purity from deteriorating in the second light emitting area PXA2 by absorbing the first light incident toward the second color filter CF2 without being changed by the second light conversion unit WCP2. there is.

The third color filter CF3 is disposed on the transmission part WCP3 to transmit the first light passing through the transmission part WCP3. For example, the transmission part WCP3 may transmit blue light provided from the third light emitting element OL3, and the blue light passing through the transmission part WCP3 may pass through the third color filter CF3.

External light, such as natural light, may be incident toward the display panel DP from the outside of the display module DM. The external light may include red light, green light, and blue light. If the display module DM does not include the color filter layer CFL, external light incident toward the display panel DP may affect the conductive patterns (eg, signal lines, electrodes) inside the display panel DP. etc.) and provided to the user, and the user can view the reflected light.

The first to third color filters CF1 , CF2 , and CF3 may prevent reflection of external light. The first color filter CF1 transmitting the second light may absorb light corresponding to a wavelength range of the first light and the third light among light provided from the outside. For example, the first color filter CF1 may be a green color filter, absorb red light and blue light among external light, and filter the light into green light. According to the same principle, the second color filter CF2 may be a red color filter, and may absorb green light and blue light among external light and filter them into red light. The third color filter CF3 may be a blue color filter, absorb red light and green light among external light, and filter the light into blue light.

According to an embodiment, the first to third color filters CF1 , CF2 , and CF3 may overlap each other within the non-emission area NPXA. For example, the first to third color filters CF1 , CF2 , and CF3 may be disposed to overlap each other along the third direction DR3 in the non-emission area NPXA. The first to third color filters CF1 , CF2 , and CF3 disposed to overlap each other block light passing through the non-emission area NPXA, thereby providing light between the first to third light-emission areas PXA1 , PXA2 , and PXA3 . color mixing can be prevented. Meanwhile, although FIG. 7 illustratively illustrates the color filters CF1, CF2, and CF3 overlapping each other in the non-emission area NPXA, the embodiment is not limited thereto, and the color filters CF1, CF2, CF3) may be spaced apart from each other with the non-emission area NPXA interposed therebetween.

The color filter layer CFL surrounds the first to third color filters CF1, CF2, and CF3 and further includes a barrier rib defining a boundary between the first to third color filters CF1, CF2, and CF3. can do. The barrier rib of the color filter layer (CFL) may include a material having a predetermined color, and for example, the barrier rib may include a black pigment or black dye. The barrier rib of the color filter layer (CFL) can absorb light and prevent color mixing.

Through one process, the circuit layer DP-CL, the light emitting element layer DP-OL, and the encapsulation layer TFE are sequentially stacked on the upper surface of the first base substrate SUB1 along the third direction DR3. Thus, a first substrate including the display panel DP may be formed. Through another process, the color filter layer (CFL), the low refractive index layer (LR), the first capping layer (CP1), the light conversion layer (LCL) and the second capping layer are formed on the rear surface of the second base substrate (SUB2). CP2 may be sequentially stacked along the third direction DR3 to form a second substrate including the light control member LCM.

An upper surface of the manufactured first substrate and a rear surface of the second substrate may face each other, and the filling member FL may be applied between the first substrate and the second substrate. Specifically, in one embodiment, the filling member FL may be disposed between the encapsulation layer TFE of the first substrate and the light conversion layer LCL of the second substrate. The display panel DP and the light control member LCM may be bonded with the filling member FL interposed therebetween, and the space between the first and second substrates overlapping the display area DA is formed by the filling member FL. ) can be filled by

In one embodiment, the distance between the first substrate and the second substrate may affect light emission efficiency of the display module DM. Specifically, as shown in FIG. 7 , the gap Gpa between the first light emitting element OL1 of the first substrate and the first light conversion part WCP1 of the second substrate in the third direction DR3 is Light emission efficiency of the light emitting element OL1 may be affected. Similarly, the gap between the second light-converting part WCP2 of the second light-emitting element OL2 and the gap between the third light-emitting element OL3 and the transmissive part WCP3 are respectively the second and third light-emitting elements OL2, OL3) may affect the light emission efficiency.

In one embodiment of the present invention, the gap between the light emitting elements OL1, OL2, and OL3 of the first substrate and the light conversion layer LCL of the second substrate satisfies the design range of the display module DM and the display area ( DA) can have a uniform value. Accordingly, the luminance of the display module DM may be uniform within the display area DA.

8A and 8B are cross-sectional views of a display module according to an embodiment. The description of each of the components shown in FIGS. 8A and 8B may be equally applicable to the above description, and will be described focusing on components that have not been described.

8A and 8B illustrate cross-sections of the display module DM corresponding to the peripheral area NDA where the sealing member SAL is disposed and the display area DA adjacent to the peripheral area NDA. 8A and 8B show the first light emitting device OL1 corresponding to the first light emitting area PXA1 disposed in the display area DA adjacent to the peripheral area NDA, the first light conversion unit WCP1, and the first light emitting device OL1. Although the color filter CF1 is illustrated as an example, elements disposed adjacent to the peripheral area NDA are not limited thereto.

Referring to FIG. 8A , the buffer layer BFL, the first insulating layer INS10, and the second insulating layer INS11 disposed on the top surface of the first base substrate SUB1 extend from the display area DA to the peripheral area NDA. ) can be extended towards The sealing member SAL according to an embodiment may be disposed on the second insulating layer INS11 overlapping the peripheral area NDA. However, the embodiment is not necessarily limited thereto, and may vary depending on the arrangement of the insulating layer of the display panel DP. For example, the sealing member SAL may be disposed on the first insulating layer INS10 or may come into contact with the first base substrate SUB1. Meanwhile, although not separately illustrated, some of the conductive patterns of the circuit layer DP-CL may be disposed between insulating layers in the peripheral area NDA, and according to an exemplary embodiment, a portion of the conductive patterns may be formed on a plane. It may overlap the sealing member SAL.

The display panel DP may include a plurality of dams DAM1 , DAM2 , and DAM3 disposed on the peripheral area NDA. The plurality of dams DAM1 , DAM2 , and DAM3 may be disposed on the first base substrate SUB1 . In one embodiment, the plurality of dams DAM1 , DAM2 , and DAM3 may be disposed on the second insulating layer INS11 .

The plurality of dams DAM1 , DAM2 , and DAM3 may include a first dam DAM1 , a second dam DAM2 , and a third dam DAM3 disposed apart from each other along one direction. Among the plurality of dams DAM1, DAM2, and DAM3, the first dam DAM1 may be disposed closest to the display area DA, and the third dam DAM3 may be disposed farthest from the display area DA. It can be. Meanwhile, the number of the plurality of dams DAM1 , DAM2 , and DAM3 is not limited to the illustrated embodiment and may be more or less.

At least some of the plurality of dams DAM1 , DAM2 , and DAM3 may have different stacked structures. For example, the first dam DAM1 may include the same material as the third insulating layer INS12. Each of the second dam DAM2 and the third dam DAM3 may include a first film P1 and a second film P2 sequentially stacked along the third direction DR3 . The first layer P1 may include the same material as the third insulating layer INS12, and the second layer P2 may include the same material as the pixel defining layer PDL. The first film P1 of the first dam DAM1 and the second dam DAM2 and the first film P1 of the third dam DAM3 may be formed simultaneously in the process of forming the third insulating layer INS12, and , the second layer P2 of the second dam DAM2 and the second layer P2 of the third dam DAM3 may be formed simultaneously in the process of forming the pixel defining layer PDL. However, it is not limited thereto, and all of the plurality of dams DAM1 , DAM2 , and DAM3 may include the same material.

At least some of the plurality of dams DAM1 , DAM2 , and DAM3 may have different heights in the third direction DR3 . For example, the height of the first dam DAM1 may be smaller than the heights of the second dam DAM2 and the third dam DAM3. However, it is not limited thereto, and the heights of the plurality of dams DAM1 , DAM2 , and DAM3 may be equal to each other.

The first encapsulation film EN1 of the encapsulation layer TFE extends from the display area DA toward the peripheral area NDA and may be disposed on the plurality of dams DAM1 , DAM2 , and DAM3 . The first encapsulation film EN1 of the encapsulation layer TFE may contact the plurality of dams DAM1 , DAM2 , and DAM3 .

The second encapsulation film EN2 of the encapsulation layer TFE may be disposed on the first encapsulation film EN1. A formation area of the second encapsulation layer EN2 including an organic layer may be partitioned by a plurality of dams DAM1 , DAM2 , and DAM3 . In the process of manufacturing the display panel DP, the second encapsulation film EN2 having fluidity may flow toward the peripheral area NDA and be blocked by one of the plurality of dams DAM1 , DAM2 , and DAM3 . FIG. 8A illustratively illustrates the second encapsulation film EN2 in which the flow is blocked in the space between the first dam DAM1 and the second dam DAM2.

The third encapsulation film EN3 may be disposed on the second encapsulation film EN2 to cover the second encapsulation film EN2 . The third encapsulation film EN3 may extend more toward the outer side of the peripheral area NDA than the second encapsulation film EN2 . Referring to FIG. 8A , the third encapsulation film EN3 is the second dam DAM2 that blocks the flow of the second encapsulation film EN2 and the third dam DAM3 disposed outside the second dam DAM2. can be placed on top. The third encapsulation film EN3 may contact the first encapsulation film EN1 disposed on the second dam DAM2 and the third dam DAM3, and the second encapsulation film EN1 together with the first encapsulation film EN1. The film EN2 can be sealed. Accordingly, penetration of moisture or oxygen from the outside into the second encapsulation film EN2 can be prevented.

The plurality of dams DAM1 , DAM2 , and DAM3 may be spaced apart from the sealing member SAL on a plane. The plurality of dams DAM1 , DAM2 , and DAM3 may prevent the sealing layer TFE from extending to the outside of the peripheral area NDA where the sealing member SAL is disposed.

Referring to FIG. 8A , the light conversion layer LCL may further include a dummy pattern PU. The bank unit BK is disposed in the display area DA, and a portion of the bank unit BK may be disposed in the peripheral area NDA. Some of the openings BK-OP of the bank unit BK may overlap the peripheral area NDA, and the dummy pattern PU may overlap the opening BK of the bank unit BK overlapping the peripheral area NDA. -OP). The dummy pattern PU may be spaced apart from the light emitting element OL1 on a plane. The dummy pattern PU does not overlap the light emitting element OL1, and thus, light may not be emitted through the dummy pattern PU.

The dummy pattern PU may include a base resin and quantum dots. The light conversion unit of an embodiment may be formed by an inkjet method, and in order to prevent quantum dots from being uniformly distributed in the light conversion unit formed at an early stage of the process, a composition is applied before forming the light conversion unit in the display area DA. It can be preliminarily applied to a region that does not overlap with the light emitting element. The dummy pattern PU may correspond to a preliminarily formed portion before forming the light conversion unit overlapping the light emitting device. Meanwhile, in one embodiment, the dummy pattern PU may be omitted.

A portion of the color filter layer CFL may be disposed to overlap the peripheral area NDA. A portion of the color filter layer CFL overlapping the peripheral area NDA may include first to third color filters CF1 , CF2 , and CF3 stacked along the third direction DR3 . The first to third color filters CF1 , CF2 , and CF3 may include a red color filter, a green color filter, and a blue color filter.

The first to third color filters CF1 , CF2 , and CF3 disposed to overlap each other in the thickness direction may block light from being emitted or introduced through the peripheral area NDA. In addition, the first to third color filters CF1 , CF2 , and CF3 disposed to overlap each other in the third direction DR3 may prevent reflection of external light incident toward the peripheral area NDA. Meanwhile, the stacking order of the first to third color filters CF1 , CF2 , and CF3 is not limited to the illustrated one, and the first to third color filters CF1 and CF2 are stacked in the process of the light control member LCM. , CF3) may vary depending on the order of formation.

The low refractive index layer LR, the first capping layer CP1 and the second capping layer CP2 may be disposed to extend from the display area DA to the outside of the peripheral area NDA. Accordingly, the sealing member SAL may be disposed on the rear surface of the second capping layer CP2. However, the embodiments are not necessarily limited thereto.

The filling member FL may be disposed between the display panel DP corresponding to the first substrate and the light control member LCM corresponding to the second substrate so as to overlap the display area DA. Specifically, the filling member FL may be applied between the encapsulation layer TFE of the display panel DP and the light conversion layer LCL of the light control member LCM. In the process of attaching the light control member LCM and the display panel DP, the filling member FL fills an empty space between the display panel DP and the light control member LCM corresponding to the display area DA. can do. During this process, the filling member FL may flow from the display area DA toward the peripheral area NDA and be hardened.

By controlling the applied amount of the filling member FL, the filling member FL may be formed spaced apart from the sealing member SAL on a plane. Through this, overflow of the filling member FL to the outside of the sealing member SAL may be prevented. One side surface L-FL of the filling member FL may face one side surface L-SA of the sealing member in the first direction DR1. In one embodiment, one side surface L-FL of the filling member FL may be spaced apart from one side surface L-SA of the sealing member SAL. However, the filling member FL may contact the sealing member SAL in some regions without being limited thereto.

The sealing member SAL may be disposed between the first substrate and the second substrate. Specifically, the sealing member SAL may be disposed between the display panel DP and the light control member LCM in the peripheral area NDA to couple the display panel DP and the light control member LCM.

The display module DM of the present invention may include at least one spacer disposed between the display panel DP and the light control member LCM. The spacer according to an embodiment may be disposed to overlap the sealing member SAL and support the sealing member SAL.

Referring to FIG. 8A , the display module DM according to an exemplary embodiment may include a first spacer SP1 disposed to overlap the sealing member SAL. The first spacer SP1 is disposed on the rear surface of the second base substrate SUB2 and may have a predetermined thickness in a direction toward the first base substrate SUB1.

The first spacer SP1 may be formed on the second base substrate SUB2 during the manufacturing process of the light control member LCM. In one embodiment, the first spacer SP1 may be formed simultaneously during the formation of the bank portion BK of the light conversion layer LCL. The first spacer SP1 may include the same material as the bank part BK. Accordingly, the first spacer SP1 may be formed without adding a separate process step. The thickness of the first spacer SP1 may be substantially the same as or a small difference from the thickness of the bank part BK. However, the embodiment of the first spacer SP1 is not necessarily limited thereto.

The first spacer SP1 may be covered by the second capping layer CP2 covering the light conversion layer LCL. However, the embodiment is not necessarily limited thereto, and the first spacer SP1 may contact the sealing member SAL.

A width W1 of the first spacer SP1 may be greater than a width W2 of the sealing member SAL. In cross-section, the side surfaces L1-1 and L1-2 of the first spacer SP1 may protrude more in the first direction DR1 than the side surfaces L-SA of the sealing member SAL. Side surfaces L1 - 1 and L1 - 2 of the first spacer SP1 may be spaced apart from the sealing member SAL. That is, the side surfaces L1 - 1 and L1 - 2 of the first spacer SP1 may be exposed from the sealing member SAL. The entire upper surface of the sealing member SAL may overlap the rear surface of the first spacer SP1 on a plane, and the first spacer SP1 may support the entire upper surface of the sealing member SAL.

Referring to FIG. 8B , the display module DM according to an exemplary embodiment may include a second spacer SP2 disposed to overlap the sealing member SAL. The second spacer SP2 may contact the sealing member SAL. The second spacer SP2 is disposed on the upper surface of the first base substrate SUB1 and may have a predetermined thickness in a direction toward the second base substrate SUB2.

The second spacer SP2 may include a plurality of insulating layers S1 and S2 sequentially stacked along the third direction DR3 . Each of the plurality of insulating layers S1 and S2 may include an organic layer. The second spacer SP2 may include a first insulating layer S1 and a second insulating layer S2 disposed on the first insulating layer S1.

The second spacer SP2 may be formed on the first base substrate SUB1 during the manufacturing process of the display panel DP. In an embodiment, the second spacer SP2 may be simultaneously formed during the formation of the insulating layer of the circuit layer DP-CL of the display panel DP and/or the pixel defining layer PDL. For example, the first insulating layer S1 of the second spacer SP2 may include the same material as the third insulating layer INS12 of the circuit layer DP-CL, and the third insulating layer INS12 is formed. During the process, it may be simultaneously formed on the first base substrate SUB1. The second insulating layer S2 of the second spacer SP2 may include the same material as the pixel defining layer PDL, and may be simultaneously formed on the first insulating layer S1 during the formation of the pixel defining layer PDL. can Accordingly, the second spacer SP2 may be formed without adding a separate process step. However, the material included in the second spacer SP2 is not limited to the above embodiment.

The second spacer SP2 may be spaced apart from the plurality of dams DAM1 , DAM2 , and DAM3 in the first direction DR1 . The second spacer SP2 may be further spaced apart from the display area DA and closer to the outer side of the peripheral area NDA than the plurality of dams DAM1 , DAM2 , and DAM3 .

The second spacer SP2 may include the same material as the plurality of dams DAM1 , DAM2 , and DAM3 . The second spacer SP2 may be formed simultaneously during the formation of the plurality of dams DAM1 , DAM2 , and DAM3 . The thickness of the second spacer SP2 may be substantially the same as or a difference between the thicknesses of the second dam DAM2 and the third dam DAM3 made of the same material may be small. However, the embodiment of the second spacer SP2 is not necessarily limited thereto.

A width W3 of the second spacer SP2 may be greater than a width W2 of the sealing member SAL. In cross section, the side surfaces L2 - 1 and L2 - 2 of the second spacer SP2 may protrude more in the first direction DR1 than the side surfaces L-SA of the sealing member SAL. Side surfaces L2 - 1 and L2 - 2 of the second spacer SP2 may be spaced apart from the sealing member SAL. That is, the side surfaces L2 - 1 and L2 - 2 of the second spacer SP2 may be exposed from the sealing member SAL. The entire area of the lower surface of the sealing member SAL may overlap the upper surface of the second spacer SP2 on a plane, and the second spacer SP2 may support the entire area of the lower surface of the sealing member SAL.

Among the side surfaces L2-1 and L2-2 of the second spacer SP2, the side surface L2-2 adjacent to the display area DA includes a first encapsulation film EN1 extending toward the peripheral area NDA, and It may be covered by the third encapsulation film EN3. However, the embodiment is not necessarily limited thereto, and the second spacer SP2 may be spaced apart from the encapsulation layer TFE.

Referring to FIGS. 8A and 8B , since the display module DM includes the first spacer SP1 or the second spacer SP2, the sealing member SAL has the first spacer SP1 or the second spacer SP2. ) together with a gap between the first substrate and the second substrate corresponding to the peripheral area NDA. That is, at least one of the first spacer SP1 and the second spacer SP2 of the present invention is provided together with the sealing member SAL between the display panel DP corresponding to the peripheral area NDA and the light control member LCM. of space can be supported. In the process of attaching the display panel DP and the light control member LCM, the first spacer SP1 or the second spacer SP2 supports the sealing member SAL, so that the sealing member SAL can be removed without increasing the thickness of the sealing member SAL. The first base substrate SUB1 and the second base substrate SUB2 may be bonded to each other while maintaining substantially flatness without bending in the display area DA and the peripheral area NDA.

As the first base substrate SUB1 and the second base substrate SUB2 are bonded while maintaining flatness in the display area DA and the peripheral area NDA, the display panel DP is formed in the entire area of the display area DA. A gap between the light control member LCM and the light control member LCM may be uniform. Specifically, the gap Gpb between the first light emitting element OL1 and the first light conversion unit WCP1 in the display area DA adjacent to the boundary of the peripheral area NDA shown in FIG. 8A is shown in FIG. 7 . The gap Gpa between the first light emitting element OL1 and the first light conversion part WCP1 at the center of the display area DA may be substantially equal to the gap Gpa. In the display area DA adjacent to the boundary of the peripheral area NDA, the gap Gpb between the first light emitting element OL1 and the first light conversion unit WCP1 corresponds to the edge of the display area DA. As it may affect light emission efficiency of DM and the gaps Gpa and Gpb of the first light emitting element OL1 and the first light conversion part WCP1 are maintained uniformly within the display area DA, The electronic device DD may output an image having uniform luminance in the entire area of the display area DA.

In addition, in order to compensate for luminance non-uniformity due to a difference in the gap between the light emitting element and the light conversion unit at the border and the center of the display area DA, more current does not need to flow to the pixels adjacent to the edge of the display area DA. , Due to this, deterioration of the pixels disposed adjacent to the edge of the display area DA can be prevented, and a problem in which stains due to a difference in deterioration speed can be prevented from being recognized.

9A is a cross-sectional view schematically illustrating a cross-section of a display module according to a comparative example, and FIG. 9B is a cross-sectional view schematically illustrating a cross-section of a display module according to an exemplary embodiment. The display module DM′ of the comparative example illustrated in FIG. 9A does not include a spacer overlapping the sealing member SAL, and the display module DM according to an exemplary embodiment illustrated in FIG. 9B overlaps the sealing member SAL. A first spacer SP1 is included.

The sealing member SAL may be formed to have a predetermined thickness in the third direction DR3 . In order for the display panel DP and the light control member LCM to be formed substantially flat without bending from the display area DA toward the peripheral area NDA, the thickness of the sealing member SAL is It should be formed as much as the gap between the first substrate and the second substrate corresponding to the area where is to be placed. However, when the thickness of the sealing member SAL is extended beyond a predetermined value, defects may occur during the process.

As shown in FIG. 9A , when the thickness of the sealing member SAL is not sufficient to support the gap between the first and second substrates, the first base substrate ( SUB1) and the second base substrate SUB2 may bend toward each other in the third direction DR3. As the first base substrate SUB1 and the second base substrate SUB2 corresponding to the peripheral area NDA are bent, the first base substrate SUB1 corresponding to the display area DA adjacent to the peripheral area NDA is bent. A distance between the second base substrate SUB2 may be widened. Due to this, in the display module DM' of the comparative example, the gap Gpb' between the light emitting element layer DP-OL of the first substrate and the light conversion layer LCL of the second substrate may be larger than the designed gap, , A gap and a difference between the light emitting element layer DP-OL and the light conversion layer LCL corresponding to the central portion of the display area DA may occur.

As in the comparative example shown in FIG. 9A , when there is a deviation in the gap between the light emitting device layer DP-OL and the light conversion layer LCL in the display area DA, the display module DM′ is non-uniform. Images can be output with luminance. In order to compensate for such luminance non-uniformity, the electronic device of Comparative Example may further supply current to pixels adjacent to the peripheral area NDA and disposed at the edge of the display area DA. However, the deterioration speed of the pixels to which a relatively large current is supplied may increase, and a stain may be recognized in the display area DA due to a difference in the deterioration speed of the pixels.

However, as shown in FIG. 9B , the display module DM according to an exemplary embodiment may include a first spacer SP1 , and the first spacer SP1 supplements the sealing member SAL to separate the first substrate from the first substrate. It can support and fill the gap between the two boards. The first spacer SP1 prevents the first base substrate SUB1 and the second base substrate SUB2 from bending within the peripheral area NDA together with the sealing member SAL without expanding the thickness of the sealing member SAL. It may be supported between the first substrate and the second substrate.

As the first base substrate SUB1 and the second base substrate SUB2 are maintained substantially flat in the peripheral area NDA, the first base substrate corresponding to the display area DA adjacent to the peripheral area NDA ( Parts of SUB1) and the second base substrate SUB2 may also be maintained flat. As a result, the gap Gpb between the light emitting device layer DP-OL of the first substrate and the light conversion layer LCL of the second substrate may be formed to have a designed gap value, and the center of the display area DA It may be substantially the same as the gap between the light emitting element layer DP-OL and the light conversion layer LCL corresponding to . As the gap between the light emitting device layer DP-OL and the light conversion layer LCL is uniformly maintained in the display area DA, the electronic device DD achieves uniform luminance in the entire area of the display area DA. You can output the video with .

10 is a graph illustrating cell gaps according to positions of display regions of Examples and Comparative Examples. The cell gap, which is the y-axis of the graph shown in FIG. 10, is the gap between the light emitting element and the light conversion unit in one area and the gap between the light emitting element and the light conversion unit corresponding to the center of the display area DA (see FIG. 7) (Gpa , see FIG. 7). As the y-axis approaches 0, the gap between the light emitting element and the light conversion unit in one area and the gap between the light emitting element and the light conversion unit corresponding to the center of the display area (DA, see FIG. 7) (Gpa, see FIG. 7) is small, indicating that the gaps are substantially uniform. As the x-axis of the graph shown in FIG. 10 is closer to 0, it indicates that the display area (DA, see FIG. 8A) where the gap is measured is adjacent to the peripheral area (NDA, see FIG. 8A). , see FIG. 7).

The electronic device of the comparative example includes the display module of the comparative example shown in FIG. 9A , and the display module of the comparative example does not include a spacer overlapping the sealing member (SAL, see FIG. 9A ). The electronic device of the embodiment includes the display module of the embodiment shown in FIG. 9B , and the display module of the embodiment includes the first spacer SP1 overlapping the sealing member (SAL, see FIG. 9B ).

Referring to FIG. 10 , the electronic device of the comparative example is a gap (Gpb′) between the light emitting element corresponding to the display area DA adjacent to the peripheral area NDA and the light conversion unit, compared to the electronic device of the embodiment, FIG. 9A Reference) is relatively large in deviation from the gap (Gpa, see FIG. 7 ) between the light emitting element and the light conversion unit corresponding to the central portion of the display area DA. In the electronic device of the embodiment including the spacer, the gap (Gpb, see FIG. 9B ) between the light emitting element corresponding to the display area DA adjacent to the peripheral area NDA and the light conversion unit corresponds to the center of the display area DA. It can be seen that there is little deviation from the gap (Gpa, see FIG. 7) between the light emitting element and the light conversion unit, and is substantially the same.

The table below compares JND (Just Noticeable Difference) values of the electronic device of the comparative example and the electronic device of the example. The JND value is an index that numerically indicates whether or not a stain is recognized at the edge of the display area and the extent thereof. When the JND value exceeds 1, it means that the user can visually recognize a stain in the display area, and when the JND value is less than 1, it means that the user cannot visually recognize a stain.

The first test and the second test were performed by varying the brightness of the output image. The gray model expresses an image with brightness information, and can express a pixel of an image with a total of 256 levels of brightness, from level 0 corresponding to black to level 255, which is the maximum brightness. In the first test, the image was displayed in 128Gray corresponding to the median value, and in the second test, the image was displayed in 255Gray, which is the maximum brightness.

division 1st test (128Gray) 2nd test (255Gray) comparative example 1.38 1.62 Example 0.84 0.83

Referring to Table 1, it can be confirmed that the electronic device of Comparative Example has a JND value exceeding 1 in both the first test and the second test. That is, when the electronic device of Comparative Example outputs an image for a predetermined period of time or longer, a stain may be recognized at the edge of the display area. Referring to Table 1, it can be confirmed that the electronic device of the embodiment has a JND value of less than 1 in both the first test and the second test. That is, in the electronic device of the embodiment, a stain may not be recognized at the edge of the display area even if an image is output for a predetermined period of time or longer.

Since the electronic device of Comparative Example does not include a spacer overlapping the sealing member, the substrates may be bent and bonded to each other in the area where the sealing member is disposed, and as a result, in the area corresponding to the edge of the display area adjacent to the sealing member. A gap between the light conversion unit and the light emitting element may be increased. In order to output light with uniform luminance, the electronic device of Comparative Example may provide more current to pixels adjacent to the edge of the display area, resulting in a difference in deterioration rate between pixels, resulting in a difference in the display area of Comparative Example. Stains may be visible inside.

The electronic device of the embodiment includes a spacer overlapping the sealing member, so that the sealing member can be supplemented during the bonding process, and together with the sealing member, substrates spaced apart from each other can be supported and the substrates can be prevented from bending. The electronic device according to the embodiment can output light with uniform luminance without providing additional current to pixels adjacent to an edge and minimizing gap deviation between the light conversion unit and the light emitting element within the display area. Due to this, a difference in deterioration rate between pixels is reduced, and stains may not be recognized in the display area of the exemplary embodiment.

11A to 11C are cross-sectional views of display modules according to an exemplary embodiment. The display modules DM shown in FIGS. 11A to 11C include substantially the same configuration as the aforementioned display module DM, but there are differences in some configurations. Hereafter, it will be described later focusing on the differences between the embodiments.

Referring to FIGS. 11A to 11C , the display module DM according to an exemplary embodiment may include a first spacer SP1 and a second spacer SP2. The sealing member SAL may be disposed between the first spacer SP1 and the second spacer SP2. The description of the first spacer SP1 and the second spacer SP2 can be equally applied to the above description, and the arrangement between the first spacer SP1 and the second spacer SP2 and the sealing member SAL. There are some differences in location.

Referring to FIG. 11A , the first spacer SP1 may support the entire upper surface area of the sealing member SAL, and the second spacer SP2 may support the entire lower surface area of the sealing member SAL. . Side surfaces L1 - 1 and L1 - 2 of the first spacer SP1 may be spaced apart from the sealing member SAL in the first direction DR1 . The side surfaces L2 - 1 and L2 - 2 of the second spacer SP2 may be spaced apart from the sealing member SAL in the first direction DR1 . The first spacer SP1 of FIG. 11A may be substantially the same as the first spacer SP1 of FIG. 8A, and the second spacer SP2 of FIG. 11A may be substantially the same as the second spacer SP2 of FIG. 8B. can do.

Referring to FIG. 11B , the first spacer SP1 may overlap a portion of the sealing member SAL on a plane. Some of the side surfaces L1-1 of the side surfaces L1-1 and L1-2 of the first spacer SP1 may be covered by the sealing member SAL, and the other side surface L1-2 may be covered by the sealing member. (SAL). For example, one side L1 - 2 adjacent to the display area DA in the first direction DR1 among the side surfaces L1 - 1 and L1 - 2 of the first spacer SP1 is a sealing member SAL. It may be spaced apart from, and the other side surface L1-1 opposite to the one side surface L1-2 may be covered by the sealing member SAL.

The second spacer SP2 may overlap a portion of the sealing member SAL on a plane. Some of the side surfaces L2-1 of the side surfaces L2-1 and L2-2 of the second spacer SP2 may be covered by the sealing member SAL, and the other side surface L2-2 may be covered by the sealing member. (SAL). For example, one side L2-2 adjacent to the display area DA in the first direction DR1 among the side surfaces L2-1 and L2-2 of the second spacer SP2 is a sealing member SAL. It is spaced apart from and can be covered by the first and third encapsulation films EN1 and EN3, and the other side surface L2-1 opposite to the one side surface L2-2 is covered by the sealing member SAL. It can be.

Referring to FIG. 11C , the first spacer SP1 may be entirely covered by the sealing member SAL. The first spacer SP1 may be disposed inside the sealing member SAL. That is, the side surfaces L1 - 1 and L1 - 2 and the rear surface of the first spacer SP1 may be covered by the sealing member SAL.

The second spacer SP2 may also be entirely covered by the sealing member SAL. The second spacer SP2 may be disposed inside the sealing member SAL so that the side surfaces L2 - 1 and L2 - 2 and the upper surface of the second spacer SP2 may be covered by the sealing member SAL.

The display module DM according to an exemplary embodiment includes a first spacer SP1 and a second spacer SP2 to compensate for a gap between the first substrate and the second substrate in an area where the sealing member SAL is disposed. The first spacer SP1 and the second spacer SP2 may effectively support the first substrate and the second substrate together with the sealing member SAL.

Meanwhile, the arrangement positions of the first and second spacers SP1 and SP2 shown in FIGS. 11A to 11C are exemplary and are not limited to the illustrated embodiments. For example, in one embodiment, the first spacer SP1 may entirely overlap the sealing member SAL, and the second spacer SP2 may partially overlap the sealing member SAL. That is, the disposition position of the first and second spacers SP1 and SP2 is not limited to any one as long as each overlaps with at least a portion of the sealing member SAL.

Although the above has been described with reference to preferred embodiments of the present invention, those skilled in the art or those having ordinary knowledge in the art do not deviate from the spirit and technical scope of the present invention described in the claims to be described later. It will be understood that the present invention can be variously modified and changed within the scope not specified.

Therefore, the technical scope of the present invention is not limited to the contents described in the detailed description of the specification, but should be defined by the claims.

DD: Electronics DP: Display panel
DP-CL: circuit layer OL, OL1, OL2, OL3: light emitting element
PDL: pixel defining layer PX-OP: light emitting aperture
TFE: encapsulation layer DAM1, DAM2, DAM3: dam
SUB1: first base substrate SUB2: second base substrate
CFL: color filter layer CF1, CF2, CF3: color filter
LCL: light conversion layer BK: bank section
WCP1, WCP2: light conversion part WCP3: transmission part
SAL: sealing member FL: filling member
SP1: first spacer SP2: second spacer
S1: first insulating film S2: second insulating film

Claims (20)

A first substrate including a plurality of light emitting elements and driving elements connected to the light emitting elements;
a second substrate including a light control member and disposed to face the first substrate;
a filling member disposed between the first substrate and the second substrate and covering the plurality of light emitting elements;
a sealing member disposed between the first substrate and the second substrate and coupling the first substrate and the second substrate; and
A spacer disposed between the first substrate and the second substrate and overlapping the sealing member on a plane;
The sealing member is spaced apart from the light emitting elements on a plane. According to claim 1,
The electronic device of claim 1 , wherein the spacer includes at least one organic layer. According to claim 1,
The spacer is disposed between the first substrate and the sealing member in a thickness direction. According to claim 1,
The spacer is disposed between the second substrate and the sealing member in a thickness direction. According to claim 1,
The spacer is in the thickness direction,
a first spacer disposed between the first substrate and the sealing member; and
An electronic device comprising a second spacer disposed between the second substrate and the sealing member. According to claim 1,
The electronic device of claim 1 , wherein the spacer is entirely covered by the sealing member. According to claim 1,
A side surface of the spacer is spaced apart from the sealing member. According to claim 1,
The first substrate further includes a plurality of insulating layers disposed between the light emitting elements and the driving elements,
The electronic device of claim 1 , wherein the spacer includes the same material as at least one of the plurality of insulating layers. According to claim 1,
The first substrate further includes a pixel defining layer defining light emitting regions of the light emitting elements,
The spacer includes the same material as the pixel defining layer. According to claim 1,
The first substrate may include an encapsulation layer disposed between the filling member and the light emitting elements; and
Further comprising a dam disposed outside the encapsulation layer and in contact with the encapsulation layer,
The spacer and the sealing member are spaced apart from the dam on a plane,
The spacer includes the same material as the dam. According to claim 1,
The light control member,
a bank portion disposed on the filling member and defining a plurality of openings each overlapping the light emitting elements; and
An electronic device comprising a plurality of light conversion units, each of which is disposed in the plurality of openings. According to claim 11,
The spacer includes the same material as the bank part. According to claim 11,
Each of the light emitting elements provides source light,
The light conversion units include quantum dots that convert the wavelength of the source light. According to claim 1,
The electronic device of claim 1 , wherein the light control member includes a plurality of color filters disposed on the filling member and each overlapping the light emitting elements. A first base substrate including an upper surface;
a second base substrate including a rear surface facing the upper surface;
a pixel defining layer disposed on the upper surface and including a light emitting opening;
a light emitting element disposed in the light emitting opening;
a driving element disposed between the first base substrate and the light emitting element and connected to the light emitting element;
at least one insulating layer disposed between the driving element and the light emitting element;
a bank unit disposed on the rear surface and including an opening corresponding to the light emitting element;
a light conversion unit disposed in the opening;
a charging member disposed between the light conversion unit and the light emitting element;
a sealing member disposed between the first base substrate and the second base substrate and spaced apart from the light emitting element; and
A first spacer disposed on the same layer as the bank part,
The electronic device of claim 1 , wherein the first spacer overlaps the sealing member on a plane. According to claim 15,
A side surface of the first spacer is covered by the sealing member. According to claim 15,
The side surface of the first spacer is spaced apart from the sealing member. According to claim 15,
a dam disposed between the sealing member and the light emitting element on a plane and spaced apart from the sealing member; and
Further comprising a second spacer disposed on the same layer as the dam,
The dam includes the same material as at least one of the insulating layer and the pixel defining layer;
The second spacer includes the same material as the dam. According to claim 18,
A side surface of the second spacer is covered by the sealing member. According to claim 18,
The side surface of the second spacer is spaced apart from the sealing member.

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